; The format of the input file:
; each device definition begins with a line like this:
;
;       .devicename
;
;  after it go the port definitions in this format:
;
;       portname        address
;
;  the bit definitions (optional) are represented like this:
;
;       portname.bitname  bitnumber
;
; lines beginning with a space are ignored.
; comment lines should be started with ';' character.
;
; the default device is specified at the start of the file
;
;       .default device_name
;
; all lines non conforming to the format are passed to the callback function
;--------------------------------
; Infineon C166 SPECIFIC LINES
;--------------------------------
;
; the processor definition may include the memory configuration.
; the line format is:

;       area CLASS AREA-NAME START:END
;
; where CLASS is anything, but please use one of CODE, DATA, BSS
;       START and END are addresses, the end address is not included

; Interrupt vectors are declared in the following way:

;       entry NAME ADDRESS COMMENT

.default C165

.83C166_80C166
; m166.pdf


; MEMORY MAP
area CODE ROM_EXT       0x0000:0x2000    Internal ROM or External Memory
area DATA MEM_EXT_1     0x2000:0xFA00    External Memory 1
area DATA RAM           0xFA00:0xFE00    Internal RAM
area DATA SFR           0xFE00:0x10000   Internal SFRs
area DATA MEM_EXT_2     0x10000:0x20000  External Memory 2
area DATA MEM_EXT_3     0x20000:0x30000  External Memory 3
area DATA MEM_EXT_4     0x30000:0x40000  External Memory 4


; Interrupt and reset vector assignments
entry RESET     0x0000   RESET
entry NMITRAP   0x0008   NMITRAP Non-Maskable Interrupt (Class A Hardware Traps)
entry STOTRAP   0x0010   STOTRAP Stack Overflow (Class A Hardware Traps)
entry STUTRAP   0x0018   STUTRAP Stack Underflow (Class A Hardware Traps)
entry BTRAP     0x0028   BTRAP Class B Hardware Traps
entry CC0INT    0x0040   CAPCOM Register 0
entry CC1INT    0x0044   CAPCOM Register 1
entry CC2INT    0x0048   CAPCOM Register 2
entry CC3INT    0x004C   CAPCOM Register 3
entry CC4INT    0x0050   CAPCOM Register 4
entry CC5INT    0x0054   CAPCOM Register 5
entry CC6INT    0x0058   CAPCOM Register 6
entry CC7INT    0x005C   CAPCOM Register 7
entry CC8INT    0x0060   CAPCOM Register 8
entry CC9INT    0x0064   CAPCOM Register 9
entry CC10INT   0x0068   CAPCOM Register 10
entry CC11INT   0x006C   CAPCOM Register 11
entry CC12INT   0x0070   CAPCOM Register 12
entry CC13INT   0x0074   CAPCOM Register 13
entry CC14INT   0x0078   CAPCOM Register 14
entry CC15INT   0x007C   CAPCOM Register 15
entry T0INT     0x0080   CAPCOM Timer 0 
entry T1INT     0x0084   CAPCOM Timer 1 
entry T2INT     0x0088   GPT1 Timer 2 
entry T3INT     0x008C   GPT1 Timer 3 
entry T4INT     0x0090   GPT1 Timer 4 
entry T5INT     0x0094   GPT2 Timer 5 
entry T6INT     0x0098   GPT2 Timer 6 
entry CRINT     0x009C   GPT2 CAPREL Reg. 
entry ADCINT    0x00A0   A/D Conversion Complete 
entry ADEINT    0x00A4   A/D Overrun Error 
entry S0TINT    0x00A8   ASC0 Transmit 
entry S0RINT    0x00AC   ASC0 Receive 
entry S0EINT    0x00B0   ASC0 Error 
entry SCTINT    0x00B4   SSC Transmit 
entry SCRINT    0x00B8   SSC Receive 
entry SCEINT    0x00BC   SSC Error 


; INPUT/OUTPUT PORTS
DPP0             0xFE00 CPU Data Page Pointer 0 Register (4 bits)
DPP1             0xFE02 CPU Data Page Pointer 1 Register (4 bits)
DPP2             0xFE04 CPU Data Page Pointer 2 Register (4 bits)
DPP3             0xFE06 CPU Data Page Pointer 3 Register (4 bits)
CSP              0xFE08 CPU Code Segment Pointer Register (2 bits, read only)
reserv_FE0A      0xFE0A RESERVED
MDH              0xFE0C CPU Multiply Divide Register - High Word
MDH.MDH15         15
MDH.MDH14         14
MDH.MDH13         13
MDH.MDH12         12
MDH.MDH11         11
MDH.MDH10         10
MDH.MDH9          9
MDH.MDH8          8
MDH.MDH7          7
MDH.MDH6          6
MDH.MDH5          5
MDH.MDH4          4
MDH.MDH3          3
MDH.MDH2          2
MDH.MDH1          1
MDH.MDH0          0
MDL              0xFE0E CPU Multiply Divide Register - Low Word
MDL.MDL15         15
MDL.MDL14         14
MDL.MDL13         13
MDL.MDL12         12
MDL.MDL11         11
MDL.MDL10         10
MDL.MDL9          9
MDL.MDL8          8
MDL.MDL7          7
MDL.MDL6          6
MDL.MDL5          5
MDL.MDL4          4
MDL.MDL3          3
MDL.MDL2          2
MDL.MDL1          1
MDL.MDL0          0
CP               0xFE10 CPU Context Pointer Register
SP               0xFE12 CPU System Stack Pointer Register
STKOV            0xFE14 CPU Stack Overflow Pointer Register
STKUN            0xFE16 CPU Stack Underflow Pointer Register
STKUN.STKUN10     10
STKUN.STKUN9      9
STKUN.STKUN8      8
STKUN.STKUN7      7
STKUN.STKUN6      6
STKUN.STKUN5      5
STKUN.STKUN4      4
STKUN.STKUN3      3
STKUN.STKUN2      2
STKUN.STKUN1      1
reserv_FE18      0xFE18 RESERVED
reserv_FE1A      0xFE1A RESERVED
reserv_FE1C      0xFE1C RESERVED
reserv_FE1E      0xFE1E RESERVED
reserv_FE20      0xFE20 RESERVED
reserv_FE22      0xFE22 RESERVED
reserv_FE24      0xFE24 RESERVED
reserv_FE26      0xFE26 RESERVED
reserv_FE28      0xFE28 RESERVED
reserv_FE2A      0xFE2A RESERVED
reserv_FE2C      0xFE2C RESERVED
reserv_FE2E      0xFE2E RESERVED
reserv_FE30      0xFE30 RESERVED
reserv_FE32      0xFE32 RESERVED
reserv_FE34      0xFE34 RESERVED
reserv_FE36      0xFE36 RESERVED
reserv_FE38      0xFE38 RESERVED
reserv_FE3A      0xFE3A RESERVED
reserv_FE3C      0xFE3C RESERVED
reserv_FE3E      0xFE3E RESERVED
T2               0xFE40 GPT1 Timer 2 Register
T3               0xFE42 GPT1 Timer 3 Register
T4               0xFE44 GPT1 Timer 4 Register
T5               0xFE46 GPT2 Timer 5 Register
T6               0xFE48 GPT2 Timer 6 Register
CAPREL           0xFE4A GPT2 Capture/Reload Register
reserv_FE4C      0xFE4C RESERVED
reserv_FE4E      0xFE4E RESERVED
T0               0xFE50 CAPCOM Timer 0 Register
T1               0xFE52 CAPCOM Timer 1 Register
T0REL            0xFE54 CAPCOM Timer 0 Reload Register
T1REL            0xFE56 CAPCOM Timer 1 Reload Register
reserv_FE58      0xFE58 RESERVED
reserv_FE5A      0xFE5A RESERVED
reserv_FE5C      0xFE5C RESERVED
reserv_FE5E      0xFE5E RESERVED
reserv_FE60      0xFE60 RESERVED
reserv_FE62      0xFE62 RESERVED
reserv_FE64      0xFE64 RESERVED
reserv_FE66      0xFE66 RESERVED
reserv_FE68      0xFE68 RESERVED
reserv_FE6A      0xFE6A RESERVED
reserv_FE6C      0xFE6C RESERVED
reserv_FE6E      0xFE6E RESERVED
reserv_FE70      0xFE70 RESERVED
reserv_FE72      0xFE72 RESERVED
reserv_FE74      0xFE74 RESERVED
reserv_FE76      0xFE76 RESERVED
reserv_FE78      0xFE78 RESERVED
reserv_FE7A      0xFE7A RESERVED
reserv_FE7C      0xFE7C RESERVED
reserv_FE7E      0xFE7E RESERVED
CC0              0xFE80 CAPCOM Register 0
CC1              0xFE82 CAPCOM Register 1
CC2              0xFE84 CAPCOM Register 2
CC3              0xFE86 CAPCOM Register 3
CC4              0xFE88 CAPCOM Register 4
CC5              0xFE8A CAPCOM Register 5
CC6              0xFE8C CAPCOM Register 6
CC7              0xFE8E CAPCOM Register 7
CC8              0xFE90 CAPCOM Register 8
CC9              0xFE92 CAPCOM Register 9
CC10             0xFE94 CAPCOM Register 10
CC11             0xFE96 CAPCOM Register 11
CC12             0xFE98 CAPCOM Register 12
CC13             0xFE9A CAPCOM Register 13
CC14             0xFE9C CAPCOM Register 14
CC15             0xFE9E CAPCOM Register 15
ADDAT            0xFEA0 A/D Converter Result Register
ADDAT.CHNR15      15  4-bit Channel Number bit 15
ADDAT.CHNR14      14  4-bit Channel Number bit 14
ADDAT.CHNR13      13  4-bit Channel Number bit 13
ADDAT.CHNR12      12  4-bit Channel Number bit 12
ADDAT.ADRES9      9   10-bit Result of the A/D Conversion bit 9
ADDAT.ADRES8      8   10-bit Result of the A/D Conversion bit 8
ADDAT.ADRES7      7   10-bit Result of the A/D Conversion bit 7
ADDAT.ADRES6      6   10-bit Result of the A/D Conversion bit 6
ADDAT.ADRES5      5   10-bit Result of the A/D Conversion bit 5
ADDAT.ADRES4      4   10-bit Result of the A/D Conversion bit 4
ADDAT.ADRES3      3   10-bit Result of the A/D Conversion bit 3
ADDAT.ADRES2      2   10-bit Result of the A/D Conversion bit 2
ADDAT.ADRES1      1   10-bit Result of the A/D Conversion bit 1
ADDAT.ADRES0      0   10-bit Result of the A/D Conversion bit 0
reserv_FEA2      0xFEA2 RESERVED
reserv_FEA4      0xFEA4 RESERVED
reserv_FEA6      0xFEA6 RESERVED
reserv_FEA8      0xFEA8 RESERVED
reserv_FEAA      0xFEAA RESERVED
reserv_FEAC      0xFEAC RESERVED
WDT              0xFEAE Watchdog Timer Register (read only)
S0TBUF           0xFEB0 Serial Channel 0 Transmit Buffer Register
S0RBUF           0xFEB2 Serial Channel 0 Receive Buffer Register (read only)
S0BG             0xFEB4 Serial Channel 0 Baud Rate Generator Reload Register
S1TBUF           0xFEB8 Serial Channel 1 Transmit Buffer Register
S1RBUF           0xFEBA Serial Channel 1 Receive Buffer Register
S1BG             0xFEBC Serial Channel 1 Baud Rate Generator/Reload Register
reserv_FEBE      0xFEBE RESERVED
PECC0            0xFEC0 PEC Channel 0 Control Register
PECC0.INC10       10  Increment Control bit 10
PECC0.INC9        9   Increment Control bit 9 
PECC0.BWT         8   Byte / Word Transfer Selection
PECC0.COUNT7      7   PEC Transfer Count bit 7
PECC0.COUNT6      6   PEC Transfer Count bit 6
PECC0.COUNT5      5   PEC Transfer Count bit 5
PECC0.COUNT4      4   PEC Transfer Count bit 4
PECC0.COUNT3      3   PEC Transfer Count bit 3
PECC0.COUNT2      2   PEC Transfer Count bit 2
PECC0.COUNT1      1   PEC Transfer Count bit 1
PECC0.COUNT0      0   PEC Transfer Count bit 0
PECC1            0xFEC2 PEC Channel 1 Control Register
PECC1.INC10       10  Increment Control bit 10      
PECC1.INC9        9   Increment Control bit 9       
PECC1.BWT         8   Byte / Word Transfer Selection
PECC1.COUNT7      7   PEC Transfer Count bit 7      
PECC1.COUNT6      6   PEC Transfer Count bit 6      
PECC1.COUNT5      5   PEC Transfer Count bit 5      
PECC1.COUNT4      4   PEC Transfer Count bit 4      
PECC1.COUNT3      3   PEC Transfer Count bit 3      
PECC1.COUNT2      2   PEC Transfer Count bit 2      
PECC1.COUNT1      1   PEC Transfer Count bit 1      
PECC1.COUNT0      0   PEC Transfer Count bit 0      
PECC2            0xFEC4 PEC Channel 2 Control Register
PECC2.INC10       10  Increment Control bit 10      
PECC2.INC9        9   Increment Control bit 9       
PECC2.BWT         8   Byte / Word Transfer Selection
PECC2.COUNT7      7   PEC Transfer Count bit 7      
PECC2.COUNT6      6   PEC Transfer Count bit 6      
PECC2.COUNT5      5   PEC Transfer Count bit 5      
PECC2.COUNT4      4   PEC Transfer Count bit 4      
PECC2.COUNT3      3   PEC Transfer Count bit 3      
PECC2.COUNT2      2   PEC Transfer Count bit 2      
PECC2.COUNT1      1   PEC Transfer Count bit 1      
PECC2.COUNT0      0   PEC Transfer Count bit 0      
PECC3            0xFEC6 PEC Channel 3 Control Register
PECC3.INC10       10  Increment Control bit 10      
PECC3.INC9        9   Increment Control bit 9       
PECC3.BWT         8   Byte / Word Transfer Selection
PECC3.COUNT7      7   PEC Transfer Count bit 7      
PECC3.COUNT6      6   PEC Transfer Count bit 6      
PECC3.COUNT5      5   PEC Transfer Count bit 5      
PECC3.COUNT4      4   PEC Transfer Count bit 4      
PECC3.COUNT3      3   PEC Transfer Count bit 3      
PECC3.COUNT2      2   PEC Transfer Count bit 2      
PECC3.COUNT1      1   PEC Transfer Count bit 1      
PECC3.COUNT0      0   PEC Transfer Count bit 0      
PECC4            0xFEC8 PEC Channel 4 Control Register
PECC4.INC10       10  Increment Control bit 10      
PECC4.INC9        9   Increment Control bit 9       
PECC4.BWT         8   Byte / Word Transfer Selection
PECC4.COUNT7      7   PEC Transfer Count bit 7      
PECC4.COUNT6      6   PEC Transfer Count bit 6      
PECC4.COUNT5      5   PEC Transfer Count bit 5      
PECC4.COUNT4      4   PEC Transfer Count bit 4      
PECC4.COUNT3      3   PEC Transfer Count bit 3      
PECC4.COUNT2      2   PEC Transfer Count bit 2      
PECC4.COUNT1      1   PEC Transfer Count bit 1      
PECC4.COUNT0      0   PEC Transfer Count bit 0      
PECC5            0xFECA PEC Channel 5 Control Register
PECC5.INC10       10  Increment Control bit 10      
PECC5.INC9        9   Increment Control bit 9       
PECC5.BWT         8   Byte / Word Transfer Selection
PECC5.COUNT7      7   PEC Transfer Count bit 7      
PECC5.COUNT6      6   PEC Transfer Count bit 6      
PECC5.COUNT5      5   PEC Transfer Count bit 5      
PECC5.COUNT4      4   PEC Transfer Count bit 4      
PECC5.COUNT3      3   PEC Transfer Count bit 3      
PECC5.COUNT2      2   PEC Transfer Count bit 2      
PECC5.COUNT1      1   PEC Transfer Count bit 1      
PECC5.COUNT0      0   PEC Transfer Count bit 0      
PECC6            0xFECC PEC Channel 6 Control Register
PECC6.INC10       10  Increment Control bit 10      
PECC6.INC9        9   Increment Control bit 9       
PECC6.BWT         8   Byte / Word Transfer Selection
PECC6.COUNT7      7   PEC Transfer Count bit 7      
PECC6.COUNT6      6   PEC Transfer Count bit 6      
PECC6.COUNT5      5   PEC Transfer Count bit 5      
PECC6.COUNT4      4   PEC Transfer Count bit 4      
PECC6.COUNT3      3   PEC Transfer Count bit 3      
PECC6.COUNT2      2   PEC Transfer Count bit 2      
PECC6.COUNT1      1   PEC Transfer Count bit 1      
PECC6.COUNT0      0   PEC Transfer Count bit 0      
PECC7            0xFECE PEC Channel 7 Control Register
PECC7.INC10       10  Increment Control bit 10      
PECC7.INC9        9   Increment Control bit 9       
PECC7.BWT         8   Byte / Word Transfer Selection
PECC7.COUNT7      7   PEC Transfer Count bit 7      
PECC7.COUNT6      6   PEC Transfer Count bit 6      
PECC7.COUNT5      5   PEC Transfer Count bit 5      
PECC7.COUNT4      4   PEC Transfer Count bit 4      
PECC7.COUNT3      3   PEC Transfer Count bit 3      
PECC7.COUNT2      2   PEC Transfer Count bit 2      
PECC7.COUNT1      1   PEC Transfer Count bit 1      
PECC7.COUNT0      0   PEC Transfer Count bit 0      
reserv_FED0      0xFED0 RESERVED
reserv_FED2      0xFED2 RESERVED
reserv_FED4      0xFED4 RESERVED
reserv_FED6      0xFED6 RESERVED
reserv_FED8      0xFED8 RESERVED
reserv_FEDA      0xFEDA RESERVED
reserv_FEDC      0xFEDC RESERVED
reserv_FEDE      0xFEDE RESERVED
reserv_FEE0      0xFEE0 RESERVED
reserv_FEE2      0xFEE2 RESERVED
reserv_FEE4      0xFEE4 RESERVED
reserv_FEE6      0xFEE6 RESERVED
reserv_FEE8      0xFEE8 RESERVED
reserv_FEEA      0xFEEA RESERVED
reserv_FEEC      0xFEEC RESERVED
reserv_FEEE      0xFEEE RESERVED
reserv_FEF0      0xFEF0 RESERVED
reserv_FEF2      0xFEF2 RESERVED
reserv_FEF4      0xFEF4 RESERVED
reserv_FEF6      0xFEF6 RESERVED
reserv_FEF8      0xFEF8 RESERVED
reserv_FEFA      0xFEFA RESERVED
reserv_FEFC      0xFEFC RESERVED
reserv_FEFE      0xFEFE RESERVED
P0               0xFF00 Port 0 Register
P0.P0_15          15  Port P0 Data Register bit 15
P0.P0_14          14  Port P0 Data Register bit 14
P0.P0_13          13  Port P0 Data Register bit 13
P0.P0_12          12  Port P0 Data Register bit 12
P0.P0_11          11  Port P0 Data Register bit 11
P0.P0_10          10  Port P0 Data Register bit 10
P0.P0_9           9   Port P0 Data Register bit 9 
P0.P0_8           8   Port P0 Data Register bit 8 
P0.P0_7           7   Port P0 Data Register bit 7 
P0.P0_6           6   Port P0 Data Register bit 6 
P0.P0_5           5   Port P0 Data Register bit 5 
P0.P0_4           4   Port P0 Data Register bit 4 
P0.P0_3           3   Port P0 Data Register bit 3 
P0.P0_2           2   Port P0 Data Register bit 2 
P0.P0_1           1   Port P0 Data Register bit 1 
P0.P0_0           0   Port P0 Data Register bit 0 
DP0              0xFF02 Port 0 Direction Control Register
DP0.DP0_15        15  Port P0 Direction Control bit 15
DP0.DP0_14        14  Port P0 Direction Control bit 14
DP0.DP0_13        13  Port P0 Direction Control bit 13
DP0.DP0_12        12  Port P0 Direction Control bit 12
DP0.DP0_11        11  Port P0 Direction Control bit 11
DP0.DP0_10        10  Port P0 Direction Control bit 10
DP0.DP0_9         9   Port P0 Direction Control bit 9 
DP0.DP0_8         8   Port P0 Direction Control bit 8 
DP0.DP0_7         7   Port P0 Direction Control bit 7 
DP0.DP0_6         6   Port P0 Direction Control bit 6 
DP0.DP0_5         5   Port P0 Direction Control bit 5 
DP0.DP0_4         4   Port P0 Direction Control bit 4 
DP0.DP0_3         3   Port P0 Direction Control bit 3 
DP0.DP0_2         2   Port P0 Direction Control bit 2 
DP0.DP0_1         1   Port P0 Direction Control bit 1 
DP0.DP0_0         0   Port P0 Direction Control bit 0 
P1               0xFF04 Port 1 Register
P1.P1_15          15  Port P1 Data Register bit 15
P1.P1_14          14  Port P1 Data Register bit 14
P1.P1_13          13  Port P1 Data Register bit 13
P1.P1_12          12  Port P1 Data Register bit 12
P1.P1_11          11  Port P1 Data Register bit 11
P1.P1_10          10  Port P1 Data Register bit 10
P1.P1_9           9   Port P1 Data Register bit 9 
P1.P1_8           8   Port P1 Data Register bit 8 
P1.P1_7           7   Port P1 Data Register bit 7 
P1.P1_6           6   Port P1 Data Register bit 6 
P1.P1_5           5   Port P1 Data Register bit 5 
P1.P1_4           4   Port P1 Data Register bit 4 
P1.P1_3           3   Port P1 Data Register bit 3 
P1.P1_2           2   Port P1 Data Register bit 2 
P1.P1_1           1   Port P1 Data Register bit 1 
P1.P1_0           0   Port P1 Data Register bit 0 
DP1              0xFF06 Port 1 Direction Control Register
DP1.DP1_15        15  Port P1 Direction Control bit 15
DP1.DP1_14        14  Port P1 Direction Control bit 14
DP1.DP1_13        13  Port P1 Direction Control bit 13
DP1.DP1_12        12  Port P1 Direction Control bit 12
DP1.DP1_11        11  Port P1 Direction Control bit 11
DP1.DP1_10        10  Port P1 Direction Control bit 10
DP1.DP1_9         9   Port P1 Direction Control bit 9 
DP1.DP1_8         8   Port P1 Direction Control bit 8 
DP1.DP1_7         7   Port P1 Direction Control bit 7 
DP1.DP1_6         6   Port P1 Direction Control bit 6 
DP1.DP1_5         5   Port P1 Direction Control bit 5 
DP1.DP1_4         4   Port P1 Direction Control bit 4 
DP1.DP1_3         3   Port P1 Direction Control bit 3 
DP1.DP1_2         2   Port P1 Direction Control bit 2 
DP1.DP1_1         1   Port P1 Direction Control bit 1 
DP1.DP1_0         0   Port P1 Direction Control bit 0 
P4               0xFF08 Port 4 Register (7 bits)
P4.P4_1           1   Port P4 Data Register bit 1
P4.P4_0           0   Port P4 Data Register bit 0
DP4              0xFF0A Port 4 Direction Control Register
DP4.DP4_1         1   Port P4 Direction Control bit 1
DP4.DP4_0         0   Port P4 Direction Control bit 0
SYSCON           0xFF0C CPU System Configuration Register
SYSCON.STKSZ1     14  Maximum System Stack Size Selection of between 32 and 256 words bit 1
SYSCON.STKSZ0     13  Maximum System Stack Size Selection of between 32 and 256 words bit 0
SYSCON.RDYEN      12  READY Input Enabled control bit
SYSCON.SGTDIS     11  Segmentation Disable control bit
SYSCON.BUSACT     10  Bus Active Control Bit
SYSCON.BYTDIS     9   Byte High Enable (BHE) pin control bit
SYSCON.CLKEN      8   System Clock Output (CLKOUT) Enable bit
SYSCON.BTYP1      7   External Bus Configuration Control bit 1
SYSCON.BTYP0      6   External Bus Configuration Control bit 0
SYSCON.MTTC       5   Memory Tri-state Time Control
SYSCON.RWDC       4   Read/Write Delay Control
SYSCON.MCTC3      3   Memory Cycle Time Control bit 3
SYSCON.MCTC2      2   Memory Cycle Time Control bit 2
SYSCON.MCTC1      1   Memory Cycle Time Control bit 1
SYSCON.MCTC0      0   Memory Cycle Time Control bit 0
MDC              0xFF0E CPU Multiply/   Divide Control Register
MDC.MDRIU         4
PSW              0xFF10 CPU Program Status Word
PSW.ILVL3         15  current interrupt level being serviced bit 3
PSW.ILVL2         14  current interrupt level being serviced bit 2
PSW.ILVL1         13  current interrupt level being serviced bit 1
PSW.ILVL0         12  current interrupt level being serviced bit 0
PSW.IEN           11  globally enables/disables acceptance of interrupts
PSW.HLDEN         10  Bus Arbitration (HOLD/HLDA/BREQ) Enable Bit
PSW.USR0          6   provided as the user's general purpose flag
PSW.MULIP         5   Multiply/divide operation in progress or not
PSW.E             4   supports table search operation by signifying the end of a table
PSW.Z             3   zero result
PSW.V             2   overflow result
PSW.C             1   carry result
PSW.N             0   negative result
reserv_FF12      0xFF12 RESERVED
reserv_FF14      0xFF14 RESERVED
reserv_FF16      0xFF16 RESERVED
reserv_FF18      0xFF18 RESERVED
reserv_FF1A      0xFF1A RESERVED
ZEROS            0xFF1C Constant Value 0's Register (read only)
ONES             0xFF1E Constant Value 1's Register (read only)
reserv_FF20      0xFF20 RESERVED
reserv_FF22      0xFF22 RESERVED
reserv_FF24      0xFF24 RESERVED
reserv_FF26      0xFF26 RESERVED
reserv_FF28      0xFF28 RESERVED
reserv_FF2A      0xFF2A RESERVED
reserv_FF2C      0xFF2C RESERVED
reserv_FF2E      0xFF2E RESERVED
reserv_FF30      0xFF30 RESERVED
reserv_FF32      0xFF32 RESERVED
reserv_FF34      0xFF34 RESERVED
reserv_FF36      0xFF36 RESERVED
reserv_FF38      0xFF38 RESERVED
reserv_FF3A      0xFF3A RESERVED
reserv_FF3C      0xFF3C RESERVED
reserv_FF3E      0xFF3E RESERVED
T2CON            0xFF40 GPT1 Timer 2 Control Register
T2CON.T2UD        7   Up/Down Control Bit
T2CON.T2R         6   Timer 2 Run Bit
T2CON.T2M5        5   Timer 2 Mode Control bit 5
T2CON.T2M4        4   Timer 2 Mode Control bit 4
T2CON.T2M3        3   Timer 2 Mode Control bit 3
T2CON.T2I2        2   Timer 2 Input Selection bit 2
T2CON.T2I1        1   Timer 2 Input Selection bit 1
T2CON.T2I0        0   Timer 2 Input Selection bit 0
T3CON            0xFF42 GPT1 Timer 3 Control Register
T3CON.T3OTL       10
T3CON.T3OE        9   Alternate Output Function Enable
T3CON.T3UDE       8   Timer 3 External Up/Down Control Enable Bit
T3CON.T3UD        7   Timer 3 Up/Down Control
T3CON.T3R         6   Timer 3 Run Bit
T3CON.T3M4        4   Timer 3 Mode control bit 4
T3CON.T3M3        3   Timer 3 Mode control bit 3
T3CON.T3I2        2   Timer 3 Input Selection bit 2
T3CON.T3I1        1   Timer 3 Input Selection bit 1
T3CON.T3I0        0   Timer 3 Input Selection bit 0
T4CON            0xFF44 GPT1 Timer 4 Control Register
T4CON.T4UD        7   Up/Down Control Bit
T4CON.T4R         6   Timer 4 Run Bit
T4CON.T4M5        5   Timer 4 Mode Control bit 5
T4CON.T4M4        4   Timer 4 Mode Control bit 4
T4CON.T4M3        3   Timer 4 Mode Control bit 3
T4CON.T4I2        2   Timer 4 Input Selection bit 2
T4CON.T4I1        1   Timer 4 Input Selection bit 1
T4CON.T4I0        0   Timer 4 Input Selection bit 0
T5CON            0xFF46 GPT2 Timer 5 Control Register
T5CON.T5SC        15  Timer 5 Capture Mode Enable Bit
T5CON.T5CLR       14  Timer 5 Clear Bit
T5CON.CI13        13  Register CAPREL Input Selection bit 13
T5CON.CI12        12  Register CAPREL Input Selection bit 12 
T5CON.T5UD        7   Timer 5 Up/Down Control Bit
T5CON.T5R         6   Timer 5 Run Bit.
T5CON.T5M         3   Timer 5 Mode Control
T5CON.T5I2        2   Timer 5 Input Selection bit 2
T5CON.T5I1        1   Timer 5 Input Selection bit 1
T5CON.T5I0        0   Timer 5 Input Selection bit 0
T6CON            0xFF48 GPT2 Timer 6 Control Register
T6CON.T6SR        15  Timer 6 Reload Mode Enable Bit
T6CON.T6OTL       10  Timer 6 Output Toggle Latch.
T6CON.T6OE        9   Alternate Output Function Enable
T6CON.T6UD        7   Timer 6 Up/Down Control
T6CON.T6R         6   Timer 6 Run Bit
T6CON.T6I2        2   Timer 6 Input Selection bit 2
T6CON.T6I1        1   Timer 6 Input Selection bit 1
T6CON.T6I0        0   Timer 6 Input Selection bit 0
reserv_FF4A      0xFF4A RESERVED
reserv_FF4C      0xFF4C RESERVED
reserv_FF4E      0xFF4E RESERVED
T01CON           0xFF50 CAPCOM Timer 0 and Timer 1 Ctrl. Reg.
T01CON.T1R        14  Timer/Counter 1 Run Bit
T01CON.T1M        11  Timer/Counter 1 Mode Selection
T01CON.T1I10      10  Timer/Counter 1 Input Selection bit 10
T01CON.T1I9       9   Timer/Counter 1 Input Selection bit 9 
T01CON.T1I8       8   Timer/Counter 1 Input Selection bit 8 
T01CON.T0R        6   Timer/Counter 0 Run Bit
T01CON.T0M        3   Timer/Counter 0 Mode Selection
T01CON.T0I2       2   Timer/Counter 0 Input Selection bit 2
T01CON.T0I1       1   Timer/Counter 0 Input Selection bit 1
T01CON.T0I0       0   Timer/Counter 0 Input Selection bit 0
CCM0             0xFF52 CAPCOM Mode Control Register 0
CCM0.ACC3         15  Capture/Compare Register CC3 Allocation Bit
CCM0.CCMOD3_14    14  Capture/Compare Register CC3 Mode Selection bit 14
CCM0.CCMOD3_13    13  Capture/Compare Register CC3 Mode Selection bit 13
CCM0.CCMOD3_12    12  Capture/Compare Register CC3 Mode Selection bit 12
CCM0.ACC2         11  Capture/Compare Register CC2 Allocation Bit
CCM0.CCMOD2_10    10  Capture/Compare Register CC2 Mode Selection bit 10
CCM0.CCMOD2_9     9   Capture/Compare Register CC2 Mode Selection bit 9 
CCM0.CCMOD2_8     8   Capture/Compare Register CC2 Mode Selection bit 8 
CCM0.ACC1         7   Capture/Compare Register CC1 Allocation Bit
CCM0.CCMOD1_6     6   Capture/Compare Register CC1 Mode Selection bit 6
CCM0.CCMOD1_5     5   Capture/Compare Register CC1 Mode Selection bit 5
CCM0.CCMOD1_4     4   Capture/Compare Register CC1 Mode Selection bit 4
CCM0.ACC0         3   Capture/Compare Register CC0 Allocation Bit
CCM0.CCMOD0_2     2   Capture/Compare Register CC0 Mode Selection bit 2
CCM0.CCMOD0_1     1   Capture/Compare Register CC0 Mode Selection bit 1
CCM0.CCMOD0_0     0   Capture/Compare Register CC0 Mode Selection bit 0
CCM1             0xFF54 CAPCOM Mode Control Register 1
CCM1.ACC7         15  Capture/Compare Register CC7 Allocation Bit       
CCM1.CCMOD7_14    14  Capture/Compare Register CC7 Mode Selection bit 14
CCM1.CCMOD7_13    13  Capture/Compare Register CC7 Mode Selection bit 13
CCM1.CCMOD7_12    12  Capture/Compare Register CC7 Mode Selection bit 12
CCM1.ACC6         11  Capture/Compare Register CC6 Allocation Bit       
CCM1.CCMOD6_10    10  Capture/Compare Register CC6 Mode Selection bit 10
CCM1.CCMOD6_9     9   Capture/Compare Register CC6 Mode Selection bit 9 
CCM1.CCMOD6_8     8   Capture/Compare Register CC6 Mode Selection bit 8 
CCM1.ACC5         7   Capture/Compare Register CC5 Allocation Bit       
CCM1.CCMOD5_6     6   Capture/Compare Register CC5 Mode Selection bit 6 
CCM1.CCMOD5_5     5   Capture/Compare Register CC5 Mode Selection bit 5 
CCM1.CCMOD5_4     4   Capture/Compare Register CC5 Mode Selection bit 4 
CCM1.ACC4         3   Capture/Compare Register CC4 Allocation Bit       
CCM1.CCMOD4_2     2   Capture/Compare Register CC4 Mode Selection bit 2 
CCM1.CCMOD4_1     1   Capture/Compare Register CC4 Mode Selection bit 1 
CCM1.CCMOD4_0     0   Capture/Compare Register CC4 Mode Selection bit 0 
CCM2             0xFF56 CAPCOM Mode Control Register 2
CCM2.ACC11        15  Capture/Compare Register CC11 Allocation Bit       
CCM2.CCMOD11_14   14  Capture/Compare Register CC11 Mode Selection bit 14
CCM2.CCMOD11_13   13  Capture/Compare Register CC11 Mode Selection bit 13
CCM2.CCMOD11_12   12  Capture/Compare Register CC11 Mode Selection bit 12
CCM2.ACC10        11  Capture/Compare Register CC10 Allocation Bit       
CCM2.CCMOD10_10   10  Capture/Compare Register CC10 Mode Selection bit 10
CCM2.CCMOD10_9    9   Capture/Compare Register CC10 Mode Selection bit 9 
CCM2.CCMOD10_8    8   Capture/Compare Register CC10 Mode Selection bit 8 
CCM2.ACC9         7   Capture/Compare Register CC9  Allocation Bit       
CCM2.CCMOD9_6     6   Capture/Compare Register CC9 Mode Selection bit 6 
CCM2.CCMOD9_5     5   Capture/Compare Register CC9 Mode Selection bit 5 
CCM2.CCMOD9_4     4   Capture/Compare Register CC9 Mode Selection bit 4 
CCM2.ACC8         3   Capture/Compare Register CC8 Allocation Bit       
CCM2.CCMOD8_2     2   Capture/Compare Register CC8 Mode Selection bit 2 
CCM2.CCMOD8_1     1   Capture/Compare Register CC8 Mode Selection bit 1 
CCM2.CCMOD8_0     0   Capture/Compare Register CC8 Mode Selection bit 0 
CCM3             0xFF58 CAPCOM Mode Control Register 3
CCM3.ACC15        15  Capture/Compare Register CC15 Allocation Bit       
CCM3.CCMOD15_14   14  Capture/Compare Register CC15 Mode Selection bit 14
CCM3.CCMOD15_13   13  Capture/Compare Register CC15 Mode Selection bit 13
CCM3.CCMOD15_12   12  Capture/Compare Register CC15 Mode Selection bit 12
CCM3.ACC14        11  Capture/Compare Register CC14 Allocation Bit       
CCM3.CCMOD14_10   10  Capture/Compare Register CC14 Mode Selection bit 10
CCM3.CCMOD14_9    9   Capture/Compare Register CC14 Mode Selection bit 9 
CCM3.CCMOD14_8    8   Capture/Compare Register CC14 Mode Selection bit 8 
CCM3.ACC13        7   Capture/Compare Register CC13 Allocation Bit       
CCM3.CCMOD13_6    6   Capture/Compare Register CC13 Mode Selection bit 6 
CCM3.CCMOD13_5    5   Capture/Compare Register CC13 Mode Selection bit 5 
CCM3.CCMOD13_4    4   Capture/Compare Register CC13 Mode Selection bit 4 
CCM3.ACC12        3   Capture/Compare Register CC12 Allocation Bit       
CCM3.CCMOD12_2    2   Capture/Compare Register CC12 Mode Selection bit 2 
CCM3.CCMOD12_1    1   Capture/Compare Register CC12 Mode Selection bit 1 
CCM3.CCMOD12_0    0   Capture/Compare Register CC12 Mode Selection bit 0 
reserv_FF5A      0xFF5A RESERVED
reserv_FF5C      0xFF5C RESERVED
reserv_FF5E      0xFF5E RESERVED
T2IC             0xFF60 GPT1 Timer 2 Interrupt Control Register
T2IC.T2IR         7
T2IC.T2IE         6
T2IC.ILVL5        5
T2IC.ILVL4        4
T2IC.ILVL3        3
T2IC.ILVL2        2
T2IC.GLVL1        1
T2IC.GLVL0        0
T3IC             0xFF62 GPT1 Timer 3 Interrupt Control Register
T3IC.T3IR         7
T3IC.T3IE         6
T3IC.ILVL5        5
T3IC.ILVL4        4
T3IC.ILVL3        3
T3IC.ILVL2        2
T3IC.GLVL1        1
T3IC.GLVL0        0
T4IC             0xFF64 GPT1 Timer 4 Interrupt Control Register
T4IC.T4IR         7
T4IC.T4IE         6
T4IC.ILVL5        5
T4IC.ILVL4        4
T4IC.ILVL3        3
T4IC.ILVL2        2
T4IC.GLVL1        1
T4IC.GLVL0        0
T5IC             0xFF66 GPT2 Timer 5 Interrupt Control Register
T5IC.T5IR         7
T5IC.T5IE         6
T5IC.ILVL5        5
T5IC.ILVL4        4
T5IC.ILVL3        3
T5IC.ILVL2        2
T5IC.GLVL1        1
T5IC.GLVL0        0
T6IC             0xFF68 GPT2 Timer 6 Interrupt Control Register
T6IC.T6IR         7
T6IC.T6IE         6
T6IC.ILVL5        5
T6IC.ILVL4        4
T6IC.ILVL3        3
T6IC.ILVL2        2
T6IC.GLVL1        1
T6IC.GLVL0        0
CRIC             0xFF6A GPT2 CAPREL Interrupt Control Register
CRIC.CRIR         7
CRIC.CRIE         6
CRIC.ILVL5        5
CRIC.ILVL4        4
CRIC.ILVL3        3
CRIC.ILVL2        2
CRIC.GLVL1        1
CRIC.GLVL0        0
S0TIC            0xFF6C Serial Channel 0 Transmit Interrupt Control Register
S0TIC.S0TIR       7
S0TIC.S0TIE       6
S0TIC.ILVL5       5
S0TIC.ILVL4       4
S0TIC.ILVL3       3
S0TIC.ILVL2       2
S0TIC.GLVL1       1
S0TIC.GLVL0       0
S0RIC            0xFF6E Serial Channel 0 Receive Interrupt Control Register
S0RIC.S0RIR       7
S0RIC.S0RIE       6
S0RIC.ILVL5       5
S0RIC.ILVL4       4
S0RIC.ILVL3       3
S0RIC.ILVL2       2
S0RIC.GLVL1       1
S0RIC.GLVL0       0
S0EIC            0xFF70 Serial Channel 0 Error Interrupt Ctrl. Reg.
S0EIC.S0EIR       7
S0EIC.S0EIE       6
S0EIC.ILVL5       5
S0EIC.ILVL4       4
S0EIC.ILVL3       3
S0EIC.ILVL2       2
S0EIC.GLVL1       1
S0EIC.GLVL0       0
S1TIC            0xFF72 Serial Channel 1 Transmit Interrupt Control
S1TIC.S1TIR       7
S1TIC.S1TIE       6
S1TIC.ILVL5       5
S1TIC.ILVL4       4
S1TIC.ILVL3       3
S1TIC.ILVL2       2
S1TIC.GLVL1       1
S1TIC.GLVL0       0
S1RIC            0xFF74 Serial Channel 1 Receive Interrupt Control
S1RIC.S1RIR       7
S1RIC.S1RIE       6
S1RIC.ILVL5       5
S1RIC.ILVL4       4
S1RIC.ILVL3       3
S1RIC.ILVL2       2
S1RIC.GLVL1       1
S1RIC.GLVL0       0
S1EIC            0xFF76 Serial Channel 1 Error Interrupt control
S1EIC.S1EIR       7
S1EIC.S1EIE       6
S1EIC.ILVL5       5
S1EIC.ILVL4       4
S1EIC.ILVL3       3
S1EIC.ILVL2       2
S1EIC.GLVL1       1
S1EIC.GLVL0       0
CC0IC            0xFF78 CAPCOM Register 0 Interrupt Ctrl. Reg.
CC0IC.CC0IR       7
CC0IC.CC0IE       6
CC0IC.ILVL5       5
CC0IC.ILVL4       4
CC0IC.ILVL3       3
CC0IC.ILVL2       2  
CC0IC.GLVL1       1
CC0IC.GLVL0       0
CC1IC            0xFF7A CAPCOM Register 1 Interrupt Ctrl. Reg.
CC1IC.CC1IR       7
CC1IC.CC1IE       6
CC1IC.ILVL5       5
CC1IC.ILVL4       4
CC1IC.ILVL3       3
CC1IC.ILVL2       2  
CC1IC.GLVL1       1
CC1IC.GLVL0       0
CC2IC            0xFF7C CAPCOM Register 2 Interrupt Ctrl. Reg.
CC2IC.CC2IR       7
CC2IC.CC2IE       6
CC2IC.ILVL5       5
CC2IC.ILVL4       4
CC2IC.ILVL3       3
CC2IC.ILVL2       2  
CC2IC.GLVL1       1
CC2IC.GLVL0       0
CC3IC            0xFF7E CAPCOM Register 3 Interrupt Ctrl. Reg.
CC3IC.CC3IR       7
CC3IC.CC3IE       6
CC3IC.ILVL5       5
CC3IC.ILVL4       4
CC3IC.ILVL3       3
CC3IC.ILVL2       2  
CC3IC.GLVL1       1
CC3IC.GLVL0       0
CC4IC            0xFF80 CAPCOM Register 4 Interrupt Ctrl. Reg.
CC4IC.CC4IR       7
CC4IC.CC4IE       6
CC4IC.ILVL5       5
CC4IC.ILVL4       4
CC4IC.ILVL3       3
CC4IC.ILVL2       2  
CC4IC.GLVL1       1
CC4IC.GLVL0       0
CC5IC            0xFF82 CAPCOM Register 5 Interrupt Ctrl. Reg.
CC5IC.CC5IR       7
CC5IC.CC5IE       6
CC5IC.ILVL5       5
CC5IC.ILVL4       4
CC5IC.ILVL3       3
CC5IC.ILVL2       2  
CC5IC.GLVL1       1
CC5IC.GLVL0       0
CC6IC            0xFF84 CAPCOM Register 6Interrupt Ctrl. Reg.
CC6IC.CC6IR       7
CC6IC.CC6IE       6
CC6IC.ILVL5       5
CC6IC.ILVL4       4
CC6IC.ILVL3       3
CC6IC.ILVL2       2  
CC6IC.GLVL1       1
CC6IC.GLVL0       0
CC7IC            0xFF86 CAPCOM Register 7 Interrupt Ctrl. Reg.
CC7IC.CC7IR       7
CC7IC.CC7IE       6
CC7IC.ILVL5       5
CC7IC.ILVL4       4
CC7IC.ILVL3       3
CC7IC.ILVL2       2  
CC7IC.GLVL1       1
CC7IC.GLVL0       0
CC8IC            0xFF88 CAPCOM Register 8 Interrupt Ctrl. Reg.
CC8IC.CC8IR       7
CC8IC.CC8IE       6
CC8IC.ILVL5       5
CC8IC.ILVL4       4
CC8IC.ILVL3       3
CC8IC.ILVL2       2  
CC8IC.GLVL1       1
CC8IC.GLVL0       0
CC9IC            0xFF8A CAPCOM Register 9 Interrupt Ctrl. Reg.
CC9IC.CC9IR       7
CC9IC.CC9IE       6
CC9IC.ILVL5       5
CC9IC.ILVL4       4
CC9IC.ILVL3       3
CC9IC.ILVL2       2  
CC9IC.GLVL1       1
CC9IC.GLVL0       0
CC10IC           0xFF8C CAPCOM Register 10 Interrupt Ctrl. Reg.
CC10IC.CC10IR     7
CC10IC.CC10IE     6
CC10IC.ILVL5      5
CC10IC.ILVL4      4
CC10IC.ILVL3      3
CC10IC.ILVL2      2  
CC10IC.GLVL1      1
CC10IC.GLVL0      0
CC11IC           0xFF8E CAPCOM Register 11 Interrupt Ctrl. Reg.
CC11IC.CC11IR     7
CC11IC.CC11IE     6
CC11IC.ILVL5      5
CC11IC.ILVL4      4
CC11IC.ILVL3      3
CC11IC.ILVL2      2  
CC11IC.GLVL1      1
CC11IC.GLVL0      0
CC12IC           0xFF90 CAPCOM Register 12 Interrupt Ctrl. Reg.
CC12IC.CC12IR     7
CC12IC.CC12IE     6
CC12IC.ILVL5      5
CC12IC.ILVL4      4
CC12IC.ILVL3      3
CC12IC.ILVL2      2  
CC12IC.GLVL1      1
CC12IC.GLVL0      0
CC13IC           0xFF92 CAPCOM Register 13 Interrupt Ctrl. Reg.
CC13IC.CC13IR     7
CC13IC.CC13IE     6
CC13IC.ILVL5      5
CC13IC.ILVL4      4
CC13IC.ILVL3      3
CC13IC.ILVL2      2  
CC13IC.GLVL1      1
CC13IC.GLVL0      0
CC14IC           0xFF94 CAPCOM Register 14 Interrupt Ctrl. Reg.
CC14IC.CC14IR     7
CC14IC.CC14IE     6
CC14IC.ILVL5      5
CC14IC.ILVL4      4
CC14IC.ILVL3      3
CC14IC.ILVL2      2  
CC14IC.GLVL1      1
CC14IC.GLVL0      0
CC15IC           0xFF96 CAPCOM Register 15 Interrupt Ctrl. Reg.
CC15IC.CC15IR     7
CC15IC.CC15IE     6
CC15IC.ILVL5      5
CC15IC.ILVL4      4
CC15IC.ILVL3      3
CC15IC.ILVL2      2  
CC15IC.GLVL1      1
CC15IC.GLVL0      0
ADCIC            0xFF98 A/D Converter End of Conversion Interrupt Control Register
ADCIC.ADCIR       7
ADCIC.ADCIE       6
ADCIC.ILVL5       5
ADCIC.ILVL4       4
ADCIC.ILVL3       3
ADCIC.ILVL2       2
ADCIC.GLVL1       1
ADCIC.GLVL0       0
ADEIC            0xFF9A A/D Converter Overrun Error Interrupt Control Register
ADEIC.ADEIR       7
ADEIC.ADEIE       6
ADEIC.ILVL5       5
ADEIC.ILVL4       4
ADEIC.ILVL3       3
ADEIC.ILVL2       2
ADEIC.GLVL1       1
ADEIC.GLVL0       0
T0IC             0xFF9C CAPCOM Timer 0 Interrupt Ctrl. Reg.
T0IC.T0IR         7
T0IC.T0IE         6
T1IC             0xFF9E CAPCOM Timer 1 Interrupt Ctrl. Reg.
T1IC.T1IR         7
T1IC.T1IE         6
ADCON            0xFFA0 A/D Converter Control Register
ADCON.ADBSY       8   ADC Busy Flag
ADCON.ADST        7   ADC Start Bit
ADCON.ADM5        5   ADC Mode Selection bit 5
ADCON.ADM4        4   ADC Mode Selection bit 4  
ADCON.ADCH3       3   ADC Analog Input Channel Selection bit 3
ADCON.ADCH2       2   ADC Analog Input Channel Selection bit 2
ADCON.ADCH1       1   ADC Analog Input Channel Selection bit 1
ADCON.ADCH0       0   ADC Analog Input Channel Selection bit 0
P5               0xFFA2 Port 5 Register (read only)
P5.P5_9           9   Port 5 Data Register bit 9
P5.P5_8           8   Port 5 Data Register bit 8
P5.P5_7           7   Port 5 Data Register bit 7
P5.P5_6           6   Port 5 Data Register bit 6
P5.P5_5           5   Port 5 Data Register bit 5
P5.P5_4           4   Port 5 Data Register bit 4
P5.P5_3           3   Port 5 Data Register bit 3
P5.P5_2           2   Port 5 Data Register bit 2
P5.P5_1           1   Port 5 Data Register bit 1
P5.P5_0           0   Port 5 Data Register bit 0
reserv_FFA4      0xFFA4 RESERVED
reserv_FFA6      0xFFA6 RESERVED
reserv_FFA8      0xFFA8 RESERVED
reserv_FFAA      0xFFAA RESERVED
TFR              0xFFAC Trap Flag Register
TFR.NMI           15
TFR.STKOF         14
TFR.STKUF         13
TFR.UNDOPC        7
TFR.PRTFLT        3
TFR.ILLOPA        2
TFR.ILLINA        1
TFR.ILLBUS        0
WDTCON           0xFFAE Watchdog Timer Control Register
WDTCON.WDTREL15   15  Reload Value for the high byte of the Watchdog Timer 15
WDTCON.WDTREL14   14  Reload Value for the high byte of the Watchdog Timer 14
WDTCON.WDTREL13   13  Reload Value for the high byte of the Watchdog Timer 13
WDTCON.WDTREL12   12  Reload Value for the high byte of the Watchdog Timer 12
WDTCON.WDTREL11   11  Reload Value for the high byte of the Watchdog Timer 11
WDTCON.WDTREL10   10  Reload Value for the high byte of the Watchdog Timer 10
WDTCON.WDTREL9    9   Reload Value for the high byte of the Watchdog Timer 9 
WDTCON.WDTREL8    8   Reload Value for the high byte of the Watchdog Timer 8 
WDTCON.WDTR       1   Watchdog Timer Reset Indication Flag
WDTCON.WDTIN      0   Watchdog Timer Input Frequency Selection
S0CON            0xFFB0 Serial Channel 0 Control Register
S0CON.S0R         15  ASCx Baud Rate Generator Run Bit
S0CON.S0LB        14  Loop Back Mode Enable Bit
S0CON.S0OE        10  Overrun Error Flag
S0CON.S0FE        9   Framing Error Flag
S0CON.S0PE        8   Parity Error Flag
S0CON.S0OEN       7   Overrun Check Enable Bit
S0CON.S0FEN       6   Framing Check Enable Bit
S0CON.S0PEN       5   Parity Check Enable Bit
S0CON.S0REN       4   Receiver Enable Bit. Used to Initiate Reception
S0CON.S0STP       3   Number of Stop Bits Selection
S0CON.S0M2        2   ASC2 Mode Control
S0CON.S0M1        1   ASC1 Mode Control
S0CON.S0M0        0   ASC0 Mode Control
reserv_FFB2      0xFFB2 RESERVED
reserv_FFB4      0xFFB4 RESERVED
reserv_FFB6      0xFFB6 RESERVED
S1CON            0xFFB8   Serial Channel 1 Control Register
S1CON.S1R         15  ASC1 Baud Rate Generator Run Bit
S1CON.S1LB        14  Loop Back Mode Enable Bit         
S1CON.S1OE        10  Overrun Error Flag.
S1CON.S1FE        9   Framing Error Flag.
S1CON.S1PE        8   Parity Error Flag.
S1CON.S1OEN       7   Overrun Check Enable Bit.
S1CON.S1FEN       6   Framing Check Enable Bit.
S1CON.S1PEN       5   Parity Check Enable Bit.
S1CON.S1REN       4   Receiver Enable Bit. Used to Initiate Reception.
S1CON.S1STP       3   Number of Stop Bits Selection.
S1CON.S1M2        2   ASC1 Mode Control bit 2
S1CON.S1M1        1   ASC1 Mode Control bit 1
S1CON.S1M0        0   ASC1 Mode Control bit 0
reserv_FFBA      0xFFBA RESERVED
reserv_FFBC      0xFFBC RESERVED
reserv_FFBE      0xFFBE RESERVED
P2               0xFFC0 Port 2 Register
P2.P2_15          15  Port P2 Data Register bit 15
P2.P2_14          14  Port P2 Data Register bit 14
P2.P2_13          13  Port P2 Data Register bit 13
P2.P2_12          12  Port P2 Data Register bit 12
P2.P2_11          11  Port P2 Data Register bit 11
P2.P2_10          10  Port P2 Data Register bit 10
P2.P2_9           9   Port P2 Data Register bit 9 
P2.P2_8           8   Port P2 Data Register bit 8 
P2.P2_7           7   Port P2 Data Register bit 7 
P2.P2_6           6   Port P2 Data Register bit 6 
P2.P2_5           5   Port P2 Data Register bit 5 
P2.P2_4           4   Port P2 Data Register bit 4 
P2.P2_3           3   Port P2 Data Register bit 3 
P2.P2_2           2   Port P2 Data Register bit 2 
P2.P2_1           1   Port P2 Data Register bit 1 
P2.P2_0           0   Port P2 Data Register bit 0 
DP2              0xFFC2 Port 2 Direction Control Register
DP2.DP2_15        15  Port P2 Direction Control bit 15
DP2.DP2_14        14  Port P2 Direction Control bit 14
DP2.DP2_13        13  Port P2 Direction Control bit 13
DP2.DP2_12        12  Port P2 Direction Control bit 12
DP2.DP2_11        11  Port P2 Direction Control bit 11
DP2.DP2_10        10  Port P2 Direction Control bit 10
DP2.DP2_9         9   Port P2 Direction Control bit 9 
DP2.DP2_8         8   Port P2 Direction Control bit 8 
DP2.DP2_7         7   Port P2 Direction Control bit 7 
DP2.DP2_6         6   Port P2 Direction Control bit 6 
DP2.DP2_5         5   Port P2 Direction Control bit 5 
DP2.DP2_4         4   Port P2 Direction Control bit 4 
DP2.DP2_3         3   Port P2 Direction Control bit 3 
DP2.DP2_2         2   Port P2 Direction Control bit 2 
DP2.DP2_1         1   Port P2 Direction Control bit 1 
DP2.DP2_0         0   Port P2 Direction Control bit 0 
P3               0xFFC4 Port 3 Register
P3.P3_15          15  Port P3 Data Register bit 15
P3.P3_14          14  Port P3 Data Register bit 14
P3.P3_13          13  Port P3 Data Register bit 13
P3.P3_12          12  Port P3 Data Register bit 12
P3.P3_11          11  Port P3 Data Register bit 11
P3.P3_10          10  Port P3 Data Register bit 10
P3.P3_9           9   Port P3 Data Register bit 9 
P3.P3_8           8   Port P3 Data Register bit 8 
P3.P3_7           7   Port P3 Data Register bit 7 
P3.P3_6           6   Port P3 Data Register bit 6 
P3.P3_5           5   Port P3 Data Register bit 5 
P3.P3_4           4   Port P3 Data Register bit 4 
P3.P3_3           3   Port P3 Data Register bit 3 
P3.P3_2           2   Port P3 Data Register bit 2 
P3.P3_1           1   Port P3 Data Register bit 1 
P3.P3_0           0   Port P3 Data Register bit 0 
DP3              0xFFC6 Port 3 Direction Control Register
DP3.DP3_15        15  Port P3 Direction Control bit 15
DP3.DP3_14        14  Port P3 Direction Control bit 14
DP3.DP3_13        13  Port P3 Direction Control bit 13
DP3.DP3_12        12  Port P3 Direction Control bit 12
DP3.DP3_11        11  Port P3 Direction Control bit 11
DP3.DP3_10        10  Port P3 Direction Control bit 10
DP3.DP3_9         9   Port P3 Direction Control bit 9 
DP3.DP3_8         8   Port P3 Direction Control bit 8 
DP3.DP3_7         7   Port P3 Direction Control bit 7 
DP3.DP3_6         6   Port P3 Direction Control bit 6 
DP3.DP3_5         5   Port P3 Direction Control bit 5 
DP3.DP3_4         4   Port P3 Direction Control bit 4 
DP3.DP3_3         3   Port P3 Direction Control bit 3 
DP3.DP3_2         2   Port P3 Direction Control bit 2 
DP3.DP3_1         1   Port P3 Direction Control bit 1 
DP3.DP3_0         0   Port P3 Direction Control bit 0 
reserv_FFC8      0xFFC8 RESERVED
reserv_FFCA      0xFFCA RESERVED
reserv_FFCC      0xFFCC RESERVED
reserv_FFCE      0xFFCE RESERVED
reserv_FFD0      0xFFD0 RESERVED
reserv_FFD2      0xFFD2 RESERVED
reserv_FFD4      0xFFD4 RESERVED
reserv_FFD6      0xFFD6 RESERVED
reserv_FFD8      0xFFD8 RESERVED
reserv_FFDA      0xFFDA RESERVED
reserv_FFDC      0xFFDC RESERVED
reserv_FFDE      0xFFDE RESERVED


.C161CS
; http://www.infineon.com/cgi/ecrm.dll/ecrm/scripts/public_download.jsp?oid=18695&parent_oid=13740


; MEMORY MAP
area DATA ROM_           0x0000:0x8000   Internal ROM Area
area DATA MEM_EXT        0x8000:0xC000   External Memory
area DATA XRAM           0xC000:0xE000
area BSS  RESERVED       0xE000:0xEB00
area DATA SDLM_          0xEB00:0xEC00
area BSS  RESERVED       0xEC00:0xED00
area DATA IIC_ASC1       0xED00:0xEE00   IIC/ASC1
area BSS  RESERVED       0xEE00:0xEF00
area DATA CAN1_          0xEF00:0xF000
area DATA ESFR_          0xF000:0xF200   ESFR Area
area BSS  RESERVED       0xF200:0xF600   
area DATA IRAM_          0xF600:0xFE00   IRAM
area DATA SFR_           0xFE00:0x10000  SFR Area


; Interrupt and reset vector assignments
entry RESET     0x0000    RESET
entry NMITRAP   0x0008    NMITRAP Non-Maskable Interrupt (Class A Hardware Traps)
entry STOTRAP   0x0010    STOTRAP Stack Overflow (Class A Hardware Traps)
entry STUTRAP   0x0018    STUTRAP Stack Underflow (Class A Hardware Traps)
entry BTRAP     0x0028    BTRAP Class B Hardware Traps
entry CC0INT    0x0040    CAPCOM Register 0
entry CC1INT    0x0044    CAPCOM Register 1
entry CC2INT    0x0048    CAPCOM Register 2
entry CC3INT    0x004C    CAPCOM Register 3
entry CC4INT    0x0050    CAPCOM Register 4
entry CC5INT    0x0054    CAPCOM Register 5
entry CC6INT    0x0058    CAPCOM Register 6
entry CC7INT    0x005C    CAPCOM Register 7
entry CC8INT    0x0060    CAPCOM Register 8
entry CC9INT    0x0064    CAPCOM Register 9
entry CC10INT   0x0068    CAPCOM Register 10
entry CC11INT   0x006C    CAPCOM Register 11
entry CC12INT   0x0070    CAPCOM Register 12
entry CC13INT   0x0074    CAPCOM Register 13
entry CC14INT   0x0078    CAPCOM Register 14
entry CC15INT   0x007C    CAPCOM Register 15
entry T0INT     0x0080    CAPCOM Timer 0
entry T1INT     0x0084    CAPCOM Timer 1
entry T2INT     0x0088    GPT1 Timer 2
entry T3INT     0x008C    GPT1 Timer 3
entry T4INT     0x0090    GPT1 Timer 4
entry T5INT     0x0094    GPT2 Timer 5
entry T6INT     0x0098    GPT2 Timer 6
entry CRINT     0x009C    GPT2 CAPREL Register
entry ADCINT    0x00A0    A/D Conversion Complete
entry ADEINT    0x00A4    A/D Overrun Error
entry S0TINT    0x00A8    ASC0 Transmit
entry S0RINT    0x00AC    ASC0 Receive
entry S0EINT    0x00B0    ASC0 Error
entry SCTINT    0x00B4    SSC Transmit
entry SCRINT    0x00B8    SSC Receive
entry SCEINT    0x00BC    SSC Error
entry CC16INT   0x00C0    CAPCOM Register 16
entry CC17INT   0x00C4    CAPCOM Register 17
entry CC18INT   0x00C8    CAPCOM Register 18
entry CC19INT   0x00CC    CAPCOM Register 19
entry CC20INT   0x00D0    CAPCOM Register 20
entry CC21INT   0x00D4    CAPCOM Register 21
entry CC22INT   0x00D8    CAPCOM Register 22
entry CC23INT   0x00DC    CAPCOM Register 23
entry CC24INT   0x00E0    CAPCOM Register 24
entry CC25INT   0x00E4    CAPCOM Register 25
entry CC26INT   0x00E8    CAPCOM Register 26
entry CC27INT   0x00EC    CAPCOM Register 27
entry CC28INT   0x00F0    CAPCOM Register 28
entry T7INT     0x00F4    CAPCOM Timer 7
entry T8INT     0x00F8    CAPCOM Timer 8
entry XP0INT    0x0100    IIC Data Transfer Event
entry XP1INT    0x0104    IIC Protocol Event
entry XP2INT    0x0108    CAN1 (C161CS/JC)
entry XP3INT    0x010C    PLL/RTC (via ISNC)
entry CC29INT   0x0110    CAPCOM Register 29
entry CC30INT   0x0114    CAPCOM Register 30
entry CC31INT   0x0118    CAPCOM Register 31
entry S0TBINT   0x011C    ASC0 Transmit Buffer
entry XP4INT    0x0120    ASC1 Transmit
entry XP5INT    0x0124    ASC1 Receive
entry XP6INT    0x0128    ASC1 Error
entry XP7INT    0x012C    CAN2 (C161CS)


; INPUT/OUTPUT PORTS
IPCR             0xEB04   SDLM Interface Port Connect Register           
IPCR.IPC_2        2   Interface Port Connection - bit 2
IPCR.IPC_1        1   Interface Port Connection - bit 1
IPCR.IPC_0        0   Interface Port Connection - bit 0
GLOBCON          0xEB10   SDLM Global Control Register                   
GLOBCON.ARIFR     6   Automatic Retry of IFR
GLOBCON.OVWR      5   Overwrite Enable
GLOBCON.NB        4   Normalization Bit Polarity
GLOBCON.HDT       3   Header Type
GLOBCON.BMEN      2   Block Mode Enable
GLOBCON.EN4X      1   High Speed Transfer Enable (4x)
GLOBCON.GMEN      0   Global Module Enable
CLKDIV           0xEB14   SDLM Clock Divider Register                    
CLKDIV.CLKEN      7   Clock Enable
CLKDIV.CLKSEL     6   Clock Select
CLKDIV.CD_5       5   Clock Divider - bit 5
CLKDIV.CD_4       4   Clock Divider - bit 4
CLKDIV.CD_3       3   Clock Divider - bit 3
CLKDIV.CD_2       2   Clock Divider - bit 2
CLKDIV.CD_1       1   Clock Divider - bit 1
CLKDIV.CD_0       0   Clock Divider - bit 0
TxDELAY          0xEB16   SDLM Trabsceiver Delay Register                
TxDELAY.RINV      6   Invert Receive Input
TxDELAY.TD_5      5   Transceiver Delay - bit 5
TxDELAY.TD_4      4   Transceiver Delay - bit 4
TxDELAY.TD_3      3   Transceiver Delay - bit 3
TxDELAY.TD_2      2   Transceiver Delay - bit 2
TxDELAY.TD_1      1   Transceiver Delay - bit 1
TxDELAY.TD_0      0   Transceiver Delay - bit 0
IFR              0xEB18   SDLM In-Frame Response Value Register          
IFR.IFRVAL_7      7   In-Frame Response Value - bit 7
IFR.IFRVAL_6      6   In-Frame Response Value - bit 6
IFR.IFRVAL_5      5   In-Frame Response Value - bit 5
IFR.IFRVAL_4      4   In-Frame Response Value - bit 4
IFR.IFRVAL_3      3   In-Frame Response Value - bit 3
IFR.IFRVAL_2      2   In-Frame Response Value - bit 2
IFR.IFRVAL_1      1   In-Frame Response Value - bit 1
IFR.IFRVAL_0      0   In-Frame Response Value - bit 0
BUFFSTAT         0xEB1C   SDLM Buffer Status Register                    
BUFFSTAT.RBC      4   Receive Buffer on CPU Side Full
BUFFSTAT.RBB      3   Receive Buffer on Bus Side Full
BUFFSTAT.MSGLST   2   Message Lost
BUFFSTAT.RIP      1   Reception in Progress
BUFFSTAT.TIP      0   Transmission In Progress
TRANSSTAT        0xEB1E   SDLM Transmission Status Register              
TRANSSTAT.Y       7   Y Bit in 3 Byte Consolidated Headers
TRANSSTAT.K       6   K Bit in 3 Byte Consolidated Headers
TRANSSTAT.H       5   H Bit in Consolidated Headers
TRANSSTAT.ARL     4   Arbitration Lost
TRANSSTAT.BREAK   3   Break Received
TRANSSTAT.HEADER  2   Header Received
TRANSSTAT.MSGREC  1   Message Received
TRANSSTAT.MSGTRA  0   Message Transmitted
BUSSTAT          0xEB20   SDLM Bus Status Register                       
BUSSTAT.IDLE      3   Bus Idle
BUSSTAT.ENDF      2   End Of Frame Detected
BUSSTAT.EOD       1   End Of Data Detected
BUSSTAT.SOF       0   Start Of Frame Detected
ERRSTAT          0xEB22   SDLM Error Status Register                     
ERRSTAT.CRCER     4   CRC Error
ERRSTAT.COL       3   Collision Detected (lost arbitration)
ERRSTAT.SHORTH    2   Bus Shorted High
ERRSTAT.SHORTL    1   Bus Shorted Low
ERRSTAT.FORMAT    0   Format Error
BUFFCON          0xEB24   SDLM Buffer Control Register                   
BUFFCON.RXINCE    7   Receive Buffer Increment Enable
BUFFCON.TXINCE    6   Transmit Buffer Increment Enable
BUFFCON.IFREN     5   In-Frame Response Enable
BUFFCON.CRCEN     4   CRC Enable
BUFFCON.SBRK      3   Send Break
BUFFCON.DONE      2   Receive Buffer on CPU Side Read Out Done
BUFFCON.TXRQ      1   Transmit Request
BUFFCON.TXIFR     0   Transmit In-Frame Response
FLAGRST          0xEB28   SDLM Flag Reset Register                       
FLAGRST.ERRST     5   Reset Error
FLAGRST.BUSRST    4   Reset Bus Status
FLAGRST.RXRST     3   Reset Buffer Status
FLAGRST.TXRST     2   Reset Buffer Status
FLAGRST.ARLRST    1   Reset Buffer Status
FLAGRST.BRKRST    0   Reset Buffer Status
INTCON           0xEB2C   SDLM Interrupt Control Register                
INTCON.ERRIE      7   Enable Error Interrupt
INTCON.CRCIE      6   Enable CRC Error Interrupt
INTCON.ARLIE      5   Enable Arbitration Lost Interrupt
INTCON.BRKIE      4   Enable Break Received Interrupt
INTCON.ENDFIE     3   Enable End of Frame Detection
INTCON.HDIE       2   Enable Header Received Interrupt
INTCON.RECIE      1   Enable Receive Interrupt
INTCON.TRAIE      0   Enable Transmit Interrupt
TXD0             0xEB30   SDLM Transmit Data Register 0 
TXD0.TXDATA1_15   15  Transmit Buffer Data Byte 1 - bit 15
TXD0.TXDATA1_14   14  Transmit Buffer Data Byte 1 - bit 14
TXD0.TXDATA1_13   13  Transmit Buffer Data Byte 1 - bit 13
TXD0.TXDATA1_12   12  Transmit Buffer Data Byte 1 - bit 12
TXD0.TXDATA1_11   11  Transmit Buffer Data Byte 1 - bit 11
TXD0.TXDATA1_10   10  Transmit Buffer Data Byte 1 - bit 10
TXD0.TXDATA1_9    9   Transmit Buffer Data Byte 1 - bit 9 
TXD0.TXDATA1_8    8   Transmit Buffer Data Byte 1 - bit 8 
TXD0.TXDATA0_7    7   Transmit Buffer Data Byte 0 - bit 7 
TXD0.TXDATA0_6    6   Transmit Buffer Data Byte 0 - bit 6 
TXD0.TXDATA0_5    5   Transmit Buffer Data Byte 0 - bit 5 
TXD0.TXDATA0_4    4   Transmit Buffer Data Byte 0 - bit 4 
TXD0.TXDATA0_3    3   Transmit Buffer Data Byte 0 - bit 3 
TXD0.TXDATA0_2    2   Transmit Buffer Data Byte 0 - bit 2 
TXD0.TXDATA0_1    1   Transmit Buffer Data Byte 0 - bit 1 
TXD0.TXDATA0_0    0   Transmit Buffer Data Byte 0 - bit 0 
TXD2             0xEB32   SDLM Transmit Data Register 2 
TXD2.TXDATA3_15   15  Transmit Buffer Data Byte 3 - bit 15
TXD2.TXDATA3_14   14  Transmit Buffer Data Byte 3 - bit 14
TXD2.TXDATA3_13   13  Transmit Buffer Data Byte 3 - bit 13
TXD2.TXDATA3_12   12  Transmit Buffer Data Byte 3 - bit 12
TXD2.TXDATA3_11   11  Transmit Buffer Data Byte 3 - bit 11
TXD2.TXDATA3_10   10  Transmit Buffer Data Byte 3 - bit 10
TXD2.TXDATA3_9    9   Transmit Buffer Data Byte 3 - bit 9 
TXD2.TXDATA3_8    8   Transmit Buffer Data Byte 3 - bit 8 
TXD2.TXDATA2_7    7   Transmit Buffer Data Byte 2 - bit 7 
TXD2.TXDATA2_6    6   Transmit Buffer Data Byte 2 - bit 6 
TXD2.TXDATA2_5    5   Transmit Buffer Data Byte 2 - bit 5 
TXD2.TXDATA2_4    4   Transmit Buffer Data Byte 2 - bit 4 
TXD2.TXDATA2_3    3   Transmit Buffer Data Byte 2 - bit 3 
TXD2.TXDATA2_2    2   Transmit Buffer Data Byte 2 - bit 2 
TXD2.TXDATA2_1    1   Transmit Buffer Data Byte 2 - bit 1 
TXD2.TXDATA2_0    0   Transmit Buffer Data Byte 2 - bit 0 
TXD4             0xEB34   SDLM Transmit Data Register 4 
TXD4.TXDATA5_15   15  Transmit Buffer Data Byte 5 - bit 15
TXD4.TXDATA5_14   14  Transmit Buffer Data Byte 5 - bit 14
TXD4.TXDATA5_13   13  Transmit Buffer Data Byte 5 - bit 13
TXD4.TXDATA5_12   12  Transmit Buffer Data Byte 5 - bit 12
TXD4.TXDATA5_11   11  Transmit Buffer Data Byte 5 - bit 11
TXD4.TXDATA5_10   10  Transmit Buffer Data Byte 5 - bit 10
TXD4.TXDATA5_9    9   Transmit Buffer Data Byte 5 - bit 9 
TXD4.TXDATA5_8    8   Transmit Buffer Data Byte 5 - bit 8 
TXD4.TXDATA4_7    7   Transmit Buffer Data Byte 4 - bit 7 
TXD4.TXDATA4_6    6   Transmit Buffer Data Byte 4 - bit 6 
TXD4.TXDATA4_5    5   Transmit Buffer Data Byte 4 - bit 5 
TXD4.TXDATA4_4    4   Transmit Buffer Data Byte 4 - bit 4 
TXD4.TXDATA4_3    3   Transmit Buffer Data Byte 4 - bit 3 
TXD4.TXDATA4_2    2   Transmit Buffer Data Byte 4 - bit 2 
TXD4.TXDATA4_1    1   Transmit Buffer Data Byte 4 - bit 1 
TXD4.TXDATA4_0    0   Transmit Buffer Data Byte 4 - bit 0 
TXD6             0xEB36   SDLM Transmit Data Register 6 
TXD6.TXDATA7_15   15  Transmit Buffer Data Byte 7 - bit 15
TXD6.TXDATA7_14   14  Transmit Buffer Data Byte 7 - bit 14
TXD6.TXDATA7_13   13  Transmit Buffer Data Byte 7 - bit 13
TXD6.TXDATA7_12   12  Transmit Buffer Data Byte 7 - bit 12
TXD6.TXDATA7_11   11  Transmit Buffer Data Byte 7 - bit 11
TXD6.TXDATA7_10   10  Transmit Buffer Data Byte 7 - bit 10
TXD6.TXDATA7_9    9   Transmit Buffer Data Byte 7 - bit 9 
TXD6.TXDATA7_8    8   Transmit Buffer Data Byte 7 - bit 8 
TXD6.TXDATA6_7    7   Transmit Buffer Data Byte 6 - bit 7 
TXD6.TXDATA6_6    6   Transmit Buffer Data Byte 6 - bit 6 
TXD6.TXDATA6_5    5   Transmit Buffer Data Byte 6 - bit 5 
TXD6.TXDATA6_4    4   Transmit Buffer Data Byte 6 - bit 4 
TXD6.TXDATA6_3    3   Transmit Buffer Data Byte 6 - bit 3 
TXD6.TXDATA6_2    2   Transmit Buffer Data Byte 6 - bit 2 
TXD6.TXDATA6_1    1   Transmit Buffer Data Byte 6 - bit 1 
TXD6.TXDATA6_0    0   Transmit Buffer Data Byte 6 - bit 0 
TXD8             0xEB38   SDLM Transmit Data Register 8 
TXD8.TXDATA9_15   15  Transmit Buffer Data Byte 9 - bit 15
TXD8.TXDATA9_14   14  Transmit Buffer Data Byte 9 - bit 14
TXD8.TXDATA9_13   13  Transmit Buffer Data Byte 9 - bit 13
TXD8.TXDATA9_12   12  Transmit Buffer Data Byte 9 - bit 12
TXD8.TXDATA9_11   11  Transmit Buffer Data Byte 9 - bit 11
TXD8.TXDATA9_10   10  Transmit Buffer Data Byte 9 - bit 10
TXD8.TXDATA9_9    9   Transmit Buffer Data Byte 9 - bit 9 
TXD8.TXDATA9_8    8   Transmit Buffer Data Byte 9 - bit 8 
TXD8.TXDATA8_7    7   Transmit Buffer Data Byte 8 - bit 7 
TXD8.TXDATA8_6    6   Transmit Buffer Data Byte 8 - bit 6 
TXD8.TXDATA8_5    5   Transmit Buffer Data Byte 8 - bit 5 
TXD8.TXDATA8_4    4   Transmit Buffer Data Byte 8 - bit 4 
TXD8.TXDATA8_3    3   Transmit Buffer Data Byte 8 - bit 3 
TXD8.TXDATA8_2    2   Transmit Buffer Data Byte 8 - bit 2 
TXD8.TXDATA8_1    1   Transmit Buffer Data Byte 8 - bit 1 
TXD8.TXDATA8_0    0   Transmit Buffer Data Byte 8 - bit 0 
TXD10            0xEB3A   SDLM Transmit Data Register 10
TXD10.TXDATA10_7  7   Transmit Buffer Data Byte 10 - bit 7 
TXD10.TXDATA10_6  6   Transmit Buffer Data Byte 10 - bit 6 
TXD10.TXDATA10_5  5   Transmit Buffer Data Byte 10 - bit 5 
TXD10.TXDATA10_4  4   Transmit Buffer Data Byte 10 - bit 4 
TXD10.TXDATA10_3  3   Transmit Buffer Data Byte 10 - bit 3 
TXD10.TXDATA10_2  2   Transmit Buffer Data Byte 10 - bit 2 
TXD10.TXDATA10_1  1   Transmit Buffer Data Byte 10 - bit 1 
TXD10.TXDATA10_0  0   Transmit Buffer Data Byte 10 - bit 0 
TXCNT            0xEB3C   SDLM Bus Transmit Byte Counter                 
TXCNT.TxCNT_3     3   Bus Transmit Byte Counter bit - 3
TXCNT.TxCNT_2     2   Bus Transmit Byte Counter bit - 2
TXCNT.TxCNT_1     1   Bus Transmit Byte Counter bit - 1
TXCNT.TxCNT_0     0   Bus Transmit Byte Counter bit - 0
TXCPU            0xEB3E   SDLM CPU Transmit Byte Counter                 
TXCPU.TxCPU_3     3   CPU Transmit Byte Counter bit - 3
TXCPU.TxCPU_2     2   CPU Transmit Byte Counter bit - 2
TXCPU.TxCPU_1     1   CPU Transmit Byte Counter bit - 1
TXCPU.TxCPU_0     0   CPU Transmit Byte Counter bit - 0
RXD00            0xEB40   SDLM Receive Data Register 0
RXD00.RXDATA01_15 15  Receive Buffer 0 Data Byte 1 - bit 15
RXD00.RXDATA01_14 14  Receive Buffer 0 Data Byte 1 - bit 14
RXD00.RXDATA01_13 13  Receive Buffer 0 Data Byte 1 - bit 13
RXD00.RXDATA01_12 12  Receive Buffer 0 Data Byte 1 - bit 12
RXD00.RXDATA01_11 11  Receive Buffer 0 Data Byte 1 - bit 11
RXD00.RXDATA01_10 10  Receive Buffer 0 Data Byte 1 - bit 10
RXD00.RXDATA01_9  9   Receive Buffer 0 Data Byte 1 - bit 9 
RXD00.RXDATA01_8  8   Receive Buffer 0 Data Byte 1 - bit 8 
RXD00.RXDATA00_7  7   Receive Buffer 0 Data Byte 0 - bit 7 
RXD00.RXDATA00_6  6   Receive Buffer 0 Data Byte 0 - bit 6 
RXD00.RXDATA00_5  5   Receive Buffer 0 Data Byte 0 - bit 5 
RXD00.RXDATA00_4  4   Receive Buffer 0 Data Byte 0 - bit 4 
RXD00.RXDATA00_3  3   Receive Buffer 0 Data Byte 0 - bit 3 
RXD00.RXDATA00_2  2   Receive Buffer 0 Data Byte 0 - bit 2 
RXD00.RXDATA00_1  1   Receive Buffer 0 Data Byte 0 - bit 1 
RXD00.RXDATA00_0  0   Receive Buffer 0 Data Byte 0 - bit 0 
RXD02            0xEB42   SDLM Receive Data Register 2
RXD02.RXDATA03_15 15  Receive Buffer 0 Data Byte 3 - bit 15
RXD02.RXDATA03_14 14  Receive Buffer 0 Data Byte 3 - bit 14
RXD02.RXDATA03_13 13  Receive Buffer 0 Data Byte 3 - bit 13
RXD02.RXDATA03_12 12  Receive Buffer 0 Data Byte 3 - bit 12
RXD02.RXDATA03_11 11  Receive Buffer 0 Data Byte 3 - bit 11
RXD02.RXDATA03_10 10  Receive Buffer 0 Data Byte 3 - bit 10
RXD02.RXDATA03_9  9   Receive Buffer 0 Data Byte 3 - bit 9 
RXD02.RXDATA03_8  8   Receive Buffer 0 Data Byte 3 - bit 8 
RXD02.RXDATA02_7  7   Receive Buffer 0 Data Byte 2 - bit 7 
RXD02.RXDATA02_6  6   Receive Buffer 0 Data Byte 2 - bit 6 
RXD02.RXDATA02_5  5   Receive Buffer 0 Data Byte 2 - bit 5 
RXD02.RXDATA02_4  4   Receive Buffer 0 Data Byte 2 - bit 4 
RXD02.RXDATA02_3  3   Receive Buffer 0 Data Byte 2 - bit 3 
RXD02.RXDATA02_2  2   Receive Buffer 0 Data Byte 2 - bit 2 
RXD02.RXDATA02_1  1   Receive Buffer 0 Data Byte 2 - bit 1 
RXD02.RXDATA02_0  0   Receive Buffer 0 Data Byte 2 - bit 0 
RXD04            0xEB44   SDLM Receive Data Register 4
RXD04.RXDATA05_15 15  Receive Buffer 0 Data Byte 5 - bit 15
RXD04.RXDATA05_14 14  Receive Buffer 0 Data Byte 5 - bit 14
RXD04.RXDATA05_13 13  Receive Buffer 0 Data Byte 5 - bit 13
RXD04.RXDATA05_12 12  Receive Buffer 0 Data Byte 5 - bit 12
RXD04.RXDATA05_11 11  Receive Buffer 0 Data Byte 5 - bit 11
RXD04.RXDATA05_10 10  Receive Buffer 0 Data Byte 5 - bit 10
RXD04.RXDATA05_9  9   Receive Buffer 0 Data Byte 5 - bit 9 
RXD04.RXDATA05_8  8   Receive Buffer 0 Data Byte 5 - bit 8 
RXD04.RXDATA04_7  7   Receive Buffer 0 Data Byte 4 - bit 7 
RXD04.RXDATA04_6  6   Receive Buffer 0 Data Byte 4 - bit 6 
RXD04.RXDATA04_5  5   Receive Buffer 0 Data Byte 4 - bit 5 
RXD04.RXDATA04_4  4   Receive Buffer 0 Data Byte 4 - bit 4 
RXD04.RXDATA04_3  3   Receive Buffer 0 Data Byte 4 - bit 3 
RXD04.RXDATA04_2  2   Receive Buffer 0 Data Byte 4 - bit 2 
RXD04.RXDATA04_1  1   Receive Buffer 0 Data Byte 4 - bit 1 
RXD04.RXDATA04_0  0   Receive Buffer 0 Data Byte 4 - bit 0 
RXD06            0xEB46   SDLM Receive Data Register 6
RXD06.RXDATA07_15 15  Receive Buffer 0 Data Byte 7 - bit 15
RXD06.RXDATA07_14 14  Receive Buffer 0 Data Byte 7 - bit 14
RXD06.RXDATA07_13 13  Receive Buffer 0 Data Byte 7 - bit 13
RXD06.RXDATA07_12 12  Receive Buffer 0 Data Byte 7 - bit 12
RXD06.RXDATA07_11 11  Receive Buffer 0 Data Byte 7 - bit 11
RXD06.RXDATA07_10 10  Receive Buffer 0 Data Byte 7 - bit 10
RXD06.RXDATA07_9  9   Receive Buffer 0 Data Byte 7 - bit 9 
RXD06.RXDATA07_8  8   Receive Buffer 0 Data Byte 7 - bit 8 
RXD06.RXDATA06_7  7   Receive Buffer 0 Data Byte 6 - bit 7 
RXD06.RXDATA06_6  6   Receive Buffer 0 Data Byte 6 - bit 6 
RXD06.RXDATA06_5  5   Receive Buffer 0 Data Byte 6 - bit 5 
RXD06.RXDATA06_4  4   Receive Buffer 0 Data Byte 6 - bit 4 
RXD06.RXDATA06_3  3   Receive Buffer 0 Data Byte 6 - bit 3 
RXD06.RXDATA06_2  2   Receive Buffer 0 Data Byte 6 - bit 2 
RXD06.RXDATA06_1  1   Receive Buffer 0 Data Byte 6 - bit 1 
RXD06.RXDATA06_0  0   Receive Buffer 0 Data Byte 6 - bit 0 
RXD08            0xEB48   SDLM Receive Data Register 8
RXD08.RXDATA09_15 15  Receive Buffer 0 Data Byte 9 - bit 15
RXD08.RXDATA09_14 14  Receive Buffer 0 Data Byte 9 - bit 14
RXD08.RXDATA09_13 13  Receive Buffer 0 Data Byte 9 - bit 13
RXD08.RXDATA09_12 12  Receive Buffer 0 Data Byte 9 - bit 12
RXD08.RXDATA09_11 11  Receive Buffer 0 Data Byte 9 - bit 11
RXD08.RXDATA09_10 10  Receive Buffer 0 Data Byte 9 - bit 10
RXD08.RXDATA09_9  9   Receive Buffer 0 Data Byte 9 - bit 9 
RXD08.RXDATA09_8  8   Receive Buffer 0 Data Byte 9 - bit 8 
RXD08.RXDATA08_7  7   Receive Buffer 0 Data Byte 8 - bit 7 
RXD08.RXDATA08_6  6   Receive Buffer 0 Data Byte 8 - bit 6 
RXD08.RXDATA08_5  5   Receive Buffer 0 Data Byte 8 - bit 5 
RXD08.RXDATA08_4  4   Receive Buffer 0 Data Byte 8 - bit 4 
RXD08.RXDATA08_3  3   Receive Buffer 0 Data Byte 8 - bit 3 
RXD08.RXDATA08_2  2   Receive Buffer 0 Data Byte 8 - bit 2 
RXD08.RXDATA08_1  1   Receive Buffer 0 Data Byte 8 - bit 1 
RXD08.RXDATA08_0  0   Receive Buffer 0 Data Byte 8 - bit 0 
RXD010           0xEB4A   SDLM Receive Data Register 10
RXD010.RXDATA010_7  7 Receive Buffer 0 Data Byte 10 - bit 7 
RXD010.RXDATA010_6  6 Receive Buffer 0 Data Byte 10 - bit 6 
RXD010.RXDATA010_5  5 Receive Buffer 0 Data Byte 10 - bit 5 
RXD010.RXDATA010_4  4 Receive Buffer 0 Data Byte 10 - bit 4 
RXD010.RXDATA010_3  3 Receive Buffer 0 Data Byte 10 - bit 3 
RXD010.RXDATA010_2  2 Receive Buffer 0 Data Byte 10 - bit 2 
RXD010.RXDATA010_1  1 Receive Buffer 0 Data Byte 10 - bit 1 
RXD010.RXDATA010_0  0 Receive Buffer 0 Data Byte 10 - bit 0 
RXCNT            0xEB4C   SDLM Bus Receive Byte Counter (CPU)            
RXCNT.RxCNT_3     3   Receive Byte Count - bit 3
RXCNT.RxCNT_2     2   Receive Byte Count - bit 2
RXCNT.RxCNT_1     1   Receive Byte Count - bit 1
RXCNT.RxCNT_0     0   Receive Byte Count - bit 0
RXCPU            0xEB4E   SDLM CPU Receive Byte Counter (CPU)            
RXCPU.RxCPU_3     3   CPU Receive Byte Count - bit 3
RXCPU.RxCPU_2     2   CPU Receive Byte Count - bit 2
RXCPU.RxCPU_1     1   CPU Receive Byte Count - bit 1
RXCPU.RxCPU_0     0   CPU Receive Byte Count - bit 0
RXD10            0xEB50   Receive Data Register 10 (bus)
RXD10.RXDATA11_15 15  Receive Buffer 1 Data Byte 1 - bit 15
RXD10.RXDATA11_14 14  Receive Buffer 1 Data Byte 1 - bit 14
RXD10.RXDATA11_13 13  Receive Buffer 1 Data Byte 1 - bit 13
RXD10.RXDATA11_12 12  Receive Buffer 1 Data Byte 1 - bit 12
RXD10.RXDATA11_11 11  Receive Buffer 1 Data Byte 1 - bit 11
RXD10.RXDATA11_10 10  Receive Buffer 1 Data Byte 1 - bit 10
RXD10.RXDATA11_9  9   Receive Buffer 1 Data Byte 1 - bit 9 
RXD10.RXDATA11_8  8   Receive Buffer 1 Data Byte 1 - bit 8 
RXD10.RXDATA10_7  7   Receive Buffer 1 Data Byte 0 - bit 7 
RXD10.RXDATA10_6  6   Receive Buffer 1 Data Byte 0 - bit 6 
RXD10.RXDATA10_5  5   Receive Buffer 1 Data Byte 0 - bit 5 
RXD10.RXDATA10_4  4   Receive Buffer 1 Data Byte 0 - bit 4 
RXD10.RXDATA10_3  3   Receive Buffer 1 Data Byte 0 - bit 3 
RXD10.RXDATA10_2  2   Receive Buffer 1 Data Byte 0 - bit 2 
RXD10.RXDATA10_1  1   Receive Buffer 1 Data Byte 0 - bit 1 
RXD10.RXDATA10_0  0   Receive Buffer 1 Data Byte 0 - bit 0 
RXD12            0xEB52   Receive Data Register 12 (bus)
RXD12.RXDATA13_15 15  Receive Buffer 1 Data Byte 3 - bit 15
RXD12.RXDATA13_14 14  Receive Buffer 1 Data Byte 3 - bit 14
RXD12.RXDATA13_13 13  Receive Buffer 1 Data Byte 3 - bit 13
RXD12.RXDATA13_12 12  Receive Buffer 1 Data Byte 3 - bit 12
RXD12.RXDATA13_11 11  Receive Buffer 1 Data Byte 3 - bit 11
RXD12.RXDATA13_10 10  Receive Buffer 1 Data Byte 3 - bit 10
RXD12.RXDATA13_9  9   Receive Buffer 1 Data Byte 3 - bit 9 
RXD12.RXDATA12_8  8   Receive Buffer 1 Data Byte 2 - bit 8 
RXD12.RXDATA12_7  7   Receive Buffer 1 Data Byte 2 - bit 7 
RXD12.RXDATA12_6  6   Receive Buffer 1 Data Byte 2 - bit 6 
RXD12.RXDATA12_5  5   Receive Buffer 1 Data Byte 2 - bit 5 
RXD12.RXDATA12_4  4   Receive Buffer 1 Data Byte 2 - bit 4 
RXD12.RXDATA12_3  3   Receive Buffer 1 Data Byte 2 - bit 3 
RXD12.RXDATA12_2  2   Receive Buffer 1 Data Byte 2 - bit 2 
RXD12.RXDATA12_1  1   Receive Buffer 1 Data Byte 2 - bit 1 
RXD12.RXDATA12_0  0   Receive Buffer 1 Data Byte 2 - bit 0 
RXD14            0xEB54   Receive Data Register 14 (bus)
RXD14.RXDATA15_15 15  Receive Buffer 1 Data Byte 5 - bit 15
RXD14.RXDATA15_14 14  Receive Buffer 1 Data Byte 5 - bit 14
RXD14.RXDATA15_13 13  Receive Buffer 1 Data Byte 5 - bit 13
RXD14.RXDATA15_12 12  Receive Buffer 1 Data Byte 5 - bit 12
RXD14.RXDATA15_11 11  Receive Buffer 1 Data Byte 5 - bit 11
RXD14.RXDATA15_10 10  Receive Buffer 1 Data Byte 5 - bit 10
RXD14.RXDATA15_9  9   Receive Buffer 1 Data Byte 5 - bit 9 
RXD14.RXDATA15_8  8   Receive Buffer 1 Data Byte 5 - bit 8 
RXD14.RXDATA14_7  7   Receive Buffer 1 Data Byte 4 - bit 7 
RXD14.RXDATA14_6  6   Receive Buffer 1 Data Byte 4 - bit 6 
RXD14.RXDATA14_5  5   Receive Buffer 1 Data Byte 4 - bit 5 
RXD14.RXDATA14_4  4   Receive Buffer 1 Data Byte 4 - bit 4 
RXD14.RXDATA14_3  3   Receive Buffer 1 Data Byte 4 - bit 3 
RXD14.RXDATA14_2  2   Receive Buffer 1 Data Byte 4 - bit 2 
RXD14.RXDATA14_1  1   Receive Buffer 1 Data Byte 4 - bit 1 
RXD14.RXDATA14_0  0   Receive Buffer 1 Data Byte 4 - bit 0 
RXD16            0xEB56   Receive Data Register 16 (bus)
RXD16.RXDATA17_15 15  Receive Buffer 1 Data Byte 7 - bit 15
RXD16.RXDATA17_14 14  Receive Buffer 1 Data Byte 7 - bit 14
RXD16.RXDATA17_13 13  Receive Buffer 1 Data Byte 7 - bit 13
RXD16.RXDATA17_12 12  Receive Buffer 1 Data Byte 7 - bit 12
RXD16.RXDATA17_11 11  Receive Buffer 1 Data Byte 7 - bit 11
RXD16.RXDATA17_10 10  Receive Buffer 1 Data Byte 7 - bit 10
RXD16.RXDATA17_9  9   Receive Buffer 1 Data Byte 7 - bit 9 
RXD16.RXDATA17_8  8   Receive Buffer 1 Data Byte 7 - bit 8 
RXD16.RXDATA16_7  7   Receive Buffer 1 Data Byte 6 - bit 7 
RXD16.RXDATA16_6  6   Receive Buffer 1 Data Byte 6 - bit 6 
RXD16.RXDATA16_5  5   Receive Buffer 1 Data Byte 6 - bit 5 
RXD16.RXDATA16_4  4   Receive Buffer 1 Data Byte 6 - bit 4 
RXD16.RXDATA16_3  3   Receive Buffer 1 Data Byte 6 - bit 3 
RXD16.RXDATA16_2  2   Receive Buffer 1 Data Byte 6 - bit 2 
RXD16.RXDATA16_1  1   Receive Buffer 1 Data Byte 6 - bit 1 
RXD16.RXDATA16_0  0   Receive Buffer 1 Data Byte 6 - bit 0 
RXD18            0xEB58   Receive Data Register 18 (bus)
RXD18.RXDATA19_15 15  Receive Buffer 1 Data Byte 9 - bit 15
RXD18.RXDATA19_14 14  Receive Buffer 1 Data Byte 9 - bit 14
RXD18.RXDATA19_13 13  Receive Buffer 1 Data Byte 9 - bit 13
RXD18.RXDATA19_12 12  Receive Buffer 1 Data Byte 9 - bit 12
RXD18.RXDATA19_11 11  Receive Buffer 1 Data Byte 9 - bit 11
RXD18.RXDATA19_10 10  Receive Buffer 1 Data Byte 9 - bit 10
RXD18.RXDATA19_9  9   Receive Buffer 1 Data Byte 9 - bit 9 
RXD18.RXDATA19_8  8   Receive Buffer 1 Data Byte 9 - bit 8 
RXD18.RXDATA18_7  7   Receive Buffer 1 Data Byte 8 - bit 7 
RXD18.RXDATA18_6  6   Receive Buffer 1 Data Byte 8 - bit 6 
RXD18.RXDATA18_5  5   Receive Buffer 1 Data Byte 8 - bit 5 
RXD18.RXDATA18_4  4   Receive Buffer 1 Data Byte 8 - bit 4 
RXD18.RXDATA18_3  3   Receive Buffer 1 Data Byte 8 - bit 3 
RXD18.RXDATA18_2  2   Receive Buffer 1 Data Byte 8 - bit 2 
RXD18.RXDATA18_1  1   Receive Buffer 1 Data Byte 8 - bit 1 
RXD18.RXDATA18_0  0   Receive Buffer 1 Data Byte 8 - bit 0 
RXD110           0xEB5A   Receive Data Register 110 (bus)
RXD110.RXDATA110_7  7 Receive Buffer 1 Data Byte 10 - bit 7 
RXD110.RXDATA110_6  6 Receive Buffer 1 Data Byte 10 - bit 6 
RXD110.RXDATA110_5  5 Receive Buffer 1 Data Byte 10 - bit 5 
RXD110.RXDATA110_4  4 Receive Buffer 1 Data Byte 10 - bit 4 
RXD110.RXDATA110_3  3 Receive Buffer 1 Data Byte 10 - bit 3 
RXD110.RXDATA110_2  2 Receive Buffer 1 Data Byte 10 - bit 2 
RXD110.RXDATA110_1  1 Receive Buffer 1 Data Byte 10 - bit 1 
RXD110.RXDATA110_0  0 Receive Buffer 1 Data Byte 10 - bit 0 
RXCNTB           0xEB5C   SDLM Bus Receive Byte Counter (Bus)            
RXCNTB.RxCNTB_3   3   Receive Byte Counter - bit 3
RXCNTB.RxCNTB_2   2   Receive Byte Counter - bit 2
RXCNTB.RxCNTB_1   1   Receive Byte Counter - bit 1
RXCNTB.RxCNTB_0   0   Receive Byte Counter - bit 0
SOFPTR           0xEB60   SDLM Start-of-frame Pointer Register           
SOFPTR.SOFCNT_3   3   Start-of-Frame Counter for Block Mode - bit 3
SOFPTR.SOFCNT_2   2   Start-of-Frame Counter for Block Mode - bit 2
SOFPTR.SOFCNT_1   1   Start-of-Frame Counter for Block Mode - bit 1
SOFPTR.SOFCNT_0   0   Start-of-Frame Counter for Block Mode - bit 0
ICCFG            0xED00   IIC Configuration Register                     
ICCFG.BRP_15      15  Baudrate Prescaler  - bit 15
ICCFG.BRP_14      14  Baudrate Prescaler  - bit 14
ICCFG.BRP_13      13  Baudrate Prescaler  - bit 13
ICCFG.BRP_12      12  Baudrate Prescaler  - bit 12
ICCFG.BRP_11      11  Baudrate Prescaler  - bit 11
ICCFG.BRP_10      10  Baudrate Prescaler  - bit 10
ICCFG.BRP_9       9   Baudrate Prescaler  - bit 9 
ICCFG.BRP_8       8   Baudrate Prescaler  - bit 8 
ICCFG.SCLSEL1     5   SCL Pin Selection 1
ICCFG.SCLSEL0     4   SCL Pin Selection 0
ICCFG.SDASEL2     2   SDA Pin Selection 2
ICCFG.SDASEL1     1   SDA Pin Selection 1
ICCFG.SDASEL0     0   SDA Pin Selection 0
ICCON            0xED02   IIC Control Register                           
ICCON.TRX         7   Transmit Select
ICCON.AIRDIS      6   Auto Interrupt Reset Disable
ICCON.ACKDIS      5   Acknowledge Pulse Disable
ICCON.BUM         4   Busy Master
ICCON.MOD_3       3   Basic Operating Mode - bit 3 
ICCON.MOD_2       2   Basic Operating Mode - bit 2 
ICCON.RSC         1   Repeated Start Condition
ICCON.M10         0   Address Mode
ICST             0xED04   IIC Status Register                            
ICST.IRQP         6  IIC Interrupt Request Bit for Protocol Events
ICST.IRQD         5  IIC Interrupt Request Bit for Data Transfer Events
ICST.BB           4  Bus Busy
ICST.LRB          3  Last Received Bit
ICST.SLA          2  Slave
ICST.AL           1  Arbitration Lost
ICST.ADR          0  Address
ICADR            0xED06   IIC Address Register                           
ICADR.ICA9        9
ICADR.ICA8        8
ICADR.ICA7        7
ICADR.ICA6        6
ICADR.ICA5        5
ICADR.ICA4        4
ICADR.ICA3        3
ICADR.ICA2        2
ICADR.ICA1        1
ICADR.ICA0        0
ICRTB            0xED08   IIC Receive/Transmit Buffer                    
ICRTB.ICData_7    7   Transmit and shift data - bit 7
ICRTB.ICData_6    6   Transmit and shift data - bit 6
ICRTB.ICData_5    5   Transmit and shift data - bit 5
ICRTB.ICData_4    4   Transmit and shift data - bit 4
ICRTB.ICData_3    3   Transmit and shift data - bit 3
ICRTB.ICData_2    2   Transmit and shift data - bit 2
ICRTB.ICData_1    1   Transmit and shift data - bit 1
ICRTB.ICData_0    0   Transmit and shift data - bit 0
S1TBUF           0xEDA0   Serial Channel 1 Transmit Buffer Register      
S1RBUF           0xEDA2   Serial Channel 1 Receive Buffer Register (read only)
S1BG             0xEDA4   Serial Channel 1 Baud Rate Generator Reload Register
S1CON            0xEDA6   Serial Channel 1 Control Register              
S1CON.S1R         15  Baudrate Generator Run Bit
S1CON.S1LB        14  LoopBack Mode Enable Bit
S1CON.S1BRS       13  Baudrate Selection Bit
S1CON.S1ODD       12  Parity Selection Bit
S1CON.S1OE        10  Overrun Error Flag
S1CON.S1FE        9   Framing Error Flag
S1CON.S1PE        8   Parity Error Flag
S1CON.S1OEN       7   Overrun Check Enable Bit
S1CON.S1FEN       6   Framing Check Enable Bit
S1CON.S1PEN       5   Parity Check Enable Bit
S1CON.S1REN       4   Receiver Enable Bit
S1CON.S1STP       3   Number of Stop Bits Selection
S1CON.S1M_2       2   ASC1 Mode Control - bit 2
S1CON.S1M_1       1   ASC1 Mode Control - bit 1
S1CON.S1M_0       0   ASC1 Mode Control - bit 0
C2CSR            0xEE00   CAN2 Control/Status Register                   
C2CSR.BOFF        15  Busoff Status
C2CSR.EWRN        14  Error Warning Status
C2CSR.RXOK        12  Received Message Successfully
C2CSR.TXOK        11  Transmitted Message Successfully
C2CSR.LEC_10      10  Last Error Code - bit 10
C2CSR.LEC_9       9   Last Error Code - bit 9 
C2CSR.LEC_8       8   Last Error Code - bit 8 
C2CSR.TM          7   Test Mode
C2CSR.CCE         6   Configuration Change Enable
C2CSR.CPS         4   Clock Prescaler Control Bit
C2CSR.EIE         3   Error Interrupt Enable
C2CSR.SIE         2   Status Change Interrupt Enable
C2CSR.IE          1   Interrupt Enable
C2CSR.INIT        0   Initialization
C2PCIR           0xEE02   CAN2Port Control and Interrupt Register        
C2PCIR.IPC_10     10  Interface Port Control - bit 10
C2PCIR.IPC_9      9   Interface Port Control - bit 9 
C2PCIR.IPC_8      8   Interface Port Control - bit 8 
C2PCIR.INTID_7    7   Interrupt Identifier - bit 7
C2PCIR.INTID_6    6   Interrupt Identifier - bit 6
C2PCIR.INTID_5    5   Interrupt Identifier - bit 5
C2PCIR.INTID_4    4   Interrupt Identifier - bit 4
C2PCIR.INTID_3    3   Interrupt Identifier - bit 3
C2PCIR.INTID_2    2   Interrupt Identifier - bit 2
C2PCIR.INTID_1    1   Interrupt Identifier - bit 1
C2PCIR.INTID_0    0   Interrupt Identifier - bit 0
C2BTR            0xEE04   CAN2 Bit Timing Register                       
C2BTR.TSEG2_14    14  Time Segment after sample point - bit 14
C2BTR.TSEG2_13    13  Time Segment after sample point - bit 13
C2BTR.TSEG2_12    12  Time Segment after sample point - bit 12
C2BTR.TSEG1_11    11  Time Segment before sample point - bit 11
C2BTR.TSEG1_10    10  Time Segment before sample point - bit 10
C2BTR.TSEG1_9     9   Time Segment before sample point - bit 9 
C2BTR.TSEG1_8     8   Time Segment before sample point - bit 8 
C2BTR.SJW_7       7   (Re)Synchronization Jump Width - bit 7
C2BTR.SJW_6       6   (Re)Synchronization Jump Width - bit 6
C2BTR.BRP_5       5   Baud Rate Prescaler - bit 5
C2BTR.BRP_4       4   Baud Rate Prescaler - bit 4
C2BTR.BRP_3       3   Baud Rate Prescaler - bit 3
C2BTR.BRP_2       2   Baud Rate Prescaler - bit 2
C2BTR.BRP_1       1   Baud Rate Prescaler - bit 1
C2BTR.BRP_0       0   Baud Rate Prescaler - bit 0
C2GMS            0xEE06   CAN2 Global Mask Short                         
C2GMS.ID20        15  Identifier 20
C2GMS.ID19        14  Identifier 19
C2GMS.ID18        13  Identifier 18
C2GMS.ID28        7   Identifier 28
C2GMS.ID27        6   Identifier 27
C2GMS.ID26        5   Identifier 26
C2GMS.ID25        4   Identifier 25
C2GMS.ID24        3   Identifier 24
C2GMS.ID23        2   Identifier 23
C2GMS.ID22        1   Identifier 22
C2GMS.ID21        0   Identifier 21
C2UGML           0xEE08   CAN2 Upper Global Mask Long                    
C2UGML.ID20       15  Identifier 20
C2UGML.ID19       14  Identifier 19
C2UGML.ID18       13  Identifier 18
C2UGML.ID17       12  Identifier 17
C2UGML.ID16       11  Identifier 16
C2UGML.ID15       10  Identifier 15
C2UGML.ID14       9   Identifier 14
C2UGML.ID13       8   Identifier 13
C2UGML.ID28       7   Identifier 28
C2UGML.ID27       6   Identifier 27
C2UGML.ID26       5   Identifier 26
C2UGML.ID25       4   Identifier 25
C2UGML.ID24       3   Identifier 24
C2UGML.ID23       2   Identifier 23
C2UGML.ID22       1   Identifier 22
C2UGML.ID21       0   Identifier 21
C2LGML           0xEE0A   CAN2 Lower Global Mask Long                    
C2LGML.ID4        15  Identifier 4 
C2LGML.ID3        14  Identifier 3 
C2LGML.ID2        13  Identifier 2 
C2LGML.ID1        12  Identifier 1 
C2LGML.ID0        11  Identifier 0 
C2LGML.ID12       7   Identifier 12
C2LGML.ID11       6   Identifier 11
C2LGML.ID10       5   Identifier 10
C2LGML.ID9        4   Identifier 9 
C2LGML.ID8        3   Identifier 8 
C2LGML.ID7        2   Identifier 7 
C2LGML.ID6        1   Identifier 6 
C2LGML.ID5        0   Identifier 5 
C2UMLM           0xEE0C   CAN2 Upper Mask of Last Message                
C2UMLM.ID20       15  Identifier 20
C2UMLM.ID19       14  Identifier 19
C2UMLM.ID18       13  Identifier 18
C2UMLM.ID17       12  Identifier 17
C2UMLM.ID16       11  Identifier 16
C2UMLM.ID15       10  Identifier 15
C2UMLM.ID14       9   Identifier 14
C2UMLM.ID13       8   Identifier 13
C2UMLM.ID28       7   Identifier 28
C2UMLM.ID27       6   Identifier 27
C2UMLM.ID26       5   Identifier 26
C2UMLM.ID25       4   Identifier 25
C2UMLM.ID24       3   Identifier 24
C2UMLM.ID23       2   Identifier 23
C2UMLM.ID22       1   Identifier 22
C2UMLM.ID21       0   Identifier 21
C2LMLM           0xEE0E   CAN2 Lower Mask of Last Message                
C2LMLM.ID4        15  Identifier 4 
C2LMLM.ID3        14  Identifier 3 
C2LMLM.ID2        13  Identifier 2 
C2LMLM.ID1        12  Identifier 1 
C2LMLM.ID0        11  Identifier 0 
C2LMLM.ID12       7   Identifier 12
C2LMLM.ID11       6   Identifier 11
C2LMLM.ID10       5   Identifier 10
C2LMLM.ID9        4   Identifier 9 
C2LMLM.ID8        3   Identifier 8 
C2LMLM.ID7        2   Identifier 7 
C2LMLM.ID6        1   Identifier 6 
C2LMLM.ID5        0   Identifier 5 
C2MCR1           0xEE11   CAN2 Message Ctrl. Reg. (msg. )
C2MCR1.RMTPND_15        15  Remote Pending - bit 15
C2MCR1.RMTPND_14        14  Remote Pending - bit 14
C2MCR1.TXRQ_13          13  Transmit Request - bit 13
C2MCR1.TXRQ_12          12  Transmit Request - bit 12
C2MCR1.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C2MCR1.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C2MCR1.NEWDAT_9         9   New Data - bit 9
C2MCR1.NEWDAT_8         8   New Data - bit 8
C2MCR1.MSGVAL_7         7   Message Valid - bit 7
C2MCR1.MSGVAL_6         6   Message Valid - bit 6
C2MCR1.TXIE_5           5   Transmit Interrupt Enable - bit 5
C2MCR1.TXIE_4           4   Transmit Interrupt Enable - bit 4
C2MCR1.RXIE_3           3   Receive Interrupt Enable - bit 3
C2MCR1.RXIE_2           2   Receive Interrupt Enable - bit 2
C2MCR1.INTPND_1         1   Interrupt Pending - bit 1
C2MCR1.INTPND_0         0   Interrupt Pending - bit 0
C2UAR1           0xEE12   CAN2 Upper Arbitration Reg. (msg. )           
C2UAR1.ID20       15  Identifier 20
C2UAR1.ID19       14  Identifier 19
C2UAR1.ID18       13  Identifier 18
C2UAR1.ID17       12  Identifier 17
C2UAR1.ID16       11  Identifier 16
C2UAR1.ID15       10  Identifier 15
C2UAR1.ID14       9   Identifier 14
C2UAR1.ID13       8   Identifier 13
C2UAR1.ID28       7   Identifier 28
C2UAR1.ID27       6   Identifier 27
C2UAR1.ID26       5   Identifier 26
C2UAR1.ID25       4   Identifier 25
C2UAR1.ID24       3   Identifier 24
C2UAR1.ID23       2   Identifier 23
C2UAR1.ID22       1   Identifier 22
C2UAR1.ID21       0   Identifier 21
C2LAR1           0xEE14   CAN2 Lower Arbitration Register (msg. )       
C2LAR1.ID4        15  Identifier 4 
C2LAR1.ID3        14  Identifier 3 
C2LAR1.ID2        13  Identifier 2 
C2LAR1.ID1        12  Identifier 1 
C2LAR1.ID0        11  Identifier 0 
C2LAR1.ID12       7   Identifier 12
C2LAR1.ID11       6   Identifier 11
C2LAR1.ID10       5   Identifier 10
C2LAR1.ID9        4   Identifier 9 
C2LAR1.ID8        3   Identifier 8 
C2LAR1.ID7        2   Identifier 7 
C2LAR1.ID6        1   Identifier 6 
C2LAR1.ID5        0   Identifier 5 
C2MCFG1          0xEE16   CAN2 Message Configuration Register (msg. )
C2MCFG1.DLC_7     7   Data Length Code - bit 7
C2MCFG1.DLC_6     6   Data Length Code - bit 6
C2MCFG1.DLC_5     5   Data Length Code - bit 5
C2MCFG1.DLC_4     4   Data Length Code - bit 4
C2MCFG1.DIR       3   Message Direction
C2MCFG1.XTD       2   Extended Identifier
C2MCR2           0xEE21   CAN2 Message Ctrl. Reg. (msg. )
C2MCR2.RMTPND_15        15  Remote Pending - bit 15
C2MCR2.RMTPND_14        14  Remote Pending - bit 14
C2MCR2.TXRQ_13          13  Transmit Request - bit 13
C2MCR2.TXRQ_12          12  Transmit Request - bit 12
C2MCR2.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C2MCR2.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C2MCR2.NEWDAT_9         9   New Data - bit 9
C2MCR2.NEWDAT_8         8   New Data - bit 8
C2MCR2.MSGVAL_7         7   Message Valid - bit 7
C2MCR2.MSGVAL_6         6   Message Valid - bit 6
C2MCR2.TXIE_5           5   Transmit Interrupt Enable - bit 5
C2MCR2.TXIE_4           4   Transmit Interrupt Enable - bit 4
C2MCR2.RXIE_3           3   Receive Interrupt Enable - bit 3
C2MCR2.RXIE_2           2   Receive Interrupt Enable - bit 2
C2MCR2.INTPND_1         1   Interrupt Pending - bit 1
C2MCR2.INTPND_0         0   Interrupt Pending - bit 0
C2UAR2           0xEE22   CAN2 Upper Arbitration Reg. (msg. )           
C2UAR2.ID20       15  Identifier 20
C2UAR2.ID19       14  Identifier 19
C2UAR2.ID18       13  Identifier 18
C2UAR2.ID17       12  Identifier 17
C2UAR2.ID16       11  Identifier 16
C2UAR2.ID15       10  Identifier 15
C2UAR2.ID14       9   Identifier 14
C2UAR2.ID13       8   Identifier 13
C2UAR2.ID28       7   Identifier 28
C2UAR2.ID27       6   Identifier 27
C2UAR2.ID26       5   Identifier 26
C2UAR2.ID25       4   Identifier 25
C2UAR2.ID24       3   Identifier 24
C2UAR2.ID23       2   Identifier 23
C2UAR2.ID22       1   Identifier 22
C2UAR2.ID21       0   Identifier 21
C2LAR2           0xEE24   CAN2 Lower Arbitration Register (msg. )       
C2LAR2.ID4        15  Identifier 4 
C2LAR2.ID3        14  Identifier 3 
C2LAR2.ID2        13  Identifier 2 
C2LAR2.ID1        12  Identifier 1 
C2LAR2.ID0        11  Identifier 0 
C2LAR2.ID12       7   Identifier 12
C2LAR2.ID11       6   Identifier 11
C2LAR2.ID10       5   Identifier 10
C2LAR2.ID9        4   Identifier 9 
C2LAR2.ID8        3   Identifier 8 
C2LAR2.ID7        2   Identifier 7 
C2LAR2.ID6        1   Identifier 6 
C2LAR2.ID5        0   Identifier 5 
C2MCFG2          0xEE26   CAN2 Message Configuration Register (msg. )
C2MCFG2.DLC_7     7   Data Length Code - bit 7
C2MCFG2.DLC_6     6   Data Length Code - bit 6
C2MCFG2.DLC_5     5   Data Length Code - bit 5
C2MCFG2.DLC_4     4   Data Length Code - bit 4
C2MCFG2.DIR       3   Message Direction
C2MCFG2.XTD       2   Extended Identifier
C2MCR3           0xEE31   CAN2 Message Ctrl. Reg. (msg. )
C2MCR3.RMTPND_15        15  Remote Pending - bit 15
C2MCR3.RMTPND_14        14  Remote Pending - bit 14
C2MCR3.TXRQ_13          13  Transmit Request - bit 13
C2MCR3.TXRQ_12          12  Transmit Request - bit 12
C2MCR3.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C2MCR3.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C2MCR3.NEWDAT_9         9   New Data - bit 9
C2MCR3.NEWDAT_8         8   New Data - bit 8
C2MCR3.MSGVAL_7         7   Message Valid - bit 7
C2MCR3.MSGVAL_6         6   Message Valid - bit 6
C2MCR3.TXIE_5           5   Transmit Interrupt Enable - bit 5
C2MCR3.TXIE_4           4   Transmit Interrupt Enable - bit 4
C2MCR3.RXIE_3           3   Receive Interrupt Enable - bit 3
C2MCR3.RXIE_2           2   Receive Interrupt Enable - bit 2
C2MCR3.INTPND_1         1   Interrupt Pending - bit 1
C2MCR3.INTPND_0         0   Interrupt Pending - bit 0
C2UAR3           0xEE32   CAN2 Upper Arbitration Reg. (msg. )           
C2UAR3.ID20       15  Identifier 20
C2UAR3.ID19       14  Identifier 19
C2UAR3.ID18       13  Identifier 18
C2UAR3.ID17       12  Identifier 17
C2UAR3.ID16       11  Identifier 16
C2UAR3.ID15       10  Identifier 15
C2UAR3.ID14       9   Identifier 14
C2UAR3.ID13       8   Identifier 13
C2UAR3.ID28       7   Identifier 28
C2UAR3.ID27       6   Identifier 27
C2UAR3.ID26       5   Identifier 26
C2UAR3.ID25       4   Identifier 25
C2UAR3.ID24       3   Identifier 24
C2UAR3.ID23       2   Identifier 23
C2UAR3.ID22       1   Identifier 22
C2UAR3.ID21       0   Identifier 21
C2LAR3           0xEE34   CAN2 Lower Arbitration Register (msg. )       
C2LAR3.ID4        15  Identifier 4 
C2LAR3.ID3        14  Identifier 3 
C2LAR3.ID2        13  Identifier 2 
C2LAR3.ID1        12  Identifier 1 
C2LAR3.ID0        11  Identifier 0 
C2LAR3.ID12       7   Identifier 12
C2LAR3.ID11       6   Identifier 11
C2LAR3.ID10       5   Identifier 10
C2LAR3.ID9        4   Identifier 9 
C2LAR3.ID8        3   Identifier 8 
C2LAR3.ID7        2   Identifier 7 
C2LAR3.ID6        1   Identifier 6 
C2LAR3.ID5        0   Identifier 5 
C2MCFG3          0xEE36   CAN2 Message Configuration Register (msg. )
C2MCFG3.DLC_7     7   Data Length Code - bit 7
C2MCFG3.DLC_6     6   Data Length Code - bit 6
C2MCFG3.DLC_5     5   Data Length Code - bit 5
C2MCFG3.DLC_4     4   Data Length Code - bit 4
C2MCFG3.DIR       3   Message Direction
C2MCFG3.XTD       2   Extended Identifier
C2MCR4           0xEE41   CAN2 Message Ctrl. Reg. (msg. )
C2MCR4.RMTPND_15        15  Remote Pending - bit 15
C2MCR4.RMTPND_14        14  Remote Pending - bit 14
C2MCR4.TXRQ_13          13  Transmit Request - bit 13
C2MCR4.TXRQ_12          12  Transmit Request - bit 12
C2MCR4.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C2MCR4.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C2MCR4.NEWDAT_9         9   New Data - bit 9
C2MCR4.NEWDAT_8         8   New Data - bit 8
C2MCR4.MSGVAL_7         7   Message Valid - bit 7
C2MCR4.MSGVAL_6         6   Message Valid - bit 6
C2MCR4.TXIE_5           5   Transmit Interrupt Enable - bit 5
C2MCR4.TXIE_4           4   Transmit Interrupt Enable - bit 4
C2MCR4.RXIE_3           3   Receive Interrupt Enable - bit 3
C2MCR4.RXIE_2           2   Receive Interrupt Enable - bit 2
C2MCR4.INTPND_1         1   Interrupt Pending - bit 1
C2MCR4.INTPND_0         0   Interrupt Pending - bit 0
C2UAR4           0xEE42   CAN2 Upper Arbitration Reg. (msg. )           
C2UAR4.ID20       15  Identifier 20
C2UAR4.ID19       14  Identifier 19
C2UAR4.ID18       13  Identifier 18
C2UAR4.ID17       12  Identifier 17
C2UAR4.ID16       11  Identifier 16
C2UAR4.ID15       10  Identifier 15
C2UAR4.ID14       9   Identifier 14
C2UAR4.ID13       8   Identifier 13
C2UAR4.ID28       7   Identifier 28
C2UAR4.ID27       6   Identifier 27
C2UAR4.ID26       5   Identifier 26
C2UAR4.ID25       4   Identifier 25
C2UAR4.ID24       3   Identifier 24
C2UAR4.ID23       2   Identifier 23
C2UAR4.ID22       1   Identifier 22
C2UAR4.ID21       0   Identifier 21
C2LAR4           0xEE44   CAN2 Lower Arbitration Register (msg. )       
C2LAR4.ID4        15  Identifier 4 
C2LAR4.ID3        14  Identifier 3 
C2LAR4.ID2        13  Identifier 2 
C2LAR4.ID1        12  Identifier 1 
C2LAR4.ID0        11  Identifier 0 
C2LAR4.ID12       7   Identifier 12
C2LAR4.ID11       6   Identifier 11
C2LAR4.ID10       5   Identifier 10
C2LAR4.ID9        4   Identifier 9 
C2LAR4.ID8        3   Identifier 8 
C2LAR4.ID7        2   Identifier 7 
C2LAR4.ID6        1   Identifier 6 
C2LAR4.ID5        0   Identifier 5 
C2MCFG4          0xEE46   CAN2 Message Configuration Register (msg. )
C2MCFG4.DLC_7     7   Data Length Code - bit 7
C2MCFG4.DLC_6     6   Data Length Code - bit 6
C2MCFG4.DLC_5     5   Data Length Code - bit 5
C2MCFG4.DLC_4     4   Data Length Code - bit 4
C2MCFG4.DIR       3   Message Direction
C2MCFG4.XTD       2   Extended Identifier
C2MCR5           0xEE51   CAN2 Message Ctrl. Reg. (msg. )
C2MCR5.RMTPND_15        15  Remote Pending - bit 15
C2MCR5.RMTPND_14        14  Remote Pending - bit 14
C2MCR5.TXRQ_13          13  Transmit Request - bit 13
C2MCR5.TXRQ_12          12  Transmit Request - bit 12
C2MCR5.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C2MCR5.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C2MCR5.NEWDAT_9         9   New Data - bit 9
C2MCR5.NEWDAT_8         8   New Data - bit 8
C2MCR5.MSGVAL_7         7   Message Valid - bit 7
C2MCR5.MSGVAL_6         6   Message Valid - bit 6
C2MCR5.TXIE_5           5   Transmit Interrupt Enable - bit 5
C2MCR5.TXIE_4           4   Transmit Interrupt Enable - bit 4
C2MCR5.RXIE_3           3   Receive Interrupt Enable - bit 3
C2MCR5.RXIE_2           2   Receive Interrupt Enable - bit 2
C2MCR5.INTPND_1         1   Interrupt Pending - bit 1
C2MCR5.INTPND_0         0   Interrupt Pending - bit 0
C2UAR5           0xEE52   CAN2 Upper Arbitration Reg. (msg. )           
C2UAR5.ID20       15  Identifier 20
C2UAR5.ID19       14  Identifier 19
C2UAR5.ID18       13  Identifier 18
C2UAR5.ID17       12  Identifier 17
C2UAR5.ID16       11  Identifier 16
C2UAR5.ID15       10  Identifier 15
C2UAR5.ID14       9   Identifier 14
C2UAR5.ID13       8   Identifier 13
C2UAR5.ID28       7   Identifier 28
C2UAR5.ID27       6   Identifier 27
C2UAR5.ID26       5   Identifier 26
C2UAR5.ID25       4   Identifier 25
C2UAR5.ID24       3   Identifier 24
C2UAR5.ID23       2   Identifier 23
C2UAR5.ID22       1   Identifier 22
C2UAR5.ID21       0   Identifier 21
C2LAR5           0xEE54   CAN2 Lower Arbitration Register (msg. )       
C2LAR5.ID4        15  Identifier 4 
C2LAR5.ID3        14  Identifier 3 
C2LAR5.ID2        13  Identifier 2 
C2LAR5.ID1        12  Identifier 1 
C2LAR5.ID0        11  Identifier 0 
C2LAR5.ID12       7   Identifier 12
C2LAR5.ID11       6   Identifier 11
C2LAR5.ID10       5   Identifier 10
C2LAR5.ID9        4   Identifier 9 
C2LAR5.ID8        3   Identifier 8 
C2LAR5.ID7        2   Identifier 7 
C2LAR5.ID6        1   Identifier 6 
C2LAR5.ID5        0   Identifier 5 
C2MCFG5          0xEE56   CAN2 Message Configuration Register (msg. )
C2MCFG5.DLC_7     7   Data Length Code - bit 7
C2MCFG5.DLC_6     6   Data Length Code - bit 6
C2MCFG5.DLC_5     5   Data Length Code - bit 5
C2MCFG5.DLC_4     4   Data Length Code - bit 4
C2MCFG5.DIR       3   Message Direction
C2MCFG5.XTD       2   Extended Identifier
C2MCR6           0xEE61   CAN2 Message Ctrl. Reg. (msg. )
C2MCR6.RMTPND_15        15  Remote Pending - bit 15
C2MCR6.RMTPND_14        14  Remote Pending - bit 14
C2MCR6.TXRQ_13          13  Transmit Request - bit 13
C2MCR6.TXRQ_12          12  Transmit Request - bit 12
C2MCR6.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C2MCR6.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C2MCR6.NEWDAT_9         9   New Data - bit 9
C2MCR6.NEWDAT_8         8   New Data - bit 8
C2MCR6.MSGVAL_7         7   Message Valid - bit 7
C2MCR6.MSGVAL_6         6   Message Valid - bit 6
C2MCR6.TXIE_5           5   Transmit Interrupt Enable - bit 5
C2MCR6.TXIE_4           4   Transmit Interrupt Enable - bit 4
C2MCR6.RXIE_3           3   Receive Interrupt Enable - bit 3
C2MCR6.RXIE_2           2   Receive Interrupt Enable - bit 2
C2MCR6.INTPND_1         1   Interrupt Pending - bit 1
C2MCR6.INTPND_0         0   Interrupt Pending - bit 0
C2UAR6           0xEE62   CAN2 Upper Arbitration Reg. (msg. )           
C2UAR6.ID20       15  Identifier 20
C2UAR6.ID19       14  Identifier 19
C2UAR6.ID18       13  Identifier 18
C2UAR6.ID17       12  Identifier 17
C2UAR6.ID16       11  Identifier 16
C2UAR6.ID15       10  Identifier 15
C2UAR6.ID14       9   Identifier 14
C2UAR6.ID13       8   Identifier 13
C2UAR6.ID28       7   Identifier 28
C2UAR6.ID27       6   Identifier 27
C2UAR6.ID26       5   Identifier 26
C2UAR6.ID25       4   Identifier 25
C2UAR6.ID24       3   Identifier 24
C2UAR6.ID23       2   Identifier 23
C2UAR6.ID22       1   Identifier 22
C2UAR6.ID21       0   Identifier 21
C2LAR6           0xEE64   CAN2 Lower Arbitration Register (msg. )       
C2LAR6.ID4        15  Identifier 4 
C2LAR6.ID3        14  Identifier 3 
C2LAR6.ID2        13  Identifier 2 
C2LAR6.ID1        12  Identifier 1 
C2LAR6.ID0        11  Identifier 0 
C2LAR6.ID12       7   Identifier 12
C2LAR6.ID11       6   Identifier 11
C2LAR6.ID10       5   Identifier 10
C2LAR6.ID9        4   Identifier 9 
C2LAR6.ID8        3   Identifier 8 
C2LAR6.ID7        2   Identifier 7 
C2LAR6.ID6        1   Identifier 6 
C2LAR6.ID5        0   Identifier 5 
C2MCFG6          0xEE66   CAN2 Message Configuration Register (msg. )
C2MCFG6.DLC_7     7   Data Length Code - bit 7
C2MCFG6.DLC_6     6   Data Length Code - bit 6
C2MCFG6.DLC_5     5   Data Length Code - bit 5
C2MCFG6.DLC_4     4   Data Length Code - bit 4
C2MCFG6.DIR       3   Message Direction
C2MCFG6.XTD       2   Extended Identifier
C2MCR7           0xEE71   CAN2 Message Ctrl. Reg. (msg. )
C2MCR7.RMTPND_15        15  Remote Pending - bit 15
C2MCR7.RMTPND_14        14  Remote Pending - bit 14
C2MCR7.TXRQ_13          13  Transmit Request - bit 13
C2MCR7.TXRQ_12          12  Transmit Request - bit 12
C2MCR7.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C2MCR7.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C2MCR7.NEWDAT_9         9   New Data - bit 9
C2MCR7.NEWDAT_8         8   New Data - bit 8
C2MCR7.MSGVAL_7         7   Message Valid - bit 7
C2MCR7.MSGVAL_6         6   Message Valid - bit 6
C2MCR7.TXIE_5           5   Transmit Interrupt Enable - bit 5
C2MCR7.TXIE_4           4   Transmit Interrupt Enable - bit 4
C2MCR7.RXIE_3           3   Receive Interrupt Enable - bit 3
C2MCR7.RXIE_2           2   Receive Interrupt Enable - bit 2
C2MCR7.INTPND_1         1   Interrupt Pending - bit 1
C2MCR7.INTPND_0         0   Interrupt Pending - bit 0
C2UAR7           0xEE72   CAN2 Upper Arbitration Reg. (msg. )           
C2UAR7.ID20       15  Identifier 20
C2UAR7.ID19       14  Identifier 19
C2UAR7.ID18       13  Identifier 18
C2UAR7.ID17       12  Identifier 17
C2UAR7.ID16       11  Identifier 16
C2UAR7.ID15       10  Identifier 15
C2UAR7.ID14       9   Identifier 14
C2UAR7.ID13       8   Identifier 13
C2UAR7.ID28       7   Identifier 28
C2UAR7.ID27       6   Identifier 27
C2UAR7.ID26       5   Identifier 26
C2UAR7.ID25       4   Identifier 25
C2UAR7.ID24       3   Identifier 24
C2UAR7.ID23       2   Identifier 23
C2UAR7.ID22       1   Identifier 22
C2UAR7.ID21       0   Identifier 21
C2LAR7           0xEE74   CAN2 Lower Arbitration Register (msg. )       
C2LAR7.ID4        15  Identifier 4 
C2LAR7.ID3        14  Identifier 3 
C2LAR7.ID2        13  Identifier 2 
C2LAR7.ID1        12  Identifier 1 
C2LAR7.ID0        11  Identifier 0 
C2LAR7.ID12       7   Identifier 12
C2LAR7.ID11       6   Identifier 11
C2LAR7.ID10       5   Identifier 10
C2LAR7.ID9        4   Identifier 9 
C2LAR7.ID8        3   Identifier 8 
C2LAR7.ID7        2   Identifier 7 
C2LAR7.ID6        1   Identifier 6 
C2LAR7.ID5        0   Identifier 5 
C2MCFG7          0xEE76   CAN2 Message Configuration Register (msg. )
C2MCFG7.DLC_7     7   Data Length Code - bit 7
C2MCFG7.DLC_6     6   Data Length Code - bit 6
C2MCFG7.DLC_5     5   Data Length Code - bit 5
C2MCFG7.DLC_4     4   Data Length Code - bit 4
C2MCFG7.DIR       3   Message Direction
C2MCFG7.XTD       2   Extended Identifier
C2MCR8           0xEE81   CAN2 Message Ctrl. Reg. (msg. )
C2MCR8.RMTPND_15        15  Remote Pending - bit 15
C2MCR8.RMTPND_14        14  Remote Pending - bit 14
C2MCR8.TXRQ_13          13  Transmit Request - bit 13
C2MCR8.TXRQ_12          12  Transmit Request - bit 12
C2MCR8.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C2MCR8.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C2MCR8.NEWDAT_9         9   New Data - bit 9
C2MCR8.NEWDAT_8         8   New Data - bit 8
C2MCR8.MSGVAL_7         7   Message Valid - bit 7
C2MCR8.MSGVAL_6         6   Message Valid - bit 6
C2MCR8.TXIE_5           5   Transmit Interrupt Enable - bit 5
C2MCR8.TXIE_4           4   Transmit Interrupt Enable - bit 4
C2MCR8.RXIE_3           3   Receive Interrupt Enable - bit 3
C2MCR8.RXIE_2           2   Receive Interrupt Enable - bit 2
C2MCR8.INTPND_1         1   Interrupt Pending - bit 1
C2MCR8.INTPND_0         0   Interrupt Pending - bit 0
C2UAR8           0xEE82   CAN2 Upper Arbitration Reg. (msg. )           
C2UAR8.ID20       15  Identifier 20
C2UAR8.ID19       14  Identifier 19
C2UAR8.ID18       13  Identifier 18
C2UAR8.ID17       12  Identifier 17
C2UAR8.ID16       11  Identifier 16
C2UAR8.ID15       10  Identifier 15
C2UAR8.ID14       9   Identifier 14
C2UAR8.ID13       8   Identifier 13
C2UAR8.ID28       7   Identifier 28
C2UAR8.ID27       6   Identifier 27
C2UAR8.ID26       5   Identifier 26
C2UAR8.ID25       4   Identifier 25
C2UAR8.ID24       3   Identifier 24
C2UAR8.ID23       2   Identifier 23
C2UAR8.ID22       1   Identifier 22
C2UAR8.ID21       0   Identifier 21
C2LAR8           0xEE84   CAN2 Lower Arbitration Register (msg. )       
C2LAR8.ID4        15  Identifier 4 
C2LAR8.ID3        14  Identifier 3 
C2LAR8.ID2        13  Identifier 2 
C2LAR8.ID1        12  Identifier 1 
C2LAR8.ID0        11  Identifier 0 
C2LAR8.ID12       7   Identifier 12
C2LAR8.ID11       6   Identifier 11
C2LAR8.ID10       5   Identifier 10
C2LAR8.ID9        4   Identifier 9 
C2LAR8.ID8        3   Identifier 8 
C2LAR8.ID7        2   Identifier 7 
C2LAR8.ID6        1   Identifier 6 
C2LAR8.ID5        0   Identifier 5 
C2MCFG8          0xEE86   CAN2 Message Configuration Register (msg. )
C2MCFG8.DLC_7     7   Data Length Code - bit 7
C2MCFG8.DLC_6     6   Data Length Code - bit 6
C2MCFG8.DLC_5     5   Data Length Code - bit 5
C2MCFG8.DLC_4     4   Data Length Code - bit 4
C2MCFG8.DIR       3   Message Direction
C2MCFG8.XTD       2   Extended Identifier
C2MCR9           0xEE91   CAN2 Message Ctrl. Reg. (msg. )
C2MCR9.RMTPND_15        15  Remote Pending - bit 15
C2MCR9.RMTPND_14        14  Remote Pending - bit 14
C2MCR9.TXRQ_13          13  Transmit Request - bit 13
C2MCR9.TXRQ_12          12  Transmit Request - bit 12
C2MCR9.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C2MCR9.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C2MCR9.NEWDAT_9         9   New Data - bit 9
C2MCR9.NEWDAT_8         8   New Data - bit 8
C2MCR9.MSGVAL_7         7   Message Valid - bit 7
C2MCR9.MSGVAL_6         6   Message Valid - bit 6
C2MCR9.TXIE_5           5   Transmit Interrupt Enable - bit 5
C2MCR9.TXIE_4           4   Transmit Interrupt Enable - bit 4
C2MCR9.RXIE_3           3   Receive Interrupt Enable - bit 3
C2MCR9.RXIE_2           2   Receive Interrupt Enable - bit 2
C2MCR9.INTPND_1         1   Interrupt Pending - bit 1
C2MCR9.INTPND_0         0   Interrupt Pending - bit 0
C2UAR9           0xEE92   CAN2 Upper Arbitration Reg. (msg. )           
C2UAR9.ID20       15  Identifier 20
C2UAR9.ID19       14  Identifier 19
C2UAR9.ID18       13  Identifier 18
C2UAR9.ID17       12  Identifier 17
C2UAR9.ID16       11  Identifier 16
C2UAR9.ID15       10  Identifier 15
C2UAR9.ID14       9   Identifier 14
C2UAR9.ID13       8   Identifier 13
C2UAR9.ID28       7   Identifier 28
C2UAR9.ID27       6   Identifier 27
C2UAR9.ID26       5   Identifier 26
C2UAR9.ID25       4   Identifier 25
C2UAR9.ID24       3   Identifier 24
C2UAR9.ID23       2   Identifier 23
C2UAR9.ID22       1   Identifier 22
C2UAR9.ID21       0   Identifier 21
C2LAR9           0xEE94   CAN2 Lower Arbitration Register (msg. )       
C2LAR9.ID4        15  Identifier 4 
C2LAR9.ID3        14  Identifier 3 
C2LAR9.ID2        13  Identifier 2 
C2LAR9.ID1        12  Identifier 1 
C2LAR9.ID0        11  Identifier 0 
C2LAR9.ID12       7   Identifier 12
C2LAR9.ID11       6   Identifier 11
C2LAR9.ID10       5   Identifier 10
C2LAR9.ID9        4   Identifier 9 
C2LAR9.ID8        3   Identifier 8 
C2LAR9.ID7        2   Identifier 7 
C2LAR9.ID6        1   Identifier 6 
C2LAR9.ID5        0   Identifier 5 
C2MCFG9          0xEE96   CAN2 Message Configuration Register (msg. )
C2MCFG9.DLC_7     7   Data Length Code - bit 7
C2MCFG9.DLC_6     6   Data Length Code - bit 6
C2MCFG9.DLC_5     5   Data Length Code - bit 5
C2MCFG9.DLC_4     4   Data Length Code - bit 4
C2MCFG9.DIR       3   Message Direction
C2MCFG9.XTD       2   Extended Identifier
C2MCR10          0xEEA1   CAN2 Message Ctrl. Reg. (msg. )
C2MCR10.RMTPND_15        15  Remote Pending - bit 15
C2MCR10.RMTPND_14        14  Remote Pending - bit 14
C2MCR10.TXRQ_13          13  Transmit Request - bit 13
C2MCR10.TXRQ_12          12  Transmit Request - bit 12
C2MCR10.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C2MCR10.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C2MCR10.NEWDAT_9         9   New Data - bit 9
C2MCR10.NEWDAT_8         8   New Data - bit 8
C2MCR10.MSGVAL_7         7   Message Valid - bit 7
C2MCR10.MSGVAL_6         6   Message Valid - bit 6
C2MCR10.TXIE_5           5   Transmit Interrupt Enable - bit 5
C2MCR10.TXIE_4           4   Transmit Interrupt Enable - bit 4
C2MCR10.RXIE_3           3   Receive Interrupt Enable - bit 3
C2MCR10.RXIE_2           2   Receive Interrupt Enable - bit 2
C2MCR10.INTPND_1         1   Interrupt Pending - bit 1
C2MCR10.INTPND_0         0   Interrupt Pending - bit 0
C2UAR10          0xEEA2   CAN2 Upper Arbitration Reg. (msg. )
C2UAR10.ID20      15  Identifier 20
C2UAR10.ID19      14  Identifier 19
C2UAR10.ID18      13  Identifier 18
C2UAR10.ID17      12  Identifier 17
C2UAR10.ID16      11  Identifier 16
C2UAR10.ID15      10  Identifier 15
C2UAR10.ID14      9   Identifier 14
C2UAR10.ID13      8   Identifier 13
C2UAR10.ID28      7   Identifier 28
C2UAR10.ID27      6   Identifier 27
C2UAR10.ID26      5   Identifier 26
C2UAR10.ID25      4   Identifier 25
C2UAR10.ID24      3   Identifier 24
C2UAR10.ID23      2   Identifier 23
C2UAR10.ID22      1   Identifier 22
C2UAR10.ID21      0   Identifier 21
C2LAR10          0xEEA4   CAN2 Lower Arbitration Register (msg. )
C2LAR10.ID4       15  Identifier 4 
C2LAR10.ID3       14  Identifier 3 
C2LAR10.ID2       13  Identifier 2 
C2LAR10.ID1       12  Identifier 1 
C2LAR10.ID0       11  Identifier 0 
C2LAR10.ID12      7   Identifier 12
C2LAR10.ID11      6   Identifier 11
C2LAR10.ID10      5   Identifier 10
C2LAR10.ID9       4   Identifier 9 
C2LAR10.ID8       3   Identifier 8 
C2LAR10.ID7       2   Identifier 7 
C2LAR10.ID6       1   Identifier 6 
C2LAR10.ID5       0   Identifier 5 
C2MCFG10         0xEEA6   CAN2 Message Configuration Register (msg. )
C2MCFG10.DLC_7     7   Data Length Code - bit 7
C2MCFG10.DLC_6     6   Data Length Code - bit 6
C2MCFG10.DLC_5     5   Data Length Code - bit 5
C2MCFG10.DLC_4     4   Data Length Code - bit 4
C2MCFG10.DIR       3   Message Direction
C2MCFG10.XTD       2   Extended Identifier
C2MCR11          0xEEB1   CAN2 Message Ctrl. Reg. (msg. )
C2MCR11.RMTPND_15        15  Remote Pending - bit 15
C2MCR11.RMTPND_14        14  Remote Pending - bit 14
C2MCR11.TXRQ_13          13  Transmit Request - bit 13
C2MCR11.TXRQ_12          12  Transmit Request - bit 12
C2MCR11.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C2MCR11.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C2MCR11.NEWDAT_9         9   New Data - bit 9
C2MCR11.NEWDAT_8         8   New Data - bit 8
C2MCR11.MSGVAL_7         7   Message Valid - bit 7
C2MCR11.MSGVAL_6         6   Message Valid - bit 6
C2MCR11.TXIE_5           5   Transmit Interrupt Enable - bit 5
C2MCR11.TXIE_4           4   Transmit Interrupt Enable - bit 4
C2MCR11.RXIE_3           3   Receive Interrupt Enable - bit 3
C2MCR11.RXIE_2           2   Receive Interrupt Enable - bit 2
C2MCR11.INTPND_1         1   Interrupt Pending - bit 1
C2MCR11.INTPND_0         0   Interrupt Pending - bit 
C2UAR11          0xEEB2   CAN2 Upper Arbitration Reg. (msg. )
C2UAR11.ID20      15  Identifier 20
C2UAR11.ID19      14  Identifier 19
C2UAR11.ID18      13  Identifier 18
C2UAR11.ID17      12  Identifier 17
C2UAR11.ID16      11  Identifier 16
C2UAR11.ID15      10  Identifier 15
C2UAR11.ID14      9   Identifier 14
C2UAR11.ID13      8   Identifier 13
C2UAR11.ID28      7   Identifier 28
C2UAR11.ID27      6   Identifier 27
C2UAR11.ID26      5   Identifier 26
C2UAR11.ID25      4   Identifier 25
C2UAR11.ID24      3   Identifier 24
C2UAR11.ID23      2   Identifier 23
C2UAR11.ID22      1   Identifier 22
C2UAR11.ID21      0   Identifier 21
C2LAR11          0xEEB4   CAN2 Lower Arbitration Register (msg. )
C2LAR11.ID4       15  Identifier 4 
C2LAR11.ID3       14  Identifier 3 
C2LAR11.ID2       13  Identifier 2 
C2LAR11.ID1       12  Identifier 1 
C2LAR11.ID0       11  Identifier 0 
C2LAR11.ID12      7   Identifier 12
C2LAR11.ID11      6   Identifier 11
C2LAR11.ID10      5   Identifier 10
C2LAR11.ID9       4   Identifier 9 
C2LAR11.ID8       3   Identifier 8 
C2LAR11.ID7       2   Identifier 7 
C2LAR11.ID6       1   Identifier 6 
C2LAR11.ID5       0   Identifier 5 
C2MCFG11         0xEEB6   CAN2 Message Configuration Register (msg. )
C2MCFG11.DLC_7     7   Data Length Code - bit 7
C2MCFG11.DLC_6     6   Data Length Code - bit 6
C2MCFG11.DLC_5     5   Data Length Code - bit 5
C2MCFG11.DLC_4     4   Data Length Code - bit 4
C2MCFG11.DIR       3   Message Direction
C2MCFG11.XTD       2   Extended Identifier
C2MCR12          0xEEC1   CAN2 Message Ctrl. Reg. (msg. )
C2MCR12.RMTPND_15        15  Remote Pending - bit 15
C2MCR12.RMTPND_14        14  Remote Pending - bit 14
C2MCR12.TXRQ_13          13  Transmit Request - bit 13
C2MCR12.TXRQ_12          12  Transmit Request - bit 12
C2MCR12.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C2MCR12.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C2MCR12.NEWDAT_9         9   New Data - bit 9
C2MCR12.NEWDAT_8         8   New Data - bit 8
C2MCR12.MSGVAL_7         7   Message Valid - bit 7
C2MCR12.MSGVAL_6         6   Message Valid - bit 6
C2MCR12.TXIE_5           5   Transmit Interrupt Enable - bit 5
C2MCR12.TXIE_4           4   Transmit Interrupt Enable - bit 4
C2MCR12.RXIE_3           3   Receive Interrupt Enable - bit 3
C2MCR12.RXIE_2           2   Receive Interrupt Enable - bit 2
C2MCR12.INTPND_1         1   Interrupt Pending - bit 1
C2MCR12.INTPND_0         0   Interrupt Pending - bit 
C2UAR12          0xEEC2   CAN2 Upper Arbitration Reg. (msg. )
C2UAR12.ID20      15  Identifier 20
C2UAR12.ID19      14  Identifier 19
C2UAR12.ID18      13  Identifier 18
C2UAR12.ID17      12  Identifier 17
C2UAR12.ID16      11  Identifier 16
C2UAR12.ID15      10  Identifier 15
C2UAR12.ID14      9   Identifier 14
C2UAR12.ID13      8   Identifier 13
C2UAR12.ID28      7   Identifier 28
C2UAR12.ID27      6   Identifier 27
C2UAR12.ID26      5   Identifier 26
C2UAR12.ID25      4   Identifier 25
C2UAR12.ID24      3   Identifier 24
C2UAR12.ID23      2   Identifier 23
C2UAR12.ID22      1   Identifier 22
C2UAR12.ID21      0   Identifier 21
C2LAR12          0xEEC4   CAN2 Lower Arbitration Register (msg. )
C2LAR12.ID4       15  Identifier 4 
C2LAR12.ID3       14  Identifier 3 
C2LAR12.ID2       13  Identifier 2 
C2LAR12.ID1       12  Identifier 1 
C2LAR12.ID0       11  Identifier 0 
C2LAR12.ID12      7   Identifier 12
C2LAR12.ID11      6   Identifier 11
C2LAR12.ID10      5   Identifier 10
C2LAR12.ID9       4   Identifier 9 
C2LAR12.ID8       3   Identifier 8 
C2LAR12.ID7       2   Identifier 7 
C2LAR12.ID6       1   Identifier 6 
C2LAR12.ID5       0   Identifier 5 
C2MCFG12         0xEEC6   CAN2 Message Configuration Register (msg. )
C2MCFG12.DLC_7     7   Data Length Code - bit 7
C2MCFG12.DLC_6     6   Data Length Code - bit 6
C2MCFG12.DLC_5     5   Data Length Code - bit 5
C2MCFG12.DLC_4     4   Data Length Code - bit 4
C2MCFG12.DIR       3   Message Direction
C2MCFG12.XTD       2   Extended Identifier
C2MCR13          0xEED1   CAN2 Message Ctrl. Reg. (msg. )
C2MCR13.RMTPND_15        15  Remote Pending - bit 15
C2MCR13.RMTPND_14        14  Remote Pending - bit 14
C2MCR13.TXRQ_13          13  Transmit Request - bit 13
C2MCR13.TXRQ_12          12  Transmit Request - bit 12
C2MCR13.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C2MCR13.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C2MCR13.NEWDAT_9         9   New Data - bit 9
C2MCR13.NEWDAT_8         8   New Data - bit 8
C2MCR13.MSGVAL_7         7   Message Valid - bit 7
C2MCR13.MSGVAL_6         6   Message Valid - bit 6
C2MCR13.TXIE_5           5   Transmit Interrupt Enable - bit 5
C2MCR13.TXIE_4           4   Transmit Interrupt Enable - bit 4
C2MCR13.RXIE_3           3   Receive Interrupt Enable - bit 3
C2MCR13.RXIE_2           2   Receive Interrupt Enable - bit 2
C2MCR13.INTPND_1         1   Interrupt Pending - bit 1
C2MCR13.INTPND_0         0   Interrupt Pending - bit 
C2UAR13          0xEED2   CAN2 Upper Arbitration Reg. (msg. )
C2UAR14.ID20      15  Identifier 20
C2UAR14.ID19      14  Identifier 19
C2UAR14.ID18      13  Identifier 18
C2UAR14.ID17      12  Identifier 17
C2UAR14.ID16      11  Identifier 16
C2UAR14.ID15      10  Identifier 15
C2UAR14.ID14      9   Identifier 14
C2UAR14.ID13      8   Identifier 13
C2UAR14.ID28      7   Identifier 28
C2UAR14.ID27      6   Identifier 27
C2UAR14.ID26      5   Identifier 26
C2UAR14.ID25      4   Identifier 25
C2UAR14.ID24      3   Identifier 24
C2UAR14.ID23      2   Identifier 23
C2UAR14.ID22      1   Identifier 22
C2UAR14.ID21      0   Identifier 21
C2LAR13          0xEED4   CAN2 Lower Arbitration Register (msg. )
C2LAR13.ID4       15  Identifier 4 
C2LAR13.ID3       14  Identifier 3 
C2LAR13.ID2       13  Identifier 2 
C2LAR13.ID1       12  Identifier 1 
C2LAR13.ID0       11  Identifier 0 
C2LAR13.ID12      7   Identifier 12
C2LAR13.ID11      6   Identifier 11
C2LAR13.ID10      5   Identifier 10
C2LAR13.ID9       4   Identifier 9 
C2LAR13.ID8       3   Identifier 8 
C2LAR13.ID7       2   Identifier 7 
C2LAR13.ID6       1   Identifier 6 
C2LAR13.ID5       0   Identifier 5 
C2MCFG13         0xEED6   CAN2 Message Configuration Register (msg. )
C2MCFG13.DLC_7     7   Data Length Code - bit 7
C2MCFG13.DLC_6     6   Data Length Code - bit 6
C2MCFG13.DLC_5     5   Data Length Code - bit 5
C2MCFG13.DLC_4     4   Data Length Code - bit 4
C2MCFG13.DIR       3   Message Direction
C2MCFG13.XTD       2   Extended Identifier
C2MCR14          0xEEE1   CAN2 Message Ctrl. Reg. (msg. )
C2MCR14.RMTPND_15        15  Remote Pending - bit 15
C2MCR14.RMTPND_14        14  Remote Pending - bit 14
C2MCR14.TXRQ_13          13  Transmit Request - bit 13
C2MCR14.TXRQ_12          12  Transmit Request - bit 12
C2MCR14.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C2MCR14.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C2MCR14.NEWDAT_9         9   New Data - bit 9
C2MCR14.NEWDAT_8         8   New Data - bit 8
C2MCR14.MSGVAL_7         7   Message Valid - bit 7
C2MCR14.MSGVAL_6         6   Message Valid - bit 6
C2MCR14.TXIE_5           5   Transmit Interrupt Enable - bit 5
C2MCR14.TXIE_4           4   Transmit Interrupt Enable - bit 4
C2MCR14.RXIE_3           3   Receive Interrupt Enable - bit 3
C2MCR14.RXIE_2           2   Receive Interrupt Enable - bit 2
C2MCR14.INTPND_1         1   Interrupt Pending - bit 1
C2MCR14.INTPND_0         0   Interrupt Pending - bit 
C2UAR14          0xEEE2   CAN2 Upper Arbitration Reg. (msg. )
C2LAR14          0xEEE4   CAN2 Lower Arbitration Register (msg. )
C2LAR14.ID4       15  Identifier 4 
C2LAR14.ID3       14  Identifier 3 
C2LAR14.ID2       13  Identifier 2 
C2LAR14.ID1       12  Identifier 1 
C2LAR14.ID0       11  Identifier 0 
C2LAR14.ID12      7   Identifier 12
C2LAR14.ID11      6   Identifier 11
C2LAR14.ID10      5   Identifier 10
C2LAR14.ID9       4   Identifier 9 
C2LAR14.ID8       3   Identifier 8 
C2LAR14.ID7       2   Identifier 7 
C2LAR14.ID6       1   Identifier 6 
C2LAR14.ID5       0   Identifier 5 
C2MCFG14         0xEEE6   CAN2 Message Configuration Register (msg. )
C2MCFG14.DLC_7     7   Data Length Code - bit 7
C2MCFG14.DLC_6     6   Data Length Code - bit 6
C2MCFG14.DLC_5     5   Data Length Code - bit 5
C2MCFG14.DLC_4     4   Data Length Code - bit 4
C2MCFG14.DIR       3   Message Direction
C2MCFG14.XTD       2   Extended Identifier
C2MCR15          0xEEF1   CAN2 Message Ctrl. Reg. (msg. )
C2MCR15.RMTPND_15        15  Remote Pending - bit 15
C2MCR15.RMTPND_14        14  Remote Pending - bit 14
C2MCR15.TXRQ_13          13  Transmit Request - bit 13
C2MCR15.TXRQ_12          12  Transmit Request - bit 12
C2MCR15.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C2MCR15.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C2MCR15.NEWDAT_9         9   New Data - bit 9
C2MCR15.NEWDAT_8         8   New Data - bit 8
C2MCR15.MSGVAL_7         7   Message Valid - bit 7
C2MCR15.MSGVAL_6         6   Message Valid - bit 6
C2MCR15.TXIE_5           5   Transmit Interrupt Enable - bit 5
C2MCR15.TXIE_4           4   Transmit Interrupt Enable - bit 4
C2MCR15.RXIE_3           3   Receive Interrupt Enable - bit 3
C2MCR15.RXIE_2           2   Receive Interrupt Enable - bit 2
C2MCR15.INTPND_1         1   Interrupt Pending - bit 1
C2MCR15.INTPND_0         0   Interrupt Pending - bit 
C2UAR15          0xEEF2   CAN2 Upper Arbitration Reg. (msg. )
C2UAR15.ID20      15  Identifier 20
C2UAR15.ID19      14  Identifier 19
C2UAR15.ID18      13  Identifier 18
C2UAR15.ID17      12  Identifier 17
C2UAR15.ID16      11  Identifier 16
C2UAR15.ID15      10  Identifier 15
C2UAR15.ID14      9   Identifier 14
C2UAR15.ID13      8   Identifier 13
C2UAR15.ID28      7   Identifier 28
C2UAR15.ID27      6   Identifier 27
C2UAR15.ID26      5   Identifier 26
C2UAR15.ID25      4   Identifier 25
C2UAR15.ID24      3   Identifier 24
C2UAR15.ID23      2   Identifier 23
C2UAR15.ID22      1   Identifier 22
C2UAR15.ID21      0   Identifier 21
C2LAR15          0xEEF4   CAN2 Lower Arbitration Register (msg. )
C2LAR15.ID4       15  Identifier 4 
C2LAR15.ID3       14  Identifier 3 
C2LAR15.ID2       13  Identifier 2 
C2LAR15.ID1       12  Identifier 1 
C2LAR15.ID0       11  Identifier 0 
C2LAR15.ID12      7   Identifier 12
C2LAR15.ID11      6   Identifier 11
C2LAR15.ID10      5   Identifier 10
C2LAR15.ID9       4   Identifier 9 
C2LAR15.ID8       3   Identifier 8 
C2LAR15.ID7       2   Identifier 7 
C2LAR15.ID6       1   Identifier 6 
C2LAR15.ID5       0   Identifier 5 
C2MCFG15         0xEEF6   CAN2 Message Configuration Register (msg. )
C2MCFG15.DLC_7     7   Data Length Code - bit 7
C2MCFG15.DLC_6     6   Data Length Code - bit 6
C2MCFG15.DLC_5     5   Data Length Code - bit 5
C2MCFG15.DLC_4     4   Data Length Code - bit 4
C2MCFG15.DIR       3   Message Direction
C2MCFG15.XTD       2   Extended Identifier
C1CSR            0xEF00   CAN1 Control/Status Register                   
C1CSR.BOFF        15  Busoff Status
C1CSR.EWRN        14  Error Warning Status
C1CSR.RXOK        12  Received Message Successfully
C1CSR.TXOK        11  Transmitted Message Successfully
C1CSR.LEC_10      10  Last Error Code - bit 10
C1CSR.LEC_9       9   Last Error Code - bit 9 
C1CSR.LEC_8       8   Last Error Code - bit 8 
C1CSR.TM          7   Test Mode
C1CSR.CCE         6   Configuration Change Enable
C1CSR.CPS         4   Clock Prescaler Control Bit
C1CSR.EIE         3   Error Interrupt Enable
C1CSR.SIE         2   Status Change Interrupt Enable
C1CSR.IE          1   Interrupt Enable
C1CSR.INIT        0   Initialization
C1PCIR           0xEF02   CAN1 Port Control and Interrupt Register       
C1PCIR.IPC_10     10  Interface Port Control - bit 10
C1PCIR.IPC_9      9   Interface Port Control - bit 9 
C1PCIR.IPC_8      8   Interface Port Control - bit 8 
C1PCIR.INTID_7    7   Interrupt Identifier - bit 7
C1PCIR.INTID_6    6   Interrupt Identifier - bit 6
C1PCIR.INTID_5    5   Interrupt Identifier - bit 5
C1PCIR.INTID_4    4   Interrupt Identifier - bit 4
C1PCIR.INTID_3    3   Interrupt Identifier - bit 3
C1PCIR.INTID_2    2   Interrupt Identifier - bit 2
C1PCIR.INTID_1    1   Interrupt Identifier - bit 1
C1PCIR.INTID_0    0   Interrupt Identifier - bit 0
C1BTR            0xEF04   CAN1 Bit Timing Register                       
C1BTR.TSEG2_14    14  Time Segment after sample point - bit 14
C1BTR.TSEG2_13    13  Time Segment after sample point - bit 13
C1BTR.TSEG2_12    12  Time Segment after sample point - bit 12
C1BTR.TSEG1_11    11  Time Segment before sample point - bit 11
C1BTR.TSEG1_10    10  Time Segment before sample point - bit 10
C1BTR.TSEG1_9     9   Time Segment before sample point - bit 9 
C1BTR.TSEG1_8     8   Time Segment before sample point - bit 8 
C1BTR.SJW_7       7   (Re)Synchronization Jump Width - bit 7
C1BTR.SJW_6       6   (Re)Synchronization Jump Width - bit 6
C1BTR.BRP_5       5   Baud Rate Prescaler - bit 5
C1BTR.BRP_4       4   Baud Rate Prescaler - bit 4
C1BTR.BRP_3       3   Baud Rate Prescaler - bit 3
C1BTR.BRP_2       2   Baud Rate Prescaler - bit 2
C1BTR.BRP_1       1   Baud Rate Prescaler - bit 1
C1BTR.BRP_0       0   Baud Rate Prescaler - bit 0
C1GMS            0xEF06   CAN1 Global Mask Short                         
C1GMS.ID20        15  Identifier 20
C1GMS.ID19        14  Identifier 19
C1GMS.ID18        13  Identifier 18
C1GMS.ID28        7   Identifier 28
C1GMS.ID27        6   Identifier 27
C1GMS.ID26        5   Identifier 26
C1GMS.ID25        4   Identifier 25
C1GMS.ID24        3   Identifier 24
C1GMS.ID23        2   Identifier 23
C1GMS.ID22        1   Identifier 22
C1GMS.ID21        0   Identifier 21
C1UGML           0xEF08   CAN1 Upper Global Mask Long                    
C1UGML.ID20       15  Identifier 20
C1UGML.ID19       14  Identifier 19
C1UGML.ID18       13  Identifier 18
C1UGML.ID17       12  Identifier 17
C1UGML.ID16       11  Identifier 16
C1UGML.ID15       10  Identifier 15
C1UGML.ID14       9   Identifier 14
C1UGML.ID13       8   Identifier 13
C1UGML.ID28       7   Identifier 28
C1UGML.ID27       6   Identifier 27
C1UGML.ID26       5   Identifier 26
C1UGML.ID25       4   Identifier 25
C1UGML.ID24       3   Identifier 24
C1UGML.ID23       2   Identifier 23
C1UGML.ID22       1   Identifier 22
C1UGML.ID21       0   Identifier 21
C1LGML           0xEF0A   CAN1 Lower Global Mask Long                    
C1LGML.ID4        15  Identifier 4 
C1LGML.ID3        14  Identifier 3 
C1LGML.ID2        13  Identifier 2 
C1LGML.ID1        12  Identifier 1 
C1LGML.ID0        11  Identifier 0 
C1LGML.ID12       7   Identifier 12
C1LGML.ID11       6   Identifier 11
C1LGML.ID10       5   Identifier 10
C1LGML.ID9        4   Identifier 9 
C1LGML.ID8        3   Identifier 8 
C1LGML.ID7        2   Identifier 7 
C1LGML.ID6        1   Identifier 6 
C1LGML.ID5        0   Identifier 5 
C1UMLM           0xEF0C   CAN1 Upper Mask of Last Message                
C1UMLM.ID20       15  Identifier 20
C1UMLM.ID19       14  Identifier 19
C1UMLM.ID18       13  Identifier 18
C1UMLM.ID17       12  Identifier 17
C1UMLM.ID16       11  Identifier 16
C1UMLM.ID15       10  Identifier 15
C1UMLM.ID14       9   Identifier 14
C1UMLM.ID13       8   Identifier 13
C1UMLM.ID28       7   Identifier 28
C1UMLM.ID27       6   Identifier 27
C1UMLM.ID26       5   Identifier 26
C1UMLM.ID25       4   Identifier 25
C1UMLM.ID24       3   Identifier 24
C1UMLM.ID23       2   Identifier 23
C1UMLM.ID22       1   Identifier 22
C1UMLM.ID21       0   Identifier 21
C1LMLM           0xEF0E   CAN1 Lower Mask of Last Message                
C1LMLM.ID4        15  Identifier 4 
C1LMLM.ID3        14  Identifier 3 
C1LMLM.ID2        13  Identifier 2 
C1LMLM.ID1        12  Identifier 1 
C1LMLM.ID0        11  Identifier 0 
C1LMLM.ID12       7   Identifier 12
C1LMLM.ID11       6   Identifier 11
C1LMLM.ID10       5   Identifier 10
C1LMLM.ID9        4   Identifier 9 
C1LMLM.ID8        3   Identifier 8 
C1LMLM.ID7        2   Identifier 7 
C1LMLM.ID6        1   Identifier 6 
C1LMLM.ID5        0   Identifier 5 
C1MCR1           0xEF11   CAN1 Message Ctrl. Reg. (msg. )
C1MCR1.RMTPND_15        15  Remote Pending - bit 15
C1MCR1.RMTPND_14        14  Remote Pending - bit 14
C1MCR1.TXRQ_13          13  Transmit Request - bit 13
C1MCR1.TXRQ_12          12  Transmit Request - bit 12
C1MCR1.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C1MCR1.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C1MCR1.NEWDAT_9         9   New Data - bit 9
C1MCR1.NEWDAT_8         8   New Data - bit 8
C1MCR1.MSGVAL_7         7   Message Valid - bit 7
C1MCR1.MSGVAL_6         6   Message Valid - bit 6
C1MCR1.TXIE_5           5   Transmit Interrupt Enable - bit 5
C1MCR1.TXIE_4           4   Transmit Interrupt Enable - bit 4
C1MCR1.RXIE_3           3   Receive Interrupt Enable - bit 3
C1MCR1.RXIE_2           2   Receive Interrupt Enable - bit 2
C1MCR1.INTPND_1         1   Interrupt Pending - bit 1
C1MCR1.INTPND_0         0   Interrupt Pending - bit 0
C1UAR1           0xEF12   CAN1 Upper Arbitration Reg. (msg. )
C1UAR1.ID20       15  Identifier 20
C1UAR1.ID19       14  Identifier 19
C1UAR1.ID18       13  Identifier 18
C1UAR1.ID17       12  Identifier 17
C1UAR1.ID16       11  Identifier 16
C1UAR1.ID15       10  Identifier 15
C1UAR1.ID14       9   Identifier 14
C1UAR1.ID13       8   Identifier 13
C1UAR1.ID28       7   Identifier 28
C1UAR1.ID27       6   Identifier 27
C1UAR1.ID26       5   Identifier 26
C1UAR1.ID25       4   Identifier 25
C1UAR1.ID24       3   Identifier 24
C1UAR1.ID23       2   Identifier 23
C1UAR1.ID22       1   Identifier 22
C1UAR1.ID21       0   Identifier 21
C1LAR1           0xEF14   CAN1 Lower Arbitration Register (msg. )
C1LAR1.ID4        15  Identifier 4 
C1LAR1.ID3        14  Identifier 3 
C1LAR1.ID2        13  Identifier 2 
C1LAR1.ID1        12  Identifier 1 
C1LAR1.ID0        11  Identifier 0 
C1LAR1.ID12       7   Identifier 12
C1LAR1.ID11       6   Identifier 11
C1LAR1.ID10       5   Identifier 10
C1LAR1.ID9        4   Identifier 9 
C1LAR1.ID8        3   Identifier 8 
C1LAR1.ID7        2   Identifier 7 
C1LAR1.ID6        1   Identifier 6 
C1LAR1.ID5        0   Identifier 5 
C1MCFG1          0xEF16   CAN1 Message Configuration Register (msg. )
C1MCFG1.DLC_7     7   Data Length Code - bit 7
C1MCFG1.DLC_6     6   Data Length Code - bit 6
C1MCFG1.DLC_5     5   Data Length Code - bit 5
C1MCFG1.DLC_4     4   Data Length Code - bit 4
C1MCFG1.DIR       3   Message Direction
C1MCFG1.XTD       2   Extended Identifier
C1MCR2           0xEF21   CAN1 Message Ctrl. Reg. (msg. )
C1MCR2.RMTPND_15        15  Remote Pending - bit 15
C1MCR2.RMTPND_14        14  Remote Pending - bit 14
C1MCR2.TXRQ_13          13  Transmit Request - bit 13
C1MCR2.TXRQ_12          12  Transmit Request - bit 12
C1MCR2.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C1MCR2.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C1MCR2.NEWDAT_9         9   New Data - bit 9
C1MCR2.NEWDAT_8         8   New Data - bit 8
C1MCR2.MSGVAL_7         7   Message Valid - bit 7
C1MCR2.MSGVAL_6         6   Message Valid - bit 6
C1MCR2.TXIE_5           5   Transmit Interrupt Enable - bit 5
C1MCR2.TXIE_4           4   Transmit Interrupt Enable - bit 4
C1MCR2.RXIE_3           3   Receive Interrupt Enable - bit 3
C1MCR2.RXIE_2           2   Receive Interrupt Enable - bit 2
C1MCR2.INTPND_1         1   Interrupt Pending - bit 1
C1MCR2.INTPND_0         0   Interrupt Pending - bit 0
C1UAR2           0xEF22   CAN1 Upper Arbitration Reg. (msg. )
C1UAR2.ID20       15  Identifier 20
C1UAR2.ID19       14  Identifier 19
C1UAR2.ID18       13  Identifier 18
C1UAR2.ID17       12  Identifier 17
C1UAR2.ID16       11  Identifier 16
C1UAR2.ID15       10  Identifier 15
C1UAR2.ID14       9   Identifier 14
C1UAR2.ID13       8   Identifier 13
C1UAR2.ID28       7   Identifier 28
C1UAR2.ID27       6   Identifier 27
C1UAR2.ID26       5   Identifier 26
C1UAR2.ID25       4   Identifier 25
C1UAR2.ID24       3   Identifier 24
C1UAR2.ID23       2   Identifier 23
C1UAR2.ID22       1   Identifier 22
C1UAR2.ID21       0   Identifier 21
C1LAR2           0xEF24   CAN1 Lower Arbitration Register (msg. )
C1LAR2.ID4        15  Identifier 4 
C1LAR2.ID3        14  Identifier 3 
C1LAR2.ID2        13  Identifier 2 
C1LAR2.ID1        12  Identifier 1 
C1LAR2.ID0        11  Identifier 0 
C1LAR2.ID12       7   Identifier 12
C1LAR2.ID11       6   Identifier 11
C1LAR2.ID10       5   Identifier 10
C1LAR2.ID9        4   Identifier 9 
C1LAR2.ID8        3   Identifier 8 
C1LAR2.ID7        2   Identifier 7 
C1LAR2.ID6        1   Identifier 6 
C1LAR2.ID5        0   Identifier 5 
C1MCFG2          0xEF26   CAN1 Message Configuration Register (msg. )
C1MCFG2.DLC_7     7   Data Length Code - bit 7
C1MCFG2.DLC_6     6   Data Length Code - bit 6
C1MCFG2.DLC_5     5   Data Length Code - bit 5
C1MCFG2.DLC_4     4   Data Length Code - bit 4
C1MCFG2.DIR       3   Message Direction
C1MCFG2.XTD       2   Extended Identifier
C1MCR3           0xEF31   CAN1 Message Ctrl. Reg. (msg. )
C1MCR3.RMTPND_15        15  Remote Pending - bit 15
C1MCR3.RMTPND_14        14  Remote Pending - bit 14
C1MCR3.TXRQ_13          13  Transmit Request - bit 13
C1MCR3.TXRQ_12          12  Transmit Request - bit 12
C1MCR3.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C1MCR3.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C1MCR3.NEWDAT_9         9   New Data - bit 9
C1MCR3.NEWDAT_8         8   New Data - bit 8
C1MCR3.MSGVAL_7         7   Message Valid - bit 7
C1MCR3.MSGVAL_6         6   Message Valid - bit 6
C1MCR3.TXIE_5           5   Transmit Interrupt Enable - bit 5
C1MCR3.TXIE_4           4   Transmit Interrupt Enable - bit 4
C1MCR3.RXIE_3           3   Receive Interrupt Enable - bit 3
C1MCR3.RXIE_2           2   Receive Interrupt Enable - bit 2
C1MCR3.INTPND_1         1   Interrupt Pending - bit 1
C1MCR3.INTPND_0         0   Interrupt Pending - bit 0
C1UAR3           0xEF32   CAN1 Upper Arbitration Reg. (msg. )
C1UAR3.ID20       15  Identifier 20
C1UAR3.ID19       14  Identifier 19
C1UAR3.ID18       13  Identifier 18
C1UAR3.ID17       12  Identifier 17
C1UAR3.ID16       11  Identifier 16
C1UAR3.ID15       10  Identifier 15
C1UAR3.ID14       9   Identifier 14
C1UAR3.ID13       8   Identifier 13
C1UAR3.ID28       7   Identifier 28
C1UAR3.ID27       6   Identifier 27
C1UAR3.ID26       5   Identifier 26
C1UAR3.ID25       4   Identifier 25
C1UAR3.ID24       3   Identifier 24
C1UAR3.ID23       2   Identifier 23
C1UAR3.ID22       1   Identifier 22
C1UAR3.ID21       0   Identifier 21
C1LAR3           0xEF34   CAN1 Lower Arbitration Register (msg. )
C1LAR1.ID4        15  Identifier 4 
C1LAR1.ID3        14  Identifier 3 
C1LAR1.ID2        13  Identifier 2 
C1LAR1.ID1        12  Identifier 1 
C1LAR1.ID0        11  Identifier 0 
C1LAR1.ID12       7   Identifier 12
C1LAR1.ID11       6   Identifier 11
C1LAR1.ID10       5   Identifier 10
C1LAR1.ID9        4   Identifier 9 
C1LAR1.ID8        3   Identifier 8 
C1LAR1.ID7        2   Identifier 7 
C1LAR1.ID6        1   Identifier 6 
C1LAR1.ID5        0   Identifier 5 
C1MCFG3          0xEF36   CAN1 Message Configuration Register (msg. )
C1MCFG3.DLC_7     7   Data Length Code - bit 7
C1MCFG3.DLC_6     6   Data Length Code - bit 6
C1MCFG3.DLC_5     5   Data Length Code - bit 5
C1MCFG3.DLC_4     4   Data Length Code - bit 4
C1MCFG3.DIR       3   Message Direction
C1MCFG3.XTD       2   Extended Identifier
C1MCR4           0xEF41   CAN1 Message Ctrl. Reg. (msg. )
C1MCR4.RMTPND_15        15  Remote Pending - bit 15
C1MCR4.RMTPND_14        14  Remote Pending - bit 14
C1MCR4.TXRQ_13          13  Transmit Request - bit 13
C1MCR4.TXRQ_12          12  Transmit Request - bit 12
C1MCR4.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C1MCR4.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C1MCR4.NEWDAT_9         9   New Data - bit 9
C1MCR4.NEWDAT_8         8   New Data - bit 8
C1MCR4.MSGVAL_7         7   Message Valid - bit 7
C1MCR4.MSGVAL_6         6   Message Valid - bit 6
C1MCR4.TXIE_5           5   Transmit Interrupt Enable - bit 5
C1MCR4.TXIE_4           4   Transmit Interrupt Enable - bit 4
C1MCR4.RXIE_3           3   Receive Interrupt Enable - bit 3
C1MCR4.RXIE_2           2   Receive Interrupt Enable - bit 2
C1MCR4.INTPND_1         1   Interrupt Pending - bit 1
C1MCR4.INTPND_0         0   Interrupt Pending - bit 0
C1UAR4           0xEF42   CAN1 Upper Arbitration Reg. (msg. )
C1UAR4.ID20       15  Identifier 20
C1UAR4.ID19       14  Identifier 19
C1UAR4.ID18       13  Identifier 18
C1UAR4.ID17       12  Identifier 17
C1UAR4.ID16       11  Identifier 16
C1UAR4.ID15       10  Identifier 15
C1UAR4.ID14       9   Identifier 14
C1UAR4.ID13       8   Identifier 13
C1UAR4.ID28       7   Identifier 28
C1UAR4.ID27       6   Identifier 27
C1UAR4.ID26       5   Identifier 26
C1UAR4.ID25       4   Identifier 25
C1UAR4.ID24       3   Identifier 24
C1UAR4.ID23       2   Identifier 23
C1UAR4.ID22       1   Identifier 22
C1UAR4.ID21       0   Identifier 21
C1LAR4           0xEF44   CAN1 Lower Arbitration Register (msg. )
C1LAR4.ID4        15  Identifier 4 
C1LAR4.ID3        14  Identifier 3 
C1LAR4.ID2        13  Identifier 2 
C1LAR4.ID1        12  Identifier 1 
C1LAR4.ID0        11  Identifier 0 
C1LAR4.ID12       7   Identifier 12
C1LAR4.ID11       6   Identifier 11
C1LAR4.ID10       5   Identifier 10
C1LAR4.ID9        4   Identifier 9 
C1LAR4.ID8        3   Identifier 8 
C1LAR4.ID7        2   Identifier 7 
C1LAR4.ID6        1   Identifier 6 
C1LAR4.ID5        0   Identifier 5 
C1MCFG4          0xEF46   CAN1 Message Configuration Register (msg. )
C1MCFG4.DLC_7     7   Data Length Code - bit 7
C1MCFG4.DLC_6     6   Data Length Code - bit 6
C1MCFG4.DLC_5     5   Data Length Code - bit 5
C1MCFG4.DLC_4     4   Data Length Code - bit 4
C1MCFG4.DIR       3   Message Direction
C1MCFG4.XTD       2   Extended Identifier
C1MCR5           0xEF51   CAN1 Message Ctrl. Reg. (msg. )
C1MCR5.RMTPND_15        15  Remote Pending - bit 15
C1MCR5.RMTPND_14        14  Remote Pending - bit 14
C1MCR5.TXRQ_13          13  Transmit Request - bit 13
C1MCR5.TXRQ_12          12  Transmit Request - bit 12
C1MCR5.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C1MCR5.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C1MCR5.NEWDAT_9         9   New Data - bit 9
C1MCR5.NEWDAT_8         8   New Data - bit 8
C1MCR5.MSGVAL_7         7   Message Valid - bit 7
C1MCR5.MSGVAL_6         6   Message Valid - bit 6
C1MCR5.TXIE_5           5   Transmit Interrupt Enable - bit 5
C1MCR5.TXIE_4           4   Transmit Interrupt Enable - bit 4
C1MCR5.RXIE_3           3   Receive Interrupt Enable - bit 3
C1MCR5.RXIE_2           2   Receive Interrupt Enable - bit 2
C1MCR5.INTPND_1         1   Interrupt Pending - bit 1
C1MCR5.INTPND_0         0   Interrupt Pending - bit 0
C1UAR5           0xEF52   CAN1 Upper Arbitration Reg. (msg. )
C1UAR5.ID20       15  Identifier 20
C1UAR5.ID19       14  Identifier 19
C1UAR5.ID18       13  Identifier 18
C1UAR5.ID17       12  Identifier 17
C1UAR5.ID16       11  Identifier 16
C1UAR5.ID15       10  Identifier 15
C1UAR5.ID14       9   Identifier 14
C1UAR5.ID13       8   Identifier 13
C1UAR5.ID28       7   Identifier 28
C1UAR5.ID27       6   Identifier 27
C1UAR5.ID26       5   Identifier 26
C1UAR5.ID25       4   Identifier 25
C1UAR5.ID24       3   Identifier 24
C1UAR5.ID23       2   Identifier 23
C1UAR5.ID22       1   Identifier 22
C1UAR5.ID21       0   Identifier 21
C1LAR5           0xEF54   CAN1 Lower Arbitration Register (msg. )
C1LAR5.ID4        15  Identifier 4 
C1LAR5.ID3        14  Identifier 3 
C1LAR5.ID2        13  Identifier 2 
C1LAR5.ID1        12  Identifier 1 
C1LAR5.ID0        11  Identifier 0 
C1LAR5.ID12       7   Identifier 12
C1LAR5.ID11       6   Identifier 11
C1LAR5.ID10       5   Identifier 10
C1LAR5.ID9        4   Identifier 9 
C1LAR5.ID8        3   Identifier 8 
C1LAR5.ID7        2   Identifier 7 
C1LAR5.ID6        1   Identifier 6 
C1LAR5.ID5        0   Identifier 5 
C1MCFG5          0xEF56   CAN1 Message Configuration Register (msg. )
C1MCFG5.DLC_7     7   Data Length Code - bit 7
C1MCFG5.DLC_6     6   Data Length Code - bit 6
C1MCFG5.DLC_5     5   Data Length Code - bit 5
C1MCFG5.DLC_4     4   Data Length Code - bit 4
C1MCFG5.DIR       3   Message Direction
C1MCFG5.XTD       2   Extended Identifier
C1MCR6           0xEF61   CAN1 Message Ctrl. Reg. (msg. )
C1MCR6.RMTPND_15        15  Remote Pending - bit 15
C1MCR6.RMTPND_14        14  Remote Pending - bit 14
C1MCR6.TXRQ_13          13  Transmit Request - bit 13
C1MCR6.TXRQ_12          12  Transmit Request - bit 12
C1MCR6.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C1MCR6.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C1MCR6.NEWDAT_9         9   New Data - bit 9
C1MCR6.NEWDAT_8         8   New Data - bit 8
C1MCR6.MSGVAL_7         7   Message Valid - bit 7
C1MCR6.MSGVAL_6         6   Message Valid - bit 6
C1MCR6.TXIE_5           5   Transmit Interrupt Enable - bit 5
C1MCR6.TXIE_4           4   Transmit Interrupt Enable - bit 4
C1MCR6.RXIE_3           3   Receive Interrupt Enable - bit 3
C1MCR6.RXIE_2           2   Receive Interrupt Enable - bit 2
C1MCR6.INTPND_1         1   Interrupt Pending - bit 1
C1MCR6.INTPND_0         0   Interrupt Pending - bit 0
C1UAR6           0xEF62   CAN1 Upper Arbitration Reg. (msg. )
C1UAR6.ID20       15  Identifier 20
C1UAR6.ID19       14  Identifier 19
C1UAR6.ID18       13  Identifier 18
C1UAR6.ID17       12  Identifier 17
C1UAR6.ID16       11  Identifier 16
C1UAR6.ID15       10  Identifier 15
C1UAR6.ID14       9   Identifier 14
C1UAR6.ID13       8   Identifier 13
C1UAR6.ID28       7   Identifier 28
C1UAR6.ID27       6   Identifier 27
C1UAR6.ID26       5   Identifier 26
C1UAR6.ID25       4   Identifier 25
C1UAR6.ID24       3   Identifier 24
C1UAR6.ID23       2   Identifier 23
C1UAR6.ID22       1   Identifier 22
C1UAR6.ID21       0   Identifier 21
C1LAR6           0xEF64   CAN1 Lower Arbitration Register (msg. )
C1LAR6.ID4        15  Identifier 4 
C1LAR6.ID3        14  Identifier 3 
C1LAR6.ID2        13  Identifier 2 
C1LAR6.ID1        12  Identifier 1 
C1LAR6.ID0        11  Identifier 0 
C1LAR6.ID12       7   Identifier 12
C1LAR6.ID11       6   Identifier 11
C1LAR6.ID10       5   Identifier 10
C1LAR6.ID9        4   Identifier 9 
C1LAR6.ID8        3   Identifier 8 
C1LAR6.ID7        2   Identifier 7 
C1LAR6.ID6        1   Identifier 6 
C1LAR6.ID5        0   Identifier 5 
C1MCFG6          0xEF66   CAN1 Message Configuration Register (msg. )
C1MCFG6.DLC_7     7   Data Length Code - bit 7
C1MCFG6.DLC_6     6   Data Length Code - bit 6
C1MCFG6.DLC_5     5   Data Length Code - bit 5
C1MCFG6.DLC_4     4   Data Length Code - bit 4
C1MCFG6.DIR       3   Message Direction
C1MCFG6.XTD       2   Extended Identifier
C1MCR7           0xEF71   CAN1 Message Ctrl. Reg. (msg. )
C1MCR7.RMTPND_15        15  Remote Pending - bit 15
C1MCR7.RMTPND_14        14  Remote Pending - bit 14
C1MCR7.TXRQ_13          13  Transmit Request - bit 13
C1MCR7.TXRQ_12          12  Transmit Request - bit 12
C1MCR7.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C1MCR7.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C1MCR7.NEWDAT_9         9   New Data - bit 9
C1MCR7.NEWDAT_8         8   New Data - bit 8
C1MCR7.MSGVAL_7         7   Message Valid - bit 7
C1MCR7.MSGVAL_6         6   Message Valid - bit 6
C1MCR7.TXIE_5           5   Transmit Interrupt Enable - bit 5
C1MCR7.TXIE_4           4   Transmit Interrupt Enable - bit 4
C1MCR7.RXIE_3           3   Receive Interrupt Enable - bit 3
C1MCR7.RXIE_2           2   Receive Interrupt Enable - bit 2
C1MCR7.INTPND_1         1   Interrupt Pending - bit 1
C1MCR7.INTPND_0         0   Interrupt Pending - bit 0
C1UAR7           0xEF72   CAN1 Upper Arbitration Reg. (msg. )
C1UAR7.ID20       15  Identifier 20
C1UAR7.ID19       14  Identifier 19
C1UAR7.ID18       13  Identifier 18
C1UAR7.ID17       12  Identifier 17
C1UAR7.ID16       11  Identifier 16
C1UAR7.ID15       10  Identifier 15
C1UAR7.ID14       9   Identifier 14
C1UAR7.ID13       8   Identifier 13
C1UAR7.ID28       7   Identifier 28
C1UAR7.ID27       6   Identifier 27
C1UAR7.ID26       5   Identifier 26
C1UAR7.ID25       4   Identifier 25
C1UAR7.ID24       3   Identifier 24
C1UAR7.ID23       2   Identifier 23
C1UAR7.ID22       1   Identifier 22
C1UAR7.ID21       0   Identifier 21
C1LAR7           0xEF74   CAN1 Lower Arbitration Register (msg. )
C1LAR7.ID4        15  Identifier 4 
C1LAR7.ID3        14  Identifier 3 
C1LAR7.ID2        13  Identifier 2 
C1LAR7.ID1        12  Identifier 1 
C1LAR7.ID0        11  Identifier 0 
C1LAR7.ID12       7   Identifier 12
C1LAR7.ID11       6   Identifier 11
C1LAR7.ID10       5   Identifier 10
C1LAR7.ID9        4   Identifier 9 
C1LAR7.ID8        3   Identifier 8 
C1LAR7.ID7        2   Identifier 7 
C1LAR7.ID6        1   Identifier 6 
C1LAR7.ID5        0   Identifier 5 
C1MCFG7          0xEF76   CAN1 Message Configuration Register (msg. )
C1MCFG7.DLC_7     7   Data Length Code - bit 7
C1MCFG7.DLC_6     6   Data Length Code - bit 6
C1MCFG7.DLC_5     5   Data Length Code - bit 5
C1MCFG7.DLC_4     4   Data Length Code - bit 4
C1MCFG7.DIR       3   Message Direction
C1MCFG7.XTD       2   Extended Identifier
C1MCR8           0xEF81   CAN1 Message Ctrl. Reg. (msg. )
C1MCR8.RMTPND_15        15  Remote Pending - bit 15
C1MCR8.RMTPND_14        14  Remote Pending - bit 14
C1MCR8.TXRQ_13          13  Transmit Request - bit 13
C1MCR8.TXRQ_12          12  Transmit Request - bit 12
C1MCR8.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C1MCR8.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C1MCR8.NEWDAT_9         9   New Data - bit 9
C1MCR8.NEWDAT_8         8   New Data - bit 8
C1MCR8.MSGVAL_7         7   Message Valid - bit 7
C1MCR8.MSGVAL_6         6   Message Valid - bit 6
C1MCR8.TXIE_5           5   Transmit Interrupt Enable - bit 5
C1MCR8.TXIE_4           4   Transmit Interrupt Enable - bit 4
C1MCR8.RXIE_3           3   Receive Interrupt Enable - bit 3
C1MCR8.RXIE_2           2   Receive Interrupt Enable - bit 2
C1MCR8.INTPND_1         1   Interrupt Pending - bit 1
C1MCR8.INTPND_0         0   Interrupt Pending - bit 0
C1UAR8           0xEF82   CAN1 Upper Arbitration Reg. (msg. )
C1UAR8.ID20       15  Identifier 20
C1UAR8.ID19       14  Identifier 19
C1UAR8.ID18       13  Identifier 18
C1UAR8.ID17       12  Identifier 17
C1UAR8.ID16       11  Identifier 16
C1UAR8.ID15       10  Identifier 15
C1UAR8.ID14       9   Identifier 14
C1UAR8.ID13       8   Identifier 13
C1UAR8.ID28       7   Identifier 28
C1UAR8.ID27       6   Identifier 27
C1UAR8.ID26       5   Identifier 26
C1UAR8.ID25       4   Identifier 25
C1UAR8.ID24       3   Identifier 24
C1UAR8.ID23       2   Identifier 23
C1UAR8.ID22       1   Identifier 22
C1UAR8.ID21       0   Identifier 21
C1LAR8           0xEF84   CAN1 Lower Arbitration Register (msg. )
C1LAR8.ID4        15  Identifier 4 
C1LAR8.ID3        14  Identifier 3 
C1LAR8.ID2        13  Identifier 2 
C1LAR8.ID1        12  Identifier 1 
C1LAR8.ID0        11  Identifier 0 
C1LAR8.ID12       7   Identifier 12
C1LAR8.ID11       6   Identifier 11
C1LAR8.ID10       5   Identifier 10
C1LAR8.ID9        4   Identifier 9 
C1LAR8.ID8        3   Identifier 8 
C1LAR8.ID7        2   Identifier 7 
C1LAR8.ID6        1   Identifier 6 
C1LAR8.ID5        0   Identifier 5 
C1MCFG8          0xEF86   CAN1 Message Configuration Register (msg. )
C1MCFG8.DLC_7     7   Data Length Code - bit 7
C1MCFG8.DLC_6     6   Data Length Code - bit 6
C1MCFG8.DLC_5     5   Data Length Code - bit 5
C1MCFG8.DLC_4     4   Data Length Code - bit 4
C1MCFG8.DIR       3   Message Direction
C1MCFG8.XTD       2   Extended Identifier
C1MCR9           0xEF91   CAN1 Message Ctrl. Reg. (msg. )
C1MCR9.RMTPND_15        15  Remote Pending - bit 15
C1MCR9.RMTPND_14        14  Remote Pending - bit 14
C1MCR9.TXRQ_13          13  Transmit Request - bit 13
C1MCR9.TXRQ_12          12  Transmit Request - bit 12
C1MCR9.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C1MCR9.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C1MCR9.NEWDAT_9         9   New Data - bit 9
C1MCR9.NEWDAT_8         8   New Data - bit 8
C1MCR9.MSGVAL_7         7   Message Valid - bit 7
C1MCR9.MSGVAL_6         6   Message Valid - bit 6
C1MCR9.TXIE_5           5   Transmit Interrupt Enable - bit 5
C1MCR9.TXIE_4           4   Transmit Interrupt Enable - bit 4
C1MCR9.RXIE_3           3   Receive Interrupt Enable - bit 3
C1MCR9.RXIE_2           2   Receive Interrupt Enable - bit 2
C1MCR9.INTPND_1         1   Interrupt Pending - bit 1
C1MCR9.INTPND_0         0   Interrupt Pending - bit 0
C1UAR9           0xEF92   CAN1 Upper Arbitration Reg. (msg. )
C1UAR9.ID20       15  Identifier 20
C1UAR9.ID19       14  Identifier 19
C1UAR9.ID18       13  Identifier 18
C1UAR9.ID17       12  Identifier 17
C1UAR9.ID16       11  Identifier 16
C1UAR9.ID15       10  Identifier 15
C1UAR9.ID14       9   Identifier 14
C1UAR9.ID13       8   Identifier 13
C1UAR9.ID28       7   Identifier 28
C1UAR9.ID27       6   Identifier 27
C1UAR9.ID26       5   Identifier 26
C1UAR9.ID25       4   Identifier 25
C1UAR9.ID24       3   Identifier 24
C1UAR9.ID23       2   Identifier 23
C1UAR9.ID22       1   Identifier 22
C1UAR9.ID21       0   Identifier 21
C1LAR9           0xEF94   CAN1 Lower Arbitration Register (msg. )
C1LAR9.ID4        15  Identifier 4 
C1LAR9.ID3        14  Identifier 3 
C1LAR9.ID2        13  Identifier 2 
C1LAR9.ID1        12  Identifier 1 
C1LAR9.ID0        11  Identifier 0 
C1LAR9.ID12       7   Identifier 12
C1LAR9.ID11       6   Identifier 11
C1LAR9.ID10       5   Identifier 10
C1LAR9.ID9        4   Identifier 9 
C1LAR9.ID8        3   Identifier 8 
C1LAR9.ID7        2   Identifier 7 
C1LAR9.ID6        1   Identifier 6 
C1LAR9.ID5        0   Identifier 5 
C1MCFG9          0xEF96   CAN1 Message Configuration Register (msg. )
C1MCFG9.DLC_7     7   Data Length Code - bit 7
C1MCFG9.DLC_6     6   Data Length Code - bit 6
C1MCFG9.DLC_5     5   Data Length Code - bit 5
C1MCFG9.DLC_4     4   Data Length Code - bit 4
C1MCFG9.DIR       3   Message Direction
C1MCFG9.XTD       2   Extended Identifier
C1MCR10          0xEFA1   CAN1 Message Ctrl. Reg. (msg. )
C1MCR10.RMTPND_15        15  Remote Pending - bit 15
C1MCR10.RMTPND_14        14  Remote Pending - bit 14
C1MCR10.TXRQ_13          13  Transmit Request - bit 13
C1MCR10.TXRQ_12          12  Transmit Request - bit 12
C1MCR10.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C1MCR10.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C1MCR10.NEWDAT_9         9   New Data - bit 9
C1MCR10.NEWDAT_8         8   New Data - bit 8
C1MCR10.MSGVAL_7         7   Message Valid - bit 7
C1MCR10.MSGVAL_6         6   Message Valid - bit 6
C1MCR10.TXIE_5           5   Transmit Interrupt Enable - bit 5
C1MCR10.TXIE_4           4   Transmit Interrupt Enable - bit 4
C1MCR10.RXIE_3           3   Receive Interrupt Enable - bit 3
C1MCR10.RXIE_2           2   Receive Interrupt Enable - bit 2
C1MCR10.INTPND_1         1   Interrupt Pending - bit 1
C1MCR10.INTPND_0         0   Interrupt Pending - bit 0
C1UAR10          0xEFA2   CAN1 Upper Arbitration Reg. (msg. )
C1UAR10.ID20      15  Identifier 20
C1UAR10.ID19      14  Identifier 19
C1UAR10.ID18      13  Identifier 18
C1UAR10.ID17      12  Identifier 17
C1UAR10.ID16      11  Identifier 16
C1UAR10.ID15      10  Identifier 15
C1UAR10.ID14      9   Identifier 14
C1UAR10.ID13      8   Identifier 13
C1UAR10.ID28      7   Identifier 28
C1UAR10.ID27      6   Identifier 27
C1UAR10.ID26      5   Identifier 26
C1UAR10.ID25      4   Identifier 25
C1UAR10.ID24      3   Identifier 24
C1UAR10.ID23      2   Identifier 23
C1UAR10.ID22      1   Identifier 22
C1UAR10.ID21      0   Identifier 21
C1LAR10          0xEFA4   CAN1 Lower Arbitration Register (msg. )
C1LAR10.ID4       15  Identifier 4
C1LAR10.ID3       14  Identifier 3
C1LAR10.ID2       13  Identifier 2
C1LAR10.ID1       12  Identifier 1
C1LAR10.ID0       11  Identifier 0
C1LAR10.ID12      7   Identifier 12
C1LAR10.ID11      6   Identifier 11
C1LAR10.ID10      5   Identifier 10
C1LAR10.ID9       4   Identifier 9
C1LAR10.ID8       3   Identifier 8
C1LAR10.ID7       2   Identifier 7
C1LAR10.ID6       1   Identifier 6
C1LAR10.ID5       0   Identifier 5
C1MCFG10         0xEFA6   CAN1 Message Configuration Register (msg. )
C1MCFG10.DLC_7    7   Data Length Code - bit 7
C1MCFG10.DLC_6    6   Data Length Code - bit 6
C1MCFG10.DLC_5    5   Data Length Code - bit 5
C1MCFG10.DLC_4    4   Data Length Code - bit 4
C1MCFG10.DIR      3   Message Direction
C1MCFG10.XTD      2   Extended Identifier
C1MCR11          0xEFB1   CAN1 Message Ctrl. Reg. (msg. )
C1MCR11.RMTPND_15        15  Remote Pending - bit 15
C1MCR11.RMTPND_14        14  Remote Pending - bit 14
C1MCR11.TXRQ_13          13  Transmit Request - bit 13
C1MCR11.TXRQ_12          12  Transmit Request - bit 12
C1MCR11.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C1MCR11.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C1MCR11.NEWDAT_9         9   New Data - bit 9
C1MCR11.NEWDAT_8         8   New Data - bit 8
C1MCR11.MSGVAL_7         7   Message Valid - bit 7
C1MCR11.MSGVAL_6         6   Message Valid - bit 6
C1MCR11.TXIE_5           5   Transmit Interrupt Enable - bit 5
C1MCR11.TXIE_4           4   Transmit Interrupt Enable - bit 4
C1MCR11.RXIE_3           3   Receive Interrupt Enable - bit 3
C1MCR11.RXIE_2           2   Receive Interrupt Enable - bit 2
C1MCR11.INTPND_1         1   Interrupt Pending - bit 1
C1MCR11.INTPND_0         0   Interrupt Pending - bit 0
C1UAR11          0xEFB2   CAN1 Upper Arbitration Reg. (msg. )
C1UAR11.ID20      15  Identifier 20
C1UAR11.ID19      14  Identifier 19
C1UAR11.ID18      13  Identifier 18
C1UAR11.ID17      12  Identifier 17
C1UAR11.ID16      11  Identifier 16
C1UAR11.ID15      10  Identifier 15
C1UAR11.ID14      9   Identifier 14
C1UAR11.ID13      8   Identifier 13
C1UAR11.ID28      7   Identifier 28
C1UAR11.ID27      6   Identifier 27
C1UAR11.ID26      5   Identifier 26
C1UAR11.ID25      4   Identifier 25
C1UAR11.ID24      3   Identifier 24
C1UAR11.ID23      2   Identifier 23
C1UAR11.ID22      1   Identifier 22
C1UAR11.ID21      0   Identifier 21
C1LAR11          0xEFB4   CAN1 Lower Arbitration Register (msg. )
C1LAR11.ID4       15  Identifier 4
C1LAR11.ID3       14  Identifier 3
C1LAR11.ID2       13  Identifier 2
C1LAR11.ID1       12  Identifier 1
C1LAR11.ID0       11  Identifier 0
C1LAR11.ID12      7   Identifier 12
C1LAR11.ID11      6   Identifier 11
C1LAR11.ID10      5   Identifier 10
C1LAR11.ID9       4   Identifier 9
C1LAR11.ID8       3   Identifier 8
C1LAR11.ID7       2   Identifier 7
C1LAR11.ID6       1   Identifier 6
C1LAR11.ID5       0   Identifier 5
C1MCFG11         0xEFB6   CAN1 Message Configuration Register (msg. )
C1MCFG11.DLC_7    7   Data Length Code - bit 7
C1MCFG11.DLC_6    6   Data Length Code - bit 6
C1MCFG11.DLC_5    5   Data Length Code - bit 5
C1MCFG11.DLC_4    4   Data Length Code - bit 4
C1MCFG11.DIR      3   Message Direction
C1MCFG11.XTD      2   Extended Identifier
C1MCR12          0xEFC1   CAN1 Message Ctrl. Reg. (msg. )
C1MCR12.RMTPND_15        15  Remote Pending - bit 15
C1MCR12.RMTPND_14        14  Remote Pending - bit 14
C1MCR12.TXRQ_13          13  Transmit Request - bit 13
C1MCR12.TXRQ_12          12  Transmit Request - bit 12
C1MCR12.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C1MCR12.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C1MCR12.NEWDAT_9         9   New Data - bit 9
C1MCR12.NEWDAT_8         8   New Data - bit 8
C1MCR12.MSGVAL_7         7   Message Valid - bit 7
C1MCR12.MSGVAL_6         6   Message Valid - bit 6
C1MCR12.TXIE_5           5   Transmit Interrupt Enable - bit 5
C1MCR12.TXIE_4           4   Transmit Interrupt Enable - bit 4
C1MCR12.RXIE_3           3   Receive Interrupt Enable - bit 3
C1MCR12.RXIE_2           2   Receive Interrupt Enable - bit 2
C1MCR12.INTPND_1         1   Interrupt Pending - bit 1
C1MCR12.INTPND_0         0   Interrupt Pending - bit 0
C1UAR12          0xEFC1   CAN1 Upper Arbitration Reg. (msg. )
C1UAR12.ID20      15  Identifier 20
C1UAR12.ID19      14  Identifier 19
C1UAR12.ID18      13  Identifier 18
C1UAR12.ID17      12  Identifier 17
C1UAR12.ID16      11  Identifier 16
C1UAR12.ID15      10  Identifier 15
C1UAR12.ID14      9   Identifier 14
C1UAR12.ID13      8   Identifier 13
C1UAR12.ID28      7   Identifier 28
C1UAR12.ID27      6   Identifier 27
C1UAR12.ID26      5   Identifier 26
C1UAR12.ID25      4   Identifier 25
C1UAR12.ID24      3   Identifier 24
C1UAR12.ID23      2   Identifier 23
C1UAR12.ID22      1   Identifier 22
C1UAR12.ID21      0   Identifier 21
C1LAR12          0xEFC4   CAN1 Lower Arbitration Register (msg. )
C1LAR12.ID4       15  Identifier 4
C1LAR12.ID3       14  Identifier 3
C1LAR12.ID2       13  Identifier 2
C1LAR12.ID1       12  Identifier 1
C1LAR12.ID0       11  Identifier 0
C1LAR12.ID12      7   Identifier 12
C1LAR12.ID11      6   Identifier 11
C1LAR12.ID10      5   Identifier 10
C1LAR12.ID9       4   Identifier 9
C1LAR12.ID8       3   Identifier 8
C1LAR12.ID7       2   Identifier 7
C1LAR12.ID6       1   Identifier 6
C1LAR12.ID5       0   Identifier 5
C1MCFG12         0xEFC6   CAN1 Message Configuration Register (msg. )
C1MCFG12.DLC_7    7   Data Length Code - bit 7
C1MCFG12.DLC_6    6   Data Length Code - bit 6
C1MCFG12.DLC_5    5   Data Length Code - bit 5
C1MCFG12.DLC_4    4   Data Length Code - bit 4
C1MCFG12.DIR      3   Message Direction
C1MCFG12.XTD      2   Extended Identifier
C1MCR13          0xEFD1   CAN1 Message Ctrl. Reg. (msg. )
C1MCR13.RMTPND_15        15  Remote Pending - bit 15
C1MCR13.RMTPND_14        14  Remote Pending - bit 14
C1MCR13.TXRQ_13          13  Transmit Request - bit 13
C1MCR13.TXRQ_12          12  Transmit Request - bit 12
C1MCR13.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C1MCR13.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C1MCR13.NEWDAT_9         9   New Data - bit 9
C1MCR13.NEWDAT_8         8   New Data - bit 8
C1MCR13.MSGVAL_7         7   Message Valid - bit 7
C1MCR13.MSGVAL_6         6   Message Valid - bit 6
C1MCR13.TXIE_5           5   Transmit Interrupt Enable - bit 5
C1MCR13.TXIE_4           4   Transmit Interrupt Enable - bit 4
C1MCR13.RXIE_3           3   Receive Interrupt Enable - bit 3
C1MCR13.RXIE_2           2   Receive Interrupt Enable - bit 2
C1MCR13.INTPND_1         1   Interrupt Pending - bit 1
C1MCR13.INTPND_0         0   Interrupt Pending - bit 0
C1UAR13          0xEFD2   CAN1 Upper Arbitration Reg. (msg. )
C1UAR13.ID20      15  Identifier 20
C1UAR13.ID19      14  Identifier 19
C1UAR13.ID18      13  Identifier 18
C1UAR13.ID17      12  Identifier 17
C1UAR13.ID16      11  Identifier 16
C1UAR13.ID15      10  Identifier 15
C1UAR13.ID14      9   Identifier 14
C1UAR13.ID13      8   Identifier 13
C1UAR13.ID28      7   Identifier 28
C1UAR13.ID27      6   Identifier 27
C1UAR13.ID26      5   Identifier 26
C1UAR13.ID25      4   Identifier 25
C1UAR13.ID24      3   Identifier 24
C1UAR13.ID23      2   Identifier 23
C1UAR13.ID22      1   Identifier 22
C1UAR13.ID21      0   Identifier 21
C1LAR13          0xEFD4   CAN1 Lower Arbitration Register (msg. )
C1LAR13.ID4       15  Identifier 4
C1LAR13.ID3       14  Identifier 3
C1LAR13.ID2       13  Identifier 2
C1LAR13.ID1       12  Identifier 1
C1LAR13.ID0       11  Identifier 0
C1LAR13.ID12      7   Identifier 12
C1LAR13.ID11      6   Identifier 11
C1LAR13.ID10      5   Identifier 10
C1LAR13.ID9       4   Identifier 9
C1LAR13.ID8       3   Identifier 8
C1LAR13.ID7       2   Identifier 7
C1LAR13.ID6       1   Identifier 6
C1LAR13.ID5       0   Identifier 5
C1MCFG13         0xEFD6   CAN1 Message Configuration Register (msg. )
C1MCFG13.DLC_7    7   Data Length Code - bit 7
C1MCFG13.DLC_6    6   Data Length Code - bit 6
C1MCFG13.DLC_5    5   Data Length Code - bit 5
C1MCFG13.DLC_4    4   Data Length Code - bit 4
C1MCFG13.DIR      3   Message Direction
C1MCFG13.XTD      2   Extended Identifier
C1MCR14          0xEFE1   CAN1 Message Ctrl. Reg. (msg. )
C1MCR14.RMTPND_15        15  Remote Pending - bit 15
C1MCR14.RMTPND_14        14  Remote Pending - bit 14
C1MCR14.TXRQ_13          13  Transmit Request - bit 13
C1MCR14.TXRQ_12          12  Transmit Request - bit 12
C1MCR14.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C1MCR14.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C1MCR14.NEWDAT_9         9   New Data - bit 9
C1MCR14.NEWDAT_8         8   New Data - bit 8
C1MCR14.MSGVAL_7         7   Message Valid - bit 7
C1MCR14.MSGVAL_6         6   Message Valid - bit 6
C1MCR14.TXIE_5           5   Transmit Interrupt Enable - bit 5
C1MCR14.TXIE_4           4   Transmit Interrupt Enable - bit 4
C1MCR14.RXIE_3           3   Receive Interrupt Enable - bit 3
C1MCR14.RXIE_2           2   Receive Interrupt Enable - bit 2
C1MCR14.INTPND_1         1   Interrupt Pending - bit 1
C1MCR14.INTPND_0         0   Interrupt Pending - bit 0
C1UAR14          0xEFE2   CAN1 Upper Arbitration Reg. (msg. )
C1UAR14.ID20      15  Identifier 20
C1UAR14.ID19      14  Identifier 19
C1UAR14.ID18      13  Identifier 18
C1UAR14.ID17      12  Identifier 17
C1UAR14.ID16      11  Identifier 16
C1UAR14.ID15      10  Identifier 15
C1UAR14.ID14      9   Identifier 14
C1UAR14.ID13      8   Identifier 13
C1UAR14.ID28      7   Identifier 28
C1UAR14.ID27      6   Identifier 27
C1UAR14.ID26      5   Identifier 26
C1UAR14.ID25      4   Identifier 25
C1UAR14.ID24      3   Identifier 24
C1UAR14.ID23      2   Identifier 23
C1UAR14.ID22      1   Identifier 22
C1UAR14.ID21      0   Identifier 21
C1LAR14          0xEFE4   CAN1 Lower Arbitration Register (msg. )
C1LAR14.ID4       15  Identifier 4
C1LAR14.ID3       14  Identifier 3
C1LAR14.ID2       13  Identifier 2
C1LAR14.ID1       12  Identifier 1
C1LAR14.ID0       11  Identifier 0
C1LAR14.ID12      7   Identifier 12
C1LAR14.ID11      6   Identifier 11
C1LAR14.ID10      5   Identifier 10
C1LAR14.ID9       4   Identifier 9
C1LAR14.ID8       3   Identifier 8
C1LAR14.ID7       2   Identifier 7
C1LAR14.ID6       1   Identifier 6
C1LAR14.ID5       0   Identifier 5
C1MCFG14         0xEFE6   CAN1 Message Configuration Register (msg. )
C1MCFG14.DLC_7    7   Data Length Code - bit 7
C1MCFG14.DLC_6    6   Data Length Code - bit 6
C1MCFG14.DLC_5    5   Data Length Code - bit 5
C1MCFG14.DLC_4    4   Data Length Code - bit 4
C1MCFG14.DIR      3   Message Direction
C1MCFG14.XTD      2   Extended Identifier
C1MCR15          0xEFF1   CAN1 Message Ctrl. Reg. (msg. )
C1MCR15.RMTPND_15        15  Remote Pending - bit 15
C1MCR15.RMTPND_14        14  Remote Pending - bit 14
C1MCR15.TXRQ_13          13  Transmit Request - bit 13
C1MCR15.TXRQ_12          12  Transmit Request - bit 12
C1MCR15.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C1MCR15.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C1MCR15.NEWDAT_9         9   New Data - bit 9
C1MCR15.NEWDAT_8         8   New Data - bit 8
C1MCR15.MSGVAL_7         7   Message Valid - bit 7
C1MCR15.MSGVAL_6         6   Message Valid - bit 6
C1MCR15.TXIE_5           5   Transmit Interrupt Enable - bit 5
C1MCR15.TXIE_4           4   Transmit Interrupt Enable - bit 4
C1MCR15.RXIE_3           3   Receive Interrupt Enable - bit 3
C1MCR15.RXIE_2           2   Receive Interrupt Enable - bit 2
C1MCR15.INTPND_1         1   Interrupt Pending - bit 1
C1MCR15.INTPND_0         0   Interrupt Pending - bit 0
C1UAR15          0xEFF2   CAN1 Upper Arbitration Reg. (msg. )
C1UAR15.ID20      15  Identifier 20
C1UAR15.ID19      14  Identifier 19
C1UAR15.ID18      13  Identifier 18
C1UAR15.ID17      12  Identifier 17
C1UAR15.ID16      11  Identifier 16
C1UAR15.ID15      10  Identifier 15
C1UAR15.ID14      9   Identifier 14
C1UAR15.ID13      8   Identifier 13
C1UAR15.ID28      7   Identifier 28
C1UAR15.ID27      6   Identifier 27
C1UAR15.ID26      5   Identifier 26
C1UAR15.ID25      4   Identifier 25
C1UAR15.ID24      3   Identifier 24
C1UAR15.ID23      2   Identifier 23
C1UAR15.ID22      1   Identifier 22
C1UAR15.ID21      0   Identifier 21
C1LAR15          0xEFF4   CAN1 Lower Arbitration Register (msg. )
C1LAR15.ID4       15  Identifier 4
C1LAR15.ID3       14  Identifier 3
C1LAR15.ID2       13  Identifier 2
C1LAR15.ID1       12  Identifier 1
C1LAR15.ID0       11  Identifier 0
C1LAR15.ID12      7   Identifier 12
C1LAR15.ID11      6   Identifier 11
C1LAR15.ID10      5   Identifier 10
C1LAR15.ID9       4   Identifier 9
C1LAR15.ID8       3   Identifier 8
C1LAR15.ID7       2   Identifier 7
C1LAR15.ID6       1   Identifier 6
C1LAR15.ID5       0   Identifier 5
C1MCFG15         0xEFF6   CAN1 Message Configuration Register (msg. )
C1MCFG15.DLC_7    7   Data Length Code - bit 7
C1MCFG15.DLC_6    6   Data Length Code - bit 6
C1MCFG15.DLC_5    5   Data Length Code - bit 5
C1MCFG15.DLC_4    4   Data Length Code - bit 4
C1MCFG15.DIR      3   Message Direction
C1MCFG15.XTD      2   Extended Identifier
T7               0xF050   CAPCOM Timer 7 Register
T8               0xF052   CAPCOM Timer 8 Register
T7REL            0xF054   CAPCOM Timer 7 Reload Register
T8REL            0xF056   CAPCOM Timer 8 Reload Register
IDPROG           0xF078   Identifier
IDMEM            0xF07A   Identifier
IDCHIP           0xF07C   Identifier
IDMANUF          0xF07E   Identifier
POCON0L          0xF080   Port P0L Output Control Register
POCON0L.PN3DC_15  15  Port Nibble 3 Driver Characteristic - bit 15
POCON0L.PN3DC_14  14  Port Nibble 3 Edge Characteristic - bit 14
POCON0L.PN3EC_13  13  Port Nibble 3 Driver Characteristic - bit 13
POCON0L.PN3EC_12  12  Port Nibble 3 Edge Characteristic - bit 12
POCON0L.PN2DC_11  11  Port Nibble 2 Driver Characteristic - bit 11
POCON0L.PN2DC_10  10  Port Nibble 2 Edge Characteristic - bit 10
POCON0L.PN2EC_9   9   Port Nibble 2 Driver Characteristic - bit 9 
POCON0L.PN2EC_8   8   Port Nibble 2 Edge Characteristic - bit 8 
POCON0L.PN1DC_7   7   Port Nibble 1 Driver Characteristic - bit 7 
POCON0L.PN1DC_6   6   Port Nibble 1 Edge Characteristic - bit 6 
POCON0L.PN1EC_5   5   Port Nibble 1 Driver Characteristic - bit 5 
POCON0L.PN1EC_4   4   Port Nibble 1 Edge Characteristic - bit 4 
POCON0L.PN0DC_3   3   Port Nibble 0 Driver Characteristic - bit 3 
POCON0L.PN0DC_2   2   Port Nibble 0 Edge Characteristic - bit 2 
POCON0L.PN0EC_1   1   Port Nibble 0 Driver Characteristic - bit 1 
POCON0L.PN0EC_0   0   Port Nibble 0 Edge Characteristic - bit 0 
POCON0H          0xF082   Port P0H Output Control Register
POCON0H.PN3DC_15  15  Port Nibble 3 Driver Characteristic - bit 15
POCON0H.PN3DC_14  14  Port Nibble 3 Edge Characteristic - bit 14
POCON0H.PN3EC_13  13  Port Nibble 3 Driver Characteristic - bit 13
POCON0H.PN3EC_12  12  Port Nibble 3 Edge Characteristic - bit 12
POCON0H.PN2DC_11  11  Port Nibble 2 Driver Characteristic - bit 11
POCON0H.PN2DC_10  10  Port Nibble 2 Edge Characteristic - bit 10
POCON0H.PN2EC_9   9   Port Nibble 2 Driver Characteristic - bit 9 
POCON0H.PN2EC_8   8   Port Nibble 2 Edge Characteristic - bit 8 
POCON0H.PN1DC_7   7   Port Nibble 1 Driver Characteristic - bit 7 
POCON0H.PN1DC_6   6   Port Nibble 1 Edge Characteristic - bit 6 
POCON0H.PN1EC_5   5   Port Nibble 1 Driver Characteristic - bit 5 
POCON0H.PN1EC_4   4   Port Nibble 1 Edge Characteristic - bit 4 
POCON0H.PN0DC_3   3   Port Nibble 0 Driver Characteristic - bit 3 
POCON0H.PN0DC_2   2   Port Nibble 0 Edge Characteristic - bit 2 
POCON0H.PN0EC_1   1   Port Nibble 0 Driver Characteristic - bit 1 
POCON0H.PN0EC_0   0   Port Nibble 0 Edge Characteristic - bit 0 
POCON1L          0xF084   Port P1L Output Control Register
POCON1L.PN3DC_15  15  Port Nibble 3 Driver Characteristic - bit 15
POCON1L.PN3DC_14  14  Port Nibble 3 Edge Characteristic - bit 14
POCON1L.PN3EC_13  13  Port Nibble 3 Driver Characteristic - bit 13
POCON1L.PN3EC_12  12  Port Nibble 3 Edge Characteristic - bit 12
POCON1L.PN2DC_11  11  Port Nibble 2 Driver Characteristic - bit 11
POCON1L.PN2DC_10  10  Port Nibble 2 Edge Characteristic - bit 10
POCON1L.PN2EC_9   9   Port Nibble 2 Driver Characteristic - bit 9 
POCON1L.PN2EC_8   8   Port Nibble 2 Edge Characteristic - bit 8 
POCON1L.PN1DC_7   7   Port Nibble 1 Driver Characteristic - bit 7 
POCON1L.PN1DC_6   6   Port Nibble 1 Edge Characteristic - bit 6 
POCON1L.PN1EC_5   5   Port Nibble 1 Driver Characteristic - bit 5 
POCON1L.PN1EC_4   4   Port Nibble 1 Edge Characteristic - bit 4 
POCON1L.PN0DC_3   3   Port Nibble 0 Driver Characteristic - bit 3 
POCON1L.PN0DC_2   2   Port Nibble 0 Edge Characteristic - bit 2 
POCON1L.PN0EC_1   1   Port Nibble 0 Driver Characteristic - bit 1 
POCON1L.PN0EC_0   0   Port Nibble 0 Edge Characteristic - bit 0 
POCON1H          0xF086   Port P1H Output Control Register
POCON1H.PN3DC_15  15  Port Nibble 3 Driver Characteristic - bit 15
POCON1H.PN3DC_14  14  Port Nibble 3 Edge Characteristic - bit 14
POCON1H.PN3EC_13  13  Port Nibble 3 Driver Characteristic - bit 13
POCON1H.PN3EC_12  12  Port Nibble 3 Edge Characteristic - bit 12
POCON1H.PN2DC_11  11  Port Nibble 2 Driver Characteristic - bit 11
POCON1H.PN2DC_10  10  Port Nibble 2 Edge Characteristic - bit 10
POCON1H.PN2EC_9   9   Port Nibble 2 Driver Characteristic - bit 9 
POCON1H.PN2EC_8   8   Port Nibble 2 Edge Characteristic - bit 8 
POCON1H.PN1DC_7   7   Port Nibble 1 Driver Characteristic - bit 7 
POCON1H.PN1DC_6   6   Port Nibble 1 Edge Characteristic - bit 6 
POCON1H.PN1EC_5   5   Port Nibble 1 Driver Characteristic - bit 5 
POCON1H.PN1EC_4   4   Port Nibble 1 Edge Characteristic - bit 4 
POCON1H.PN0DC_3   3   Port Nibble 0 Driver Characteristic - bit 3 
POCON1H.PN0DC_2   2   Port Nibble 0 Edge Characteristic - bit 2 
POCON1H.PN0EC_1   1   Port Nibble 0 Driver Characteristic - bit 1 
POCON1H.PN0EC_0   0   Port Nibble 0 Edge Characteristic - bit 0 
POCON2           0xF088   Port P2 Output Control Register
POCON2.PN3DC_15   15  Port Nibble 3 Driver Characteristic - bit 15
POCON2.PN3DC_14   14  Port Nibble 3 Edge Characteristic - bit 14
POCON2.PN3EC_13   13  Port Nibble 3 Driver Characteristic - bit 13
POCON2.PN3EC_12   12  Port Nibble 3 Edge Characteristic - bit 12
POCON2.PN2DC_11   11  Port Nibble 2 Driver Characteristic - bit 11
POCON2.PN2DC_10   10  Port Nibble 2 Edge Characteristic - bit 10
POCON2.PN2EC_9    9   Port Nibble 2 Driver Characteristic - bit 9
POCON2.PN2EC_8    8   Port Nibble 2 Edge Characteristic - bit 8
POCON2.PN1DC_7    7   Port Nibble 1 Driver Characteristic - bit 7
POCON2.PN1DC_6    6   Port Nibble 1 Edge Characteristic - bit 6
POCON2.PN1EC_5    5   Port Nibble 1 Driver Characteristic - bit 5
POCON2.PN1EC_4    4   Port Nibble 1 Edge Characteristic - bit 4
POCON2.PN0DC_3    3   Port Nibble 0 Driver Characteristic - bit 3
POCON2.PN0DC_2    2   Port Nibble 0 Edge Characteristic - bit 2
POCON2.PN0EC_1    1   Port Nibble 0 Driver Characteristic - bit 1
POCON2.PN0EC_0    0   Port Nibble 0 Edge Characteristic - bit 0
POCON3           0xF08A   Port P3 Output Control Register
POCON3.PN3DC_15   15  Port Nibble 3 Driver Characteristic - bit 15
POCON3.PN3DC_14   14  Port Nibble 3 Edge Characteristic - bit 14
POCON3.PN3EC_13   13  Port Nibble 3 Driver Characteristic - bit 13
POCON3.PN3EC_12   12  Port Nibble 3 Edge Characteristic - bit 12
POCON3.PN2DC_11   11  Port Nibble 2 Driver Characteristic - bit 11
POCON3.PN2DC_10   10  Port Nibble 2 Edge Characteristic - bit 10
POCON3.PN2EC_9    9   Port Nibble 2 Driver Characteristic - bit 9
POCON3.PN2EC_8    8   Port Nibble 2 Edge Characteristic - bit 8
POCON3.PN1DC_7    7   Port Nibble 1 Driver Characteristic - bit 7
POCON3.PN1DC_6    6   Port Nibble 1 Edge Characteristic - bit 6
POCON3.PN1EC_5    5   Port Nibble 1 Driver Characteristic - bit 5
POCON3.PN1EC_4    4   Port Nibble 1 Edge Characteristic - bit 4
POCON3.PN0DC_3    3   Port Nibble 0 Driver Characteristic - bit 3
POCON3.PN0DC_2    2   Port Nibble 0 Edge Characteristic - bit 2
POCON3.PN0EC_1    1   Port Nibble 0 Driver Characteristic - bit 1
POCON3.PN0EC_0    0   Port Nibble 0 Edge Characteristic - bit 0
POCON4           0xF08C   Port P4 Output Control Register
POCON4.PN3DC_15   15  Port Nibble 3 Driver Characteristic - bit 15
POCON4.PN3DC_14   14  Port Nibble 3 Edge Characteristic - bit 14
POCON4.PN3EC_13   13  Port Nibble 3 Driver Characteristic - bit 13
POCON4.PN3EC_12   12  Port Nibble 3 Edge Characteristic - bit 12
POCON4.PN2DC_11   11  Port Nibble 2 Driver Characteristic - bit 11
POCON4.PN2DC_10   10  Port Nibble 2 Edge Characteristic - bit 10
POCON4.PN2EC_9    9   Port Nibble 2 Driver Characteristic - bit 9
POCON4.PN2EC_8    8   Port Nibble 2 Edge Characteristic - bit 8
POCON4.PN1DC_7    7   Port Nibble 1 Driver Characteristic - bit 7
POCON4.PN1DC_6    6   Port Nibble 1 Edge Characteristic - bit 6
POCON4.PN1EC_5    5   Port Nibble 1 Driver Characteristic - bit 5
POCON4.PN1EC_4    4   Port Nibble 1 Edge Characteristic - bit 4
POCON4.PN0DC_3    3   Port Nibble 0 Driver Characteristic - bit 3
POCON4.PN0DC_2    2   Port Nibble 0 Edge Characteristic - bit 2
POCON4.PN0EC_1    1   Port Nibble 0 Driver Characteristic - bit 1
POCON4.PN0EC_0    0   Port Nibble 0 Edge Characteristic - bit 0
POCON6           0xF08E   Port P6 Output Control Register
POCON6.PN3DC_15   15  Port Nibble 3 Driver Characteristic - bit 15
POCON6.PN3DC_14   14  Port Nibble 3 Edge Characteristic - bit 14
POCON6.PN3EC_13   13  Port Nibble 3 Driver Characteristic - bit 13
POCON6.PN3EC_12   12  Port Nibble 3 Edge Characteristic - bit 12
POCON6.PN2DC_11   11  Port Nibble 2 Driver Characteristic - bit 11
POCON6.PN2DC_10   10  Port Nibble 2 Edge Characteristic - bit 10
POCON6.PN2EC_9    9   Port Nibble 2 Driver Characteristic - bit 9
POCON6.PN2EC_8    8   Port Nibble 2 Edge Characteristic - bit 8
POCON6.PN1DC_7    7   Port Nibble 1 Driver Characteristic - bit 7
POCON6.PN1DC_6    6   Port Nibble 1 Edge Characteristic - bit 6
POCON6.PN1EC_5    5   Port Nibble 1 Driver Characteristic - bit 5
POCON6.PN1EC_4    4   Port Nibble 1 Edge Characteristic - bit 4
POCON6.PN0DC_3    3   Port Nibble 0 Driver Characteristic - bit 3
POCON6.PN0DC_2    2   Port Nibble 0 Edge Characteristic - bit 2
POCON6.PN0EC_1    1   Port Nibble 0 Driver Characteristic - bit 1
POCON6.PN0EC_0    0   Port Nibble 0 Edge Characteristic - bit 0
POCON7           0xF090   Port P7 Output Control Register
POCON7.PN3DC_15   15  Port Nibble 3 Driver Characteristic - bit 15
POCON7.PN3DC_14   14  Port Nibble 3 Edge Characteristic - bit 14
POCON7.PN3EC_13   13  Port Nibble 3 Driver Characteristic - bit 13
POCON7.PN3EC_12   12  Port Nibble 3 Edge Characteristic - bit 12
POCON7.PN2DC_11   11  Port Nibble 2 Driver Characteristic - bit 11
POCON7.PN2DC_10   10  Port Nibble 2 Edge Characteristic - bit 10
POCON7.PN2EC_9    9   Port Nibble 2 Driver Characteristic - bit 9
POCON7.PN2EC_8    8   Port Nibble 2 Edge Characteristic - bit 8
POCON7.PN1DC_7    7   Port Nibble 1 Driver Characteristic - bit 7
POCON7.PN1DC_6    6   Port Nibble 1 Edge Characteristic - bit 6
POCON7.PN1EC_5    5   Port Nibble 1 Driver Characteristic - bit 5
POCON7.PN1EC_4    4   Port Nibble 1 Edge Characteristic - bit 4
POCON7.PN0DC_3    3   Port Nibble 0 Driver Characteristic - bit 3
POCON7.PN0DC_2    2   Port Nibble 0 Edge Characteristic - bit 2
POCON7.PN0EC_1    1   Port Nibble 0 Driver Characteristic - bit 1
POCON7.PN0EC_0    0   Port Nibble 0 Edge Characteristic - bit 0
ADDAT2           0xF0A0   A/D Converter 2 Result Register
ADDAT2.CHNR_15    15  Channel Number - bit 15
ADDAT2.CHNR_14    14  Channel Number - bit 14
ADDAT2.CHNR_13    13  Channel Number - bit 13
ADDAT2.CHNR_12    12  Channel Number - bit 12
ADDAT2.ADRES_9    9   A/D Conversion Result - bit 9
ADDAT2.ADRES_8    8   A/D Conversion Result - bit 8
ADDAT2.ADRES_7    7   A/D Conversion Result - bit 7
ADDAT2.ADRES_6    6   A/D Conversion Result - bit 6
ADDAT2.ADRES_5    5   A/D Conversion Result - bit 5
ADDAT2.ADRES_4    4   A/D Conversion Result - bit 4
ADDAT2.ADRES_3    3   A/D Conversion Result - bit 3
ADDAT2.ADRES_2    2   A/D Conversion Result - bit 2
ADDAT2.ADRES_1    1   A/D Conversion Result - bit 1
ADDAT2.ADRES_0    0   A/D Conversion Result - bit 0
POCON20          0xF0AA   Dedicated Pin Output Control Register
POCON20.PN3DC_15  15  Port Nibble 3 Driver Characteristic - bit 15
POCON20.PN3DC_14  14  Port Nibble 3 Edge Characteristic - bit 14
POCON20.PN3EC_13  13  Port Nibble 3 Driver Characteristic - bit 13
POCON20.PN3EC_12  12  Port Nibble 3 Edge Characteristic - bit 12
POCON20.PN2DC_11  11  Port Nibble 2 Driver Characteristic - bit 11
POCON20.PN2DC_10  10  Port Nibble 2 Edge Characteristic - bit 10
POCON20.PN2EC_9   9   Port Nibble 2 Driver Characteristic - bit 9
POCON20.PN2EC_8   8   Port Nibble 2 Edge Characteristic - bit 8
POCON20.PN1DC_7   7   Port Nibble 1 Driver Characteristic - bit 7
POCON20.PN1DC_6   6   Port Nibble 1 Edge Characteristic - bit 6
POCON20.PN1EC_5   5   Port Nibble 1 Driver Characteristic - bit 5
POCON20.PN1EC_4   4   Port Nibble 1 Edge Characteristic - bit 4
POCON20.PN0DC_3   3   Port Nibble 0 Driver Characteristic - bit 3
POCON20.PN0DC_2   2   Port Nibble 0 Edge Characteristic - bit 2
POCON20.PN0EC_1   1   Port Nibble 0 Driver Characteristic - bit 1
POCON20.PN0EC_0   0   Port Nibble 0 Edge Characteristic - bit 0
SSCTB            0xF0B0   SSC Transmit Buffer
SSCRB            0xF0B2   SSC Receive Buffer
SSCBR            0xF0B4   SSC Baudrate Register
T14REL           0xF0D0   RTC Timer 14 Reload Register
T14              0xF0D2   RTC Timer 14 Register
RTCL             0xF0D4   RTC Low Register
RTCH             0xF0D6   RTC High Register
DP0L             0xF100   P0L Direction Control Register
DP0L.DP0L7        7   Port direction register DP0L bit 7
DP0L.DP0L6        6   Port direction register DP0L bit 6
DP0L.DP0L5        5   Port direction register DP0L bit 5
DP0L.DP0L4        4   Port direction register DP0L bit 4
DP0L.DP0L3        3   Port direction register DP0L bit 3
DP0L.DP0L2        2   Port direction register DP0L bit 2
DP0L.DP0L1        1   Port direction register DP0L bit 1
DP0L.DP0L0        0   Port direction register DP0L bit 0
DP0H             0xF102   P0H Direction Control Register
DP0H.DP0H7        7   Port direction register DP0H bit 7
DP0H.DP0H6        6   Port direction register DP0H bit 6
DP0H.DP0H5        5   Port direction register DP0H bit 5
DP0H.DP0H4        4   Port direction register DP0H bit 4
DP0H.DP0H3        3   Port direction register DP0H bit 3
DP0H.DP0H2        2   Port direction register DP0H bit 2
DP0H.DP0H1        1   Port direction register DP0H bit 1
DP0H.DP0H0        0   Port direction register DP0H bit 0
DP1L             0xF104   P1L Direction Control Register
DP1L.DP1L7        7   Port direction register DP1L bit 7
DP1L.DP1L6        6   Port direction register DP1L bit 6
DP1L.DP1L5        5   Port direction register DP1L bit 5
DP1L.DP1L4        4   Port direction register DP1L bit 4
DP1L.DP1L3        3   Port direction register DP1L bit 3
DP1L.DP1L2        2   Port direction register DP1L bit 2
DP1L.DP1L1        1   Port direction register DP1L bit 1
DP1L.DP1L0        0   Port direction register DP1L bit 0
DP1H             0xF106   P1H Direction Control Register
DP1H.DP1H7        7   Port direction register DP1H bit 7
DP1H.DP1H6        6   Port direction register DP1H bit 6
DP1H.DP1H5        5   Port direction register DP1H bit 5
DP1H.DP1H4        4   Port direction register DP1H bit 4
DP1H.DP1H3        3   Port direction register DP1H bit 3
DP1H.DP1H2        2   Port direction register DP1H bit 2
DP1H.DP1H1        1   Port direction register DP1H bit 1
DP1H.DP1H0        0   Port direction register DP1L bit 0
RP0H             0xF108   System Startup Configuration Register (read only)
RP0H.CLKCFG_7     7   Clock Generation Mode Configuration - bit 7
RP0H.CLKCFG_6     6   Clock Generation Mode Configuration - bit 6
RP0H.CLKCFG_5     5   Clock Generation Mode Configuration - bit 5
RP0H.SALSEL_4     4   Segment Address Line Selection - bit 4
RP0H.SALSEL_3     3   Segment Address Line Selection - bit 3
RP0H.CSSEL_2      2   Chip Select Line Selection - bit 2
RP0H.CSSEL_1      1   Chip Select Line Selection - bit 1
RP0H.WRC          0   Write Configuration
CC16IC           0xF160   CAPCOM Register 16 Interrupt Ctrl. Reg.
CC16IC.CC16IR     7   Interrupt Request Flag
CC16IC.CC16IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC16IC.ILVL_5     5   Interrupt Priority Level - bit 5
CC16IC.ILVL_4     4   Interrupt Priority Level - bit 4
CC16IC.ILVL_3     3   Interrupt Priority Level - bit 3
CC16IC.ILVL_2     2   Interrupt Priority Level - bit 2
CC16IC.GLVL_1     1   Group Level - bit 1
CC16IC.GLVL_0     0   Group Level - bit 0
CC17IC           0xF162   CAPCOM Register 17 Interrupt Ctrl. Reg.
CC17IC.CC17IR     7   Interrupt Request Flag
CC17IC.CC17IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC17IC.ILVL_5     5   Interrupt Priority Level - bit 5
CC17IC.ILVL_4     4   Interrupt Priority Level - bit 4
CC17IC.ILVL_3     3   Interrupt Priority Level - bit 3
CC17IC.ILVL_2     2   Interrupt Priority Level - bit 2
CC17IC.GLVL_1     1   Group Level - bit 1
CC17IC.GLVL_0     0   Group Level - bit 0
CC18IC           0xF164   CAPCOM Register 18 Interrupt Ctrl. Reg.
CC18IC.CC18IR     7   Interrupt Request Flag
CC18IC.CC18IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC18IC.ILVL_5     5   Interrupt Priority Level - bit 5
CC18IC.ILVL_4     4   Interrupt Priority Level - bit 4
CC18IC.ILVL_3     3   Interrupt Priority Level - bit 3
CC18IC.ILVL_2     2   Interrupt Priority Level - bit 2
CC18IC.GLVL_1     1   Group Level - bit 1
CC18IC.GLVL_0     0   Group Level - bit 0
CC19IC           0xF166   CAPCOM Register 19 Interrupt Ctrl. Reg.
CC19IC.CC19IR     7   Interrupt Request Flag
CC19IC.CC19IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC19IC.ILVL_5     5   Interrupt Priority Level - bit 5
CC19IC.ILVL_4     4   Interrupt Priority Level - bit 4
CC19IC.ILVL_3     3   Interrupt Priority Level - bit 3
CC19IC.ILVL_2     2   Interrupt Priority Level - bit 2
CC19IC.GLVL_1     1   Group Level - bit 1
CC19IC.GLVL_0     0   Group Level - bit 0
CC20IC           0xF168   CAPCOM Register 20 Interrupt Ctrl. Reg.
CC20IC.CC20IR     7   Interrupt Request Flag
CC20IC.CC20IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC20IC.ILVL_5     5   Interrupt Priority Level - bit 5
CC20IC.ILVL_4     4   Interrupt Priority Level - bit 4
CC20IC.ILVL_3     3   Interrupt Priority Level - bit 3
CC20IC.ILVL_2     2   Interrupt Priority Level - bit 2
CC20IC.GLVL_1     1   Group Level - bit 1
CC20IC.GLVL_0     0   Group Level - bit 0
CC21IC           0xF16A   CAPCOM Register 21 Interrupt Ctrl. Reg.
CC21IC.CC21IR     7   Interrupt Request Flag
CC21IC.CC21IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC21IC.ILVL_5     5   Interrupt Priority Level - bit 5
CC21IC.ILVL_4     4   Interrupt Priority Level - bit 4
CC21IC.ILVL_3     3   Interrupt Priority Level - bit 3
CC21IC.ILVL_2     2   Interrupt Priority Level - bit 2
CC21IC.GLVL_1     1   Group Level - bit 1
CC21IC.GLVL_0     0   Group Level - bit 0
CC22IC           0xF16C   CAPCOM Register 22 Interrupt Ctrl. Reg.
CC22IC.CC22IR     7   Interrupt Request Flag
CC22IC.CC22IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC22IC.ILVL_5     5   Interrupt Priority Level - bit 5
CC22IC.ILVL_4     4   Interrupt Priority Level - bit 4
CC22IC.ILVL_3     3   Interrupt Priority Level - bit 3
CC22IC.ILVL_2     2   Interrupt Priority Level - bit 2
CC22IC.GLVL_1     1   Group Level - bit 1
CC22IC.GLVL_0     0   Group Level - bit 0
CC23IC           0xF16E   CAPCOM Register 23 Interrupt Ctrl. Reg.
CC23IC.CC23IR     7   Interrupt Request Flag
CC23IC.CC23IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC23IC.ILVL_5     5   Interrupt Priority Level - bit 5
CC23IC.ILVL_4     4   Interrupt Priority Level - bit 4
CC23IC.ILVL_3     3   Interrupt Priority Level - bit 3
CC23IC.ILVL_2     2   Interrupt Priority Level - bit 2
CC23IC.GLVL_1     1   Group Level - bit 1
CC23IC.GLVL_0     0   Group Level - bit 0
CC24IC           0xF170   CAPCOM Register 24 Interrupt Ctrl. Reg.
CC24IC.CC24IR     7   Interrupt Request Flag
CC24IC.CC24IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC24IC.ILVL_5     5   Interrupt Priority Level - bit 5
CC24IC.ILVL_4     4   Interrupt Priority Level - bit 4
CC24IC.ILVL_3     3   Interrupt Priority Level - bit 3
CC24IC.ILVL_2     2   Interrupt Priority Level - bit 2
CC24IC.GLVL_1     1   Group Level - bit 1
CC24IC.GLVL_0     0   Group Level - bit 0
CC25IC           0xF172   CAPCOM Register 25 Interrupt Ctrl. Reg.
CC25IC.CC25IR     7   Interrupt Request Flag
CC25IC.CC25IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC25IC.ILVL_5     5   Interrupt Priority Level - bit 5
CC25IC.ILVL_4     4   Interrupt Priority Level - bit 4
CC25IC.ILVL_3     3   Interrupt Priority Level - bit 3
CC25IC.ILVL_2     2   Interrupt Priority Level - bit 2
CC25IC.GLVL_1     1   Group Level - bit 1
CC25IC.GLVL_0     0   Group Level - bit 0
CC26IC           0xF174   CAPCOM Register 26 Interrupt Ctrl. Reg.
CC26IC.CC26IR     7   Interrupt Request Flag
CC26IC.CC26IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC26IC.ILVL_5     5   Interrupt Priority Level - bit 5
CC26IC.ILVL_4     4   Interrupt Priority Level - bit 4
CC26IC.ILVL_3     3   Interrupt Priority Level - bit 3
CC26IC.ILVL_2     2   Interrupt Priority Level - bit 2
CC26IC.GLVL_1     1   Group Level - bit 1
CC26IC.GLVL_0     0   Group Level - bit 0
CC27IC           0xF176   CAPCOM Register 27 Interrupt Ctrl. Reg.
CC27IC.CC27IR     7   Interrupt Request Flag
CC27IC.CC27IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC27IC.ILVL_5     5   Interrupt Priority Level - bit 5
CC27IC.ILVL_4     4   Interrupt Priority Level - bit 4
CC27IC.ILVL_3     3   Interrupt Priority Level - bit 3
CC27IC.ILVL_2     2   Interrupt Priority Level - bit 2
CC27IC.GLVL_1     1   Group Level - bit 1
CC27IC.GLVL_0     0   Group Level - bit 0
CC28IC           0xF178   CAPCOM Register 28 Interrupt Ctrl. Reg.
CC28IC.CC28IR     7   Interrupt Request Flag
CC28IC.CC28IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC28IC.ILVL_5     5   Interrupt Priority Level - bit 5
CC28IC.ILVL_4     4   Interrupt Priority Level - bit 4
CC28IC.ILVL_3     3   Interrupt Priority Level - bit 3
CC28IC.ILVL_2     2   Interrupt Priority Level - bit 2
CC28IC.GLVL_1     1   Group Level - bit 1
CC28IC.GLVL_0     0   Group Level - bit 0
T7IC             0xF17A   CAPCOM Timer 7 Interrupt Ctrl. Reg.
T7IC.T7IR         7   Interrupt Request Flag
T7IC.T7IE         6   Interrupt Enable Control Bit (individually enables/disables a specific source)
T7IC.ILVL_5       5   Interrupt Priority Level - bit 5
T7IC.ILVL_4       4   Interrupt Priority Level - bit 4
T7IC.ILVL_3       3   Interrupt Priority Level - bit 3
T7IC.ILVL_2       2   Interrupt Priority Level - bit 2
T7IC.GLVL_1       1   Group Level - bit 1
T7IC.GLVL_0       0   Group Level - bit 0
T8IC             0xF17C   CAPCOM Timer 8 Interrupt Ctrl. Reg.
T8IC.T8IR         7   Interrupt Request Flag
T8IC.T8IE         6   Interrupt Enable Control Bit (individually enables/disables a specific source)
T8IC.ILVL_5       5   Interrupt Priority Level - bit 5
T8IC.ILVL_4       4   Interrupt Priority Level - bit 4
T8IC.ILVL_3       3   Interrupt Priority Level - bit 3
T8IC.ILVL_2       2   Interrupt Priority Level - bit 2
T8IC.GLVL_1       1   Group Level - bit 1
T8IC.GLVL_0       0   Group Level - bit 0
XP4IC            0xF182   ASC1 Transmit Interrupt Control Register
XP4IC.XP4IR       7   Interrupt Request Flag
XP4IC.XP4IE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
XP4IC.ILVL_5      5   Interrupt Priority Level - bit 5
XP4IC.ILVL_4      4   Interrupt Priority Level - bit 4
XP4IC.ILVL_3      3   Interrupt Priority Level - bit 3
XP4IC.ILVL_2      2   Interrupt Priority Level - bit 2
XP4IC.GLVL_1      1   Group Level - bit 1
XP4IC.GLVL_0      0   Group Level - bit 0
CC29IC           0xF184   CAPCOM Register 29 Interrupt Ctrl. Reg.
CC29IC.CC29IR     7   Interrupt Request Flag
CC29IC.CC29IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC29IC.ILVL_5     5   Interrupt Priority Level - bit 5
CC29IC.ILVL_4     4   Interrupt Priority Level - bit 4
CC29IC.ILVL_3     3   Interrupt Priority Level - bit 3
CC29IC.ILVL_2     2   Interrupt Priority Level - bit 2
CC29IC.GLVL_1     1   Group Level - bit 1
CC29IC.GLVL_0     0   Group Level - bit 0
XP0IC            0xF186   IIC Data Interrupt Control Register
XP0IC.XP0IR       7   Interrupt Request Flag
XP0IC.XP0IE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
XP0IC.ILVL_5      5   Interrupt Priority Level - bit 5
XP0IC.ILVL_4      4   Interrupt Priority Level - bit 4
XP0IC.ILVL_3      3   Interrupt Priority Level - bit 3
XP0IC.ILVL_2      2   Interrupt Priority Level - bit 2
XP0IC.GLVL_1      1   Group Level - bit 1
XP0IC.GLVL_0      0   Group Level - bit 0
XP5IC            0xF18A   ASC1 Receive Interrupt Control Register
XP5IC.XP5IR       7   Interrupt Request Flag
XP5IC.XP5IE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
XP5IC.ILVL_5      5   Interrupt Priority Level - bit 5
XP5IC.ILVL_4      4   Interrupt Priority Level - bit 4
XP5IC.ILVL_3      3   Interrupt Priority Level - bit 3
XP5IC.ILVL_2      2   Interrupt Priority Level - bit 2
XP5IC.GLVL_1      1   Group Level - bit 1
XP5IC.GLVL_0      0   Group Level - bit 0
CC30IC           0xF18C   CAPCOM Register 30 Interrupt Ctrl. Reg.
CC30IC.CC30IR     7   Interrupt Request Flag
CC30IC.CC30IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC30IC.ILVL_5     5   Interrupt Priority Level - bit 5
CC30IC.ILVL_4     4   Interrupt Priority Level - bit 4
CC30IC.ILVL_3     3   Interrupt Priority Level - bit 3
CC30IC.ILVL_2     2   Interrupt Priority Level - bit 2
CC30IC.GLVL_1     1   Group Level - bit 1
CC30IC.GLVL_0     0   Group Level - bit 0
XP1IC            0xF18E   IIC Protocol Interrupt Control Register
XP1IC.XP1IR       7   Interrupt Request Flag
XP1IC.XP1IE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
XP1IC.ILVL_5      5   Interrupt Priority Level - bit 5
XP1IC.ILVL_4      4   Interrupt Priority Level - bit 4
XP1IC.ILVL_3      3   Interrupt Priority Level - bit 3
XP1IC.ILVL_2      2   Interrupt Priority Level - bit 2
XP1IC.GLVL_1      1   Group Level - bit 1
XP1IC.GLVL_0      0   Group Level - bit 0
XP6IC            0xF192   ASC1 Error Interrupt Control Register
XP6IC.XP6IR       7   Interrupt Request Flag
XP6IC.XP6IE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
XP6IC.ILVL_5      5   Interrupt Priority Level - bit 5
XP6IC.ILVL_4      4   Interrupt Priority Level - bit 4
XP6IC.ILVL_3      3   Interrupt Priority Level - bit 3
XP6IC.ILVL_2      2   Interrupt Priority Level - bit 2
XP6IC.GLVL_1      1   Group Level - bit 1
XP6IC.GLVL_0      0   Group Level - bit 0
CC31IC           0xF194   CAPCOM Register 31 Interrupt Ctrl. Reg.
CC31IC.CC31IR     7   Interrupt Request Flag
CC31IC.CC31IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC31IC.ILVL_5     5   Interrupt Priority Level - bit 5
CC31IC.ILVL_4     4   Interrupt Priority Level - bit 4
CC31IC.ILVL_3     3   Interrupt Priority Level - bit 3
CC31IC.ILVL_2     2   Interrupt Priority Level - bit 2
CC31IC.GLVL_1     1   Group Level - bit 1
CC31IC.GLVL_0     0   Group Level - bit 0
XP2IC            0xF196   CAN1 Interrupt Control Register
XP2IC.XP2IR       7   Interrupt Request Flag
XP2IC.XP2IE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
XP2IC.ILVL_5      5   Interrupt Priority Level - bit 5
XP2IC.ILVL_4      4   Interrupt Priority Level - bit 4
XP2IC.ILVL_3      3   Interrupt Priority Level - bit 3
XP2IC.ILVL_2      2   Interrupt Priority Level - bit 2
XP2IC.GLVL_1      1   Group Level - bit 1
XP2IC.GLVL_0      0   Group Level - bit 0
XP7IC            0xF19A   CAN2/SDLM Interrupt Control Register
XP7IC.XP7IR       7   Interrupt Request Flag
XP7IC.XP7IE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
XP7IC.ILVL_5      5   Interrupt Priority Level - bit 5
XP7IC.ILVL_4      4   Interrupt Priority Level - bit 4
XP7IC.ILVL_3      3   Interrupt Priority Level - bit 3
XP7IC.ILVL_2      2   Interrupt Priority Level - bit 2
XP7IC.GLVL_1      1   Group Level - bit 1
XP7IC.GLVL_0      0   Group Level - bit 0
S0TBIC           0xF19C   Serial Channel 0 Transmit Buffer Interrupt Control Register
S0TBIC.S0TBIR     7   Interrupt Request Flag
S0TBIC.S0TBIE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
S0TBIC.ILVL_5     5   Interrupt Priority Level - bit 5
S0TBIC.ILVL_4     4   Interrupt Priority Level - bit 4
S0TBIC.ILVL_3     3   Interrupt Priority Level - bit 3
S0TBIC.ILVL_2     2   Interrupt Priority Level - bit 2
S0TBIC.GLVL_1     1   Group Level - bit 1
S0TBIC.GLVL_0     0   Group Level - bit 0
XP3IC            0xF19E   RTC/PLL/OWD Interrupt Control Register
XP3IC.XP7IR       7   Interrupt Request Flag
XP3IC.XP7IE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
XP3IC.ILVL_5      5   Interrupt Priority Level - bit 5
XP3IC.ILVL_4      4   Interrupt Priority Level - bit 4
XP3IC.ILVL_3      3   Interrupt Priority Level - bit 3
XP3IC.ILVL_2      2   Interrupt Priority Level - bit 2
XP3IC.GLVL_1      1   Group Level - bit 1
XP3IC.GLVL_0      0   Group Level - bit 0
EXICON           0xF1C0   External Interrupt Control Register
EXICON.EXI7ES_15  15  External Interrupt 15 Edge Selection Field - bit 15
EXICON.EXI7ES_14  14  External Interrupt 14 Edge Selection Field - bit 14
EXICON.EXI6ES_13  13  External Interrupt 13 Edge Selection Field - bit 13
EXICON.EXI6ES_12  12  External Interrupt 12 Edge Selection Field - bit 12
EXICON.EXI5ES_11  11  External Interrupt 11 Edge Selection Field - bit 11
EXICON.EXI5ES_10  10  External Interrupt 10 Edge Selection Field - bit 10
EXICON.EXI4ES_9   9   External Interrupt 9 Edge Selection Field - bit 9 
EXICON.EXI4ES_8   8   External Interrupt 8 Edge Selection Field - bit 8 
EXICON.EXI3ES_7   7   External Interrupt 7 Edge Selection Field - bit 7 
EXICON.EXI3ES_6   6   External Interrupt 6 Edge Selection Field - bit 6 
EXICON.EXI2ES_5   5   External Interrupt 5 Edge Selection Field - bit 5 
EXICON.EXI2ES_4   4   External Interrupt 4 Edge Selection Field - bit 4 
EXICON.EXI1ES_3   3   External Interrupt 3 Edge Selection Field - bit 3 
EXICON.EXI1ES_2   2   External Interrupt 2 Edge Selection Field - bit 2 
EXICON.EXI0ES_1   1   External Interrupt 1 Edge Selection Field - bit 1 
EXICON.EXI0ES_0   0   External Interrupt 0 Edge Selection Field - bit 0 
ODP2             0xF1C2   Port 2 Open Drain Control Register
ODP2.ODP2_15      15  Port 2 Open Drain control register bit 15
ODP2.ODP2_14      14  Port 2 Open Drain control register bit 14
ODP2.ODP2_13      13  Port 2 Open Drain control register bit 13
ODP2.ODP2_12      12  Port 2 Open Drain control register bit 12
ODP2.ODP2_11      11  Port 2 Open Drain control register bit 11
ODP2.ODP2_10      10  Port 2 Open Drain control register bit 10
ODP2.ODP2_9       9   Port 2 Open Drain control register bit 9 
ODP2.ODP2_8       8   Port 2 Open Drain control register bit 8 
PICON            0xF1C4   Port Input Threshold Control Register
PICON.P7LIN       6   Port 7 Low Byte Input Level Selection
PICON.P6LIN       5   Port 6 Low Byte Input Level Selection
PICON.P5LIN       4   Port 5 Low Byte Input Level Selection
PICON.P3HIN       3   Port 3 High Byte Input Level Selection
PICON.P3LIN       2   Port 3 Low Byte Input Level Selection
PICON.P2HIN       1   Port 2 High Byte Input Level Selection
ODP3             0xF1C6   Port 3 Open Drain Control Register
ODP3.ODP3_13      13  Port 3 Open Drain control register bit 13
ODP3.ODP3_11      11  Port 3 Open Drain control register bit 11
ODP3.ODP3_10      10  Port 3 Open Drain control register bit 10
ODP3.ODP3_9       9   Port 3 Open Drain control register bit 9 
ODP3.ODP3_8       8   Port 3 Open Drain control register bit 8 
ODP3.ODP3_7       7   Port 3 Open Drain control register bit 7 
ODP3.ODP3_6       6   Port 3 Open Drain control register bit 6 
ODP3.ODP3_5       5   Port 3 Open Drain control register bit 5 
ODP3.ODP3_4       4   Port 3 Open Drain control register bit 4 
ODP3.ODP3_3       3   Port 3 Open Drain control register bit 3 
ODP3.ODP3_2       2   Port 3 Open Drain control register bit 2 
ODP3.ODP3_1       1   Port 3 Open Drain control register bit 1 
ODP3.ODP3_0       0   Port 3 Open Drain control register bit 0 
ODP4             0xF1CA   Port 4 Open Drain Control Register
ODP4.ODP4_7       7   Port 4 Open Drain control register bit 7 
ODP4.ODP4_6       6   Port 4 Open Drain control register bit 6 
ODP4.ODP4_5       5   Port 4 Open Drain control register bit 5 
ODP4.ODP4_4       4   Port 4 Open Drain control register bit 4 
ODP4.ODP4_3       3   Port 4 Open Drain control register bit 3 
ODP4.ODP4_2       2   Port 4 Open Drain control register bit 2 
ODP4.ODP4_1       1   Port 4 Open Drain control register bit 1 
ODP4.ODP4_0       0   Port 4 Open Drain control register bit 0 
ODP6             0xF1CE   Port 6 Open Drain Control Register
ODP6.ODP6_7       7   Port 6 Open Drain control register bit 7
ODP6.ODP6_6       6   Port 6 Open Drain control register bit 6
ODP6.ODP6_5       5   Port 6 Open Drain control register bit 5
ODP6.ODP6_4       4   Port 6 Open Drain control register bit 4
ODP6.ODP6_3       3   Port 6 Open Drain control register bit 3
ODP6.ODP6_2       2   Port 6 Open Drain control register bit 2
ODP6.ODP6_1       1   Port 6 Open Drain control register bit 1
ODP6.ODP6_0       0   Port 6 Open Drain control register bit 0
SYSCON2          0xF1D0   CPU System Configuration Register 2
SYSCON2.CLKLOCK   15  Clock Signal Status Bit
SYSCON2.CLKREL_14 14  Reload Counter Value for Slowdown Divider - 14
SYSCON2.CLKREL_13 13  Reload Counter Value for Slowdown Divider - 13
SYSCON2.CLKREL_12 12  Reload Counter Value for Slowdown Divider - 12
SYSCON2.CLKREL_11 11  Reload Counter Value for Slowdown Divider - 11
SYSCON2.CLKREL_10 10  Reload Counter Value for Slowdown Divider - 10
SYSCON2.CLKCON_9  9   Clock State Control - bit 9
SYSCON2.CLKCON_8  8   Clock State Control - bit 8
SYSCON2.SCS       7   SDD Clock Source
SYSCON2.RCS       6   RTC Clock Source
SYSCON2.PDCON_5   5   Power Down Control - bit 5
SYSCON2.PDCON_4   4   Power Down Control - bit 4
SYSCON2.SYSRLS_3  3   Register Release Function - bit 3
SYSCON2.SYSRLS_2  2   Register Release Function - bit 2
SYSCON2.SYSRLS_1  1   Register Release Function - bit 1
SYSCON2.SYSRLS_0  0   Register Release Function - bit 0
ODP7             0xF1D2   Port 7 Open Drain Control Register
ODP7.ODP7_7       7   Port 7 Open Drain control register bit 7
ODP7.ODP7_6       6   Port 7 Open Drain control register bit 6
ODP7.ODP7_5       5   Port 7 Open Drain control register bit 5
ODP7.ODP7_4       4   Port 7 Open Drain control register bit 4
SYSCON3          0xF1D4   CPU System Configuration Register 3
SYSCON3.PCDDIS    15  Peripheral Clock Driver
SYSCON3.CAN2DIS   14  On-chip CAN Module 2 1) exists only in the C161CS
SYSCON3.CAN1DIS   13  On-chip CAN Module 1
SYSCON3.IICDIS    11  On-chip IIC Bus Module
SYSCON3.ASC1DIS   10  USART ASC1
SYSCON3.CC2DIS    7   CAPCOM Unit 2
SYSCON3.CC1DIS    6   CAPCOM Unit 1
SYSCON3.GPTDIS    3   General Purpose Timer Blocks
SYSCON3.SSCDIS    2   Synchronous Serial Channel SSC
SYSCON3.ASC0DIS   1   USART ASC0
SYSCON3.ADCDIS    0   Analog/Digital Converter
EXISEL           0xF1DA   External Interrupt Source Select Register
EXISEL.EXI7SS_15  15  External Interrupt 15 Source Selection Field - bit 15
EXISEL.EXI7SS_14  14  External Interrupt 14 Source Selection Field - bit 14
EXISEL.EXI6SS_13  13  External Interrupt 13 Source Selection Field - bit 13
EXISEL.EXI6SS_12  12  External Interrupt 12 Source Selection Field - bit 12
EXISEL.EXI5SS_11  11  External Interrupt 11 Source Selection Field - bit 11
EXISEL.EXI5SS_10  10  External Interrupt 10 Source Selection Field - bit 10
EXISEL.EXI4SS_9   9   External Interrupt 9 Source Selection Field - bit 9 
EXISEL.EXI4SS_8   8   External Interrupt 8 Source Selection Field - bit 8 
EXISEL.EXI3SS_7   7   External Interrupt 7 Source Selection Field - bit 7 
EXISEL.EXI3SS_6   6   External Interrupt 6 Source Selection Field - bit 6 
EXISEL.EXI2SS_5   5   External Interrupt 5 Source Selection Field - bit 5 
EXISEL.EXI2SS_4   4   External Interrupt 4 Source Selection Field - bit 4 
EXISEL.EXI1SS_3   3   External Interrupt 3 Source Selection Field - bit 3 
EXISEL.EXI1SS_2   2   External Interrupt 2 Source Selection Field - bit 2 
EXISEL.EXI0SS_1   1   External Interrupt 1 Source Selection Field - bit 1 
EXISEL.EXI0SS_0   0   External Interrupt 0 Source Selection Field - bit 0 
SYSCON1          0xF1DC   CPU System Configuration Register 1
SYSCON1.SLEEPCON_1 1  SLEEP Mode Configuration - bit 1
SYSCON1.SLEEPCON_0 0  SLEEP Mode Configuration - bit 0
ISNC             0xF1DE   Interrupt Subnode Control Register
ISNC.PLLIE        3   Interrupt Enable Control Bit for Source PLL
ISNC.PLLIR        2   Interrupt Request Flag for Source PLL
ISNC.RTCIE        1   Interrupt Enable Control Bit for Source RTC
ISNC.RTCIR        0   Interrupt Request Flag for Source RTC
RSTCON           0xF1E0   Reset Control Register
RSTCON.CLKCFG_15  15  Clock Generation Mode Configuration - bit 15
RSTCON.CLKCFG_14  14  Clock Generation Mode Configuration - bit 14
RSTCON.CLKCFG_13  13  Clock Generation Mode Configuration - bit 13
RSTCON.SALSEL_12  12  Segment Address Line Selection - bit 12
RSTCON.SALSEL_11  11  Segment Address Line Selection - bit 11
RSTCON.CSSEL_10   10  Chip Select Line Selection - bit 10
RSTCON.CSSEL_9    9   Chip Select Line Selection - bit 9
RSTCON.SUE        8   Software Update Enable
RSTCON.RSTLEN_1   1   Reset Length Control - bit 1
RSTCON.RSTLEN_0   0   Reset Length Control - bit 0
DPP0             0xFE00   CPU Data Page Pointer 0 Register (10 bits)
DPP0.DPP0PN_9     9   Data Page Number of DPP0 - bit 9
DPP0.DPP0PN_8     8   Data Page Number of DPP0 - bit 8
DPP0.DPP0PN_7     7   Data Page Number of DPP0 - bit 7
DPP0.DPP0PN_6     6   Data Page Number of DPP0 - bit 6
DPP0.DPP0PN_5     5   Data Page Number of DPP0 - bit 5
DPP0.DPP0PN_4     4   Data Page Number of DPP0 - bit 4
DPP0.DPP0PN_3     3   Data Page Number of DPP0 - bit 3
DPP0.DPP0PN_2     2   Data Page Number of DPP0 - bit 2
DPP0.DPP0PN_1     1   Data Page Number of DPP0 - bit 1
DPP0.DPP0PN_0     0   Data Page Number of DPP0 - bit 0
DPP1             0xFE02   CPU Data Page Pointer 1 Register (10 bits)
DPP1.DPP1PN_9     9   Data Page Number of DPP1 - bit 9
DPP1.DPP1PN_8     8   Data Page Number of DPP1 - bit 8
DPP1.DPP1PN_7     7   Data Page Number of DPP1 - bit 7
DPP1.DPP1PN_6     6   Data Page Number of DPP1 - bit 6
DPP1.DPP1PN_5     5   Data Page Number of DPP1 - bit 5
DPP1.DPP1PN_4     4   Data Page Number of DPP1 - bit 4
DPP1.DPP1PN_3     3   Data Page Number of DPP1 - bit 3
DPP1.DPP1PN_2     2   Data Page Number of DPP1 - bit 2
DPP1.DPP1PN_1     1   Data Page Number of DPP1 - bit 1
DPP1.DPP1PN_0     0   Data Page Number of DPP1 - bit 0
DPP2             0xFE04   CPU Data Page Pointer 2 Register (10 bits)
DPP2.DPP2PN_9     9   Data Page Number of DPP2 - bit 9
DPP2.DPP2PN_8     8   Data Page Number of DPP2 - bit 8
DPP2.DPP2PN_7     7   Data Page Number of DPP2 - bit 7
DPP2.DPP2PN_6     6   Data Page Number of DPP2 - bit 6
DPP2.DPP2PN_5     5   Data Page Number of DPP2 - bit 5
DPP2.DPP2PN_4     4   Data Page Number of DPP2 - bit 4
DPP2.DPP2PN_3     3   Data Page Number of DPP2 - bit 3
DPP2.DPP2PN_2     2   Data Page Number of DPP2 - bit 2
DPP2.DPP2PN_1     1   Data Page Number of DPP2 - bit 1
DPP2.DPP2PN_0     0   Data Page Number of DPP2 - bit 0
DPP3             0xFE06   CPU Data Page Pointer 3 Register (10 bits)
DPP3.DPP3PN_9     9   Data Page Number of DPP3 - bit 9
DPP3.DPP3PN_8     8   Data Page Number of DPP3 - bit 8
DPP3.DPP3PN_7     7   Data Page Number of DPP3 - bit 7
DPP3.DPP3PN_6     6   Data Page Number of DPP3 - bit 6
DPP3.DPP3PN_5     5   Data Page Number of DPP3 - bit 5
DPP3.DPP3PN_4     4   Data Page Number of DPP3 - bit 4
DPP3.DPP3PN_3     3   Data Page Number of DPP3 - bit 3
DPP3.DPP3PN_2     2   Data Page Number of DPP3 - bit 2
DPP3.DPP3PN_1     1   Data Page Number of DPP3 - bit 1
DPP3.DPP3PN_0     0   Data Page Number of DPP3 - bit 0
CSP              0xFE08   CPU Code Segment Pointer Register (8 bits, not directly writeable)
CSP.SEGNR_7       7   Segment Number - bit 7
CSP.SEGNR_6       6   Segment Number - bit 6
CSP.SEGNR_5       5   Segment Number - bit 5
CSP.SEGNR_4       4   Segment Number - bit 4
CSP.SEGNR_3       3   Segment Number - bit 3
CSP.SEGNR_2       2   Segment Number - bit 2
CSP.SEGNR_1       1   Segment Number - bit 1
CSP.SEGNR_0       0   Segment Number - bit 0
MDH              0xFE0C   CPU Multiply Divide Register ­ High Word
MDH.mdh_15        15
MDH.mdh_14        14
MDH.mdh_13        13
MDH.mdh_12        12
MDH.mdh_11        11
MDH.mdh_10        10
MDH.mdh_9         9 
MDH.mdh_8         8 
MDH.mdh_7         7 
MDH.mdh_6         6 
MDH.mdh_5         5 
MDH.mdh_4         4 
MDH.mdh_3         3 
MDH.mdh_2         2 
MDH.mdh_1         1 
MDH.mdh_0         0 
MDL              0xFE0E   CPU Multiply Divide Register ­ Low Word
MDL.MDL_15        15
MDL.MDL_14        14
MDL.MDL_13        13
MDL.MDL_12        12
MDL.MDL_11        11
MDL.MDL_10        10
MDL.MDL_9         9 
MDL.MDL_8         8 
MDL.MDL_7         7 
MDL.MDL_6         6 
MDL.MDL_5         5 
MDL.MDL_4         4 
MDL.MDL_3         3 
MDL.MDL_2         2 
MDL.MDL_1         1 
MDL.MDL_0         0 
CP               0xFE10   CPU Context Pointer Register
CP.cp_11          11  Modifiable portion of register CP - bit 11
CP.cp_10          10  Modifiable portion of register CP - bit 10
CP.cp_9           9   Modifiable portion of register CP - bit 9
CP.cp_8           8   Modifiable portion of register CP - bit 8
CP.cp_7           7   Modifiable portion of register CP - bit 7
CP.cp_6           6   Modifiable portion of register CP - bit 6
CP.cp_5           5   Modifiable portion of register CP - bit 5
CP.cp_4           4   Modifiable portion of register CP - bit 4
CP.cp_3           3   Modifiable portion of register CP - bit 3
CP.cp_2           2   Modifiable portion of register CP - bit 2
CP.cp_1           1   Modifiable portion of register CP - bit 1
SP               0xFE12   CPU System Stack Pointer Register
SP.sp_11          11  Modifiable portion of register SP - bit 11
SP.sp_10          10  Modifiable portion of register SP - bit 10
SP.sp_9           9   Modifiable portion of register SP - bit 9
SP.sp_8           8   Modifiable portion of register SP - bit 8
SP.sp_7           7   Modifiable portion of register SP - bit 7
SP.sp_6           6   Modifiable portion of register SP - bit 6
SP.sp_5           5   Modifiable portion of register SP - bit 5
SP.sp_4           4   Modifiable portion of register SP - bit 4
SP.sp_3           3   Modifiable portion of register SP - bit 3
SP.sp_2           2   Modifiable portion of register SP - bit 2
SP.sp_1           1   Modifiable portion of register SP - bit 1
STKOV            0xFE14   CPU Stack Overflow Pointer Register
STKOV.stkov_11    11  Modifiable portion of register STKOV - bit 11
STKOV.stkov_10    10  Modifiable portion of register STKOV - bit 10
STKOV.stkov_9     9   Modifiable portion of register STKOV - bit 9
STKOV.stkov_8     8   Modifiable portion of register STKOV - bit 8
STKOV.stkov_7     7   Modifiable portion of register STKOV - bit 7
STKOV.stkov_6     6   Modifiable portion of register STKOV - bit 6
STKOV.stkov_5     5   Modifiable portion of register STKOV - bit 5
STKOV.stkov_4     4   Modifiable portion of register STKOV - bit 4
STKOV.stkov_3     3   Modifiable portion of register STKOV - bit 3
STKOV.stkov_2     2   Modifiable portion of register STKOV - bit 2
STKOV.stkov_1     1   Modifiable portion of register STKOV - bit 1
STKUN            0xFE16   CPU Stack Underflow Pointer Register
STKUN.STKUN_11    11  Modifiable portion of register STKUN - bit 11
STKUN.STKUN_10    10  Modifiable portion of register STKUN - bit 10
STKUN.STKUN_9     9   Modifiable portion of register STKUN - bit 9
STKUN.STKUN_8     8   Modifiable portion of register STKUN - bit 8
STKUN.STKUN_7     7   Modifiable portion of register STKUN - bit 7
STKUN.STKUN_6     6   Modifiable portion of register STKUN - bit 6
STKUN.STKUN_5     5   Modifiable portion of register STKUN - bit 5
STKUN.STKUN_4     4   Modifiable portion of register STKUN - bit 4
STKUN.STKUN_3     3   Modifiable portion of register STKUN - bit 3
STKUN.STKUN_2     2   Modifiable portion of register STKUN - bit 2
STKUN.STKUN_1     1   Modifiable portion of register STKUN - bit 1
ADDRSEL1         0xFE18   Address Select Register 1
ADDRSEL1.RGSAD15  15  Range Start Address bit 15
ADDRSEL1.RGSAD14  14  Range Start Address bit 14
ADDRSEL1.RGSAD13  13  Range Start Address bit 13
ADDRSEL1.RGSAD12  12  Range Start Address bit 12
ADDRSEL1.RGSAD11  11  Range Start Address bit 11
ADDRSEL1.RGSAD10  10  Range Start Address bit 10
ADDRSEL1.RGSAD9   9   Range Start Address bit 9 
ADDRSEL1.RGSAD8   8   Range Start Address bit 8 
ADDRSEL1.RGSAD7   7   Range Start Address bit 7 
ADDRSEL1.RGSAD6   6   Range Start Address bit 6 
ADDRSEL1.RGSAD5   5   Range Start Address bit 5 
ADDRSEL1.RGSAD4   4   Range Start Address bit 4 
ADDRSEL1.RGSZ3    3   Range Size Selection bit 3
ADDRSEL1.RGSZ2    2   Range Size Selection bit 2
ADDRSEL1.RGSZ1    1   Range Size Selection bit 1
ADDRSEL1.RGSZ0    0   Range Size Selection bit 0
ADDRSEL2         0xFE1A   Address Select Register 2
ADDRSEL2.RGSAD15  15  Range Start Address bit 15
ADDRSEL2.RGSAD14  14  Range Start Address bit 14
ADDRSEL2.RGSAD13  13  Range Start Address bit 13
ADDRSEL2.RGSAD12  12  Range Start Address bit 12
ADDRSEL2.RGSAD11  11  Range Start Address bit 11
ADDRSEL2.RGSAD10  10  Range Start Address bit 10
ADDRSEL2.RGSAD9   9   Range Start Address bit 9 
ADDRSEL2.RGSAD8   8   Range Start Address bit 8 
ADDRSEL2.RGSAD7   7   Range Start Address bit 7 
ADDRSEL2.RGSAD6   6   Range Start Address bit 6 
ADDRSEL2.RGSAD5   5   Range Start Address bit 5 
ADDRSEL2.RGSAD4   4   Range Start Address bit 4 
ADDRSEL2.RGSZ3    3   Range Size Selection bit 3
ADDRSEL2.RGSZ2    2   Range Size Selection bit 2
ADDRSEL2.RGSZ1    1   Range Size Selection bit 1
ADDRSEL2.RGSZ0    0   Range Size Selection bit 0
ADDRSEL3         0xFE1C   Address Select Register 3
ADDRSEL3.RGSAD15  15  Range Start Address bit 15
ADDRSEL3.RGSAD14  14  Range Start Address bit 14
ADDRSEL3.RGSAD13  13  Range Start Address bit 13
ADDRSEL3.RGSAD12  12  Range Start Address bit 12
ADDRSEL3.RGSAD11  11  Range Start Address bit 11
ADDRSEL3.RGSAD10  10  Range Start Address bit 10
ADDRSEL3.RGSAD9   9   Range Start Address bit 9 
ADDRSEL3.RGSAD8   8   Range Start Address bit 8 
ADDRSEL3.RGSAD7   7   Range Start Address bit 7 
ADDRSEL3.RGSAD6   6   Range Start Address bit 6 
ADDRSEL3.RGSAD5   5   Range Start Address bit 5 
ADDRSEL3.RGSAD4   4   Range Start Address bit 4 
ADDRSEL3.RGSZ3    3   Range Size Selection bit 3
ADDRSEL3.RGSZ2    2   Range Size Selection bit 2
ADDRSEL3.RGSZ1    1   Range Size Selection bit 1
ADDRSEL3.RGSZ0    0   Range Size Selection bit 0
ADDRSEL4         0xFE1E   Address Select Register 4
ADDRSEL4.RGSAD15  15  Range Start Address bit 15
ADDRSEL4.RGSAD14  14  Range Start Address bit 14
ADDRSEL4.RGSAD13  13  Range Start Address bit 13
ADDRSEL4.RGSAD12  12  Range Start Address bit 12
ADDRSEL4.RGSAD11  11  Range Start Address bit 11
ADDRSEL4.RGSAD10  10  Range Start Address bit 10
ADDRSEL4.RGSAD9   9   Range Start Address bit 9 
ADDRSEL4.RGSAD8   8   Range Start Address bit 8 
ADDRSEL4.RGSAD7   7   Range Start Address bit 7 
ADDRSEL4.RGSAD6   6   Range Start Address bit 6 
ADDRSEL4.RGSAD5   5   Range Start Address bit 5 
ADDRSEL4.RGSAD4   4   Range Start Address bit 4 
ADDRSEL4.RGSZ3    3   Range Size Selection bit 3
ADDRSEL4.RGSZ2    2   Range Size Selection bit 2
ADDRSEL4.RGSZ1    1   Range Size Selection bit 1
ADDRSEL4.RGSZ0    0   Range Size Selection bit 0
T2               0xFE40   GPT1 Timer 2 Register
T3               0xFE42   GPT1 Timer 3 Register
T4               0xFE44   GPT1 Timer 4 Register
T5               0xFE46   GPT2 Timer 5 Register
T6               0xFE48   GPT2 Timer 6 Register
CAPREL           0xFE4A   GPT2 Capture/Reload Register
T0               0xFE50   CAPCOM Timer 0 Register
T1               0xFE52   CAPCOM Timer 1 Register
T0REL            0xFE54   CAPCOM Timer 0 Reload Register
T1REL            0xFE56   CAPCOM Timer 1 Reload Register
CC16             0xFE60   CAPCOM Register 16
CC17             0xFE62   CAPCOM Register 17
CC18             0xFE64   CAPCOM Register 18
CC19             0xFE66   CAPCOM Register 19
CC20             0xFE68   CAPCOM Register 20
CC21             0xFE6A   CAPCOM Register 21
CC22             0xFE6C   CAPCOM Register 22
CC23             0xFE6E   CAPCOM Register 23
CC24             0xFE70   CAPCOM Register 24
CC25             0xFE72   CAPCOM Register 25
CC26             0xFE74   CAPCOM Register 26
CC27             0xFE76   CAPCOM Register 27
CC28             0xFE78   CAPCOM Register 28
CC29             0xFE7A   CAPCOM Register 29
CC30             0xFE7C   CAPCOM Register 30
CC31             0xFE7E   CAPCOM Register 31
CC0              0xFE80   CAPCOM Register 0
CC1              0xFE82   CAPCOM Register 1
CC2              0xFE84   CAPCOM Register 2
CC3              0xFE86   CAPCOM Register 3
CC4              0xFE88   CAPCOM Register 4
CC5              0xFE8A   CAPCOM Register 5
CC6              0xFE8C   CAPCOM Register 6
CC7              0xFE8E   CAPCOM Register 7
CC8              0xFE90   CAPCOM Register 8
CC9              0xFE92   CAPCOM Register 9
CC10             0xFE94   CAPCOM Register 10
CC11             0xFE96   CAPCOM Register 11
CC12             0xFE98   CAPCOM Register 12
CC13             0xFE9A   CAPCOM Register 13
CC14             0xFE9C   CAPCOM Register 14
CC15             0xFE9E   CAPCOM Register 15
ADDAT            0xFEA0   A/D Converter Result Register
ADDAT.CHNR_15     15  Channel Number - bit 15      
ADDAT.CHNR_14     14  Channel Number - bit 14      
ADDAT.CHNR_13     13  Channel Number - bit 13      
ADDAT.CHNR_12     12  Channel Number - bit 12      
ADDAT.ADRES_9     9   A/D Conversion Result - bit 9
ADDAT.ADRES_8     8   A/D Conversion Result - bit 8
ADDAT.ADRES_7     7   A/D Conversion Result - bit 7
ADDAT.ADRES_6     6   A/D Conversion Result - bit 6
ADDAT.ADRES_5     5   A/D Conversion Result - bit 5
ADDAT.ADRES_4     4   A/D Conversion Result - bit 4
ADDAT.ADRES_3     3   A/D Conversion Result - bit 3
ADDAT.ADRES_2     2   A/D Conversion Result - bit 2
ADDAT.ADRES_1     1   A/D Conversion Result - bit 1
ADDAT.ADRES_0     0   A/D Conversion Result - bit 0
P1DIDIS          0xFEA4   PORT1 Digital Input Disable Register
WDT              0xFEAE   Watchdog Timer Register (read only)
S0TBUF           0xFEB0   Serial Channel 0 Transmit Buffer Register
S0RBUF           0xFEB2   Serial Channel 0 Receive Buffer Register (read only)
S0BG             0xFEB4   Serial Channel 0 Baud Rate Generator Reload Register
PECC0            0xFEC0   PEC Channel 0 Control Register             
PECC0.INC_10      10  Increment Control - bit 10
PECC0.INC_9       9   Increment Control - bit 9 
PECC0.BWT         8   Byte/Word Transfer Selection
PECC0.COUNT_7     7    PEC Transfer Count - bit 7
PECC0.COUNT_6     6    PEC Transfer Count - bit 6
PECC0.COUNT_5     5    PEC Transfer Count - bit 5
PECC0.COUNT_4     4    PEC Transfer Count - bit 4
PECC0.COUNT_3     3    PEC Transfer Count - bit 3
PECC0.COUNT_2     2    PEC Transfer Count - bit 2
PECC0.COUNT_1     1    PEC Transfer Count - bit 1
PECC0.COUNT_0     0    PEC Transfer Count - bit 0
PECC1            0xFEC2   PEC Channel 1 Control Register             
PECC1.INC_10      10  Increment Control - bit 10
PECC1.INC_9       9   Increment Control - bit 9 
PECC1.BWT         8   Byte/Word Transfer Selection
PECC1.COUNT_7     7    PEC Transfer Count - bit 7
PECC1.COUNT_6     6    PEC Transfer Count - bit 6
PECC1.COUNT_5     5    PEC Transfer Count - bit 5
PECC1.COUNT_4     4    PEC Transfer Count - bit 4
PECC1.COUNT_3     3    PEC Transfer Count - bit 3
PECC1.COUNT_2     2    PEC Transfer Count - bit 2
PECC1.COUNT_1     1    PEC Transfer Count - bit 1
PECC1.COUNT_0     0    PEC Transfer Count - bit 0
PECC2            0xFEC4   PEC Channel 2 Control Register             
PECC2.INC_10      10  Increment Control - bit 10
PECC2.INC_9       9   Increment Control - bit 9 
PECC2.BWT         8   Byte/Word Transfer Selection
PECC2.COUNT_7     7    PEC Transfer Count - bit 7
PECC2.COUNT_6     6    PEC Transfer Count - bit 6
PECC2.COUNT_5     5    PEC Transfer Count - bit 5
PECC2.COUNT_4     4    PEC Transfer Count - bit 4
PECC2.COUNT_3     3    PEC Transfer Count - bit 3
PECC2.COUNT_2     2    PEC Transfer Count - bit 2
PECC2.COUNT_1     1    PEC Transfer Count - bit 1
PECC2.COUNT_0     0    PEC Transfer Count - bit 0
PECC3            0xFEC6   PEC Channel 3 Control Register             
PECC3.INC_10      10  Increment Control - bit 10
PECC3.INC_9       9   Increment Control - bit 9 
PECC3.BWT         8   Byte/Word Transfer Selection
PECC3.COUNT_7     7    PEC Transfer Count - bit 7
PECC3.COUNT_6     6    PEC Transfer Count - bit 6
PECC3.COUNT_5     5    PEC Transfer Count - bit 5
PECC3.COUNT_4     4    PEC Transfer Count - bit 4
PECC3.COUNT_3     3    PEC Transfer Count - bit 3
PECC3.COUNT_2     2    PEC Transfer Count - bit 2
PECC3.COUNT_1     1    PEC Transfer Count - bit 1
PECC3.COUNT_0     0    PEC Transfer Count - bit 0
PECC4            0xFEC8   PEC Channel 4 Control Register             
PECC4.INC_10      10  Increment Control - bit 10
PECC4.INC_9       9   Increment Control - bit 9 
PECC4.BWT         8   Byte/Word Transfer Selection
PECC4.COUNT_7     7    PEC Transfer Count - bit 7
PECC4.COUNT_6     6    PEC Transfer Count - bit 6
PECC4.COUNT_5     5    PEC Transfer Count - bit 5
PECC4.COUNT_4     4    PEC Transfer Count - bit 4
PECC4.COUNT_3     3    PEC Transfer Count - bit 3
PECC4.COUNT_2     2    PEC Transfer Count - bit 2
PECC4.COUNT_1     1    PEC Transfer Count - bit 1
PECC4.COUNT_0     0    PEC Transfer Count - bit 0
PECC5            0xFECA   PEC Channel 5 Control Register             
PECC5.INC_10      10  Increment Control - bit 10
PECC5.INC_9       9   Increment Control - bit 9 
PECC5.BWT         8   Byte/Word Transfer Selection
PECC5.COUNT_7     7    PEC Transfer Count - bit 7
PECC5.COUNT_6     6    PEC Transfer Count - bit 6
PECC5.COUNT_5     5    PEC Transfer Count - bit 5
PECC5.COUNT_4     4    PEC Transfer Count - bit 4
PECC5.COUNT_3     3    PEC Transfer Count - bit 3
PECC5.COUNT_2     2    PEC Transfer Count - bit 2
PECC5.COUNT_1     1    PEC Transfer Count - bit 1
PECC5.COUNT_0     0    PEC Transfer Count - bit 0
PECC6            0xFECC   PEC Channel 6 Control Register             
PECC6.INC_10      10  Increment Control - bit 10
PECC6.INC_9       9   Increment Control - bit 9 
PECC6.BWT         8   Byte/Word Transfer Selection
PECC6.COUNT_7     7    PEC Transfer Count - bit 7
PECC6.COUNT_6     6    PEC Transfer Count - bit 6
PECC6.COUNT_5     5    PEC Transfer Count - bit 5
PECC6.COUNT_4     4    PEC Transfer Count - bit 4
PECC6.COUNT_3     3    PEC Transfer Count - bit 3
PECC6.COUNT_2     2    PEC Transfer Count - bit 2
PECC6.COUNT_1     1    PEC Transfer Count - bit 1
PECC6.COUNT_0     0    PEC Transfer Count - bit 0
PECC7            0xFECE   PEC Channel 7 Control Register             
PECC7.INC_10      10  Increment Control - bit 10
PECC7.INC_9       9   Increment Control - bit 9 
PECC7.BWT         8   Byte/Word Transfer Selection
PECC7.COUNT_7     7    PEC Transfer Count - bit 7
PECC7.COUNT_6     6    PEC Transfer Count - bit 6
PECC7.COUNT_5     5    PEC Transfer Count - bit 5
PECC7.COUNT_4     4    PEC Transfer Count - bit 4
PECC7.COUNT_3     3    PEC Transfer Count - bit 3
PECC7.COUNT_2     2    PEC Transfer Count - bit 2
PECC7.COUNT_1     1    PEC Transfer Count - bit 1
PECC7.COUNT_0     0    PEC Transfer Count - bit 0
P0L              0xFF00   Port 0 Low Register (Lower half of PORT0)
P0L.P0L7          7   Port data register P0L bit 7
P0L.P0L6          6   Port data register P0L bit 6
P0L.P0L5          5   Port data register P0L bit 5
P0L.P0L4          4   Port data register P0L bit 4
P0L.P0L3          3   Port data register P0L bit 3
P0L.P0L2          2   Port data register P0L bit 2
P0L.P0L1          1   Port data register P0L bit 1
P0L.P0L0          0   Port data register P0L bit 0
P0H              0xFF02   Port 0 High Register (Upper half of PORT0)
P0H.P0H7          7   Port data register P0H bit 7
P0H.P0H6          6   Port data register P0H bit 6
P0H.P0H5          5   Port data register P0H bit 5
P0H.P0H4          4   Port data register P0H bit 4
P0H.P0H3          3   Port data register P0H bit 3
P0H.P0H2          2   Port data register P0H bit 2
P0H.P0H1          1   Port data register P0H bit 1
P0H.P0H0          0   Port data register P0H bit 0
P1L              0xFF04   Port 1 Low Register (Lower half of PORT1)
P1L.P1L7          7   Port data register P1L bit 7
P1L.P1L6          6   Port data register P1L bit 6
P1L.P1L5          5   Port data register P1L bit 5
P1L.P1L4          4   Port data register P1L bit 4
P1L.P1L3          3   Port data register P1L bit 3
P1L.P1L2          2   Port data register P1L bit 2
P1L.P1L1          1   Port data register P1L bit 1
P1L.P1L0          0   Port data register P1L bit 0
P1H              0xFF06   Port 1 High Register (Upper half of PORT1)
P1H.P1H7          7   Port data register P1H bit 7
P1H.P1H6          6   Port data register P1H bit 6
P1H.P1H5          5   Port data register P1H bit 5
P1H.P1H4          4   Port data register P1H bit 4
P1H.P1H3          3   Port data register P1H bit 3
P1H.P1H2          2   Port data register P1H bit 2
P1H.P1H1          1   Port data register P1H bit 1
P1H.P1H0          0   Port data register P1H bit 0
BUSCON0          0xFF0C   Bus Configuration Register 0
BUSCON0.CSWEN0    15  Write Chip Select Enable
BUSCON0.CSREN0    14  Read Chip Select Enable
BUSCON0.RDYEN0    12  READY Input Enable
BUSCON0.BSWC0     11  BUSCON Switch Control
BUSCON0.BUSACT0   10  Bus Active Control
BUSCON0.ALECTL0   9   ALE Lengthening Control
BUSCON0.EWEN0     8   Early Write Enable
BUSCON0.BTYP_7    7   External Bus Configuration - bit 7
BUSCON0.BTYP_6    6   External Bus Configuration - bit 6
BUSCON0.MTTC0     5   Memory Tristate Time Control
BUSCON0.RWDC0     4   Read/Write Delay Control for BUSCON
BUSCON0.MCTC_3    3   Memory Cycle Time Control - bit 3
BUSCON0.MCTC_2    2   Memory Cycle Time Control - bit 2
BUSCON0.MCTC_1    1   Memory Cycle Time Control - bit 1
BUSCON0.MCTC_0    0   Memory Cycle Time Control - bit 0
MDC              0xFF0E   CPU Multiply Divide Control Register
MDC.MDRIU         4   Multiply/Divide Register In Use
PSW              0xFF10   CPU Program Status Word
PSW.ILVL_15       15  Interrupt and EBC Control Field - bit 15
PSW.ILVL_14       14  Interrupt and EBC Control Field - bit 14
PSW.ILVL_13       13  Interrupt and EBC Control Field - bit 13
PSW.ILVL_12       12  Interrupt and EBC Control Field - bit 12
PSW.IEN           11  Interrupt and EBC Control Field
PSW.HLDEN         10  Interrupt and EBC Control Field
PSW.USR0          6   User General Purpose Flag
PSW.MULIP         5   Multiplication/Division In Progress
PSW.E             4   End of Table Flag
PSW.Z             3   Zero F lag
PSW.V             2   Overflow Result
PSW.C             1   Carry Flag
PSW.N             0   Negative Result
SYSCON           0xFF12   CPU System Configuration Register
SYSCON.STKSZ_15   15  System Stack Size - bit 15
SYSCON.STKSZ_14   14  System Stack Size - bit 14
SYSCON.STKSZ_13   13  System Stack Size - bit 13
SYSCON.ROMS1      12  Internal ROM Mapping
SYSCON.SGTDIS     11  Segmentation Disable/Enable Control (Cleared after reset)
SYSCON.ROMEN      10  Internal ROM Enable (Set according to pin EA during reset)
SYSCON.BYTDIS     9   Disable/Enable Control for Pin BHE (Set according to data bus width)
SYSCON.CLKEN      8   System Clock Output Enable (CLKOUT, cleared after reset)
SYSCON.WRCFG      7   Write Configuration Control (Set according to pin P0H.0 during reset)
SYSCON.CSCFG      6   Chip Select Configuration Control (Cleared after reset)
SYSCON.OWDDIS     4   Oscillator Watchdog Disable Bit (Depending on reset configuration)
SYSCON.BDRSTEN    3   Bidirectional Reset Enable Bit
SYSCON.XPEN       2   Peripheral Enable Bit
SYSCON.VISIBLE    1   Visible Mode Control
SYSCON.XPER_SHARE 0   XBUS Peripheral Share Mode Control
BUSCON1          0xFF14   Bus Configuration Register 1
BUSCON1.CSWEN1    15  Write Chip Select Enable
BUSCON1.CSREN1    14  Read Chip Select Enable
BUSCON1.RDYEN1    12  READY Input Enable
BUSCON1.BSWC1     11  BUSCON Switch Control
BUSCON1.BUSACT1   10  Bus Active Control
BUSCON1.ALECTL1   9   ALE Lengthening Control
BUSCON1.EWEN1     8   Early Write Enable
BUSCON1.BTYP_7    7   External Bus Configuration - bit 7
BUSCON1.BTYP_6    6   External Bus Configuration - bit 6
BUSCON1.MTTC1     5   Memory Tristate Time Control
BUSCON1.RWDC1     4   Read/Write Delay Control for BUSCON
BUSCON1.MCTC_3    3   Memory Cycle Time Control - bit 3
BUSCON1.MCTC_2    2   Memory Cycle Time Control - bit 2
BUSCON1.MCTC_1    1   Memory Cycle Time Control - bit 1
BUSCON1.MCTC_0    0   Memory Cycle Time Control - bit 0
BUSCON2          0xFF16   Bus Configuration Register 2
BUSCON2.CSWEN2    15  Write Chip Select Enable
BUSCON2.CSREN2    14  Read Chip Select Enable
BUSCON2.RDYEN2    12  READY Input Enable
BUSCON2.BSWC2     11  BUSCON Switch Control
BUSCON2.BUSACT2   10  Bus Active Control
BUSCON2.ALECTL2   9   ALE Lengthening Control
BUSCON2.EWEN2     8   Early Write Enable
BUSCON2.BTYP_7    7   External Bus Configuration - bit 7
BUSCON2.BTYP_6    6   External Bus Configuration - bit 6
BUSCON2.MTTC2     5   Memory Tristate Time Control
BUSCON2.RWDC2     4   Read/Write Delay Control for BUSCON
BUSCON2.MCTC_3    3   Memory Cycle Time Control - bit 3
BUSCON2.MCTC_2    2   Memory Cycle Time Control - bit 2
BUSCON2.MCTC_1    1   Memory Cycle Time Control - bit 1
BUSCON2.MCTC_0    0   Memory Cycle Time Control - bit 0
BUSCON3          0xFF18   Bus Configuration Register 3
BUSCON3.CSWEN3    15  Write Chip Select Enable
BUSCON3.CSREN3    14  Read Chip Select Enable
BUSCON3.RDYEN3    12  READY Input Enable
BUSCON3.BSWC3     11  BUSCON Switch Control
BUSCON3.BUSACT3   10  Bus Active Control
BUSCON3.ALECTL3   9   ALE Lengthening Control
BUSCON3.EWEN3     8   Early Write Enable
BUSCON3.BTYP_7    7   External Bus Configuration - bit 7
BUSCON3.BTYP_6    6   External Bus Configuration - bit 6
BUSCON3.MTTC3     5   Memory Tristate Time Control
BUSCON3.RWDC3     4   Read/Write Delay Control for BUSCON
BUSCON3.MCTC_3    3   Memory Cycle Time Control - bit 3
BUSCON3.MCTC_2    2   Memory Cycle Time Control - bit 2
BUSCON3.MCTC_1    1   Memory Cycle Time Control - bit 1
BUSCON3.MCTC_0    0   Memory Cycle Time Control - bit 0
BUSCON4          0xFF1A   Bus Configuration Register 4
BUSCON4.CSWEN4    15  Write Chip Select Enable
BUSCON4.CSREN4    14  Read Chip Select Enable
BUSCON4.RDYEN4    12  READY Input Enable
BUSCON4.BSWC4     11  BUSCON Switch Control
BUSCON4.BUSACT4   10  Bus Active Control
BUSCON4.ALECTL4   9   ALE Lengthening Control
BUSCON4.EWEN4     8   Early Write Enable
BUSCON4.BTYP_7    7   External Bus Configuration - bit 7
BUSCON4.BTYP_6    6   External Bus Configuration - bit 6
BUSCON4.MTTC4     5   Memory Tristate Time Control
BUSCON4.RWDC4     4   Read/Write Delay Control for BUSCON
BUSCON4.MCTC_3    3   Memory Cycle Time Control - bit 3
BUSCON4.MCTC_2    2   Memory Cycle Time Control - bit 2
BUSCON4.MCTC_1    1   Memory Cycle Time Control - bit 1
BUSCON4.MCTC_0    0   Memory Cycle Time Control - bit 0
ZEROS            0xFF1C   Constant Value 0's Register (read only)
ONES             0xFF1E   Constant Value 1's Register (read only)
T78CON           0xFF20   CAPCOM Timer 7 and 8 Control Register      
T78CON.T8R        14  Timer/Counter 8 Run Control
T78CON.T8M        11  Timer/Counter 8 Mode Selection
T78CON.T8I_10     10  Timer/Counter 8 Input Selection - bit 10
T78CON.T8I_9      9   Timer/Counter 8 Input Selection - bit 9 
T78CON.T8I_8      8   Timer/Counter 8 Input Selection - bit 8 
T78CON.T7R        6   Timer/Counter 7 Run Control
T78CON.T7M        3   Timer/Counter 7 Mode Selection
T78CON.T7I_2      2   Timer/Counter 7 Input Selection - bit 2
T78CON.T7I_1      1   Timer/Counter 7 Input Selection - bit 1
T78CON.T7I_0      0   Timer/Counter 7 Input Selection - bit 0
CCM4             0xFF22   CAPCOM Mode Control Register 4
CCM4.ACC19        15  Allocation Bit for Capture/Compare Register CC4
CCM4.CCMOD19_14   14  Mode Selection for Capture/Compare Register CC4 bit 14
CCM4.CCMOD19_13   13  Mode Selection for Capture/Compare Register CC4 bit 13
CCM4.CCMOD19_12   12  Mode Selection for Capture/Compare Register CC4 bit 12
CCM4.ACC18        11  Allocation Bit for Capture/Compare Register CC4       
CCM4.CCMOD18_10   10  Mode Selection for Capture/Compare Register CC4 bit 10
CCM4.CCMOD18_9    9   Mode Selection for Capture/Compare Register CC4 bit 9 
CCM4.CCMOD18_8    8   Mode Selection for Capture/Compare Register CC4 bit 8 
CCM4.ACC17        7   Allocation Bit for Capture/Compare Register CC4       
CCM4.CCMOD17_6    6   Mode Selection for Capture/Compare Register CC4 bit 6 
CCM4.CCMOD17_5    5   Mode Selection for Capture/Compare Register CC4 bit 5 
CCM4.CCMOD17_4    4   Mode Selection for Capture/Compare Register CC4 bit 4 
CCM4.ACC16        3   Allocation Bit for Capture/Compare Register CC4       
CCM4.CCMOD16_2    2   Mode Selection for Capture/Compare Register CC4 bit 2 
CCM4.CCMOD16_1    1   Mode Selection for Capture/Compare Register CC4 bit 1 
CCM4.CCMOD16_0    0   Mode Selection for Capture/Compare Register CC4 bit 0 
CCM5             0xFF24 CAPCOM Mode Control Register 5
CCM5.ACC23        15  Allocation Bit for Capture/Compare Register CC4       
CCM5.CCMOD23_14   14  Mode Selection for Capture/Compare Register CC4 bit 14
CCM5.CCMOD23_13   13  Mode Selection for Capture/Compare Register CC4 bit 13
CCM5.CCMOD23_12   12  Mode Selection for Capture/Compare Register CC4 bit 12
CCM5.ACC22        11  Allocation Bit for Capture/Compare Register CC4       
CCM5.CCMOD22_10   10  Mode Selection for Capture/Compare Register CC4 bit 10
CCM5.CCMOD22_9    9   Mode Selection for Capture/Compare Register CC4 bit 9 
CCM5.CCMOD22_8    8   Mode Selection for Capture/Compare Register CC4 bit 8 
CCM5.ACC21        7   Allocation Bit for Capture/Compare Register CC4       
CCM5.CCMOD21_6    6   Mode Selection for Capture/Compare Register CC4 bit 6 
CCM5.CCMOD21_5    5   Mode Selection for Capture/Compare Register CC4 bit 5 
CCM5.CCMOD21_4    4   Mode Selection for Capture/Compare Register CC4 bit 4 
CCM5.ACC20        3   Allocation Bit for Capture/Compare Register CC4       
CCM5.CCMOD20_2    2   Mode Selection for Capture/Compare Register CC4 bit 2 
CCM5.CCMOD20_1    1   Mode Selection for Capture/Compare Register CC4 bit 1 
CCM5.CCMOD20_0    0   Mode Selection for Capture/Compare Register CC4 bit 0 
CCM6             0xFF26 CAPCOM Mode Control Register 6
CCM6.ACC27        15  Allocation Bit for Capture/Compare Register CC4       
CCM6.CCMOD27_14   14  Mode Selection for Capture/Compare Register CC4 bit 14
CCM6.CCMOD27_13   13  Mode Selection for Capture/Compare Register CC4 bit 13
CCM6.CCMOD27_12   12  Mode Selection for Capture/Compare Register CC4 bit 12
CCM6.ACC26        11  Allocation Bit for Capture/Compare Register CC4       
CCM6.CCMOD26_10   10  Mode Selection for Capture/Compare Register CC4 bit 10
CCM6.CCMOD26_9    9   Mode Selection for Capture/Compare Register CC4 bit 9 
CCM6.CCMOD26_8    8   Mode Selection for Capture/Compare Register CC4 bit 8 
CCM6.ACC25        7   Allocation Bit for Capture/Compare Register CC4       
CCM6.CCMOD25_6    6   Mode Selection for Capture/Compare Register CC4 bit 6 
CCM6.CCMOD25_5    5   Mode Selection for Capture/Compare Register CC4 bit 5 
CCM6.CCMOD25_4    4   Mode Selection for Capture/Compare Register CC4 bit 4 
CCM6.ACC24        3   Allocation Bit for Capture/Compare Register CC4       
CCM6.CCMOD24_2    2   Mode Selection for Capture/Compare Register CC4 bit 2 
CCM6.CCMOD24_1    1   Mode Selection for Capture/Compare Register CC4 bit 1 
CCM6.CCMOD24_0    0   Mode Selection for Capture/Compare Register CC4 bit 0 
CCM7             0xFF28 CAPCOM Mode Control Register 7
CCM7.ACC31        15  Allocation Bit for Capture/Compare Register CC4       
CCM7.CCMOD31_14   14  Mode Selection for Capture/Compare Register CC4 bit 14
CCM7.CCMOD31_13   13  Mode Selection for Capture/Compare Register CC4 bit 13
CCM7.CCMOD31_12   12  Mode Selection for Capture/Compare Register CC4 bit 12
CCM7.ACC30        11  Allocation Bit for Capture/Compare Register CC4       
CCM7.CCMOD30_10   10  Mode Selection for Capture/Compare Register CC4 bit 10
CCM7.CCMOD30_9    9   Mode Selection for Capture/Compare Register CC4 bit 9 
CCM7.CCMOD30_8    8   Mode Selection for Capture/Compare Register CC4 bit 8 
CCM7.ACC29        7   Allocation Bit for Capture/Compare Register CC4       
CCM7.CCMOD29_6    6   Mode Selection for Capture/Compare Register CC4 bit 6 
CCM7.CCMOD29_5    5   Mode Selection for Capture/Compare Register CC4 bit 5 
CCM7.CCMOD29_4    4   Mode Selection for Capture/Compare Register CC4 bit 4 
CCM7.ACC28        3   Allocation Bit for Capture/Compare Register CC4       
CCM7.CCMOD28_2    2   Mode Selection for Capture/Compare Register CC4 bit 2 
CCM7.CCMOD28_1    1   Mode Selection for Capture/Compare Register CC4 bit 1 
CCM7.CCMOD28_0    0   Mode Selection for Capture/Compare Register CC4 bit 0 
T2CON            0xFF40   GPT1 Timer 2 Control Register
T2CON.T2OTL       10  Timer 2 Output Toggle Latch
T2CON.T2OE        9   Alternate Output Function Enable
T2CON.T2UDE       8   Timer 2 External Up/Down Enable
T2CON.T2UD        7   Timer 2 Up / Down Control
T2CON.T2R         6   Timer 2 Run Bit
T2CON.T2M_5       5   Timer 2 Mode Control - bit 5
T2CON.T2M_4       4   Timer 2 Mode Control - bit 4
T2CON.T2M_3       3   Timer 2 Mode Control - bit 3
T2CON.T2I_2       2   Timer 2 Input Selection - bit 2
T2CON.T2I_1       1   Timer 2 Input Selection - bit 1
T2CON.T2I_0       0   Timer 2 Input Selection - bit 0
T3CON            0xFF42   GPT1 Timer 3 Control Register
T3CON.T3OTL       10  Timer 3 Output Toggle Latch
T3CON.T3OE        9   Alternate Output Function Enable
T3CON.T3UDE       8   Timer 3 External Up/Down Enable
T3CON.T3UD        7   Timer 3 Up / Down Control
T3CON.T3R         6   Timer 3 Run Bit
T3CON.T3M_5       5   Timer 3 Mode Control - bit 5
T3CON.T3M_4       4   Timer 3 Mode Control - bit 4
T3CON.T3M_3       3   Timer 3 Mode Control - bit 3
T3CON.T3I_2       2   Timer 3 Input Selection - bit 2
T3CON.T3I_1       1   Timer 3 Input Selection - bit 1
T3CON.T3I_0       0   Timer 3 Input Selection - bit 0
T4CON            0xFF44   GPT1 Timer 4 Control Register
T4CON.T4OTL       10  Timer 4 Output Toggle Latch
T4CON.T4OE        9   Alternate Output Function Enable
T4CON.T4UDE       8   Timer 4 External Up/Down Enable
T4CON.T4UD        7   Timer 4 Up / Down Control
T4CON.T4R         6   Timer 4 Run Bit
T4CON.T4M_5       5   Timer 4 Mode Control - bit 5
T4CON.T4M_4       4   Timer 4 Mode Control - bit 4
T4CON.T4M_3       3   Timer 4 Mode Control - bit 3
T4CON.T4I_2       2   Timer 4 Input Selection - bit 2
T4CON.T4I_1       1   Timer 4 Input Selection - bit 1
T4CON.T4I_0       0   Timer 4 Input Selection - bit 0
T5CON            0xFF46   GPT2 Timer 5 Control Register
T5CON.T5SR        15  Timer 5 Reload Mode Enable
T5CON.T5CLR       14  Timer 5 Clear Bit
T5CON.CI_13       13  Register CAPREL Capture Trigger Selection - bit 13
T5CON.CI_12       12  Register CAPREL Capture Trigger Selection - bit 12
T5CON.CT3         10  Timer 3 Capture Trigger Enable
T5CON.T5UD        7   Timer 5 Up / Down Control
T5CON.T5R         6   Timer 5 Run Bit
T5CON.T5M_5       5   Timer 5 Mode Control - bit 5
T5CON.T5M_4       4   Timer 5 Mode Control - bit 4
T5CON.T5M_3       3   Timer 5 Mode Control - bit 3
T5CON.T5I_2       2   Timer 5 Input Selection - bit 2
T5CON.T5I_1       1   Timer 5 Input Selection - bit 1
T5CON.T5I_0       0   Timer 5 Input Selection - bit 0
T6CON            0xFF48   GPT2 Timer 6 Control Register
T6CON.T6SR        15  Timer 6 Reload Mode Enable
T6CON.T6OTL       10  Timer 6 Output Toggle Latch
T6CON.T6OE        9   Alternate Output Function Enable
T6CON.T6UD        7   Timer 6 Up / Down Control
T6CON.T6R         6   Timer 6 Run Bit
T6CON.T6M_5       5   Timer 6 Mode Control - bit 5
T6CON.T6M_4       4   Timer 6 Mode Control - bit 4
T6CON.T6M_3       3   Timer 6 Mode Control - bit 3
T6CON.T6I_2       2   Timer 6 Input Selection - bit 2
T6CON.T6I_1       1   Timer 6 Input Selection - bit 1
T6CON.T6I_0       0   Timer 6 Input Selection - bit 0
T01CON           0xFF50   CAPCOM Timer 0 and Timer 1 Ctrl. Reg.
T01CON.T1R        14  Timer/Counter 1 Run Control
T01CON.T1M        11  Timer/Counter 1 Mode Selection
T01CON.T1I_10     10  Timer/Counter 1 Input Selection - bit 10
T01CON.T1I_9      9   Timer/Counter 1 Input Selection - bit 9 
T01CON.T1I_8      8   Timer/Counter 1 Input Selection - bit 8 
T01CON.T0R        6   Timer/Counter 0 Run Control
T01CON.T0M        3   Timer/Counter 0 Mode Selection
T01CON.T0I_2      2   Timer/Counter 0 Input Selection - bit 2
T01CON.T0I_1      1   Timer/Counter 0 Input Selection - bit 1
T01CON.T0I_0      0   Timer/Counter 0 Input Selection - bit 0
CCM0             0xFF52   CAPCOM Mode Control Register 0
CCM0.ACC3         15  Allocation Bit for Capture/Compare Register CC0       
CCM0.CCMOD3_14    14  Mode Selection for Capture/Compare Register CC0 bit 14
CCM0.CCMOD3_13    13  Mode Selection for Capture/Compare Register CC0 bit 13
CCM0.CCMOD3_12    12  Mode Selection for Capture/Compare Register CC0 bit 12
CCM0.ACC2         11  Allocation Bit for Capture/Compare Register CC0       
CCM0.CCMOD2_10    10  Mode Selection for Capture/Compare Register CC0 bit 10
CCM0.CCMOD2_9     9   Mode Selection for Capture/Compare Register CC0 bit 9 
CCM0.CCMOD2_8     8   Mode Selection for Capture/Compare Register CC0 bit 8 
CCM0.ACC1         7   Allocation Bit for Capture/Compare Register CC0       
CCM0.CCMOD1_6     6   Mode Selection for Capture/Compare Register CC0 bit 6 
CCM0.CCMOD1_5     5   Mode Selection for Capture/Compare Register CC0 bit 5 
CCM0.CCMOD1_4     4   Mode Selection for Capture/Compare Register CC0 bit 4 
CCM0.ACC0         3   Allocation Bit for Capture/Compare Register CC0       
CCM0.CCMOD0_2     2   Mode Selection for Capture/Compare Register CC0 bit 2 
CCM0.CCMOD0_1     1   Mode Selection for Capture/Compare Register CC0 bit 1 
CCM0.CCMOD0_0     0   Mode Selection for Capture/Compare Register CC0 bit 0 
CCM1             0xFF54   CAPCOM Mode Control Register 1
CCM1.ACC7         15  Allocation Bit for Capture/Compare Register CC1       
CCM1.CCMOD7_14    14  Mode Selection for Capture/Compare Register CC1 bit 14
CCM1.CCMOD7_13    13  Mode Selection for Capture/Compare Register CC1 bit 13
CCM1.CCMOD7_12    12  Mode Selection for Capture/Compare Register CC1 bit 12
CCM1.ACC6         11  Allocation Bit for Capture/Compare Register CC1       
CCM1.CCMOD6_10    10  Mode Selection for Capture/Compare Register CC1 bit 10
CCM1.CCMOD6_9     9   Mode Selection for Capture/Compare Register CC1 bit 9 
CCM1.CCMOD6_8     8   Mode Selection for Capture/Compare Register CC1 bit 8 
CCM1.ACC5         7   Allocation Bit for Capture/Compare Register CC1       
CCM1.CCMOD5_6     6   Mode Selection for Capture/Compare Register CC1 bit 6 
CCM1.CCMOD5_5     5   Mode Selection for Capture/Compare Register CC1 bit 5 
CCM1.CCMOD5_4     4   Mode Selection for Capture/Compare Register CC1 bit 4 
CCM1.ACC4         3   Allocation Bit for Capture/Compare Register CC1       
CCM1.CCMOD4_2     2   Mode Selection for Capture/Compare Register CC1 bit 2 
CCM1.CCMOD4_1     1   Mode Selection for Capture/Compare Register CC1 bit 1 
CCM1.CCMOD4_0     0   Mode Selection for Capture/Compare Register CC1 bit 0 
CCM2             0xFF56 CAPCOM Mode Control Register 2
CCM2.ACC11        15  Allocation Bit for Capture/Compare Register CC2
CCM2.CCMOD11_14   14  Mode Selection for Capture/Compare Register CC2 bit 14
CCM2.CCMOD11_13   13  Mode Selection for Capture/Compare Register CC2 bit 13
CCM2.CCMOD11_12   12  Mode Selection for Capture/Compare Register CC2 bit 12
CCM2.ACC10        11  Allocation Bit for Capture/Compare Register CC2     
CCM2.CCMOD10_10   10  Mode Selection for Capture/Compare Register CC2 bit 10
CCM2.CCMOD10_9    9   Mode Selection for Capture/Compare Register CC2 bit 9 
CCM2.CCMOD10_8    8   Mode Selection for Capture/Compare Register CC2 bit 8 
CCM2.ACC9         7   Allocation Bit for Capture/Compare Register CC2     
CCM2.CCMOD9_6     6   Mode Selection for Capture/Compare Register CC2 bit 6
CCM2.CCMOD9_5     5   Mode Selection for Capture/Compare Register CC2 bit 5
CCM2.CCMOD9_4     4   Mode Selection for Capture/Compare Register CC2 bit 4
CCM2.ACC8         3   Allocation Bit for Capture/Compare Register CC2      
CCM2.CCMOD8_2     2   Mode Selection for Capture/Compare Register CC2 bit 2
CCM2.CCMOD8_1     1   Mode Selection for Capture/Compare Register CC2 bit 1
CCM2.CCMOD8_0     0   Mode Selection for Capture/Compare Register CC2 bit 0
CCM3             0xFF58 CAPCOM Mode Control Register 3
CCM3.ACC15        15  Allocation Bit for Capture/Compare Register CC3       
CCM3.CCMOD15_14   14  Mode Selection for Capture/Compare Register CC3 bit 14
CCM3.CCMOD15_13   13  Mode Selection for Capture/Compare Register CC3 bit 13
CCM3.CCMOD15_12   12  Mode Selection for Capture/Compare Register CC3 bit 12
CCM3.ACC14        11  Allocation Bit for Capture/Compare Register CC3       
CCM3.CCMOD14_10   10  Mode Selection for Capture/Compare Register CC3 bit 10
CCM3.CCMOD14_9    9   Mode Selection for Capture/Compare Register CC3 bit 9 
CCM3.CCMOD14_8    8   Mode Selection for Capture/Compare Register CC3 bit 8 
CCM3.ACC13        7   Allocation Bit for Capture/Compare Register CC3       
CCM3.CCMOD13_6    6   Mode Selection for Capture/Compare Register CC3 bit 6 
CCM3.CCMOD13_5    5   Mode Selection for Capture/Compare Register CC3 bit 5 
CCM3.CCMOD13_4    4   Mode Selection for Capture/Compare Register CC3 bit 4 
CCM3.ACC12        3   Allocation Bit for Capture/Compare Register CC3       
CCM3.CCMOD12_2    2   Mode Selection for Capture/Compare Register CC3 bit 2 
CCM3.CCMOD12_1    1   Mode Selection for Capture/Compare Register CC3 bit 1 
CCM3.CCMOD12_0    0   Mode Selection for Capture/Compare Register CC3 bit 0 
T2IC             0xFF60   GPT1 Timer 2 Interrupt Control Register
T2IC.T2IR         7   Interrupt Request Flag
T2IC.T2IE         6   Interrupt Enable Control Bit (individually enables/disables a specific source)
T2IC.ILVL_5       5   Interrupt Priority Level - bit 5
T2IC.ILVL_4       4   Interrupt Priority Level - bit 4
T2IC.ILVL_3       3   Interrupt Priority Level - bit 3
T2IC.ILVL_2       2   Interrupt Priority Level - bit 2
T2IC.GLVL_1       1   Group Level - bit 1
T2IC.GLVL_0       0   Group Level - bit 0
T3IC             0xFF62   GPT1 Timer 3 Interrupt Control Register
T3IC.T3IR         7   Interrupt Request Flag
T3IC.T3IE         6   Interrupt Enable Control Bit (individually enables/disables a specific source)
T3IC.ILVL_5       5   Interrupt Priority Level - bit 5
T3IC.ILVL_4       4   Interrupt Priority Level - bit 4
T3IC.ILVL_3       3   Interrupt Priority Level - bit 3
T3IC.ILVL_2       2   Interrupt Priority Level - bit 2
T3IC.GLVL_1       1   Group Level - bit 1
T3IC.GLVL_0       0   Group Level - bit 0
T4IC             0xFF64   GPT1 Timer 4 Interrupt Control Register
T4IC.T4IR         7   Interrupt Request Flag
T4IC.T4IE         6   Interrupt Enable Control Bit (individually enables/disables a specific source)
T4IC.ILVL_5       5   Interrupt Priority Level - bit 5
T4IC.ILVL_4       4   Interrupt Priority Level - bit 4
T4IC.ILVL_3       3   Interrupt Priority Level - bit 3
T4IC.ILVL_2       2   Interrupt Priority Level - bit 2
T4IC.GLVL_1       1   Group Level - bit 1
T4IC.GLVL_0       0   Group Level - bit 0
T5IC             0xFF66   GPT2 Timer 5 Interrupt Control Register
T5IC.T5IR         7   Interrupt Request Flag
T5IC.T5IE         6   Interrupt Enable Control Bit (individually enables/disables a specific source)
T5IC.ILVL_5       5   Interrupt Priority Level - bit 5
T5IC.ILVL_4       4   Interrupt Priority Level - bit 4
T5IC.ILVL_3       3   Interrupt Priority Level - bit 3
T5IC.ILVL_2       2   Interrupt Priority Level - bit 2
T5IC.GLVL_1       1   Group Level - bit 1
T5IC.GLVL_0       0   Group Level - bit 0
T6IC             0xFF68   GPT2 Timer 6 Interrupt Control Register
T6IC.T2IR         7   Interrupt Request Flag
T6IC.T2IE         6   Interrupt Enable Control Bit (individually enables/disables a specific source)
T6IC.ILVL_5       5   Interrupt Priority Level - bit 5
T6IC.ILVL_4       4   Interrupt Priority Level - bit 4
T6IC.ILVL_3       3   Interrupt Priority Level - bit 3
T6IC.ILVL_2       2   Interrupt Priority Level - bit 2
T6IC.GLVL_1       1   Group Level - bit 1
T6IC.GLVL_0       0   Group Level - bit 0
CRIC             0xFF6A   GPT2 CAPREL Interrupt Control Register
CRIC.CRIR         7   Interrupt Request Flag
CRIC.CRIE         6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CRIC.ILVL_5       5   Interrupt Priority Level - bit 5
CRIC.ILVL_4       4   Interrupt Priority Level - bit 4
CRIC.ILVL_3       3   Interrupt Priority Level - bit 3
CRIC.ILVL_2       2   Interrupt Priority Level - bit 2
CRIC.GLVL_1       1   Group Level - bit 1
CRIC.GLVL_0       0   Group Level - bit 0
S0TIC            0xFF6C   Serial Channel 0 Transmit Interrupt Control Register
S0TIC.S0TIR       7   Interrupt Request Flag
S0TIC.S0TIE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
S0TIC.ILVL_5      5   Interrupt Priority Level - bit 5
S0TIC.ILVL_4      4   Interrupt Priority Level - bit 4
S0TIC.ILVL_3      3   Interrupt Priority Level - bit 3
S0TIC.ILVL_2      2   Interrupt Priority Level - bit 2
S0TIC.GLVL_1      1   Group Level - bit 1
S0TIC.GLVL_0      0   Group Level - bit 0
S0RIC            0xFF6E   Serial Channel 0 Receive Interrupt Control Register
S0RIC.S0RIR       7   Interrupt Request Flag
S0RIC.S0RIE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
S0RIC.ILVL_5      5   Interrupt Priority Level - bit 5
S0RIC.ILVL_4      4   Interrupt Priority Level - bit 4
S0RIC.ILVL_3      3   Interrupt Priority Level - bit 3
S0RIC.ILVL_2      2   Interrupt Priority Level - bit 2
S0RIC.GLVL_1      1   Group Level - bit 1
S0RIC.GLVL_0      0   Group Level - bit 0
S0EIC            0xFF70   Serial Channel 0 Error Interrupt Control Register
S0EIC.S0EIR       7   Interrupt Request Flag
S0EIC.S0EIE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
S0EIC.ILVL_5      5   Interrupt Priority Level - bit 5
S0EIC.ILVL_4      4   Interrupt Priority Level - bit 4
S0EIC.ILVL_3      3   Interrupt Priority Level - bit 3
S0EIC.ILVL_2      2   Interrupt Priority Level - bit 2
S0EIC.GLVL_1      1   Group Level - bit 1
S0EIC.GLVL_0      0   Group Level - bit 0
SSCTIC           0xFF72   SSC Transmit Interrupt Control Register
SSCTIC.SSCTIR     7   Interrupt Request Flag
SSCTIC.SSCTIE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
SSCTIC.ILVL_5     5   Interrupt Priority Level - bit 5
SSCTIC.ILVL_4     4   Interrupt Priority Level - bit 4
SSCTIC.ILVL_3     3   Interrupt Priority Level - bit 3
SSCTIC.ILVL_2     2   Interrupt Priority Level - bit 2
SSCTIC.GLVL_1     1   Group Level - bit 1
SSCTIC.GLVL_0     0   Group Level - bit 0
SSCRIC           0xFF74   SSC Receive Interrupt Control Register
SSCRIC.SSCRIR     7   Interrupt Request Flag
SSCRIC.SSCRIE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
SSCRIC.ILVL_5     5   Interrupt Priority Level - bit 5
SSCRIC.ILVL_4     4   Interrupt Priority Level - bit 4
SSCRIC.ILVL_3     3   Interrupt Priority Level - bit 3
SSCRIC.ILVL_2     2   Interrupt Priority Level - bit 2
SSCRIC.GLVL_1     1   Group Level - bit 1
SSCRIC.GLVL_0     0   Group Level - bit 0
SSCEIC           0xFF76   SSC Error Interrupt Control Register
SSCEIC.SSCEIR     7   Interrupt Request Flag
SSCEIC.SSCEIE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
SSCEIC.ILVL_5     5   Interrupt Priority Level - bit 5
SSCEIC.ILVL_4     4   Interrupt Priority Level - bit 4
SSCEIC.ILVL_3     3   Interrupt Priority Level - bit 3
SSCEIC.ILVL_2     2   Interrupt Priority Level - bit 2
SSCEIC.GLVL_1     1   Group Level - bit 1
SSCEIC.GLVL_0     0   Group Level - bit 0
CC0IC            0xFF78   CAPCOM Register 0 Interrupt Ctrl. Reg.
CC0IC.CC0IR       7   Interrupt Request Flag
CC0IC.CC0IE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC0IC.ILVL_5      5   Interrupt Priority Level - bit 5
CC0IC.ILVL_4      4   Interrupt Priority Level - bit 4
CC0IC.ILVL_3      3   Interrupt Priority Level - bit 3
CC0IC.ILVL_2      2   Interrupt Priority Level - bit 2
CC0IC.GLVL_1      1   Group Level - bit 1
CC0IC.GLVL_0      0   Group Level - bit 0
CC1IC            0xFF7A   CAPCOM Register 1 Interrupt Ctrl. Reg.
CC1IC.CC1IR       7   Interrupt Request Flag
CC1IC.CC1IE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC1IC.ILVL_5      5   Interrupt Priority Level - bit 5
CC1IC.ILVL_4      4   Interrupt Priority Level - bit 4
CC1IC.ILVL_3      3   Interrupt Priority Level - bit 3
CC1IC.ILVL_2      2   Interrupt Priority Level - bit 2
CC1IC.GLVL_1      1   Group Level - bit 1
CC1IC.GLVL_0      0   Group Level - bit 0
CC2IC            0xFF7C   CAPCOM Register 2 Interrupt Ctrl. Reg.
CC2IC.CC2IR       7   Interrupt Request Flag
CC2IC.CC2IE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC2IC.ILVL_5      5   Interrupt Priority Level - bit 5
CC2IC.ILVL_4      4   Interrupt Priority Level - bit 4
CC2IC.ILVL_3      3   Interrupt Priority Level - bit 3
CC2IC.ILVL_2      2   Interrupt Priority Level - bit 2
CC2IC.GLVL_1      1   Group Level - bit 1
CC2IC.GLVL_0      0   Group Level - bit 0
CC3IC            0xFF7E   CAPCOM Register 3 Interrupt Ctrl. Reg.
CC3IC.CC3IR       7   Interrupt Request Flag
CC3IC.CC3IE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC3IC.ILVL_5      5   Interrupt Priority Level - bit 5
CC3IC.ILVL_4      4   Interrupt Priority Level - bit 4
CC3IC.ILVL_3      3   Interrupt Priority Level - bit 3
CC3IC.ILVL_2      2   Interrupt Priority Level - bit 2
CC3IC.GLVL_1      1   Group Level - bit 1
CC3IC.GLVL_0      0   Group Level - bit 0
CC4IC            0xFF80   CAPCOM Register 4 Interrupt Ctrl. Reg.
CC4IC.CC4IR       7   Interrupt Request Flag
CC4IC.CC4IE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC4IC.ILVL_5      5   Interrupt Priority Level - bit 5
CC4IC.ILVL_4      4   Interrupt Priority Level - bit 4
CC4IC.ILVL_3      3   Interrupt Priority Level - bit 3
CC4IC.ILVL_2      2   Interrupt Priority Level - bit 2
CC4IC.GLVL_1      1   Group Level - bit 1
CC4IC.GLVL_0      0   Group Level - bit 0
CC5IC            0xFF82   CAPCOM Register 5 Interrupt Ctrl. Reg.
CC5IC.CC5IR       7   Interrupt Request Flag
CC5IC.CC5IE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC5IC.ILVL_5      5   Interrupt Priority Level - bit 5
CC5IC.ILVL_4      4   Interrupt Priority Level - bit 4
CC5IC.ILVL_3      3   Interrupt Priority Level - bit 3
CC5IC.ILVL_2      2   Interrupt Priority Level - bit 2
CC5IC.GLVL_1      1   Group Level - bit 1
CC5IC.GLVL_0      0   Group Level - bit 0
CC6IC            0xFF84   CAPCOM Register 6 Interrupt Ctrl. Reg.
CC6IC.CC6IR       7   Interrupt Request Flag
CC6IC.CC6IE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC6IC.ILVL_5      5   Interrupt Priority Level - bit 5
CC6IC.ILVL_4      4   Interrupt Priority Level - bit 4
CC6IC.ILVL_3      3   Interrupt Priority Level - bit 3
CC6IC.ILVL_2      2   Interrupt Priority Level - bit 2
CC6IC.GLVL_1      1   Group Level - bit 1
CC6IC.GLVL_0      0   Group Level - bit 0
CC7IC            0xFF86   CAPCOM Register 7 Interrupt Ctrl. Reg.
CC7IC.CC7IR       7   Interrupt Request Flag
CC7IC.CC7IE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC7IC.ILVL_5      5   Interrupt Priority Level - bit 5
CC7IC.ILVL_4      4   Interrupt Priority Level - bit 4
CC7IC.ILVL_3      3   Interrupt Priority Level - bit 3
CC7IC.ILVL_2      2   Interrupt Priority Level - bit 2
CC7IC.GLVL_1      1   Group Level - bit 1
CC7IC.GLVL_0      0   Group Level - bit 0
CC8IC            0xFF88   CAPCOM Register 8 Interrupt Ctrl. Reg.
CC8IC.CC8IR       7   Interrupt Request Flag
CC8IC.CC8IE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC8IC.ILVL_5      5   Interrupt Priority Level - bit 5
CC8IC.ILVL_4      4   Interrupt Priority Level - bit 4
CC8IC.ILVL_3      3   Interrupt Priority Level - bit 3
CC8IC.ILVL_2      2   Interrupt Priority Level - bit 2
CC8IC.GLVL_1      1   Group Level - bit 1
CC8IC.GLVL_0      0   Group Level - bit 0
CC9IC            0xFF8A   CAPCOM Register 9 Interrupt Ctrl. Reg.
CC9IC.CC9IR       7   Interrupt Request Flag
CC9IC.CC9IE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC9IC.ILVL_5      5   Interrupt Priority Level - bit 5
CC9IC.ILVL_4      4   Interrupt Priority Level - bit 4
CC9IC.ILVL_3      3   Interrupt Priority Level - bit 3
CC9IC.ILVL_2      2   Interrupt Priority Level - bit 2
CC9IC.GLVL_1      1   Group Level - bit 1
CC9IC.GLVL_0      0   Group Level - bit 0
CC10IC           0xFF8C   CAPCOM Register 10 Interrupt Ctrl. Reg.
CC10IC.CC10IR     7   Interrupt Request Flag
CC10IC.CC10IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC10IC.ILVL_5     5   Interrupt Priority Level - bit 5
CC10IC.ILVL_4     4   Interrupt Priority Level - bit 4
CC10IC.ILVL_3     3   Interrupt Priority Level - bit 3
CC10IC.ILVL_2     2   Interrupt Priority Level - bit 2
CC10IC.GLVL_1     1   Group Level - bit 1
CC10IC.GLVL_0     0   Group Level - bit 0
CC11IC           0xFF8E   CAPCOM Register 11 Interrupt Ctrl. Reg.
CC11IC.CC11IR     7   Interrupt Request Flag
CC11IC.CC11IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC11IC.ILVL_5     5   Interrupt Priority Level - bit 5
CC11IC.ILVL_4     4   Interrupt Priority Level - bit 4
CC11IC.ILVL_3     3   Interrupt Priority Level - bit 3
CC11IC.ILVL_2     2   Interrupt Priority Level - bit 2
CC11IC.GLVL_1     1   Group Level - bit 1
CC11IC.GLVL_0     0   Group Level - bit 0
CC12IC           0xFF90   CAPCOM Register 12 Interrupt Ctrl. Reg.
CC12IC.CC12IR     7   Interrupt Request Flag
CC12IC.CC12IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC12IC.ILVL_5     5   Interrupt Priority Level - bit 5
CC12IC.ILVL_4     4   Interrupt Priority Level - bit 4
CC12IC.ILVL_3     3   Interrupt Priority Level - bit 3
CC12IC.ILVL_2     2   Interrupt Priority Level - bit 2
CC12IC.GLVL_1     1   Group Level - bit 1
CC12IC.GLVL_0     0   Group Level - bit 0
CC13IC           0xFF92   CAPCOM Register 13 Interrupt Ctrl. Reg.
CC13IC.CC13IR     7   Interrupt Request Flag
CC13IC.CC13IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC13IC.ILVL_5     5   Interrupt Priority Level - bit 5
CC13IC.ILVL_4     4   Interrupt Priority Level - bit 4
CC13IC.ILVL_3     3   Interrupt Priority Level - bit 3
CC13IC.ILVL_2     2   Interrupt Priority Level - bit 2
CC13IC.GLVL_1     1   Group Level - bit 1
CC13IC.GLVL_0     0   Group Level - bit 0
CC14IC           0xFF94   CAH CAPCOM Register 14 Interrupt Ctrl. Reg.
CC14IC.CC14IR     7   Interrupt Request Flag
CC14IC.CC14IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC14IC.ILVL_5     5   Interrupt Priority Level - bit 5
CC14IC.ILVL_4     4   Interrupt Priority Level - bit 4
CC14IC.ILVL_3     3   Interrupt Priority Level - bit 3
CC14IC.ILVL_2     2   Interrupt Priority Level - bit 2
CC14IC.GLVL_1     1   Group Level - bit 1
CC14IC.GLVL_0     0   Group Level - bit 0
CC15IC           0xFF96   CBH CAPCOM Register 15 Interrupt Ctrl. Reg.
CC15IC.CC15IR     7   Interrupt Request Flag
CC15IC.CC15IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC15IC.ILVL_5     5   Interrupt Priority Level - bit 5
CC15IC.ILVL_4     4   Interrupt Priority Level - bit 4
CC15IC.ILVL_3     3   Interrupt Priority Level - bit 3
CC15IC.ILVL_2     2   Interrupt Priority Level - bit 2
CC15IC.GLVL_1     1   Group Level - bit 1
CC15IC.GLVL_0     0   Group Level - bit 0
ADCIC            0xFF98   CCH A/D Converter End of Conversion Interrupt Control Register
ADCIC.ADCIR       7   Interrupt Request Flag
ADCIC.ADCIE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
ADCIC.ILVL_5      5   Interrupt Priority Level - bit 5
ADCIC.ILVL_4      4   Interrupt Priority Level - bit 4
ADCIC.ILVL_3      3   Interrupt Priority Level - bit 3
ADCIC.ILVL_2      2   Interrupt Priority Level - bit 2
ADCIC.GLVL_1      1   Group Level - bit 1
ADCIC.GLVL_0      0   Group Level - bit 0
ADEIC            0xFF9A   CDH A/D Converter Overrun Error Interrupt Control Register
ADEIC.ADEIR       7   Interrupt Request Flag
ADEIC.ADEIE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
ADEIC.ILVL_5      5   Interrupt Priority Level - bit 5
ADEIC.ILVL_4      4   Interrupt Priority Level - bit 4
ADEIC.ILVL_3      3   Interrupt Priority Level - bit 3
ADEIC.ILVL_2      2   Interrupt Priority Level - bit 2
ADEIC.GLVL_1      1   Group Level - bit 1
ADEIC.GLVL_0      0   Group Level - bit 0
T0IC             0xFF9C   CEH CAPCOM Timer 0 Interrupt Ctrl. Reg.
T0IC.T0IR         7   Interrupt Request Flag
T0IC.T0IE         6   Interrupt Enable Control Bit (individually enables/disables a specific source)
T0IC.ILVL_5       5   Interrupt Priority Level - bit 5
T0IC.ILVL_4       4   Interrupt Priority Level - bit 4
T0IC.ILVL_3       3   Interrupt Priority Level - bit 3
T0IC.ILVL_2       2   Interrupt Priority Level - bit 2
T0IC.GLVL_1       1   Group Level - bit 1
T0IC.GLVL_0       0   Group Level - bit 0
T1IC             0xFF9E   CFH CAPCOM Timer 1 Interrupt Ctrl. Reg.
T1IC.T1IR         7   Interrupt Request Flag
T1IC.T1IE         6   Interrupt Enable Control Bit (individually enables/disables a specific source)
T1IC.ILVL_5       5   Interrupt Priority Level - bit 5
T1IC.ILVL_4       4   Interrupt Priority Level - bit 4
T1IC.ILVL_3       3   Interrupt Priority Level - bit 3
T1IC.ILVL_2       2   Interrupt Priority Level - bit 2
T1IC.GLVL_1       1   Group Level - bit 1
T1IC.GLVL_0       0   Group Level - bit 0
ADCON            0xFFA0   A/D Converter Control Register
ADCON.ADCTC_15    15  ADC Conversion Time Control - bit 15
ADCON.ADCTC_14    14  ADC Conversion Time Control - bit 14
ADCON.ADSTC_13    13  ADC Sample Time Control - bit 13
ADCON.ADSTC_12    12  ADC Sample Time Control - bit 12
ADCON.ADCRQ       11  ADC Channel Injection Request Flag
ADCON.ADCIN       10  ADC Channel Injection Enable
ADCON.ADWR        9   ADC Wait for Read Control
ADCON.ADBSY       8   ADC Busy Flag
ADCON.ADST        7   ADC Start Bit
ADCON.ADM_5       5   ADC Mode Selection - bit 5
ADCON.ADM_4       4   ADC Mode Selection - bit 4
ADCON.ADCH_3      3   ADC Analog Channel Input Selection - bit 3
ADCON.ADCH_2      2   ADC Analog Channel Input Selection - bit 2
ADCON.ADCH_1      1   ADC Analog Channel Input Selection - bit 1
ADCON.ADCH_0      0   ADC Analog Channel Input Selection - bit 0
P5               0xFFA2   Port 5 Register (read only)
P5.P5_15          15  Port data register P5 bit 15
P5.P5_14          14  Port data register P5 bit 14
P5.P5_13          13  Port data register P5 bit 13
P5.P5_12          12  Port data register P5 bit 12
P5.P5_7           7   Port data register P5 bit 7 
P5.P5_6           6   Port data register P5 bit 6 
P5.P5_5           5   Port data register P5 bit 5 
P5.P5_4           4   Port data register P5 bit 4 
P5.P5_3           3   Port data register P5 bit 3 
P5.P5_2           2   Port data register P5 bit 2 
P5.P5_1           1   Port data register P5 bit 1 
P5.P5_0           0   Port data register P5 bit 0 
P5DIDIS          0xFFA4   Port 5 Digital Input Disable Register
P5DIDIS.P5D_15    15  Port 5 Bit 15 Digital Input Control
P5DIDIS.P5D_14    14  Port 5 Bit 14 Digital Input Control
P5DIDIS.P5D_13    13  Port 5 Bit 13 Digital Input Control
P5DIDIS.P5D_12    12  Port 5 Bit 12 Digital Input Control
P5DIDIS.P5D_7     7   Port 5 Bit 7  Digital Input Control
P5DIDIS.P5D_6     6   Port 5 Bit 6  Digital Input Control
P5DIDIS.P5D_5     5   Port 5 Bit 5  Digital Input Control
P5DIDIS.P5D_4     4   Port 5 Bit 4  Digital Input Control
P5DIDIS.P5D_3     3   Port 5 Bit 3  Digital Input Control
P5DIDIS.P5D_2     2   Port 5 Bit 2  Digital Input Control
P5DIDIS.P5D_1     1   Port 5 Bit 1  Digital Input Control
P5DIDIS.P5D_0     0   Port 5 Bit 0  Digital Input Control
FOCON            0xFFAA   Frequency Output Control Register
FOCON.FOEN        15  Frequency Output Enable
FOCON.FOSS        14  Frequency Output Signal Select
FOCON.FORV_13     13  Frequency Output Reload Value - bit 13
FOCON.FORV_12     12  Frequency Output Reload Value - bit 12
FOCON.FORV_11     11  Frequency Output Reload Value - bit 11
FOCON.FORV_10     10  Frequency Output Reload Value - bit 10
FOCON.FORV_9      9   Frequency Output Reload Value - bit 9 
FOCON.FORV_8      8   Frequency Output Reload Value - bit 8 
FOCON.FOTL        6   Frequency Output Toggle Latch
FOCON.FOCNT_5     5   Frequency Output Counter - bit 5
FOCON.FOCNT_4     4   Frequency Output Counter - bit 4
FOCON.FOCNT_3     3   Frequency Output Counter - bit 3
FOCON.FOCNT_2     2   Frequency Output Counter - bit 2
FOCON.FOCNT_1     1   Frequency Output Counter - bit 1
FOCON.FOCNT_0     0   Frequency Output Counter - bit 0
TFR              0xFFAC   Trap Flag Register
TFR.NMI           15  Non Maskable Interrupt Flag
TFR.STKOF         14  Stack Overflow Flag
TFR.STKUF         13  Stack Underflow Flag
TFR.UNDOPC        7   Undefined Opcode Flag
TFR.PRTFLT        3   Protection Fault Flag
TFR.ILLOPA        2   Illegal Word Operand Access Flag
TFR.ILLINA        1   Illegal Instruction Access Flag
TFR.ILLBUS        0   Illegal External Bus Access Flag
WDTCON           0xFFAE   Watchdog Timer Control Register      
WDTCON.WDTREL_15  15  Watchdog Timer Reload Value - bit 15
WDTCON.WDTREL_14  14  Watchdog Timer Reload Value - bit 14
WDTCON.WDTREL_13  13  Watchdog Timer Reload Value - bit 13
WDTCON.WDTREL_12  12  Watchdog Timer Reload Value - bit 12
WDTCON.WDTREL_11  11  Watchdog Timer Reload Value - bit 11
WDTCON.WDTREL_10  10  Watchdog Timer Reload Value - bit 10
WDTCON.WDTREL_9   9   Watchdog Timer Reload Value - bit 9 
WDTCON.WDTREL_8   8   Watchdog Timer Reload Value - bit 8 
WDTCON.WDTPRE     7   Watchdog Timer Input Prescaler Control
WDTCON.LHWR       4   Long Hardware Reset Indication Flag
WDTCON.SHWR       3   Short Hardware Reset Indication Flag
WDTCON.SWR        2   Software Reset Indication Flag
WDTCON.WDTR       1   Watchdog Timer Reset Indication Flag
WDTCON.WDTIN      0   Watchdog Timer Input Frequency Select
S0CON            0xFFB0   Serial Channel 0 Control Register    
S0CON.S0R         15  Baudrate Generator Run Bit
S0CON.S0LB        14  LoopBack Mode Enable Bit
S0CON.S0BRS       13  Baudrate Selection Bit
S0CON.S0ODD       12  Parity Selection Bit
S0CON.S0OE        10  Overrun Error Flag
S0CON.S0FE        9   Framing Error Flag
S0CON.S0PE        8   Parity Error Flag
S0CON.S0OEN       7   Overrun Check Enable Bit
S0CON.S0FEN       6   Framing Check Enable Bit
S0CON.S0PEN       5   Parity Check Enable Bit
S0CON.S0REN       4   Receiver Enable Bit
S0CON.S0STP       3   Number of Stop Bits Selection
S0CON.S0M_2       2   ASC0 Mode Control - bit 2
S0CON.S0M_1       1   ASC0 Mode Control - bit 1
S0CON.S0M_0       0   ASC0 Mode Control - bit 0
SSCCON           0xFFB2   SSC Control Register                 
P2               0xFFC0   Port 2 Register
P2.P2_15          15  Port data register P2 bit 15
P2.P2_14          14  Port data register P2 bit 14
P2.P2_13          13  Port data register P2 bit 13
P2.P2_12          12  Port data register P2 bit 12
P2.P2_11          11  Port data register P2 bit 11
P2.P2_10          10  Port data register P2 bit 10
P2.P2_9           9   Port data register P2 bit 9 
P2.P2_8           8   Port data register P2 bit 8 
DP2              0xFFC2   Port 2 Direction Control Register
DP2.DP2_15        15  Port direction register DP2 bit 15
DP2.DP2_14        14  Port direction register DP2 bit 14
DP2.DP2_13        13  Port direction register DP2 bit 13
DP2.DP2_12        12  Port direction register DP2 bit 12
DP2.DP2_11        11  Port direction register DP2 bit 11
DP2.DP2_10        10  Port direction register DP2 bit 10
DP2.DP2_9         9   Port direction register DP2 bit 9 
DP2.DP2_8         8   Port direction register DP2 bit 8 
P3               0xFFC4   Port 3 Register
P3.P3_15          15  Port data register P3 bit 15
P3.P3_13          13  Port data register P3 bit 13
P3.P3_12          12  Port data register P3 bit 12
P3.P3_11          11  Port data register P3 bit 11
P3.P3_10          10  Port data register P3 bit 10
P3.P3_9           9   Port data register P3 bit 9 
P3.P3_8           8   Port data register P3 bit 8 
P3.P3_7           7   Port data register P3 bit 7 
P3.P3_6           6   Port data register P3 bit 6 
P3.P3_5           5   Port data register P3 bit 5 
P3.P3_4           4   Port data register P3 bit 4 
P3.P3_3           3   Port data register P3 bit 3 
P3.P3_2           2   Port data register P3 bit 2 
P3.P3_1           1   Port data register P3 bit 1 
P3.P3_0           0   Port data register P3 bit 0 
DP3              0xFFC6   Port 3 Direction Control Register
DP3.DP3_15        15  Port direction register DP3 bit 15
DP3.DP3_13        13  Port direction register DP3 bit 13
DP3.DP3_12        12  Port direction register DP3 bit 12
DP3.DP3_11        11  Port direction register DP3 bit 11
DP3.DP3_10        10  Port direction register DP3 bit 10
DP3.DP3_9         9   Port direction register DP3 bit 9 
DP3.DP3_8         8   Port direction register DP3 bit 8 
DP3.DP3_7         7   Port direction register DP3 bit 7 
DP3.DP3_6         6   Port direction register DP3 bit 6 
DP3.DP3_5         5   Port direction register DP3 bit 5 
DP3.DP3_4         4   Port direction register DP3 bit 4 
DP3.DP3_3         3   Port direction register DP3 bit 3 
DP3.DP3_2         2   Port direction register DP3 bit 2 
DP3.DP3_1         1   Port direction register DP3 bit 1 
DP3.DP3_0         0   Port direction register DP3 bit 0 
P4               0xFFC8   Port 4 Register (7 bits)
P4.P4_7           7   Port data register P4 bit 7 
P4.P4_6           6   Port data register P4 bit 6 
P4.P4_5           5   Port data register P4 bit 5 
P4.P4_4           4   Port data register P4 bit 4 
P4.P4_3           3   Port data register P4 bit 3 
P4.P4_2           2   Port data register P4 bit 2 
P4.P4_1           1   Port data register P4 bit 1 
P4.P4_0           0   Port data register P4 bit 0 
DP4              0xFFCA   Port 4 Direction Control Register
DP4.DP4_7         7   Port direction register DP4 bit 7 
DP4.DP4_6         6   Port direction register DP4 bit 6 
DP4.DP4_5         5   Port direction register DP4 bit 5 
DP4.DP4_4         4   Port direction register DP4 bit 4 
DP4.DP4_3         3   Port direction register DP4 bit 3 
DP4.DP4_2         2   Port direction register DP4 bit 2 
DP4.DP4_1         1   Port direction register DP4 bit 1 
DP4.DP4_0         0   Port direction register DP4 bit 0 
P6               0xFFCC   Port 6 Register (8 bits)
P6.P6_7           7   Port data register P6 bit 7 
P6.P6_6           6   Port data register P6 bit 6 
P6.P6_5           5   Port data register P6 bit 5 
P6.P6_4           4   Port data register P6 bit 4 
P6.P6_3           3   Port data register P6 bit 3 
P6.P6_2           2   Port data register P6 bit 2 
P6.P6_1           1   Port data register P6 bit 1 
P6.P6_0           0   Port data register P6 bit 0 
DP6              0xFFCE   Port 6 Direction Control Register
DP6.DP6_7         7   Port direction register DP6 bit 7 
DP6.DP6_6         6   Port direction register DP6 bit 6 
DP6.DP6_5         5   Port direction register DP6 bit 5 
DP6.DP6_4         4   Port direction register DP6 bit 4 
DP6.DP6_3         3   Port direction register DP6 bit 3 
DP6.DP6_2         2   Port direction register DP6 bit 2 
DP6.DP6_1         1   Port direction register DP6 bit 1 
DP6.DP6_0         0   Port direction register DP6 bit 0 
P7               0xFFD0   Port 7 Register (8 bits)
P7.P7_7           7   Port data register P7 bit 7 
P7.P7_6           6   Port data register P7 bit 6 
P7.P7_5           5   Port data register P7 bit 5 
P7.P7_4           4   Port data register P7 bit 4 
DP7              0xFFD2   Port 7 Direction Control Register
DP7.DP7_7         7   Port direction register DP7 bit 7 
DP7.DP7_6         6   Port direction register DP7 bit 6 
DP7.DP7_5         5   Port direction register DP7 bit 5 
DP7.DP7_4         4   Port direction register DP7 bit 4 
P9               0xFFD8   Port 9 Register (8 bits)
P9.P9_5           5   Port data register P9 bit 5 
P9.P9_4           4   Port data register P9 bit 4 
P9.P9_3           3   Port data register P9 bit 3 
P9.P9_2           2   Port data register P9 bit 2 
P9.P9_1           1   Port data register P9 bit 1 
P9.P9_0           0   Port data register P9 bit 0 
DP9              0xFFDA   Port 9 Direction Control Register
DP9.DP9_5         5   Port direction register DP9 bit 5 
DP9.DP9_4         4   Port direction register DP9 bit 4 
DP9.DP9_3         3   Port direction register DP9 bit 3 
DP9.DP9_2         2   Port direction register DP9 bit 2 
DP9.DP9_1         1   Port direction register DP9 bit 1 
DP9.DP9_0         0   Port direction register DP9 bit 0 


.C161JC
; http://www.infineon.com/cgi/ecrm.dll/ecrm/scripts/public_download.jsp?oid=18695&parent_oid=13740


; MEMORY MAP
area DATA ROM_           0x0000:0x8000   Internal ROM Area
area DATA MEM_EXT        0x8000:0xC000   External Memory
area DATA XRAM           0xC000:0xE000
area BSS  RESERVED       0xE000:0xEB00
area DATA SDLM_          0xEB00:0xEC00
area BSS  RESERVED       0xEC00:0xED00
area DATA IIC_ASC1       0xED00:0xEE00   IIC/ASC1
area BSS  RESERVED       0xEE00:0xEF00
area DATA CAN1_          0xEF00:0xF000
area DATA ESFR_          0xF000:0xF200   ESFR Area
area BSS  RESERVED       0xF200:0xF600   
area DATA IRAM_          0xF600:0xFE00   IRAM
area DATA SFR_           0xFE00:0x10000  SFR Area


; Interrupt and reset vector assignments
entry RESET     0x0000    RESET
entry NMITRAP   0x0008    NMITRAP Non-Maskable Interrupt (Class A Hardware Traps)
entry STOTRAP   0x0010    STOTRAP Stack Overflow (Class A Hardware Traps)
entry STUTRAP   0x0018    STUTRAP Stack Underflow (Class A Hardware Traps)
entry BTRAP     0x0028    BTRAP Class B Hardware Traps
entry CC0INT    0x0040    CAPCOM Register 0
entry CC1INT    0x0044    CAPCOM Register 1
entry CC2INT    0x0048    CAPCOM Register 2
entry CC3INT    0x004C    CAPCOM Register 3
entry CC4INT    0x0050    CAPCOM Register 4
entry CC5INT    0x0054    CAPCOM Register 5
entry CC6INT    0x0058    CAPCOM Register 6
entry CC7INT    0x005C    CAPCOM Register 7
entry CC8INT    0x0060    CAPCOM Register 8
entry CC9INT    0x0064    CAPCOM Register 9
entry CC10INT   0x0068    CAPCOM Register 10
entry CC11INT   0x006C    CAPCOM Register 11
entry CC12INT   0x0070    CAPCOM Register 12
entry CC13INT   0x0074    CAPCOM Register 13
entry CC14INT   0x0078    CAPCOM Register 14
entry CC15INT   0x007C    CAPCOM Register 15
entry T0INT     0x0080    CAPCOM Timer 0
entry T1INT     0x0084    CAPCOM Timer 1
entry T2INT     0x0088    GPT1 Timer 2
entry T3INT     0x008C    GPT1 Timer 3
entry T4INT     0x0090    GPT1 Timer 4
entry T5INT     0x0094    GPT2 Timer 5
entry T6INT     0x0098    GPT2 Timer 6
entry CRINT     0x009C    GPT2 CAPREL Register
entry ADCINT    0x00A0    A/D Conversion Complete
entry ADEINT    0x00A4    A/D Overrun Error
entry S0TINT    0x00A8    ASC0 Transmit
entry S0RINT    0x00AC    ASC0 Receive
entry S0EINT    0x00B0    ASC0 Error
entry SCTINT    0x00B4    SSC Transmit
entry SCRINT    0x00B8    SSC Receive
entry SCEINT    0x00BC    SSC Error
entry CC16INT   0x00C0    CAPCOM Register 16
entry CC17INT   0x00C4    CAPCOM Register 17
entry CC18INT   0x00C8    CAPCOM Register 18
entry CC19INT   0x00CC    CAPCOM Register 19
entry CC20INT   0x00D0    CAPCOM Register 20
entry CC21INT   0x00D4    CAPCOM Register 21
entry CC22INT   0x00D8    CAPCOM Register 22
entry CC23INT   0x00DC    CAPCOM Register 23
entry CC24INT   0x00E0    CAPCOM Register 24
entry CC25INT   0x00E4    CAPCOM Register 25
entry CC26INT   0x00E8    CAPCOM Register 26
entry CC27INT   0x00EC    CAPCOM Register 27
entry CC28INT   0x00F0    CAPCOM Register 28
entry T7INT     0x00F4    CAPCOM Timer 7
entry T8INT     0x00F8    CAPCOM Timer 8
entry XP0INT    0x0100    IIC Data Transfer Event
entry XP1INT    0x0104    IIC Protocol Event
entry XP2INT    0x0108    CAN1 (C161CS/JC)
entry XP3INT    0x010C    PLL/RTC (via ISNC)
entry CC29INT   0x0110    CAPCOM Register 29
entry CC30INT   0x0114    CAPCOM Register 30
entry CC31INT   0x0118    CAPCOM Register 31
entry S0TBINT   0x011C    ASC0 Transmit Buffer
entry XP4INT    0x0120    ASC1 Transmit
entry XP5INT    0x0124    ASC1 Receive
entry XP6INT    0x0128    ASC1 Error
entry XP7INT    0x012C    SDLM (C161JC/JI)


; INPUT/OUTPUT PORTS
IPCR             0xEB04   SDLM Interface Port Connect Register           
IPCR.IPC_2        2   Interface Port Connection - bit 2
IPCR.IPC_1        1   Interface Port Connection - bit 1
IPCR.IPC_0        0   Interface Port Connection - bit 0
GLOBCON          0xEB10   SDLM Global Control Register                   
GLOBCON.ARIFR     6   Automatic Retry of IFR
GLOBCON.OVWR      5   Overwrite Enable
GLOBCON.NB        4   Normalization Bit Polarity
GLOBCON.HDT       3   Header Type
GLOBCON.BMEN      2   Block Mode Enable
GLOBCON.EN4X      1   High Speed Transfer Enable (4x)
GLOBCON.GMEN      0   Global Module Enable
CLKDIV           0xEB14   SDLM Clock Divider Register                    
CLKDIV.CLKEN      7   Clock Enable
CLKDIV.CLKSEL     6   Clock Select
CLKDIV.CD_5       5   Clock Divider - bit 5
CLKDIV.CD_4       4   Clock Divider - bit 4
CLKDIV.CD_3       3   Clock Divider - bit 3
CLKDIV.CD_2       2   Clock Divider - bit 2
CLKDIV.CD_1       1   Clock Divider - bit 1
CLKDIV.CD_0       0   Clock Divider - bit 0
TxDELAY          0xEB16   SDLM Trabsceiver Delay Register                
TxDELAY.RINV      6   Invert Receive Input
TxDELAY.TD_5      5   Transceiver Delay - bit 5
TxDELAY.TD_4      4   Transceiver Delay - bit 4
TxDELAY.TD_3      3   Transceiver Delay - bit 3
TxDELAY.TD_2      2   Transceiver Delay - bit 2
TxDELAY.TD_1      1   Transceiver Delay - bit 1
TxDELAY.TD_0      0   Transceiver Delay - bit 0
IFR              0xEB18   SDLM In-Frame Response Value Register          
IFR.IFRVAL_7      7   In-Frame Response Value - bit 7
IFR.IFRVAL_6      6   In-Frame Response Value - bit 6
IFR.IFRVAL_5      5   In-Frame Response Value - bit 5
IFR.IFRVAL_4      4   In-Frame Response Value - bit 4
IFR.IFRVAL_3      3   In-Frame Response Value - bit 3
IFR.IFRVAL_2      2   In-Frame Response Value - bit 2
IFR.IFRVAL_1      1   In-Frame Response Value - bit 1
IFR.IFRVAL_0      0   In-Frame Response Value - bit 0
BUFFSTAT         0xEB1C   SDLM Buffer Status Register                    
BUFFSTAT.RBC      4   Receive Buffer on CPU Side Full
BUFFSTAT.RBB      3   Receive Buffer on Bus Side Full
BUFFSTAT.MSGLST   2   Message Lost
BUFFSTAT.RIP      1   Reception in Progress
BUFFSTAT.TIP      0   Transmission In Progress
TRANSSTAT        0xEB1E   SDLM Transmission Status Register              
TRANSSTAT.Y       7   Y Bit in 3 Byte Consolidated Headers
TRANSSTAT.K       6   K Bit in 3 Byte Consolidated Headers
TRANSSTAT.H       5   H Bit in Consolidated Headers
TRANSSTAT.ARL     4   Arbitration Lost
TRANSSTAT.BREAK   3   Break Received
TRANSSTAT.HEADER  2   Header Received
TRANSSTAT.MSGREC  1   Message Received
TRANSSTAT.MSGTRA  0   Message Transmitted
BUSSTAT          0xEB20   SDLM Bus Status Register                       
BUSSTAT.IDLE      3   Bus Idle
BUSSTAT.ENDF      2   End Of Frame Detected
BUSSTAT.EOD       1   End Of Data Detected
BUSSTAT.SOF       0   Start Of Frame Detected
ERRSTAT          0xEB22   SDLM Error Status Register                     
ERRSTAT.CRCER     4   CRC Error
ERRSTAT.COL       3   Collision Detected (lost arbitration)
ERRSTAT.SHORTH    2   Bus Shorted High
ERRSTAT.SHORTL    1   Bus Shorted Low
ERRSTAT.FORMAT    0   Format Error
BUFFCON          0xEB24   SDLM Buffer Control Register                   
BUFFCON.RXINCE    7   Receive Buffer Increment Enable
BUFFCON.TXINCE    6   Transmit Buffer Increment Enable
BUFFCON.IFREN     5   In-Frame Response Enable
BUFFCON.CRCEN     4   CRC Enable
BUFFCON.SBRK      3   Send Break
BUFFCON.DONE      2   Receive Buffer on CPU Side Read Out Done
BUFFCON.TXRQ      1   Transmit Request
BUFFCON.TXIFR     0   Transmit In-Frame Response
FLAGRST          0xEB28   SDLM Flag Reset Register                       
FLAGRST.ERRST     5   Reset Error
FLAGRST.BUSRST    4   Reset Bus Status
FLAGRST.RXRST     3   Reset Buffer Status
FLAGRST.TXRST     2   Reset Buffer Status
FLAGRST.ARLRST    1   Reset Buffer Status
FLAGRST.BRKRST    0   Reset Buffer Status
INTCON           0xEB2C   SDLM Interrupt Control Register                
INTCON.ERRIE      7   Enable Error Interrupt
INTCON.CRCIE      6   Enable CRC Error Interrupt
INTCON.ARLIE      5   Enable Arbitration Lost Interrupt
INTCON.BRKIE      4   Enable Break Received Interrupt
INTCON.ENDFIE     3   Enable End of Frame Detection
INTCON.HDIE       2   Enable Header Received Interrupt
INTCON.RECIE      1   Enable Receive Interrupt
INTCON.TRAIE      0   Enable Transmit Interrupt
TXD0             0xEB30   SDLM Transmit Data Register 0 
TXD0.TXDATA1_15   15  Transmit Buffer Data Byte 1 - bit 15
TXD0.TXDATA1_14   14  Transmit Buffer Data Byte 1 - bit 14
TXD0.TXDATA1_13   13  Transmit Buffer Data Byte 1 - bit 13
TXD0.TXDATA1_12   12  Transmit Buffer Data Byte 1 - bit 12
TXD0.TXDATA1_11   11  Transmit Buffer Data Byte 1 - bit 11
TXD0.TXDATA1_10   10  Transmit Buffer Data Byte 1 - bit 10
TXD0.TXDATA1_9    9   Transmit Buffer Data Byte 1 - bit 9 
TXD0.TXDATA1_8    8   Transmit Buffer Data Byte 1 - bit 8 
TXD0.TXDATA0_7    7   Transmit Buffer Data Byte 0 - bit 7 
TXD0.TXDATA0_6    6   Transmit Buffer Data Byte 0 - bit 6 
TXD0.TXDATA0_5    5   Transmit Buffer Data Byte 0 - bit 5 
TXD0.TXDATA0_4    4   Transmit Buffer Data Byte 0 - bit 4 
TXD0.TXDATA0_3    3   Transmit Buffer Data Byte 0 - bit 3 
TXD0.TXDATA0_2    2   Transmit Buffer Data Byte 0 - bit 2 
TXD0.TXDATA0_1    1   Transmit Buffer Data Byte 0 - bit 1 
TXD0.TXDATA0_0    0   Transmit Buffer Data Byte 0 - bit 0 
TXD2             0xEB32   SDLM Transmit Data Register 2 
TXD2.TXDATA3_15   15  Transmit Buffer Data Byte 3 - bit 15
TXD2.TXDATA3_14   14  Transmit Buffer Data Byte 3 - bit 14
TXD2.TXDATA3_13   13  Transmit Buffer Data Byte 3 - bit 13
TXD2.TXDATA3_12   12  Transmit Buffer Data Byte 3 - bit 12
TXD2.TXDATA3_11   11  Transmit Buffer Data Byte 3 - bit 11
TXD2.TXDATA3_10   10  Transmit Buffer Data Byte 3 - bit 10
TXD2.TXDATA3_9    9   Transmit Buffer Data Byte 3 - bit 9 
TXD2.TXDATA3_8    8   Transmit Buffer Data Byte 3 - bit 8 
TXD2.TXDATA2_7    7   Transmit Buffer Data Byte 2 - bit 7 
TXD2.TXDATA2_6    6   Transmit Buffer Data Byte 2 - bit 6 
TXD2.TXDATA2_5    5   Transmit Buffer Data Byte 2 - bit 5 
TXD2.TXDATA2_4    4   Transmit Buffer Data Byte 2 - bit 4 
TXD2.TXDATA2_3    3   Transmit Buffer Data Byte 2 - bit 3 
TXD2.TXDATA2_2    2   Transmit Buffer Data Byte 2 - bit 2 
TXD2.TXDATA2_1    1   Transmit Buffer Data Byte 2 - bit 1 
TXD2.TXDATA2_0    0   Transmit Buffer Data Byte 2 - bit 0 
TXD4             0xEB34   SDLM Transmit Data Register 4 
TXD4.TXDATA5_15   15  Transmit Buffer Data Byte 5 - bit 15
TXD4.TXDATA5_14   14  Transmit Buffer Data Byte 5 - bit 14
TXD4.TXDATA5_13   13  Transmit Buffer Data Byte 5 - bit 13
TXD4.TXDATA5_12   12  Transmit Buffer Data Byte 5 - bit 12
TXD4.TXDATA5_11   11  Transmit Buffer Data Byte 5 - bit 11
TXD4.TXDATA5_10   10  Transmit Buffer Data Byte 5 - bit 10
TXD4.TXDATA5_9    9   Transmit Buffer Data Byte 5 - bit 9 
TXD4.TXDATA5_8    8   Transmit Buffer Data Byte 5 - bit 8 
TXD4.TXDATA4_7    7   Transmit Buffer Data Byte 4 - bit 7 
TXD4.TXDATA4_6    6   Transmit Buffer Data Byte 4 - bit 6 
TXD4.TXDATA4_5    5   Transmit Buffer Data Byte 4 - bit 5 
TXD4.TXDATA4_4    4   Transmit Buffer Data Byte 4 - bit 4 
TXD4.TXDATA4_3    3   Transmit Buffer Data Byte 4 - bit 3 
TXD4.TXDATA4_2    2   Transmit Buffer Data Byte 4 - bit 2 
TXD4.TXDATA4_1    1   Transmit Buffer Data Byte 4 - bit 1 
TXD4.TXDATA4_0    0   Transmit Buffer Data Byte 4 - bit 0 
TXD6             0xEB36   SDLM Transmit Data Register 6 
TXD6.TXDATA7_15   15  Transmit Buffer Data Byte 7 - bit 15
TXD6.TXDATA7_14   14  Transmit Buffer Data Byte 7 - bit 14
TXD6.TXDATA7_13   13  Transmit Buffer Data Byte 7 - bit 13
TXD6.TXDATA7_12   12  Transmit Buffer Data Byte 7 - bit 12
TXD6.TXDATA7_11   11  Transmit Buffer Data Byte 7 - bit 11
TXD6.TXDATA7_10   10  Transmit Buffer Data Byte 7 - bit 10
TXD6.TXDATA7_9    9   Transmit Buffer Data Byte 7 - bit 9 
TXD6.TXDATA7_8    8   Transmit Buffer Data Byte 7 - bit 8 
TXD6.TXDATA6_7    7   Transmit Buffer Data Byte 6 - bit 7 
TXD6.TXDATA6_6    6   Transmit Buffer Data Byte 6 - bit 6 
TXD6.TXDATA6_5    5   Transmit Buffer Data Byte 6 - bit 5 
TXD6.TXDATA6_4    4   Transmit Buffer Data Byte 6 - bit 4 
TXD6.TXDATA6_3    3   Transmit Buffer Data Byte 6 - bit 3 
TXD6.TXDATA6_2    2   Transmit Buffer Data Byte 6 - bit 2 
TXD6.TXDATA6_1    1   Transmit Buffer Data Byte 6 - bit 1 
TXD6.TXDATA6_0    0   Transmit Buffer Data Byte 6 - bit 0 
TXD8             0xEB38   SDLM Transmit Data Register 8 
TXD8.TXDATA9_15   15  Transmit Buffer Data Byte 9 - bit 15
TXD8.TXDATA9_14   14  Transmit Buffer Data Byte 9 - bit 14
TXD8.TXDATA9_13   13  Transmit Buffer Data Byte 9 - bit 13
TXD8.TXDATA9_12   12  Transmit Buffer Data Byte 9 - bit 12
TXD8.TXDATA9_11   11  Transmit Buffer Data Byte 9 - bit 11
TXD8.TXDATA9_10   10  Transmit Buffer Data Byte 9 - bit 10
TXD8.TXDATA9_9    9   Transmit Buffer Data Byte 9 - bit 9 
TXD8.TXDATA9_8    8   Transmit Buffer Data Byte 9 - bit 8 
TXD8.TXDATA8_7    7   Transmit Buffer Data Byte 8 - bit 7 
TXD8.TXDATA8_6    6   Transmit Buffer Data Byte 8 - bit 6 
TXD8.TXDATA8_5    5   Transmit Buffer Data Byte 8 - bit 5 
TXD8.TXDATA8_4    4   Transmit Buffer Data Byte 8 - bit 4 
TXD8.TXDATA8_3    3   Transmit Buffer Data Byte 8 - bit 3 
TXD8.TXDATA8_2    2   Transmit Buffer Data Byte 8 - bit 2 
TXD8.TXDATA8_1    1   Transmit Buffer Data Byte 8 - bit 1 
TXD8.TXDATA8_0    0   Transmit Buffer Data Byte 8 - bit 0 
TXD10            0xEB3A   SDLM Transmit Data Register 10
TXD10.TXDATA10_7  7   Transmit Buffer Data Byte 10 - bit 7 
TXD10.TXDATA10_6  6   Transmit Buffer Data Byte 10 - bit 6 
TXD10.TXDATA10_5  5   Transmit Buffer Data Byte 10 - bit 5 
TXD10.TXDATA10_4  4   Transmit Buffer Data Byte 10 - bit 4 
TXD10.TXDATA10_3  3   Transmit Buffer Data Byte 10 - bit 3 
TXD10.TXDATA10_2  2   Transmit Buffer Data Byte 10 - bit 2 
TXD10.TXDATA10_1  1   Transmit Buffer Data Byte 10 - bit 1 
TXD10.TXDATA10_0  0   Transmit Buffer Data Byte 10 - bit 0 
TXCNT            0xEB3C   SDLM Bus Transmit Byte Counter                 
TXCNT.TxCNT_3     3   Bus Transmit Byte Counter bit - 3
TXCNT.TxCNT_2     2   Bus Transmit Byte Counter bit - 2
TXCNT.TxCNT_1     1   Bus Transmit Byte Counter bit - 1
TXCNT.TxCNT_0     0   Bus Transmit Byte Counter bit - 0
TXCPU            0xEB3E   SDLM CPU Transmit Byte Counter                 
TXCPU.TxCPU_3     3   CPU Transmit Byte Counter bit - 3
TXCPU.TxCPU_2     2   CPU Transmit Byte Counter bit - 2
TXCPU.TxCPU_1     1   CPU Transmit Byte Counter bit - 1
TXCPU.TxCPU_0     0   CPU Transmit Byte Counter bit - 0
RXD00            0xEB40   SDLM Receive Data Register 0
RXD00.RXDATA01_15 15  Receive Buffer 0 Data Byte 1 - bit 15
RXD00.RXDATA01_14 14  Receive Buffer 0 Data Byte 1 - bit 14
RXD00.RXDATA01_13 13  Receive Buffer 0 Data Byte 1 - bit 13
RXD00.RXDATA01_12 12  Receive Buffer 0 Data Byte 1 - bit 12
RXD00.RXDATA01_11 11  Receive Buffer 0 Data Byte 1 - bit 11
RXD00.RXDATA01_10 10  Receive Buffer 0 Data Byte 1 - bit 10
RXD00.RXDATA01_9  9   Receive Buffer 0 Data Byte 1 - bit 9 
RXD00.RXDATA01_8  8   Receive Buffer 0 Data Byte 1 - bit 8 
RXD00.RXDATA00_7  7   Receive Buffer 0 Data Byte 0 - bit 7 
RXD00.RXDATA00_6  6   Receive Buffer 0 Data Byte 0 - bit 6 
RXD00.RXDATA00_5  5   Receive Buffer 0 Data Byte 0 - bit 5 
RXD00.RXDATA00_4  4   Receive Buffer 0 Data Byte 0 - bit 4 
RXD00.RXDATA00_3  3   Receive Buffer 0 Data Byte 0 - bit 3 
RXD00.RXDATA00_2  2   Receive Buffer 0 Data Byte 0 - bit 2 
RXD00.RXDATA00_1  1   Receive Buffer 0 Data Byte 0 - bit 1 
RXD00.RXDATA00_0  0   Receive Buffer 0 Data Byte 0 - bit 0 
RXD02            0xEB42   SDLM Receive Data Register 2
RXD02.RXDATA03_15 15  Receive Buffer 0 Data Byte 3 - bit 15
RXD02.RXDATA03_14 14  Receive Buffer 0 Data Byte 3 - bit 14
RXD02.RXDATA03_13 13  Receive Buffer 0 Data Byte 3 - bit 13
RXD02.RXDATA03_12 12  Receive Buffer 0 Data Byte 3 - bit 12
RXD02.RXDATA03_11 11  Receive Buffer 0 Data Byte 3 - bit 11
RXD02.RXDATA03_10 10  Receive Buffer 0 Data Byte 3 - bit 10
RXD02.RXDATA03_9  9   Receive Buffer 0 Data Byte 3 - bit 9 
RXD02.RXDATA03_8  8   Receive Buffer 0 Data Byte 3 - bit 8 
RXD02.RXDATA02_7  7   Receive Buffer 0 Data Byte 2 - bit 7 
RXD02.RXDATA02_6  6   Receive Buffer 0 Data Byte 2 - bit 6 
RXD02.RXDATA02_5  5   Receive Buffer 0 Data Byte 2 - bit 5 
RXD02.RXDATA02_4  4   Receive Buffer 0 Data Byte 2 - bit 4 
RXD02.RXDATA02_3  3   Receive Buffer 0 Data Byte 2 - bit 3 
RXD02.RXDATA02_2  2   Receive Buffer 0 Data Byte 2 - bit 2 
RXD02.RXDATA02_1  1   Receive Buffer 0 Data Byte 2 - bit 1 
RXD02.RXDATA02_0  0   Receive Buffer 0 Data Byte 2 - bit 0 
RXD04            0xEB44   SDLM Receive Data Register 4
RXD04.RXDATA05_15 15  Receive Buffer 0 Data Byte 5 - bit 15
RXD04.RXDATA05_14 14  Receive Buffer 0 Data Byte 5 - bit 14
RXD04.RXDATA05_13 13  Receive Buffer 0 Data Byte 5 - bit 13
RXD04.RXDATA05_12 12  Receive Buffer 0 Data Byte 5 - bit 12
RXD04.RXDATA05_11 11  Receive Buffer 0 Data Byte 5 - bit 11
RXD04.RXDATA05_10 10  Receive Buffer 0 Data Byte 5 - bit 10
RXD04.RXDATA05_9  9   Receive Buffer 0 Data Byte 5 - bit 9 
RXD04.RXDATA05_8  8   Receive Buffer 0 Data Byte 5 - bit 8 
RXD04.RXDATA04_7  7   Receive Buffer 0 Data Byte 4 - bit 7 
RXD04.RXDATA04_6  6   Receive Buffer 0 Data Byte 4 - bit 6 
RXD04.RXDATA04_5  5   Receive Buffer 0 Data Byte 4 - bit 5 
RXD04.RXDATA04_4  4   Receive Buffer 0 Data Byte 4 - bit 4 
RXD04.RXDATA04_3  3   Receive Buffer 0 Data Byte 4 - bit 3 
RXD04.RXDATA04_2  2   Receive Buffer 0 Data Byte 4 - bit 2 
RXD04.RXDATA04_1  1   Receive Buffer 0 Data Byte 4 - bit 1 
RXD04.RXDATA04_0  0   Receive Buffer 0 Data Byte 4 - bit 0 
RXD06            0xEB46   SDLM Receive Data Register 6
RXD06.RXDATA07_15 15  Receive Buffer 0 Data Byte 7 - bit 15
RXD06.RXDATA07_14 14  Receive Buffer 0 Data Byte 7 - bit 14
RXD06.RXDATA07_13 13  Receive Buffer 0 Data Byte 7 - bit 13
RXD06.RXDATA07_12 12  Receive Buffer 0 Data Byte 7 - bit 12
RXD06.RXDATA07_11 11  Receive Buffer 0 Data Byte 7 - bit 11
RXD06.RXDATA07_10 10  Receive Buffer 0 Data Byte 7 - bit 10
RXD06.RXDATA07_9  9   Receive Buffer 0 Data Byte 7 - bit 9 
RXD06.RXDATA07_8  8   Receive Buffer 0 Data Byte 7 - bit 8 
RXD06.RXDATA06_7  7   Receive Buffer 0 Data Byte 6 - bit 7 
RXD06.RXDATA06_6  6   Receive Buffer 0 Data Byte 6 - bit 6 
RXD06.RXDATA06_5  5   Receive Buffer 0 Data Byte 6 - bit 5 
RXD06.RXDATA06_4  4   Receive Buffer 0 Data Byte 6 - bit 4 
RXD06.RXDATA06_3  3   Receive Buffer 0 Data Byte 6 - bit 3 
RXD06.RXDATA06_2  2   Receive Buffer 0 Data Byte 6 - bit 2 
RXD06.RXDATA06_1  1   Receive Buffer 0 Data Byte 6 - bit 1 
RXD06.RXDATA06_0  0   Receive Buffer 0 Data Byte 6 - bit 0 
RXD08            0xEB48   SDLM Receive Data Register 8
RXD08.RXDATA09_15 15  Receive Buffer 0 Data Byte 9 - bit 15
RXD08.RXDATA09_14 14  Receive Buffer 0 Data Byte 9 - bit 14
RXD08.RXDATA09_13 13  Receive Buffer 0 Data Byte 9 - bit 13
RXD08.RXDATA09_12 12  Receive Buffer 0 Data Byte 9 - bit 12
RXD08.RXDATA09_11 11  Receive Buffer 0 Data Byte 9 - bit 11
RXD08.RXDATA09_10 10  Receive Buffer 0 Data Byte 9 - bit 10
RXD08.RXDATA09_9  9   Receive Buffer 0 Data Byte 9 - bit 9 
RXD08.RXDATA09_8  8   Receive Buffer 0 Data Byte 9 - bit 8 
RXD08.RXDATA08_7  7   Receive Buffer 0 Data Byte 8 - bit 7 
RXD08.RXDATA08_6  6   Receive Buffer 0 Data Byte 8 - bit 6 
RXD08.RXDATA08_5  5   Receive Buffer 0 Data Byte 8 - bit 5 
RXD08.RXDATA08_4  4   Receive Buffer 0 Data Byte 8 - bit 4 
RXD08.RXDATA08_3  3   Receive Buffer 0 Data Byte 8 - bit 3 
RXD08.RXDATA08_2  2   Receive Buffer 0 Data Byte 8 - bit 2 
RXD08.RXDATA08_1  1   Receive Buffer 0 Data Byte 8 - bit 1 
RXD08.RXDATA08_0  0   Receive Buffer 0 Data Byte 8 - bit 0 
RXD010           0xEB4A   SDLM Receive Data Register 10
RXD010.RXDATA010_7  7 Receive Buffer 0 Data Byte 10 - bit 7 
RXD010.RXDATA010_6  6 Receive Buffer 0 Data Byte 10 - bit 6 
RXD010.RXDATA010_5  5 Receive Buffer 0 Data Byte 10 - bit 5 
RXD010.RXDATA010_4  4 Receive Buffer 0 Data Byte 10 - bit 4 
RXD010.RXDATA010_3  3 Receive Buffer 0 Data Byte 10 - bit 3 
RXD010.RXDATA010_2  2 Receive Buffer 0 Data Byte 10 - bit 2 
RXD010.RXDATA010_1  1 Receive Buffer 0 Data Byte 10 - bit 1 
RXD010.RXDATA010_0  0 Receive Buffer 0 Data Byte 10 - bit 0 
RXCNT            0xEB4C   SDLM Bus Receive Byte Counter (CPU)            
RXCNT.RxCNT_3     3   Receive Byte Count - bit 3
RXCNT.RxCNT_2     2   Receive Byte Count - bit 2
RXCNT.RxCNT_1     1   Receive Byte Count - bit 1
RXCNT.RxCNT_0     0   Receive Byte Count - bit 0
RXCPU            0xEB4E   SDLM CPU Receive Byte Counter (CPU)            
RXCPU.RxCPU_3     3   CPU Receive Byte Count - bit 3
RXCPU.RxCPU_2     2   CPU Receive Byte Count - bit 2
RXCPU.RxCPU_1     1   CPU Receive Byte Count - bit 1
RXCPU.RxCPU_0     0   CPU Receive Byte Count - bit 0
RXD10            0xEB50   Receive Data Register 10 (bus)
RXD10.RXDATA11_15 15  Receive Buffer 1 Data Byte 1 - bit 15
RXD10.RXDATA11_14 14  Receive Buffer 1 Data Byte 1 - bit 14
RXD10.RXDATA11_13 13  Receive Buffer 1 Data Byte 1 - bit 13
RXD10.RXDATA11_12 12  Receive Buffer 1 Data Byte 1 - bit 12
RXD10.RXDATA11_11 11  Receive Buffer 1 Data Byte 1 - bit 11
RXD10.RXDATA11_10 10  Receive Buffer 1 Data Byte 1 - bit 10
RXD10.RXDATA11_9  9   Receive Buffer 1 Data Byte 1 - bit 9 
RXD10.RXDATA11_8  8   Receive Buffer 1 Data Byte 1 - bit 8 
RXD10.RXDATA10_7  7   Receive Buffer 1 Data Byte 0 - bit 7 
RXD10.RXDATA10_6  6   Receive Buffer 1 Data Byte 0 - bit 6 
RXD10.RXDATA10_5  5   Receive Buffer 1 Data Byte 0 - bit 5 
RXD10.RXDATA10_4  4   Receive Buffer 1 Data Byte 0 - bit 4 
RXD10.RXDATA10_3  3   Receive Buffer 1 Data Byte 0 - bit 3 
RXD10.RXDATA10_2  2   Receive Buffer 1 Data Byte 0 - bit 2 
RXD10.RXDATA10_1  1   Receive Buffer 1 Data Byte 0 - bit 1 
RXD10.RXDATA10_0  0   Receive Buffer 1 Data Byte 0 - bit 0 
RXD12            0xEB52   Receive Data Register 12 (bus)
RXD12.RXDATA13_15 15  Receive Buffer 1 Data Byte 3 - bit 15
RXD12.RXDATA13_14 14  Receive Buffer 1 Data Byte 3 - bit 14
RXD12.RXDATA13_13 13  Receive Buffer 1 Data Byte 3 - bit 13
RXD12.RXDATA13_12 12  Receive Buffer 1 Data Byte 3 - bit 12
RXD12.RXDATA13_11 11  Receive Buffer 1 Data Byte 3 - bit 11
RXD12.RXDATA13_10 10  Receive Buffer 1 Data Byte 3 - bit 10
RXD12.RXDATA13_9  9   Receive Buffer 1 Data Byte 3 - bit 9 
RXD12.RXDATA12_8  8   Receive Buffer 1 Data Byte 2 - bit 8 
RXD12.RXDATA12_7  7   Receive Buffer 1 Data Byte 2 - bit 7 
RXD12.RXDATA12_6  6   Receive Buffer 1 Data Byte 2 - bit 6 
RXD12.RXDATA12_5  5   Receive Buffer 1 Data Byte 2 - bit 5 
RXD12.RXDATA12_4  4   Receive Buffer 1 Data Byte 2 - bit 4 
RXD12.RXDATA12_3  3   Receive Buffer 1 Data Byte 2 - bit 3 
RXD12.RXDATA12_2  2   Receive Buffer 1 Data Byte 2 - bit 2 
RXD12.RXDATA12_1  1   Receive Buffer 1 Data Byte 2 - bit 1 
RXD12.RXDATA12_0  0   Receive Buffer 1 Data Byte 2 - bit 0 
RXD14            0xEB54   Receive Data Register 14 (bus)
RXD14.RXDATA15_15 15  Receive Buffer 1 Data Byte 5 - bit 15
RXD14.RXDATA15_14 14  Receive Buffer 1 Data Byte 5 - bit 14
RXD14.RXDATA15_13 13  Receive Buffer 1 Data Byte 5 - bit 13
RXD14.RXDATA15_12 12  Receive Buffer 1 Data Byte 5 - bit 12
RXD14.RXDATA15_11 11  Receive Buffer 1 Data Byte 5 - bit 11
RXD14.RXDATA15_10 10  Receive Buffer 1 Data Byte 5 - bit 10
RXD14.RXDATA15_9  9   Receive Buffer 1 Data Byte 5 - bit 9 
RXD14.RXDATA15_8  8   Receive Buffer 1 Data Byte 5 - bit 8 
RXD14.RXDATA14_7  7   Receive Buffer 1 Data Byte 4 - bit 7 
RXD14.RXDATA14_6  6   Receive Buffer 1 Data Byte 4 - bit 6 
RXD14.RXDATA14_5  5   Receive Buffer 1 Data Byte 4 - bit 5 
RXD14.RXDATA14_4  4   Receive Buffer 1 Data Byte 4 - bit 4 
RXD14.RXDATA14_3  3   Receive Buffer 1 Data Byte 4 - bit 3 
RXD14.RXDATA14_2  2   Receive Buffer 1 Data Byte 4 - bit 2 
RXD14.RXDATA14_1  1   Receive Buffer 1 Data Byte 4 - bit 1 
RXD14.RXDATA14_0  0   Receive Buffer 1 Data Byte 4 - bit 0 
RXD16            0xEB56   Receive Data Register 16 (bus)
RXD16.RXDATA17_15 15  Receive Buffer 1 Data Byte 7 - bit 15
RXD16.RXDATA17_14 14  Receive Buffer 1 Data Byte 7 - bit 14
RXD16.RXDATA17_13 13  Receive Buffer 1 Data Byte 7 - bit 13
RXD16.RXDATA17_12 12  Receive Buffer 1 Data Byte 7 - bit 12
RXD16.RXDATA17_11 11  Receive Buffer 1 Data Byte 7 - bit 11
RXD16.RXDATA17_10 10  Receive Buffer 1 Data Byte 7 - bit 10
RXD16.RXDATA17_9  9   Receive Buffer 1 Data Byte 7 - bit 9 
RXD16.RXDATA17_8  8   Receive Buffer 1 Data Byte 7 - bit 8 
RXD16.RXDATA16_7  7   Receive Buffer 1 Data Byte 6 - bit 7 
RXD16.RXDATA16_6  6   Receive Buffer 1 Data Byte 6 - bit 6 
RXD16.RXDATA16_5  5   Receive Buffer 1 Data Byte 6 - bit 5 
RXD16.RXDATA16_4  4   Receive Buffer 1 Data Byte 6 - bit 4 
RXD16.RXDATA16_3  3   Receive Buffer 1 Data Byte 6 - bit 3 
RXD16.RXDATA16_2  2   Receive Buffer 1 Data Byte 6 - bit 2 
RXD16.RXDATA16_1  1   Receive Buffer 1 Data Byte 6 - bit 1 
RXD16.RXDATA16_0  0   Receive Buffer 1 Data Byte 6 - bit 0 
RXD18            0xEB58   Receive Data Register 18 (bus)
RXD18.RXDATA19_15 15  Receive Buffer 1 Data Byte 9 - bit 15
RXD18.RXDATA19_14 14  Receive Buffer 1 Data Byte 9 - bit 14
RXD18.RXDATA19_13 13  Receive Buffer 1 Data Byte 9 - bit 13
RXD18.RXDATA19_12 12  Receive Buffer 1 Data Byte 9 - bit 12
RXD18.RXDATA19_11 11  Receive Buffer 1 Data Byte 9 - bit 11
RXD18.RXDATA19_10 10  Receive Buffer 1 Data Byte 9 - bit 10
RXD18.RXDATA19_9  9   Receive Buffer 1 Data Byte 9 - bit 9 
RXD18.RXDATA19_8  8   Receive Buffer 1 Data Byte 9 - bit 8 
RXD18.RXDATA18_7  7   Receive Buffer 1 Data Byte 8 - bit 7 
RXD18.RXDATA18_6  6   Receive Buffer 1 Data Byte 8 - bit 6 
RXD18.RXDATA18_5  5   Receive Buffer 1 Data Byte 8 - bit 5 
RXD18.RXDATA18_4  4   Receive Buffer 1 Data Byte 8 - bit 4 
RXD18.RXDATA18_3  3   Receive Buffer 1 Data Byte 8 - bit 3 
RXD18.RXDATA18_2  2   Receive Buffer 1 Data Byte 8 - bit 2 
RXD18.RXDATA18_1  1   Receive Buffer 1 Data Byte 8 - bit 1 
RXD18.RXDATA18_0  0   Receive Buffer 1 Data Byte 8 - bit 0 
RXD110           0xEB5A   Receive Data Register 110 (bus)
RXD110.RXDATA110_7  7 Receive Buffer 1 Data Byte 10 - bit 7 
RXD110.RXDATA110_6  6 Receive Buffer 1 Data Byte 10 - bit 6 
RXD110.RXDATA110_5  5 Receive Buffer 1 Data Byte 10 - bit 5 
RXD110.RXDATA110_4  4 Receive Buffer 1 Data Byte 10 - bit 4 
RXD110.RXDATA110_3  3 Receive Buffer 1 Data Byte 10 - bit 3 
RXD110.RXDATA110_2  2 Receive Buffer 1 Data Byte 10 - bit 2 
RXD110.RXDATA110_1  1 Receive Buffer 1 Data Byte 10 - bit 1 
RXD110.RXDATA110_0  0 Receive Buffer 1 Data Byte 10 - bit 0 
RXCNTB           0xEB5C   SDLM Bus Receive Byte Counter (Bus)            
RXCNTB.RxCNTB_3   3   Receive Byte Counter - bit 3
RXCNTB.RxCNTB_2   2   Receive Byte Counter - bit 2
RXCNTB.RxCNTB_1   1   Receive Byte Counter - bit 1
RXCNTB.RxCNTB_0   0   Receive Byte Counter - bit 0
SOFPTR           0xEB60   SDLM Start-of-frame Pointer Register           
SOFPTR.SOFCNT_3   3   Start-of-Frame Counter for Block Mode - bit 3
SOFPTR.SOFCNT_2   2   Start-of-Frame Counter for Block Mode - bit 2
SOFPTR.SOFCNT_1   1   Start-of-Frame Counter for Block Mode - bit 1
SOFPTR.SOFCNT_0   0   Start-of-Frame Counter for Block Mode - bit 0
ICCFG            0xED00   IIC Configuration Register                     
ICCFG.BRP_15      15  Baudrate Prescaler  - bit 15
ICCFG.BRP_14      14  Baudrate Prescaler  - bit 14
ICCFG.BRP_13      13  Baudrate Prescaler  - bit 13
ICCFG.BRP_12      12  Baudrate Prescaler  - bit 12
ICCFG.BRP_11      11  Baudrate Prescaler  - bit 11
ICCFG.BRP_10      10  Baudrate Prescaler  - bit 10
ICCFG.BRP_9       9   Baudrate Prescaler  - bit 9 
ICCFG.BRP_8       8   Baudrate Prescaler  - bit 8 
ICCFG.SCLSEL1     5   SCL Pin Selection 1
ICCFG.SCLSEL0     4   SCL Pin Selection 0
ICCFG.SDASEL2     2   SDA Pin Selection 2
ICCFG.SDASEL1     1   SDA Pin Selection 1
ICCFG.SDASEL0     0   SDA Pin Selection 0
ICCON            0xED02   IIC Control Register                           
ICCON.TRX         7   Transmit Select
ICCON.AIRDIS      6   Auto Interrupt Reset Disable
ICCON.ACKDIS      5   Acknowledge Pulse Disable
ICCON.BUM         4   Busy Master
ICCON.MOD_3       3   Basic Operating Mode - bit 3 
ICCON.MOD_2       2   Basic Operating Mode - bit 2 
ICCON.RSC         1   Repeated Start Condition
ICCON.M10         0   Address Mode
ICST             0xED04   IIC Status Register                            
ICST.IRQP         6  IIC Interrupt Request Bit for Protocol Events
ICST.IRQD         5  IIC Interrupt Request Bit for Data Transfer Events
ICST.BB           4  Bus Busy
ICST.LRB          3  Last Received Bit
ICST.SLA          2  Slave
ICST.AL           1  Arbitration Lost
ICST.ADR          0  Address
ICADR            0xED06   IIC Address Register                           
ICADR.ICA9        9
ICADR.ICA8        8
ICADR.ICA7        7
ICADR.ICA6        6
ICADR.ICA5        5
ICADR.ICA4        4
ICADR.ICA3        3
ICADR.ICA2        2
ICADR.ICA1        1
ICADR.ICA0        0
ICRTB            0xED08   IIC Receive/Transmit Buffer                    
ICRTB.ICData_7    7   Transmit and shift data - bit 7
ICRTB.ICData_6    6   Transmit and shift data - bit 6
ICRTB.ICData_5    5   Transmit and shift data - bit 5
ICRTB.ICData_4    4   Transmit and shift data - bit 4
ICRTB.ICData_3    3   Transmit and shift data - bit 3
ICRTB.ICData_2    2   Transmit and shift data - bit 2
ICRTB.ICData_1    1   Transmit and shift data - bit 1
ICRTB.ICData_0    0   Transmit and shift data - bit 0
S1TBUF           0xEDA0   Serial Channel 1 Transmit Buffer Register      
S1RBUF           0xEDA2   Serial Channel 1 Receive Buffer Register (read only)
S1BG             0xEDA4   Serial Channel 1 Baud Rate Generator Reload Register
S1CON            0xEDA6   Serial Channel 1 Control Register              
S1CON.S1R         15  Baudrate Generator Run Bit
S1CON.S1LB        14  LoopBack Mode Enable Bit
S1CON.S1BRS       13  Baudrate Selection Bit
S1CON.S1ODD       12  Parity Selection Bit
S1CON.S1OE        10  Overrun Error Flag
S1CON.S1FE        9   Framing Error Flag
S1CON.S1PE        8   Parity Error Flag
S1CON.S1OEN       7   Overrun Check Enable Bit
S1CON.S1FEN       6   Framing Check Enable Bit
S1CON.S1PEN       5   Parity Check Enable Bit
S1CON.S1REN       4   Receiver Enable Bit
S1CON.S1STP       3   Number of Stop Bits Selection
S1CON.S1M_2       2   ASC1 Mode Control - bit 2
S1CON.S1M_1       1   ASC1 Mode Control - bit 1
S1CON.S1M_0       0   ASC1 Mode Control - bit 0
C2CSR            0xEE00   CAN2 Control/Status Register                   
C2CSR.BOFF        15  Busoff Status
C2CSR.EWRN        14  Error Warning Status
C2CSR.RXOK        12  Received Message Successfully
C2CSR.TXOK        11  Transmitted Message Successfully
C2CSR.LEC_10      10  Last Error Code - bit 10
C2CSR.LEC_9       9   Last Error Code - bit 9 
C2CSR.LEC_8       8   Last Error Code - bit 8 
C2CSR.TM          7   Test Mode
C2CSR.CCE         6   Configuration Change Enable
C2CSR.CPS         4   Clock Prescaler Control Bit
C2CSR.EIE         3   Error Interrupt Enable
C2CSR.SIE         2   Status Change Interrupt Enable
C2CSR.IE          1   Interrupt Enable
C2CSR.INIT        0   Initialization
C2PCIR           0xEE02   CAN2Port Control and Interrupt Register        
C2PCIR.IPC_10     10  Interface Port Control - bit 10
C2PCIR.IPC_9      9   Interface Port Control - bit 9 
C2PCIR.IPC_8      8   Interface Port Control - bit 8 
C2PCIR.INTID_7    7   Interrupt Identifier - bit 7
C2PCIR.INTID_6    6   Interrupt Identifier - bit 6
C2PCIR.INTID_5    5   Interrupt Identifier - bit 5
C2PCIR.INTID_4    4   Interrupt Identifier - bit 4
C2PCIR.INTID_3    3   Interrupt Identifier - bit 3
C2PCIR.INTID_2    2   Interrupt Identifier - bit 2
C2PCIR.INTID_1    1   Interrupt Identifier - bit 1
C2PCIR.INTID_0    0   Interrupt Identifier - bit 0
C2BTR            0xEE04   CAN2 Bit Timing Register                       
C2BTR.TSEG2_14    14  Time Segment after sample point - bit 14
C2BTR.TSEG2_13    13  Time Segment after sample point - bit 13
C2BTR.TSEG2_12    12  Time Segment after sample point - bit 12
C2BTR.TSEG1_11    11  Time Segment before sample point - bit 11
C2BTR.TSEG1_10    10  Time Segment before sample point - bit 10
C2BTR.TSEG1_9     9   Time Segment before sample point - bit 9 
C2BTR.TSEG1_8     8   Time Segment before sample point - bit 8 
C2BTR.SJW_7       7   (Re)Synchronization Jump Width - bit 7
C2BTR.SJW_6       6   (Re)Synchronization Jump Width - bit 6
C2BTR.BRP_5       5   Baud Rate Prescaler - bit 5
C2BTR.BRP_4       4   Baud Rate Prescaler - bit 4
C2BTR.BRP_3       3   Baud Rate Prescaler - bit 3
C2BTR.BRP_2       2   Baud Rate Prescaler - bit 2
C2BTR.BRP_1       1   Baud Rate Prescaler - bit 1
C2BTR.BRP_0       0   Baud Rate Prescaler - bit 0
C2GMS            0xEE06   CAN2 Global Mask Short                         
C2GMS.ID20        15  Identifier 20
C2GMS.ID19        14  Identifier 19
C2GMS.ID18        13  Identifier 18
C2GMS.ID28        7   Identifier 28
C2GMS.ID27        6   Identifier 27
C2GMS.ID26        5   Identifier 26
C2GMS.ID25        4   Identifier 25
C2GMS.ID24        3   Identifier 24
C2GMS.ID23        2   Identifier 23
C2GMS.ID22        1   Identifier 22
C2GMS.ID21        0   Identifier 21
C2UGML           0xEE08   CAN2 Upper Global Mask Long                    
C2UGML.ID20       15  Identifier 20
C2UGML.ID19       14  Identifier 19
C2UGML.ID18       13  Identifier 18
C2UGML.ID17       12  Identifier 17
C2UGML.ID16       11  Identifier 16
C2UGML.ID15       10  Identifier 15
C2UGML.ID14       9   Identifier 14
C2UGML.ID13       8   Identifier 13
C2UGML.ID28       7   Identifier 28
C2UGML.ID27       6   Identifier 27
C2UGML.ID26       5   Identifier 26
C2UGML.ID25       4   Identifier 25
C2UGML.ID24       3   Identifier 24
C2UGML.ID23       2   Identifier 23
C2UGML.ID22       1   Identifier 22
C2UGML.ID21       0   Identifier 21
C2LGML           0xEE0A   CAN2 Lower Global Mask Long                    
C2LGML.ID4        15  Identifier 4 
C2LGML.ID3        14  Identifier 3 
C2LGML.ID2        13  Identifier 2 
C2LGML.ID1        12  Identifier 1 
C2LGML.ID0        11  Identifier 0 
C2LGML.ID12       7   Identifier 12
C2LGML.ID11       6   Identifier 11
C2LGML.ID10       5   Identifier 10
C2LGML.ID9        4   Identifier 9 
C2LGML.ID8        3   Identifier 8 
C2LGML.ID7        2   Identifier 7 
C2LGML.ID6        1   Identifier 6 
C2LGML.ID5        0   Identifier 5 
C2UMLM           0xEE0C   CAN2 Upper Mask of Last Message                
C2UMLM.ID20       15  Identifier 20
C2UMLM.ID19       14  Identifier 19
C2UMLM.ID18       13  Identifier 18
C2UMLM.ID17       12  Identifier 17
C2UMLM.ID16       11  Identifier 16
C2UMLM.ID15       10  Identifier 15
C2UMLM.ID14       9   Identifier 14
C2UMLM.ID13       8   Identifier 13
C2UMLM.ID28       7   Identifier 28
C2UMLM.ID27       6   Identifier 27
C2UMLM.ID26       5   Identifier 26
C2UMLM.ID25       4   Identifier 25
C2UMLM.ID24       3   Identifier 24
C2UMLM.ID23       2   Identifier 23
C2UMLM.ID22       1   Identifier 22
C2UMLM.ID21       0   Identifier 21
C2LMLM           0xEE0E   CAN2 Lower Mask of Last Message                
C2LMLM.ID4        15  Identifier 4 
C2LMLM.ID3        14  Identifier 3 
C2LMLM.ID2        13  Identifier 2 
C2LMLM.ID1        12  Identifier 1 
C2LMLM.ID0        11  Identifier 0 
C2LMLM.ID12       7   Identifier 12
C2LMLM.ID11       6   Identifier 11
C2LMLM.ID10       5   Identifier 10
C2LMLM.ID9        4   Identifier 9 
C2LMLM.ID8        3   Identifier 8 
C2LMLM.ID7        2   Identifier 7 
C2LMLM.ID6        1   Identifier 6 
C2LMLM.ID5        0   Identifier 5 
C2MCR1           0xEE11   CAN2 Message Ctrl. Reg. (msg. )
C2MCR1.RMTPND_15        15  Remote Pending - bit 15
C2MCR1.RMTPND_14        14  Remote Pending - bit 14
C2MCR1.TXRQ_13          13  Transmit Request - bit 13
C2MCR1.TXRQ_12          12  Transmit Request - bit 12
C2MCR1.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C2MCR1.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C2MCR1.NEWDAT_9         9   New Data - bit 9
C2MCR1.NEWDAT_8         8   New Data - bit 8
C2MCR1.MSGVAL_7         7   Message Valid - bit 7
C2MCR1.MSGVAL_6         6   Message Valid - bit 6
C2MCR1.TXIE_5           5   Transmit Interrupt Enable - bit 5
C2MCR1.TXIE_4           4   Transmit Interrupt Enable - bit 4
C2MCR1.RXIE_3           3   Receive Interrupt Enable - bit 3
C2MCR1.RXIE_2           2   Receive Interrupt Enable - bit 2
C2MCR1.INTPND_1         1   Interrupt Pending - bit 1
C2MCR1.INTPND_0         0   Interrupt Pending - bit 0
C2UAR1           0xEE12   CAN2 Upper Arbitration Reg. (msg. )           
C2UAR1.ID20       15  Identifier 20
C2UAR1.ID19       14  Identifier 19
C2UAR1.ID18       13  Identifier 18
C2UAR1.ID17       12  Identifier 17
C2UAR1.ID16       11  Identifier 16
C2UAR1.ID15       10  Identifier 15
C2UAR1.ID14       9   Identifier 14
C2UAR1.ID13       8   Identifier 13
C2UAR1.ID28       7   Identifier 28
C2UAR1.ID27       6   Identifier 27
C2UAR1.ID26       5   Identifier 26
C2UAR1.ID25       4   Identifier 25
C2UAR1.ID24       3   Identifier 24
C2UAR1.ID23       2   Identifier 23
C2UAR1.ID22       1   Identifier 22
C2UAR1.ID21       0   Identifier 21
C2LAR1           0xEE14   CAN2 Lower Arbitration Register (msg. )       
C2LAR1.ID4        15  Identifier 4 
C2LAR1.ID3        14  Identifier 3 
C2LAR1.ID2        13  Identifier 2 
C2LAR1.ID1        12  Identifier 1 
C2LAR1.ID0        11  Identifier 0 
C2LAR1.ID12       7   Identifier 12
C2LAR1.ID11       6   Identifier 11
C2LAR1.ID10       5   Identifier 10
C2LAR1.ID9        4   Identifier 9 
C2LAR1.ID8        3   Identifier 8 
C2LAR1.ID7        2   Identifier 7 
C2LAR1.ID6        1   Identifier 6 
C2LAR1.ID5        0   Identifier 5 
C2MCFG1          0xEE16   CAN2 Message Configuration Register (msg. )
C2MCFG1.DLC_7     7   Data Length Code - bit 7
C2MCFG1.DLC_6     6   Data Length Code - bit 6
C2MCFG1.DLC_5     5   Data Length Code - bit 5
C2MCFG1.DLC_4     4   Data Length Code - bit 4
C2MCFG1.DIR       3   Message Direction
C2MCFG1.XTD       2   Extended Identifier
C2MCR2           0xEE21   CAN2 Message Ctrl. Reg. (msg. )
C2MCR2.RMTPND_15        15  Remote Pending - bit 15
C2MCR2.RMTPND_14        14  Remote Pending - bit 14
C2MCR2.TXRQ_13          13  Transmit Request - bit 13
C2MCR2.TXRQ_12          12  Transmit Request - bit 12
C2MCR2.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C2MCR2.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C2MCR2.NEWDAT_9         9   New Data - bit 9
C2MCR2.NEWDAT_8         8   New Data - bit 8
C2MCR2.MSGVAL_7         7   Message Valid - bit 7
C2MCR2.MSGVAL_6         6   Message Valid - bit 6
C2MCR2.TXIE_5           5   Transmit Interrupt Enable - bit 5
C2MCR2.TXIE_4           4   Transmit Interrupt Enable - bit 4
C2MCR2.RXIE_3           3   Receive Interrupt Enable - bit 3
C2MCR2.RXIE_2           2   Receive Interrupt Enable - bit 2
C2MCR2.INTPND_1         1   Interrupt Pending - bit 1
C2MCR2.INTPND_0         0   Interrupt Pending - bit 0
C2UAR2           0xEE22   CAN2 Upper Arbitration Reg. (msg. )           
C2UAR2.ID20       15  Identifier 20
C2UAR2.ID19       14  Identifier 19
C2UAR2.ID18       13  Identifier 18
C2UAR2.ID17       12  Identifier 17
C2UAR2.ID16       11  Identifier 16
C2UAR2.ID15       10  Identifier 15
C2UAR2.ID14       9   Identifier 14
C2UAR2.ID13       8   Identifier 13
C2UAR2.ID28       7   Identifier 28
C2UAR2.ID27       6   Identifier 27
C2UAR2.ID26       5   Identifier 26
C2UAR2.ID25       4   Identifier 25
C2UAR2.ID24       3   Identifier 24
C2UAR2.ID23       2   Identifier 23
C2UAR2.ID22       1   Identifier 22
C2UAR2.ID21       0   Identifier 21
C2LAR2           0xEE24   CAN2 Lower Arbitration Register (msg. )       
C2LAR2.ID4        15  Identifier 4 
C2LAR2.ID3        14  Identifier 3 
C2LAR2.ID2        13  Identifier 2 
C2LAR2.ID1        12  Identifier 1 
C2LAR2.ID0        11  Identifier 0 
C2LAR2.ID12       7   Identifier 12
C2LAR2.ID11       6   Identifier 11
C2LAR2.ID10       5   Identifier 10
C2LAR2.ID9        4   Identifier 9 
C2LAR2.ID8        3   Identifier 8 
C2LAR2.ID7        2   Identifier 7 
C2LAR2.ID6        1   Identifier 6 
C2LAR2.ID5        0   Identifier 5 
C2MCFG2          0xEE26   CAN2 Message Configuration Register (msg. )
C2MCFG2.DLC_7     7   Data Length Code - bit 7
C2MCFG2.DLC_6     6   Data Length Code - bit 6
C2MCFG2.DLC_5     5   Data Length Code - bit 5
C2MCFG2.DLC_4     4   Data Length Code - bit 4
C2MCFG2.DIR       3   Message Direction
C2MCFG2.XTD       2   Extended Identifier
C2MCR3           0xEE31   CAN2 Message Ctrl. Reg. (msg. )
C2MCR3.RMTPND_15        15  Remote Pending - bit 15
C2MCR3.RMTPND_14        14  Remote Pending - bit 14
C2MCR3.TXRQ_13          13  Transmit Request - bit 13
C2MCR3.TXRQ_12          12  Transmit Request - bit 12
C2MCR3.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C2MCR3.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C2MCR3.NEWDAT_9         9   New Data - bit 9
C2MCR3.NEWDAT_8         8   New Data - bit 8
C2MCR3.MSGVAL_7         7   Message Valid - bit 7
C2MCR3.MSGVAL_6         6   Message Valid - bit 6
C2MCR3.TXIE_5           5   Transmit Interrupt Enable - bit 5
C2MCR3.TXIE_4           4   Transmit Interrupt Enable - bit 4
C2MCR3.RXIE_3           3   Receive Interrupt Enable - bit 3
C2MCR3.RXIE_2           2   Receive Interrupt Enable - bit 2
C2MCR3.INTPND_1         1   Interrupt Pending - bit 1
C2MCR3.INTPND_0         0   Interrupt Pending - bit 0
C2UAR3           0xEE32   CAN2 Upper Arbitration Reg. (msg. )           
C2UAR3.ID20       15  Identifier 20
C2UAR3.ID19       14  Identifier 19
C2UAR3.ID18       13  Identifier 18
C2UAR3.ID17       12  Identifier 17
C2UAR3.ID16       11  Identifier 16
C2UAR3.ID15       10  Identifier 15
C2UAR3.ID14       9   Identifier 14
C2UAR3.ID13       8   Identifier 13
C2UAR3.ID28       7   Identifier 28
C2UAR3.ID27       6   Identifier 27
C2UAR3.ID26       5   Identifier 26
C2UAR3.ID25       4   Identifier 25
C2UAR3.ID24       3   Identifier 24
C2UAR3.ID23       2   Identifier 23
C2UAR3.ID22       1   Identifier 22
C2UAR3.ID21       0   Identifier 21
C2LAR3           0xEE34   CAN2 Lower Arbitration Register (msg. )       
C2LAR3.ID4        15  Identifier 4 
C2LAR3.ID3        14  Identifier 3 
C2LAR3.ID2        13  Identifier 2 
C2LAR3.ID1        12  Identifier 1 
C2LAR3.ID0        11  Identifier 0 
C2LAR3.ID12       7   Identifier 12
C2LAR3.ID11       6   Identifier 11
C2LAR3.ID10       5   Identifier 10
C2LAR3.ID9        4   Identifier 9 
C2LAR3.ID8        3   Identifier 8 
C2LAR3.ID7        2   Identifier 7 
C2LAR3.ID6        1   Identifier 6 
C2LAR3.ID5        0   Identifier 5 
C2MCFG3          0xEE36   CAN2 Message Configuration Register (msg. )
C2MCFG3.DLC_7     7   Data Length Code - bit 7
C2MCFG3.DLC_6     6   Data Length Code - bit 6
C2MCFG3.DLC_5     5   Data Length Code - bit 5
C2MCFG3.DLC_4     4   Data Length Code - bit 4
C2MCFG3.DIR       3   Message Direction
C2MCFG3.XTD       2   Extended Identifier
C2MCR4           0xEE41   CAN2 Message Ctrl. Reg. (msg. )
C2MCR4.RMTPND_15        15  Remote Pending - bit 15
C2MCR4.RMTPND_14        14  Remote Pending - bit 14
C2MCR4.TXRQ_13          13  Transmit Request - bit 13
C2MCR4.TXRQ_12          12  Transmit Request - bit 12
C2MCR4.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C2MCR4.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C2MCR4.NEWDAT_9         9   New Data - bit 9
C2MCR4.NEWDAT_8         8   New Data - bit 8
C2MCR4.MSGVAL_7         7   Message Valid - bit 7
C2MCR4.MSGVAL_6         6   Message Valid - bit 6
C2MCR4.TXIE_5           5   Transmit Interrupt Enable - bit 5
C2MCR4.TXIE_4           4   Transmit Interrupt Enable - bit 4
C2MCR4.RXIE_3           3   Receive Interrupt Enable - bit 3
C2MCR4.RXIE_2           2   Receive Interrupt Enable - bit 2
C2MCR4.INTPND_1         1   Interrupt Pending - bit 1
C2MCR4.INTPND_0         0   Interrupt Pending - bit 0
C2UAR4           0xEE42   CAN2 Upper Arbitration Reg. (msg. )           
C2UAR4.ID20       15  Identifier 20
C2UAR4.ID19       14  Identifier 19
C2UAR4.ID18       13  Identifier 18
C2UAR4.ID17       12  Identifier 17
C2UAR4.ID16       11  Identifier 16
C2UAR4.ID15       10  Identifier 15
C2UAR4.ID14       9   Identifier 14
C2UAR4.ID13       8   Identifier 13
C2UAR4.ID28       7   Identifier 28
C2UAR4.ID27       6   Identifier 27
C2UAR4.ID26       5   Identifier 26
C2UAR4.ID25       4   Identifier 25
C2UAR4.ID24       3   Identifier 24
C2UAR4.ID23       2   Identifier 23
C2UAR4.ID22       1   Identifier 22
C2UAR4.ID21       0   Identifier 21
C2LAR4           0xEE44   CAN2 Lower Arbitration Register (msg. )       
C2LAR4.ID4        15  Identifier 4 
C2LAR4.ID3        14  Identifier 3 
C2LAR4.ID2        13  Identifier 2 
C2LAR4.ID1        12  Identifier 1 
C2LAR4.ID0        11  Identifier 0 
C2LAR4.ID12       7   Identifier 12
C2LAR4.ID11       6   Identifier 11
C2LAR4.ID10       5   Identifier 10
C2LAR4.ID9        4   Identifier 9 
C2LAR4.ID8        3   Identifier 8 
C2LAR4.ID7        2   Identifier 7 
C2LAR4.ID6        1   Identifier 6 
C2LAR4.ID5        0   Identifier 5 
C2MCFG4          0xEE46   CAN2 Message Configuration Register (msg. )
C2MCFG4.DLC_7     7   Data Length Code - bit 7
C2MCFG4.DLC_6     6   Data Length Code - bit 6
C2MCFG4.DLC_5     5   Data Length Code - bit 5
C2MCFG4.DLC_4     4   Data Length Code - bit 4
C2MCFG4.DIR       3   Message Direction
C2MCFG4.XTD       2   Extended Identifier
C2MCR5           0xEE51   CAN2 Message Ctrl. Reg. (msg. )
C2MCR5.RMTPND_15        15  Remote Pending - bit 15
C2MCR5.RMTPND_14        14  Remote Pending - bit 14
C2MCR5.TXRQ_13          13  Transmit Request - bit 13
C2MCR5.TXRQ_12          12  Transmit Request - bit 12
C2MCR5.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C2MCR5.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C2MCR5.NEWDAT_9         9   New Data - bit 9
C2MCR5.NEWDAT_8         8   New Data - bit 8
C2MCR5.MSGVAL_7         7   Message Valid - bit 7
C2MCR5.MSGVAL_6         6   Message Valid - bit 6
C2MCR5.TXIE_5           5   Transmit Interrupt Enable - bit 5
C2MCR5.TXIE_4           4   Transmit Interrupt Enable - bit 4
C2MCR5.RXIE_3           3   Receive Interrupt Enable - bit 3
C2MCR5.RXIE_2           2   Receive Interrupt Enable - bit 2
C2MCR5.INTPND_1         1   Interrupt Pending - bit 1
C2MCR5.INTPND_0         0   Interrupt Pending - bit 0
C2UAR5           0xEE52   CAN2 Upper Arbitration Reg. (msg. )           
C2UAR5.ID20       15  Identifier 20
C2UAR5.ID19       14  Identifier 19
C2UAR5.ID18       13  Identifier 18
C2UAR5.ID17       12  Identifier 17
C2UAR5.ID16       11  Identifier 16
C2UAR5.ID15       10  Identifier 15
C2UAR5.ID14       9   Identifier 14
C2UAR5.ID13       8   Identifier 13
C2UAR5.ID28       7   Identifier 28
C2UAR5.ID27       6   Identifier 27
C2UAR5.ID26       5   Identifier 26
C2UAR5.ID25       4   Identifier 25
C2UAR5.ID24       3   Identifier 24
C2UAR5.ID23       2   Identifier 23
C2UAR5.ID22       1   Identifier 22
C2UAR5.ID21       0   Identifier 21
C2LAR5           0xEE54   CAN2 Lower Arbitration Register (msg. )       
C2LAR5.ID4        15  Identifier 4 
C2LAR5.ID3        14  Identifier 3 
C2LAR5.ID2        13  Identifier 2 
C2LAR5.ID1        12  Identifier 1 
C2LAR5.ID0        11  Identifier 0 
C2LAR5.ID12       7   Identifier 12
C2LAR5.ID11       6   Identifier 11
C2LAR5.ID10       5   Identifier 10
C2LAR5.ID9        4   Identifier 9 
C2LAR5.ID8        3   Identifier 8 
C2LAR5.ID7        2   Identifier 7 
C2LAR5.ID6        1   Identifier 6 
C2LAR5.ID5        0   Identifier 5 
C2MCFG5          0xEE56   CAN2 Message Configuration Register (msg. )
C2MCFG5.DLC_7     7   Data Length Code - bit 7
C2MCFG5.DLC_6     6   Data Length Code - bit 6
C2MCFG5.DLC_5     5   Data Length Code - bit 5
C2MCFG5.DLC_4     4   Data Length Code - bit 4
C2MCFG5.DIR       3   Message Direction
C2MCFG5.XTD       2   Extended Identifier
C2MCR6           0xEE61   CAN2 Message Ctrl. Reg. (msg. )
C2MCR6.RMTPND_15        15  Remote Pending - bit 15
C2MCR6.RMTPND_14        14  Remote Pending - bit 14
C2MCR6.TXRQ_13          13  Transmit Request - bit 13
C2MCR6.TXRQ_12          12  Transmit Request - bit 12
C2MCR6.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C2MCR6.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C2MCR6.NEWDAT_9         9   New Data - bit 9
C2MCR6.NEWDAT_8         8   New Data - bit 8
C2MCR6.MSGVAL_7         7   Message Valid - bit 7
C2MCR6.MSGVAL_6         6   Message Valid - bit 6
C2MCR6.TXIE_5           5   Transmit Interrupt Enable - bit 5
C2MCR6.TXIE_4           4   Transmit Interrupt Enable - bit 4
C2MCR6.RXIE_3           3   Receive Interrupt Enable - bit 3
C2MCR6.RXIE_2           2   Receive Interrupt Enable - bit 2
C2MCR6.INTPND_1         1   Interrupt Pending - bit 1
C2MCR6.INTPND_0         0   Interrupt Pending - bit 0
C2UAR6           0xEE62   CAN2 Upper Arbitration Reg. (msg. )           
C2UAR6.ID20       15  Identifier 20
C2UAR6.ID19       14  Identifier 19
C2UAR6.ID18       13  Identifier 18
C2UAR6.ID17       12  Identifier 17
C2UAR6.ID16       11  Identifier 16
C2UAR6.ID15       10  Identifier 15
C2UAR6.ID14       9   Identifier 14
C2UAR6.ID13       8   Identifier 13
C2UAR6.ID28       7   Identifier 28
C2UAR6.ID27       6   Identifier 27
C2UAR6.ID26       5   Identifier 26
C2UAR6.ID25       4   Identifier 25
C2UAR6.ID24       3   Identifier 24
C2UAR6.ID23       2   Identifier 23
C2UAR6.ID22       1   Identifier 22
C2UAR6.ID21       0   Identifier 21
C2LAR6           0xEE64   CAN2 Lower Arbitration Register (msg. )       
C2LAR6.ID4        15  Identifier 4 
C2LAR6.ID3        14  Identifier 3 
C2LAR6.ID2        13  Identifier 2 
C2LAR6.ID1        12  Identifier 1 
C2LAR6.ID0        11  Identifier 0 
C2LAR6.ID12       7   Identifier 12
C2LAR6.ID11       6   Identifier 11
C2LAR6.ID10       5   Identifier 10
C2LAR6.ID9        4   Identifier 9 
C2LAR6.ID8        3   Identifier 8 
C2LAR6.ID7        2   Identifier 7 
C2LAR6.ID6        1   Identifier 6 
C2LAR6.ID5        0   Identifier 5 
C2MCFG6          0xEE66   CAN2 Message Configuration Register (msg. )
C2MCFG6.DLC_7     7   Data Length Code - bit 7
C2MCFG6.DLC_6     6   Data Length Code - bit 6
C2MCFG6.DLC_5     5   Data Length Code - bit 5
C2MCFG6.DLC_4     4   Data Length Code - bit 4
C2MCFG6.DIR       3   Message Direction
C2MCFG6.XTD       2   Extended Identifier
C2MCR7           0xEE71   CAN2 Message Ctrl. Reg. (msg. )
C2MCR7.RMTPND_15        15  Remote Pending - bit 15
C2MCR7.RMTPND_14        14  Remote Pending - bit 14
C2MCR7.TXRQ_13          13  Transmit Request - bit 13
C2MCR7.TXRQ_12          12  Transmit Request - bit 12
C2MCR7.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C2MCR7.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C2MCR7.NEWDAT_9         9   New Data - bit 9
C2MCR7.NEWDAT_8         8   New Data - bit 8
C2MCR7.MSGVAL_7         7   Message Valid - bit 7
C2MCR7.MSGVAL_6         6   Message Valid - bit 6
C2MCR7.TXIE_5           5   Transmit Interrupt Enable - bit 5
C2MCR7.TXIE_4           4   Transmit Interrupt Enable - bit 4
C2MCR7.RXIE_3           3   Receive Interrupt Enable - bit 3
C2MCR7.RXIE_2           2   Receive Interrupt Enable - bit 2
C2MCR7.INTPND_1         1   Interrupt Pending - bit 1
C2MCR7.INTPND_0         0   Interrupt Pending - bit 0
C2UAR7           0xEE72   CAN2 Upper Arbitration Reg. (msg. )           
C2UAR7.ID20       15  Identifier 20
C2UAR7.ID19       14  Identifier 19
C2UAR7.ID18       13  Identifier 18
C2UAR7.ID17       12  Identifier 17
C2UAR7.ID16       11  Identifier 16
C2UAR7.ID15       10  Identifier 15
C2UAR7.ID14       9   Identifier 14
C2UAR7.ID13       8   Identifier 13
C2UAR7.ID28       7   Identifier 28
C2UAR7.ID27       6   Identifier 27
C2UAR7.ID26       5   Identifier 26
C2UAR7.ID25       4   Identifier 25
C2UAR7.ID24       3   Identifier 24
C2UAR7.ID23       2   Identifier 23
C2UAR7.ID22       1   Identifier 22
C2UAR7.ID21       0   Identifier 21
C2LAR7           0xEE74   CAN2 Lower Arbitration Register (msg. )       
C2LAR7.ID4        15  Identifier 4 
C2LAR7.ID3        14  Identifier 3 
C2LAR7.ID2        13  Identifier 2 
C2LAR7.ID1        12  Identifier 1 
C2LAR7.ID0        11  Identifier 0 
C2LAR7.ID12       7   Identifier 12
C2LAR7.ID11       6   Identifier 11
C2LAR7.ID10       5   Identifier 10
C2LAR7.ID9        4   Identifier 9 
C2LAR7.ID8        3   Identifier 8 
C2LAR7.ID7        2   Identifier 7 
C2LAR7.ID6        1   Identifier 6 
C2LAR7.ID5        0   Identifier 5 
C2MCFG7          0xEE76   CAN2 Message Configuration Register (msg. )
C2MCFG7.DLC_7     7   Data Length Code - bit 7
C2MCFG7.DLC_6     6   Data Length Code - bit 6
C2MCFG7.DLC_5     5   Data Length Code - bit 5
C2MCFG7.DLC_4     4   Data Length Code - bit 4
C2MCFG7.DIR       3   Message Direction
C2MCFG7.XTD       2   Extended Identifier
C2MCR8           0xEE81   CAN2 Message Ctrl. Reg. (msg. )
C2MCR8.RMTPND_15        15  Remote Pending - bit 15
C2MCR8.RMTPND_14        14  Remote Pending - bit 14
C2MCR8.TXRQ_13          13  Transmit Request - bit 13
C2MCR8.TXRQ_12          12  Transmit Request - bit 12
C2MCR8.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C2MCR8.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C2MCR8.NEWDAT_9         9   New Data - bit 9
C2MCR8.NEWDAT_8         8   New Data - bit 8
C2MCR8.MSGVAL_7         7   Message Valid - bit 7
C2MCR8.MSGVAL_6         6   Message Valid - bit 6
C2MCR8.TXIE_5           5   Transmit Interrupt Enable - bit 5
C2MCR8.TXIE_4           4   Transmit Interrupt Enable - bit 4
C2MCR8.RXIE_3           3   Receive Interrupt Enable - bit 3
C2MCR8.RXIE_2           2   Receive Interrupt Enable - bit 2
C2MCR8.INTPND_1         1   Interrupt Pending - bit 1
C2MCR8.INTPND_0         0   Interrupt Pending - bit 0
C2UAR8           0xEE82   CAN2 Upper Arbitration Reg. (msg. )           
C2UAR8.ID20       15  Identifier 20
C2UAR8.ID19       14  Identifier 19
C2UAR8.ID18       13  Identifier 18
C2UAR8.ID17       12  Identifier 17
C2UAR8.ID16       11  Identifier 16
C2UAR8.ID15       10  Identifier 15
C2UAR8.ID14       9   Identifier 14
C2UAR8.ID13       8   Identifier 13
C2UAR8.ID28       7   Identifier 28
C2UAR8.ID27       6   Identifier 27
C2UAR8.ID26       5   Identifier 26
C2UAR8.ID25       4   Identifier 25
C2UAR8.ID24       3   Identifier 24
C2UAR8.ID23       2   Identifier 23
C2UAR8.ID22       1   Identifier 22
C2UAR8.ID21       0   Identifier 21
C2LAR8           0xEE84   CAN2 Lower Arbitration Register (msg. )       
C2LAR8.ID4        15  Identifier 4 
C2LAR8.ID3        14  Identifier 3 
C2LAR8.ID2        13  Identifier 2 
C2LAR8.ID1        12  Identifier 1 
C2LAR8.ID0        11  Identifier 0 
C2LAR8.ID12       7   Identifier 12
C2LAR8.ID11       6   Identifier 11
C2LAR8.ID10       5   Identifier 10
C2LAR8.ID9        4   Identifier 9 
C2LAR8.ID8        3   Identifier 8 
C2LAR8.ID7        2   Identifier 7 
C2LAR8.ID6        1   Identifier 6 
C2LAR8.ID5        0   Identifier 5 
C2MCFG8          0xEE86   CAN2 Message Configuration Register (msg. )
C2MCFG8.DLC_7     7   Data Length Code - bit 7
C2MCFG8.DLC_6     6   Data Length Code - bit 6
C2MCFG8.DLC_5     5   Data Length Code - bit 5
C2MCFG8.DLC_4     4   Data Length Code - bit 4
C2MCFG8.DIR       3   Message Direction
C2MCFG8.XTD       2   Extended Identifier
C2MCR9           0xEE91   CAN2 Message Ctrl. Reg. (msg. )
C2MCR9.RMTPND_15        15  Remote Pending - bit 15
C2MCR9.RMTPND_14        14  Remote Pending - bit 14
C2MCR9.TXRQ_13          13  Transmit Request - bit 13
C2MCR9.TXRQ_12          12  Transmit Request - bit 12
C2MCR9.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C2MCR9.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C2MCR9.NEWDAT_9         9   New Data - bit 9
C2MCR9.NEWDAT_8         8   New Data - bit 8
C2MCR9.MSGVAL_7         7   Message Valid - bit 7
C2MCR9.MSGVAL_6         6   Message Valid - bit 6
C2MCR9.TXIE_5           5   Transmit Interrupt Enable - bit 5
C2MCR9.TXIE_4           4   Transmit Interrupt Enable - bit 4
C2MCR9.RXIE_3           3   Receive Interrupt Enable - bit 3
C2MCR9.RXIE_2           2   Receive Interrupt Enable - bit 2
C2MCR9.INTPND_1         1   Interrupt Pending - bit 1
C2MCR9.INTPND_0         0   Interrupt Pending - bit 0
C2UAR9           0xEE92   CAN2 Upper Arbitration Reg. (msg. )           
C2UAR9.ID20       15  Identifier 20
C2UAR9.ID19       14  Identifier 19
C2UAR9.ID18       13  Identifier 18
C2UAR9.ID17       12  Identifier 17
C2UAR9.ID16       11  Identifier 16
C2UAR9.ID15       10  Identifier 15
C2UAR9.ID14       9   Identifier 14
C2UAR9.ID13       8   Identifier 13
C2UAR9.ID28       7   Identifier 28
C2UAR9.ID27       6   Identifier 27
C2UAR9.ID26       5   Identifier 26
C2UAR9.ID25       4   Identifier 25
C2UAR9.ID24       3   Identifier 24
C2UAR9.ID23       2   Identifier 23
C2UAR9.ID22       1   Identifier 22
C2UAR9.ID21       0   Identifier 21
C2LAR9           0xEE94   CAN2 Lower Arbitration Register (msg. )       
C2LAR9.ID4        15  Identifier 4 
C2LAR9.ID3        14  Identifier 3 
C2LAR9.ID2        13  Identifier 2 
C2LAR9.ID1        12  Identifier 1 
C2LAR9.ID0        11  Identifier 0 
C2LAR9.ID12       7   Identifier 12
C2LAR9.ID11       6   Identifier 11
C2LAR9.ID10       5   Identifier 10
C2LAR9.ID9        4   Identifier 9 
C2LAR9.ID8        3   Identifier 8 
C2LAR9.ID7        2   Identifier 7 
C2LAR9.ID6        1   Identifier 6 
C2LAR9.ID5        0   Identifier 5 
C2MCFG9          0xEE96   CAN2 Message Configuration Register (msg. )
C2MCFG9.DLC_7     7   Data Length Code - bit 7
C2MCFG9.DLC_6     6   Data Length Code - bit 6
C2MCFG9.DLC_5     5   Data Length Code - bit 5
C2MCFG9.DLC_4     4   Data Length Code - bit 4
C2MCFG9.DIR       3   Message Direction
C2MCFG9.XTD       2   Extended Identifier
C2MCR10          0xEEA1   CAN2 Message Ctrl. Reg. (msg. )
C2MCR10.RMTPND_15        15  Remote Pending - bit 15
C2MCR10.RMTPND_14        14  Remote Pending - bit 14
C2MCR10.TXRQ_13          13  Transmit Request - bit 13
C2MCR10.TXRQ_12          12  Transmit Request - bit 12
C2MCR10.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C2MCR10.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C2MCR10.NEWDAT_9         9   New Data - bit 9
C2MCR10.NEWDAT_8         8   New Data - bit 8
C2MCR10.MSGVAL_7         7   Message Valid - bit 7
C2MCR10.MSGVAL_6         6   Message Valid - bit 6
C2MCR10.TXIE_5           5   Transmit Interrupt Enable - bit 5
C2MCR10.TXIE_4           4   Transmit Interrupt Enable - bit 4
C2MCR10.RXIE_3           3   Receive Interrupt Enable - bit 3
C2MCR10.RXIE_2           2   Receive Interrupt Enable - bit 2
C2MCR10.INTPND_1         1   Interrupt Pending - bit 1
C2MCR10.INTPND_0         0   Interrupt Pending - bit 0
C2UAR10          0xEEA2   CAN2 Upper Arbitration Reg. (msg. )
C2UAR10.ID20      15  Identifier 20
C2UAR10.ID19      14  Identifier 19
C2UAR10.ID18      13  Identifier 18
C2UAR10.ID17      12  Identifier 17
C2UAR10.ID16      11  Identifier 16
C2UAR10.ID15      10  Identifier 15
C2UAR10.ID14      9   Identifier 14
C2UAR10.ID13      8   Identifier 13
C2UAR10.ID28      7   Identifier 28
C2UAR10.ID27      6   Identifier 27
C2UAR10.ID26      5   Identifier 26
C2UAR10.ID25      4   Identifier 25
C2UAR10.ID24      3   Identifier 24
C2UAR10.ID23      2   Identifier 23
C2UAR10.ID22      1   Identifier 22
C2UAR10.ID21      0   Identifier 21
C2LAR10          0xEEA4   CAN2 Lower Arbitration Register (msg. )
C2LAR10.ID4       15  Identifier 4 
C2LAR10.ID3       14  Identifier 3 
C2LAR10.ID2       13  Identifier 2 
C2LAR10.ID1       12  Identifier 1 
C2LAR10.ID0       11  Identifier 0 
C2LAR10.ID12      7   Identifier 12
C2LAR10.ID11      6   Identifier 11
C2LAR10.ID10      5   Identifier 10
C2LAR10.ID9       4   Identifier 9 
C2LAR10.ID8       3   Identifier 8 
C2LAR10.ID7       2   Identifier 7 
C2LAR10.ID6       1   Identifier 6 
C2LAR10.ID5       0   Identifier 5 
C2MCFG10         0xEEA6   CAN2 Message Configuration Register (msg. )
C2MCFG10.DLC_7     7   Data Length Code - bit 7
C2MCFG10.DLC_6     6   Data Length Code - bit 6
C2MCFG10.DLC_5     5   Data Length Code - bit 5
C2MCFG10.DLC_4     4   Data Length Code - bit 4
C2MCFG10.DIR       3   Message Direction
C2MCFG10.XTD       2   Extended Identifier
C2MCR11          0xEEB1   CAN2 Message Ctrl. Reg. (msg. )
C2MCR11.RMTPND_15        15  Remote Pending - bit 15
C2MCR11.RMTPND_14        14  Remote Pending - bit 14
C2MCR11.TXRQ_13          13  Transmit Request - bit 13
C2MCR11.TXRQ_12          12  Transmit Request - bit 12
C2MCR11.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C2MCR11.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C2MCR11.NEWDAT_9         9   New Data - bit 9
C2MCR11.NEWDAT_8         8   New Data - bit 8
C2MCR11.MSGVAL_7         7   Message Valid - bit 7
C2MCR11.MSGVAL_6         6   Message Valid - bit 6
C2MCR11.TXIE_5           5   Transmit Interrupt Enable - bit 5
C2MCR11.TXIE_4           4   Transmit Interrupt Enable - bit 4
C2MCR11.RXIE_3           3   Receive Interrupt Enable - bit 3
C2MCR11.RXIE_2           2   Receive Interrupt Enable - bit 2
C2MCR11.INTPND_1         1   Interrupt Pending - bit 1
C2MCR11.INTPND_0         0   Interrupt Pending - bit 
C2UAR11          0xEEB2   CAN2 Upper Arbitration Reg. (msg. )
C2UAR11.ID20      15  Identifier 20
C2UAR11.ID19      14  Identifier 19
C2UAR11.ID18      13  Identifier 18
C2UAR11.ID17      12  Identifier 17
C2UAR11.ID16      11  Identifier 16
C2UAR11.ID15      10  Identifier 15
C2UAR11.ID14      9   Identifier 14
C2UAR11.ID13      8   Identifier 13
C2UAR11.ID28      7   Identifier 28
C2UAR11.ID27      6   Identifier 27
C2UAR11.ID26      5   Identifier 26
C2UAR11.ID25      4   Identifier 25
C2UAR11.ID24      3   Identifier 24
C2UAR11.ID23      2   Identifier 23
C2UAR11.ID22      1   Identifier 22
C2UAR11.ID21      0   Identifier 21
C2LAR11          0xEEB4   CAN2 Lower Arbitration Register (msg. )
C2LAR11.ID4       15  Identifier 4 
C2LAR11.ID3       14  Identifier 3 
C2LAR11.ID2       13  Identifier 2 
C2LAR11.ID1       12  Identifier 1 
C2LAR11.ID0       11  Identifier 0 
C2LAR11.ID12      7   Identifier 12
C2LAR11.ID11      6   Identifier 11
C2LAR11.ID10      5   Identifier 10
C2LAR11.ID9       4   Identifier 9 
C2LAR11.ID8       3   Identifier 8 
C2LAR11.ID7       2   Identifier 7 
C2LAR11.ID6       1   Identifier 6 
C2LAR11.ID5       0   Identifier 5 
C2MCFG11         0xEEB6   CAN2 Message Configuration Register (msg. )
C2MCFG11.DLC_7     7   Data Length Code - bit 7
C2MCFG11.DLC_6     6   Data Length Code - bit 6
C2MCFG11.DLC_5     5   Data Length Code - bit 5
C2MCFG11.DLC_4     4   Data Length Code - bit 4
C2MCFG11.DIR       3   Message Direction
C2MCFG11.XTD       2   Extended Identifier
C2MCR12          0xEEC1   CAN2 Message Ctrl. Reg. (msg. )
C2MCR12.RMTPND_15        15  Remote Pending - bit 15
C2MCR12.RMTPND_14        14  Remote Pending - bit 14
C2MCR12.TXRQ_13          13  Transmit Request - bit 13
C2MCR12.TXRQ_12          12  Transmit Request - bit 12
C2MCR12.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C2MCR12.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C2MCR12.NEWDAT_9         9   New Data - bit 9
C2MCR12.NEWDAT_8         8   New Data - bit 8
C2MCR12.MSGVAL_7         7   Message Valid - bit 7
C2MCR12.MSGVAL_6         6   Message Valid - bit 6
C2MCR12.TXIE_5           5   Transmit Interrupt Enable - bit 5
C2MCR12.TXIE_4           4   Transmit Interrupt Enable - bit 4
C2MCR12.RXIE_3           3   Receive Interrupt Enable - bit 3
C2MCR12.RXIE_2           2   Receive Interrupt Enable - bit 2
C2MCR12.INTPND_1         1   Interrupt Pending - bit 1
C2MCR12.INTPND_0         0   Interrupt Pending - bit 
C2UAR12          0xEEC2   CAN2 Upper Arbitration Reg. (msg. )
C2UAR12.ID20      15  Identifier 20
C2UAR12.ID19      14  Identifier 19
C2UAR12.ID18      13  Identifier 18
C2UAR12.ID17      12  Identifier 17
C2UAR12.ID16      11  Identifier 16
C2UAR12.ID15      10  Identifier 15
C2UAR12.ID14      9   Identifier 14
C2UAR12.ID13      8   Identifier 13
C2UAR12.ID28      7   Identifier 28
C2UAR12.ID27      6   Identifier 27
C2UAR12.ID26      5   Identifier 26
C2UAR12.ID25      4   Identifier 25
C2UAR12.ID24      3   Identifier 24
C2UAR12.ID23      2   Identifier 23
C2UAR12.ID22      1   Identifier 22
C2UAR12.ID21      0   Identifier 21
C2LAR12          0xEEC4   CAN2 Lower Arbitration Register (msg. )
C2LAR12.ID4       15  Identifier 4 
C2LAR12.ID3       14  Identifier 3 
C2LAR12.ID2       13  Identifier 2 
C2LAR12.ID1       12  Identifier 1 
C2LAR12.ID0       11  Identifier 0 
C2LAR12.ID12      7   Identifier 12
C2LAR12.ID11      6   Identifier 11
C2LAR12.ID10      5   Identifier 10
C2LAR12.ID9       4   Identifier 9 
C2LAR12.ID8       3   Identifier 8 
C2LAR12.ID7       2   Identifier 7 
C2LAR12.ID6       1   Identifier 6 
C2LAR12.ID5       0   Identifier 5 
C2MCFG12         0xEEC6   CAN2 Message Configuration Register (msg. )
C2MCFG12.DLC_7     7   Data Length Code - bit 7
C2MCFG12.DLC_6     6   Data Length Code - bit 6
C2MCFG12.DLC_5     5   Data Length Code - bit 5
C2MCFG12.DLC_4     4   Data Length Code - bit 4
C2MCFG12.DIR       3   Message Direction
C2MCFG12.XTD       2   Extended Identifier
C2MCR13          0xEED1   CAN2 Message Ctrl. Reg. (msg. )
C2MCR13.RMTPND_15        15  Remote Pending - bit 15
C2MCR13.RMTPND_14        14  Remote Pending - bit 14
C2MCR13.TXRQ_13          13  Transmit Request - bit 13
C2MCR13.TXRQ_12          12  Transmit Request - bit 12
C2MCR13.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C2MCR13.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C2MCR13.NEWDAT_9         9   New Data - bit 9
C2MCR13.NEWDAT_8         8   New Data - bit 8
C2MCR13.MSGVAL_7         7   Message Valid - bit 7
C2MCR13.MSGVAL_6         6   Message Valid - bit 6
C2MCR13.TXIE_5           5   Transmit Interrupt Enable - bit 5
C2MCR13.TXIE_4           4   Transmit Interrupt Enable - bit 4
C2MCR13.RXIE_3           3   Receive Interrupt Enable - bit 3
C2MCR13.RXIE_2           2   Receive Interrupt Enable - bit 2
C2MCR13.INTPND_1         1   Interrupt Pending - bit 1
C2MCR13.INTPND_0         0   Interrupt Pending - bit 
C2UAR13          0xEED2   CAN2 Upper Arbitration Reg. (msg. )
C2UAR14.ID20      15  Identifier 20
C2UAR14.ID19      14  Identifier 19
C2UAR14.ID18      13  Identifier 18
C2UAR14.ID17      12  Identifier 17
C2UAR14.ID16      11  Identifier 16
C2UAR14.ID15      10  Identifier 15
C2UAR14.ID14      9   Identifier 14
C2UAR14.ID13      8   Identifier 13
C2UAR14.ID28      7   Identifier 28
C2UAR14.ID27      6   Identifier 27
C2UAR14.ID26      5   Identifier 26
C2UAR14.ID25      4   Identifier 25
C2UAR14.ID24      3   Identifier 24
C2UAR14.ID23      2   Identifier 23
C2UAR14.ID22      1   Identifier 22
C2UAR14.ID21      0   Identifier 21
C2LAR13          0xEED4   CAN2 Lower Arbitration Register (msg. )
C2LAR13.ID4       15  Identifier 4 
C2LAR13.ID3       14  Identifier 3 
C2LAR13.ID2       13  Identifier 2 
C2LAR13.ID1       12  Identifier 1 
C2LAR13.ID0       11  Identifier 0 
C2LAR13.ID12      7   Identifier 12
C2LAR13.ID11      6   Identifier 11
C2LAR13.ID10      5   Identifier 10
C2LAR13.ID9       4   Identifier 9 
C2LAR13.ID8       3   Identifier 8 
C2LAR13.ID7       2   Identifier 7 
C2LAR13.ID6       1   Identifier 6 
C2LAR13.ID5       0   Identifier 5 
C2MCFG13         0xEED6   CAN2 Message Configuration Register (msg. )
C2MCFG13.DLC_7     7   Data Length Code - bit 7
C2MCFG13.DLC_6     6   Data Length Code - bit 6
C2MCFG13.DLC_5     5   Data Length Code - bit 5
C2MCFG13.DLC_4     4   Data Length Code - bit 4
C2MCFG13.DIR       3   Message Direction
C2MCFG13.XTD       2   Extended Identifier
C2MCR14          0xEEE1   CAN2 Message Ctrl. Reg. (msg. )
C2MCR14.RMTPND_15        15  Remote Pending - bit 15
C2MCR14.RMTPND_14        14  Remote Pending - bit 14
C2MCR14.TXRQ_13          13  Transmit Request - bit 13
C2MCR14.TXRQ_12          12  Transmit Request - bit 12
C2MCR14.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C2MCR14.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C2MCR14.NEWDAT_9         9   New Data - bit 9
C2MCR14.NEWDAT_8         8   New Data - bit 8
C2MCR14.MSGVAL_7         7   Message Valid - bit 7
C2MCR14.MSGVAL_6         6   Message Valid - bit 6
C2MCR14.TXIE_5           5   Transmit Interrupt Enable - bit 5
C2MCR14.TXIE_4           4   Transmit Interrupt Enable - bit 4
C2MCR14.RXIE_3           3   Receive Interrupt Enable - bit 3
C2MCR14.RXIE_2           2   Receive Interrupt Enable - bit 2
C2MCR14.INTPND_1         1   Interrupt Pending - bit 1
C2MCR14.INTPND_0         0   Interrupt Pending - bit 
C2UAR14          0xEEE2   CAN2 Upper Arbitration Reg. (msg. )
C2LAR14          0xEEE4   CAN2 Lower Arbitration Register (msg. )
C2LAR14.ID4       15  Identifier 4 
C2LAR14.ID3       14  Identifier 3 
C2LAR14.ID2       13  Identifier 2 
C2LAR14.ID1       12  Identifier 1 
C2LAR14.ID0       11  Identifier 0 
C2LAR14.ID12      7   Identifier 12
C2LAR14.ID11      6   Identifier 11
C2LAR14.ID10      5   Identifier 10
C2LAR14.ID9       4   Identifier 9 
C2LAR14.ID8       3   Identifier 8 
C2LAR14.ID7       2   Identifier 7 
C2LAR14.ID6       1   Identifier 6 
C2LAR14.ID5       0   Identifier 5 
C2MCFG14         0xEEE6   CAN2 Message Configuration Register (msg. )
C2MCFG14.DLC_7     7   Data Length Code - bit 7
C2MCFG14.DLC_6     6   Data Length Code - bit 6
C2MCFG14.DLC_5     5   Data Length Code - bit 5
C2MCFG14.DLC_4     4   Data Length Code - bit 4
C2MCFG14.DIR       3   Message Direction
C2MCFG14.XTD       2   Extended Identifier
C2MCR15          0xEEF1   CAN2 Message Ctrl. Reg. (msg. )
C2MCR15.RMTPND_15        15  Remote Pending - bit 15
C2MCR15.RMTPND_14        14  Remote Pending - bit 14
C2MCR15.TXRQ_13          13  Transmit Request - bit 13
C2MCR15.TXRQ_12          12  Transmit Request - bit 12
C2MCR15.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C2MCR15.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C2MCR15.NEWDAT_9         9   New Data - bit 9
C2MCR15.NEWDAT_8         8   New Data - bit 8
C2MCR15.MSGVAL_7         7   Message Valid - bit 7
C2MCR15.MSGVAL_6         6   Message Valid - bit 6
C2MCR15.TXIE_5           5   Transmit Interrupt Enable - bit 5
C2MCR15.TXIE_4           4   Transmit Interrupt Enable - bit 4
C2MCR15.RXIE_3           3   Receive Interrupt Enable - bit 3
C2MCR15.RXIE_2           2   Receive Interrupt Enable - bit 2
C2MCR15.INTPND_1         1   Interrupt Pending - bit 1
C2MCR15.INTPND_0         0   Interrupt Pending - bit 
C2UAR15          0xEEF2   CAN2 Upper Arbitration Reg. (msg. )
C2UAR15.ID20      15  Identifier 20
C2UAR15.ID19      14  Identifier 19
C2UAR15.ID18      13  Identifier 18
C2UAR15.ID17      12  Identifier 17
C2UAR15.ID16      11  Identifier 16
C2UAR15.ID15      10  Identifier 15
C2UAR15.ID14      9   Identifier 14
C2UAR15.ID13      8   Identifier 13
C2UAR15.ID28      7   Identifier 28
C2UAR15.ID27      6   Identifier 27
C2UAR15.ID26      5   Identifier 26
C2UAR15.ID25      4   Identifier 25
C2UAR15.ID24      3   Identifier 24
C2UAR15.ID23      2   Identifier 23
C2UAR15.ID22      1   Identifier 22
C2UAR15.ID21      0   Identifier 21
C2LAR15          0xEEF4   CAN2 Lower Arbitration Register (msg. )
C2LAR15.ID4       15  Identifier 4 
C2LAR15.ID3       14  Identifier 3 
C2LAR15.ID2       13  Identifier 2 
C2LAR15.ID1       12  Identifier 1 
C2LAR15.ID0       11  Identifier 0 
C2LAR15.ID12      7   Identifier 12
C2LAR15.ID11      6   Identifier 11
C2LAR15.ID10      5   Identifier 10
C2LAR15.ID9       4   Identifier 9 
C2LAR15.ID8       3   Identifier 8 
C2LAR15.ID7       2   Identifier 7 
C2LAR15.ID6       1   Identifier 6 
C2LAR15.ID5       0   Identifier 5 
C2MCFG15         0xEEF6   CAN2 Message Configuration Register (msg. )
C2MCFG15.DLC_7     7   Data Length Code - bit 7
C2MCFG15.DLC_6     6   Data Length Code - bit 6
C2MCFG15.DLC_5     5   Data Length Code - bit 5
C2MCFG15.DLC_4     4   Data Length Code - bit 4
C2MCFG15.DIR       3   Message Direction
C2MCFG15.XTD       2   Extended Identifier
C1CSR            0xEF00   CAN1 Control/Status Register                   
C1CSR.BOFF        15  Busoff Status
C1CSR.EWRN        14  Error Warning Status
C1CSR.RXOK        12  Received Message Successfully
C1CSR.TXOK        11  Transmitted Message Successfully
C1CSR.LEC_10      10  Last Error Code - bit 10
C1CSR.LEC_9       9   Last Error Code - bit 9 
C1CSR.LEC_8       8   Last Error Code - bit 8 
C1CSR.TM          7   Test Mode
C1CSR.CCE         6   Configuration Change Enable
C1CSR.CPS         4   Clock Prescaler Control Bit
C1CSR.EIE         3   Error Interrupt Enable
C1CSR.SIE         2   Status Change Interrupt Enable
C1CSR.IE          1   Interrupt Enable
C1CSR.INIT        0   Initialization
C1PCIR           0xEF02   CAN1 Port Control and Interrupt Register       
C1PCIR.IPC_10     10  Interface Port Control - bit 10
C1PCIR.IPC_9      9   Interface Port Control - bit 9 
C1PCIR.IPC_8      8   Interface Port Control - bit 8 
C1PCIR.INTID_7    7   Interrupt Identifier - bit 7
C1PCIR.INTID_6    6   Interrupt Identifier - bit 6
C1PCIR.INTID_5    5   Interrupt Identifier - bit 5
C1PCIR.INTID_4    4   Interrupt Identifier - bit 4
C1PCIR.INTID_3    3   Interrupt Identifier - bit 3
C1PCIR.INTID_2    2   Interrupt Identifier - bit 2
C1PCIR.INTID_1    1   Interrupt Identifier - bit 1
C1PCIR.INTID_0    0   Interrupt Identifier - bit 0
C1BTR            0xEF04   CAN1 Bit Timing Register                       
C1BTR.TSEG2_14    14  Time Segment after sample point - bit 14
C1BTR.TSEG2_13    13  Time Segment after sample point - bit 13
C1BTR.TSEG2_12    12  Time Segment after sample point - bit 12
C1BTR.TSEG1_11    11  Time Segment before sample point - bit 11
C1BTR.TSEG1_10    10  Time Segment before sample point - bit 10
C1BTR.TSEG1_9     9   Time Segment before sample point - bit 9 
C1BTR.TSEG1_8     8   Time Segment before sample point - bit 8 
C1BTR.SJW_7       7   (Re)Synchronization Jump Width - bit 7
C1BTR.SJW_6       6   (Re)Synchronization Jump Width - bit 6
C1BTR.BRP_5       5   Baud Rate Prescaler - bit 5
C1BTR.BRP_4       4   Baud Rate Prescaler - bit 4
C1BTR.BRP_3       3   Baud Rate Prescaler - bit 3
C1BTR.BRP_2       2   Baud Rate Prescaler - bit 2
C1BTR.BRP_1       1   Baud Rate Prescaler - bit 1
C1BTR.BRP_0       0   Baud Rate Prescaler - bit 0
C1GMS            0xEF06   CAN1 Global Mask Short                         
C1GMS.ID20        15  Identifier 20
C1GMS.ID19        14  Identifier 19
C1GMS.ID18        13  Identifier 18
C1GMS.ID28        7   Identifier 28
C1GMS.ID27        6   Identifier 27
C1GMS.ID26        5   Identifier 26
C1GMS.ID25        4   Identifier 25
C1GMS.ID24        3   Identifier 24
C1GMS.ID23        2   Identifier 23
C1GMS.ID22        1   Identifier 22
C1GMS.ID21        0   Identifier 21
C1UGML           0xEF08   CAN1 Upper Global Mask Long                    
C1UGML.ID20       15  Identifier 20
C1UGML.ID19       14  Identifier 19
C1UGML.ID18       13  Identifier 18
C1UGML.ID17       12  Identifier 17
C1UGML.ID16       11  Identifier 16
C1UGML.ID15       10  Identifier 15
C1UGML.ID14       9   Identifier 14
C1UGML.ID13       8   Identifier 13
C1UGML.ID28       7   Identifier 28
C1UGML.ID27       6   Identifier 27
C1UGML.ID26       5   Identifier 26
C1UGML.ID25       4   Identifier 25
C1UGML.ID24       3   Identifier 24
C1UGML.ID23       2   Identifier 23
C1UGML.ID22       1   Identifier 22
C1UGML.ID21       0   Identifier 21
C1LGML           0xEF0A   CAN1 Lower Global Mask Long                    
C1LGML.ID4        15  Identifier 4 
C1LGML.ID3        14  Identifier 3 
C1LGML.ID2        13  Identifier 2 
C1LGML.ID1        12  Identifier 1 
C1LGML.ID0        11  Identifier 0 
C1LGML.ID12       7   Identifier 12
C1LGML.ID11       6   Identifier 11
C1LGML.ID10       5   Identifier 10
C1LGML.ID9        4   Identifier 9 
C1LGML.ID8        3   Identifier 8 
C1LGML.ID7        2   Identifier 7 
C1LGML.ID6        1   Identifier 6 
C1LGML.ID5        0   Identifier 5 
C1UMLM           0xEF0C   CAN1 Upper Mask of Last Message                
C1UMLM.ID20       15  Identifier 20
C1UMLM.ID19       14  Identifier 19
C1UMLM.ID18       13  Identifier 18
C1UMLM.ID17       12  Identifier 17
C1UMLM.ID16       11  Identifier 16
C1UMLM.ID15       10  Identifier 15
C1UMLM.ID14       9   Identifier 14
C1UMLM.ID13       8   Identifier 13
C1UMLM.ID28       7   Identifier 28
C1UMLM.ID27       6   Identifier 27
C1UMLM.ID26       5   Identifier 26
C1UMLM.ID25       4   Identifier 25
C1UMLM.ID24       3   Identifier 24
C1UMLM.ID23       2   Identifier 23
C1UMLM.ID22       1   Identifier 22
C1UMLM.ID21       0   Identifier 21
C1LMLM           0xEF0E   CAN1 Lower Mask of Last Message                
C1LMLM.ID4        15  Identifier 4 
C1LMLM.ID3        14  Identifier 3 
C1LMLM.ID2        13  Identifier 2 
C1LMLM.ID1        12  Identifier 1 
C1LMLM.ID0        11  Identifier 0 
C1LMLM.ID12       7   Identifier 12
C1LMLM.ID11       6   Identifier 11
C1LMLM.ID10       5   Identifier 10
C1LMLM.ID9        4   Identifier 9 
C1LMLM.ID8        3   Identifier 8 
C1LMLM.ID7        2   Identifier 7 
C1LMLM.ID6        1   Identifier 6 
C1LMLM.ID5        0   Identifier 5 
C1MCR1           0xEF11   CAN1 Message Ctrl. Reg. (msg. )
C1MCR1.RMTPND_15        15  Remote Pending - bit 15
C1MCR1.RMTPND_14        14  Remote Pending - bit 14
C1MCR1.TXRQ_13          13  Transmit Request - bit 13
C1MCR1.TXRQ_12          12  Transmit Request - bit 12
C1MCR1.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C1MCR1.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C1MCR1.NEWDAT_9         9   New Data - bit 9
C1MCR1.NEWDAT_8         8   New Data - bit 8
C1MCR1.MSGVAL_7         7   Message Valid - bit 7
C1MCR1.MSGVAL_6         6   Message Valid - bit 6
C1MCR1.TXIE_5           5   Transmit Interrupt Enable - bit 5
C1MCR1.TXIE_4           4   Transmit Interrupt Enable - bit 4
C1MCR1.RXIE_3           3   Receive Interrupt Enable - bit 3
C1MCR1.RXIE_2           2   Receive Interrupt Enable - bit 2
C1MCR1.INTPND_1         1   Interrupt Pending - bit 1
C1MCR1.INTPND_0         0   Interrupt Pending - bit 0
C1UAR1           0xEF12   CAN1 Upper Arbitration Reg. (msg. )
C1UAR1.ID20       15  Identifier 20
C1UAR1.ID19       14  Identifier 19
C1UAR1.ID18       13  Identifier 18
C1UAR1.ID17       12  Identifier 17
C1UAR1.ID16       11  Identifier 16
C1UAR1.ID15       10  Identifier 15
C1UAR1.ID14       9   Identifier 14
C1UAR1.ID13       8   Identifier 13
C1UAR1.ID28       7   Identifier 28
C1UAR1.ID27       6   Identifier 27
C1UAR1.ID26       5   Identifier 26
C1UAR1.ID25       4   Identifier 25
C1UAR1.ID24       3   Identifier 24
C1UAR1.ID23       2   Identifier 23
C1UAR1.ID22       1   Identifier 22
C1UAR1.ID21       0   Identifier 21
C1LAR1           0xEF14   CAN1 Lower Arbitration Register (msg. )
C1LAR1.ID4        15  Identifier 4 
C1LAR1.ID3        14  Identifier 3 
C1LAR1.ID2        13  Identifier 2 
C1LAR1.ID1        12  Identifier 1 
C1LAR1.ID0        11  Identifier 0 
C1LAR1.ID12       7   Identifier 12
C1LAR1.ID11       6   Identifier 11
C1LAR1.ID10       5   Identifier 10
C1LAR1.ID9        4   Identifier 9 
C1LAR1.ID8        3   Identifier 8 
C1LAR1.ID7        2   Identifier 7 
C1LAR1.ID6        1   Identifier 6 
C1LAR1.ID5        0   Identifier 5 
C1MCFG1          0xEF16   CAN1 Message Configuration Register (msg. )
C1MCFG1.DLC_7     7   Data Length Code - bit 7
C1MCFG1.DLC_6     6   Data Length Code - bit 6
C1MCFG1.DLC_5     5   Data Length Code - bit 5
C1MCFG1.DLC_4     4   Data Length Code - bit 4
C1MCFG1.DIR       3   Message Direction
C1MCFG1.XTD       2   Extended Identifier
C1MCR2           0xEF21   CAN1 Message Ctrl. Reg. (msg. )
C1MCR2.RMTPND_15        15  Remote Pending - bit 15
C1MCR2.RMTPND_14        14  Remote Pending - bit 14
C1MCR2.TXRQ_13          13  Transmit Request - bit 13
C1MCR2.TXRQ_12          12  Transmit Request - bit 12
C1MCR2.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C1MCR2.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C1MCR2.NEWDAT_9         9   New Data - bit 9
C1MCR2.NEWDAT_8         8   New Data - bit 8
C1MCR2.MSGVAL_7         7   Message Valid - bit 7
C1MCR2.MSGVAL_6         6   Message Valid - bit 6
C1MCR2.TXIE_5           5   Transmit Interrupt Enable - bit 5
C1MCR2.TXIE_4           4   Transmit Interrupt Enable - bit 4
C1MCR2.RXIE_3           3   Receive Interrupt Enable - bit 3
C1MCR2.RXIE_2           2   Receive Interrupt Enable - bit 2
C1MCR2.INTPND_1         1   Interrupt Pending - bit 1
C1MCR2.INTPND_0         0   Interrupt Pending - bit 0
C1UAR2           0xEF22   CAN1 Upper Arbitration Reg. (msg. )
C1UAR2.ID20       15  Identifier 20
C1UAR2.ID19       14  Identifier 19
C1UAR2.ID18       13  Identifier 18
C1UAR2.ID17       12  Identifier 17
C1UAR2.ID16       11  Identifier 16
C1UAR2.ID15       10  Identifier 15
C1UAR2.ID14       9   Identifier 14
C1UAR2.ID13       8   Identifier 13
C1UAR2.ID28       7   Identifier 28
C1UAR2.ID27       6   Identifier 27
C1UAR2.ID26       5   Identifier 26
C1UAR2.ID25       4   Identifier 25
C1UAR2.ID24       3   Identifier 24
C1UAR2.ID23       2   Identifier 23
C1UAR2.ID22       1   Identifier 22
C1UAR2.ID21       0   Identifier 21
C1LAR2           0xEF24   CAN1 Lower Arbitration Register (msg. )
C1LAR2.ID4        15  Identifier 4 
C1LAR2.ID3        14  Identifier 3 
C1LAR2.ID2        13  Identifier 2 
C1LAR2.ID1        12  Identifier 1 
C1LAR2.ID0        11  Identifier 0 
C1LAR2.ID12       7   Identifier 12
C1LAR2.ID11       6   Identifier 11
C1LAR2.ID10       5   Identifier 10
C1LAR2.ID9        4   Identifier 9 
C1LAR2.ID8        3   Identifier 8 
C1LAR2.ID7        2   Identifier 7 
C1LAR2.ID6        1   Identifier 6 
C1LAR2.ID5        0   Identifier 5 
C1MCFG2          0xEF26   CAN1 Message Configuration Register (msg. )
C1MCFG2.DLC_7     7   Data Length Code - bit 7
C1MCFG2.DLC_6     6   Data Length Code - bit 6
C1MCFG2.DLC_5     5   Data Length Code - bit 5
C1MCFG2.DLC_4     4   Data Length Code - bit 4
C1MCFG2.DIR       3   Message Direction
C1MCFG2.XTD       2   Extended Identifier
C1MCR3           0xEF31   CAN1 Message Ctrl. Reg. (msg. )
C1MCR3.RMTPND_15        15  Remote Pending - bit 15
C1MCR3.RMTPND_14        14  Remote Pending - bit 14
C1MCR3.TXRQ_13          13  Transmit Request - bit 13
C1MCR3.TXRQ_12          12  Transmit Request - bit 12
C1MCR3.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C1MCR3.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C1MCR3.NEWDAT_9         9   New Data - bit 9
C1MCR3.NEWDAT_8         8   New Data - bit 8
C1MCR3.MSGVAL_7         7   Message Valid - bit 7
C1MCR3.MSGVAL_6         6   Message Valid - bit 6
C1MCR3.TXIE_5           5   Transmit Interrupt Enable - bit 5
C1MCR3.TXIE_4           4   Transmit Interrupt Enable - bit 4
C1MCR3.RXIE_3           3   Receive Interrupt Enable - bit 3
C1MCR3.RXIE_2           2   Receive Interrupt Enable - bit 2
C1MCR3.INTPND_1         1   Interrupt Pending - bit 1
C1MCR3.INTPND_0         0   Interrupt Pending - bit 0
C1UAR3           0xEF32   CAN1 Upper Arbitration Reg. (msg. )
C1UAR3.ID20       15  Identifier 20
C1UAR3.ID19       14  Identifier 19
C1UAR3.ID18       13  Identifier 18
C1UAR3.ID17       12  Identifier 17
C1UAR3.ID16       11  Identifier 16
C1UAR3.ID15       10  Identifier 15
C1UAR3.ID14       9   Identifier 14
C1UAR3.ID13       8   Identifier 13
C1UAR3.ID28       7   Identifier 28
C1UAR3.ID27       6   Identifier 27
C1UAR3.ID26       5   Identifier 26
C1UAR3.ID25       4   Identifier 25
C1UAR3.ID24       3   Identifier 24
C1UAR3.ID23       2   Identifier 23
C1UAR3.ID22       1   Identifier 22
C1UAR3.ID21       0   Identifier 21
C1LAR3           0xEF34   CAN1 Lower Arbitration Register (msg. )
C1LAR1.ID4        15  Identifier 4 
C1LAR1.ID3        14  Identifier 3 
C1LAR1.ID2        13  Identifier 2 
C1LAR1.ID1        12  Identifier 1 
C1LAR1.ID0        11  Identifier 0 
C1LAR1.ID12       7   Identifier 12
C1LAR1.ID11       6   Identifier 11
C1LAR1.ID10       5   Identifier 10
C1LAR1.ID9        4   Identifier 9 
C1LAR1.ID8        3   Identifier 8 
C1LAR1.ID7        2   Identifier 7 
C1LAR1.ID6        1   Identifier 6 
C1LAR1.ID5        0   Identifier 5 
C1MCFG3          0xEF36   CAN1 Message Configuration Register (msg. )
C1MCFG3.DLC_7     7   Data Length Code - bit 7
C1MCFG3.DLC_6     6   Data Length Code - bit 6
C1MCFG3.DLC_5     5   Data Length Code - bit 5
C1MCFG3.DLC_4     4   Data Length Code - bit 4
C1MCFG3.DIR       3   Message Direction
C1MCFG3.XTD       2   Extended Identifier
C1MCR4           0xEF41   CAN1 Message Ctrl. Reg. (msg. )
C1MCR4.RMTPND_15        15  Remote Pending - bit 15
C1MCR4.RMTPND_14        14  Remote Pending - bit 14
C1MCR4.TXRQ_13          13  Transmit Request - bit 13
C1MCR4.TXRQ_12          12  Transmit Request - bit 12
C1MCR4.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C1MCR4.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C1MCR4.NEWDAT_9         9   New Data - bit 9
C1MCR4.NEWDAT_8         8   New Data - bit 8
C1MCR4.MSGVAL_7         7   Message Valid - bit 7
C1MCR4.MSGVAL_6         6   Message Valid - bit 6
C1MCR4.TXIE_5           5   Transmit Interrupt Enable - bit 5
C1MCR4.TXIE_4           4   Transmit Interrupt Enable - bit 4
C1MCR4.RXIE_3           3   Receive Interrupt Enable - bit 3
C1MCR4.RXIE_2           2   Receive Interrupt Enable - bit 2
C1MCR4.INTPND_1         1   Interrupt Pending - bit 1
C1MCR4.INTPND_0         0   Interrupt Pending - bit 0
C1UAR4           0xEF42   CAN1 Upper Arbitration Reg. (msg. )
C1UAR4.ID20       15  Identifier 20
C1UAR4.ID19       14  Identifier 19
C1UAR4.ID18       13  Identifier 18
C1UAR4.ID17       12  Identifier 17
C1UAR4.ID16       11  Identifier 16
C1UAR4.ID15       10  Identifier 15
C1UAR4.ID14       9   Identifier 14
C1UAR4.ID13       8   Identifier 13
C1UAR4.ID28       7   Identifier 28
C1UAR4.ID27       6   Identifier 27
C1UAR4.ID26       5   Identifier 26
C1UAR4.ID25       4   Identifier 25
C1UAR4.ID24       3   Identifier 24
C1UAR4.ID23       2   Identifier 23
C1UAR4.ID22       1   Identifier 22
C1UAR4.ID21       0   Identifier 21
C1LAR4           0xEF44   CAN1 Lower Arbitration Register (msg. )
C1LAR4.ID4        15  Identifier 4 
C1LAR4.ID3        14  Identifier 3 
C1LAR4.ID2        13  Identifier 2 
C1LAR4.ID1        12  Identifier 1 
C1LAR4.ID0        11  Identifier 0 
C1LAR4.ID12       7   Identifier 12
C1LAR4.ID11       6   Identifier 11
C1LAR4.ID10       5   Identifier 10
C1LAR4.ID9        4   Identifier 9 
C1LAR4.ID8        3   Identifier 8 
C1LAR4.ID7        2   Identifier 7 
C1LAR4.ID6        1   Identifier 6 
C1LAR4.ID5        0   Identifier 5 
C1MCFG4          0xEF46   CAN1 Message Configuration Register (msg. )
C1MCFG4.DLC_7     7   Data Length Code - bit 7
C1MCFG4.DLC_6     6   Data Length Code - bit 6
C1MCFG4.DLC_5     5   Data Length Code - bit 5
C1MCFG4.DLC_4     4   Data Length Code - bit 4
C1MCFG4.DIR       3   Message Direction
C1MCFG4.XTD       2   Extended Identifier
C1MCR5           0xEF51   CAN1 Message Ctrl. Reg. (msg. )
C1MCR5.RMTPND_15        15  Remote Pending - bit 15
C1MCR5.RMTPND_14        14  Remote Pending - bit 14
C1MCR5.TXRQ_13          13  Transmit Request - bit 13
C1MCR5.TXRQ_12          12  Transmit Request - bit 12
C1MCR5.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C1MCR5.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C1MCR5.NEWDAT_9         9   New Data - bit 9
C1MCR5.NEWDAT_8         8   New Data - bit 8
C1MCR5.MSGVAL_7         7   Message Valid - bit 7
C1MCR5.MSGVAL_6         6   Message Valid - bit 6
C1MCR5.TXIE_5           5   Transmit Interrupt Enable - bit 5
C1MCR5.TXIE_4           4   Transmit Interrupt Enable - bit 4
C1MCR5.RXIE_3           3   Receive Interrupt Enable - bit 3
C1MCR5.RXIE_2           2   Receive Interrupt Enable - bit 2
C1MCR5.INTPND_1         1   Interrupt Pending - bit 1
C1MCR5.INTPND_0         0   Interrupt Pending - bit 0
C1UAR5           0xEF52   CAN1 Upper Arbitration Reg. (msg. )
C1UAR5.ID20       15  Identifier 20
C1UAR5.ID19       14  Identifier 19
C1UAR5.ID18       13  Identifier 18
C1UAR5.ID17       12  Identifier 17
C1UAR5.ID16       11  Identifier 16
C1UAR5.ID15       10  Identifier 15
C1UAR5.ID14       9   Identifier 14
C1UAR5.ID13       8   Identifier 13
C1UAR5.ID28       7   Identifier 28
C1UAR5.ID27       6   Identifier 27
C1UAR5.ID26       5   Identifier 26
C1UAR5.ID25       4   Identifier 25
C1UAR5.ID24       3   Identifier 24
C1UAR5.ID23       2   Identifier 23
C1UAR5.ID22       1   Identifier 22
C1UAR5.ID21       0   Identifier 21
C1LAR5           0xEF54   CAN1 Lower Arbitration Register (msg. )
C1LAR5.ID4        15  Identifier 4 
C1LAR5.ID3        14  Identifier 3 
C1LAR5.ID2        13  Identifier 2 
C1LAR5.ID1        12  Identifier 1 
C1LAR5.ID0        11  Identifier 0 
C1LAR5.ID12       7   Identifier 12
C1LAR5.ID11       6   Identifier 11
C1LAR5.ID10       5   Identifier 10
C1LAR5.ID9        4   Identifier 9 
C1LAR5.ID8        3   Identifier 8 
C1LAR5.ID7        2   Identifier 7 
C1LAR5.ID6        1   Identifier 6 
C1LAR5.ID5        0   Identifier 5 
C1MCFG5          0xEF56   CAN1 Message Configuration Register (msg. )
C1MCFG5.DLC_7     7   Data Length Code - bit 7
C1MCFG5.DLC_6     6   Data Length Code - bit 6
C1MCFG5.DLC_5     5   Data Length Code - bit 5
C1MCFG5.DLC_4     4   Data Length Code - bit 4
C1MCFG5.DIR       3   Message Direction
C1MCFG5.XTD       2   Extended Identifier
C1MCR6           0xEF61   CAN1 Message Ctrl. Reg. (msg. )
C1MCR6.RMTPND_15        15  Remote Pending - bit 15
C1MCR6.RMTPND_14        14  Remote Pending - bit 14
C1MCR6.TXRQ_13          13  Transmit Request - bit 13
C1MCR6.TXRQ_12          12  Transmit Request - bit 12
C1MCR6.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C1MCR6.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C1MCR6.NEWDAT_9         9   New Data - bit 9
C1MCR6.NEWDAT_8         8   New Data - bit 8
C1MCR6.MSGVAL_7         7   Message Valid - bit 7
C1MCR6.MSGVAL_6         6   Message Valid - bit 6
C1MCR6.TXIE_5           5   Transmit Interrupt Enable - bit 5
C1MCR6.TXIE_4           4   Transmit Interrupt Enable - bit 4
C1MCR6.RXIE_3           3   Receive Interrupt Enable - bit 3
C1MCR6.RXIE_2           2   Receive Interrupt Enable - bit 2
C1MCR6.INTPND_1         1   Interrupt Pending - bit 1
C1MCR6.INTPND_0         0   Interrupt Pending - bit 0
C1UAR6           0xEF62   CAN1 Upper Arbitration Reg. (msg. )
C1UAR6.ID20       15  Identifier 20
C1UAR6.ID19       14  Identifier 19
C1UAR6.ID18       13  Identifier 18
C1UAR6.ID17       12  Identifier 17
C1UAR6.ID16       11  Identifier 16
C1UAR6.ID15       10  Identifier 15
C1UAR6.ID14       9   Identifier 14
C1UAR6.ID13       8   Identifier 13
C1UAR6.ID28       7   Identifier 28
C1UAR6.ID27       6   Identifier 27
C1UAR6.ID26       5   Identifier 26
C1UAR6.ID25       4   Identifier 25
C1UAR6.ID24       3   Identifier 24
C1UAR6.ID23       2   Identifier 23
C1UAR6.ID22       1   Identifier 22
C1UAR6.ID21       0   Identifier 21
C1LAR6           0xEF64   CAN1 Lower Arbitration Register (msg. )
C1LAR6.ID4        15  Identifier 4 
C1LAR6.ID3        14  Identifier 3 
C1LAR6.ID2        13  Identifier 2 
C1LAR6.ID1        12  Identifier 1 
C1LAR6.ID0        11  Identifier 0 
C1LAR6.ID12       7   Identifier 12
C1LAR6.ID11       6   Identifier 11
C1LAR6.ID10       5   Identifier 10
C1LAR6.ID9        4   Identifier 9 
C1LAR6.ID8        3   Identifier 8 
C1LAR6.ID7        2   Identifier 7 
C1LAR6.ID6        1   Identifier 6 
C1LAR6.ID5        0   Identifier 5 
C1MCFG6          0xEF66   CAN1 Message Configuration Register (msg. )
C1MCFG6.DLC_7     7   Data Length Code - bit 7
C1MCFG6.DLC_6     6   Data Length Code - bit 6
C1MCFG6.DLC_5     5   Data Length Code - bit 5
C1MCFG6.DLC_4     4   Data Length Code - bit 4
C1MCFG6.DIR       3   Message Direction
C1MCFG6.XTD       2   Extended Identifier
C1MCR7           0xEF71   CAN1 Message Ctrl. Reg. (msg. )
C1MCR7.RMTPND_15        15  Remote Pending - bit 15
C1MCR7.RMTPND_14        14  Remote Pending - bit 14
C1MCR7.TXRQ_13          13  Transmit Request - bit 13
C1MCR7.TXRQ_12          12  Transmit Request - bit 12
C1MCR7.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C1MCR7.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C1MCR7.NEWDAT_9         9   New Data - bit 9
C1MCR7.NEWDAT_8         8   New Data - bit 8
C1MCR7.MSGVAL_7         7   Message Valid - bit 7
C1MCR7.MSGVAL_6         6   Message Valid - bit 6
C1MCR7.TXIE_5           5   Transmit Interrupt Enable - bit 5
C1MCR7.TXIE_4           4   Transmit Interrupt Enable - bit 4
C1MCR7.RXIE_3           3   Receive Interrupt Enable - bit 3
C1MCR7.RXIE_2           2   Receive Interrupt Enable - bit 2
C1MCR7.INTPND_1         1   Interrupt Pending - bit 1
C1MCR7.INTPND_0         0   Interrupt Pending - bit 0
C1UAR7           0xEF72   CAN1 Upper Arbitration Reg. (msg. )
C1UAR7.ID20       15  Identifier 20
C1UAR7.ID19       14  Identifier 19
C1UAR7.ID18       13  Identifier 18
C1UAR7.ID17       12  Identifier 17
C1UAR7.ID16       11  Identifier 16
C1UAR7.ID15       10  Identifier 15
C1UAR7.ID14       9   Identifier 14
C1UAR7.ID13       8   Identifier 13
C1UAR7.ID28       7   Identifier 28
C1UAR7.ID27       6   Identifier 27
C1UAR7.ID26       5   Identifier 26
C1UAR7.ID25       4   Identifier 25
C1UAR7.ID24       3   Identifier 24
C1UAR7.ID23       2   Identifier 23
C1UAR7.ID22       1   Identifier 22
C1UAR7.ID21       0   Identifier 21
C1LAR7           0xEF74   CAN1 Lower Arbitration Register (msg. )
C1LAR7.ID4        15  Identifier 4 
C1LAR7.ID3        14  Identifier 3 
C1LAR7.ID2        13  Identifier 2 
C1LAR7.ID1        12  Identifier 1 
C1LAR7.ID0        11  Identifier 0 
C1LAR7.ID12       7   Identifier 12
C1LAR7.ID11       6   Identifier 11
C1LAR7.ID10       5   Identifier 10
C1LAR7.ID9        4   Identifier 9 
C1LAR7.ID8        3   Identifier 8 
C1LAR7.ID7        2   Identifier 7 
C1LAR7.ID6        1   Identifier 6 
C1LAR7.ID5        0   Identifier 5 
C1MCFG7          0xEF76   CAN1 Message Configuration Register (msg. )
C1MCFG7.DLC_7     7   Data Length Code - bit 7
C1MCFG7.DLC_6     6   Data Length Code - bit 6
C1MCFG7.DLC_5     5   Data Length Code - bit 5
C1MCFG7.DLC_4     4   Data Length Code - bit 4
C1MCFG7.DIR       3   Message Direction
C1MCFG7.XTD       2   Extended Identifier
C1MCR8           0xEF81   CAN1 Message Ctrl. Reg. (msg. )
C1MCR8.RMTPND_15        15  Remote Pending - bit 15
C1MCR8.RMTPND_14        14  Remote Pending - bit 14
C1MCR8.TXRQ_13          13  Transmit Request - bit 13
C1MCR8.TXRQ_12          12  Transmit Request - bit 12
C1MCR8.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C1MCR8.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C1MCR8.NEWDAT_9         9   New Data - bit 9
C1MCR8.NEWDAT_8         8   New Data - bit 8
C1MCR8.MSGVAL_7         7   Message Valid - bit 7
C1MCR8.MSGVAL_6         6   Message Valid - bit 6
C1MCR8.TXIE_5           5   Transmit Interrupt Enable - bit 5
C1MCR8.TXIE_4           4   Transmit Interrupt Enable - bit 4
C1MCR8.RXIE_3           3   Receive Interrupt Enable - bit 3
C1MCR8.RXIE_2           2   Receive Interrupt Enable - bit 2
C1MCR8.INTPND_1         1   Interrupt Pending - bit 1
C1MCR8.INTPND_0         0   Interrupt Pending - bit 0
C1UAR8           0xEF82   CAN1 Upper Arbitration Reg. (msg. )
C1UAR8.ID20       15  Identifier 20
C1UAR8.ID19       14  Identifier 19
C1UAR8.ID18       13  Identifier 18
C1UAR8.ID17       12  Identifier 17
C1UAR8.ID16       11  Identifier 16
C1UAR8.ID15       10  Identifier 15
C1UAR8.ID14       9   Identifier 14
C1UAR8.ID13       8   Identifier 13
C1UAR8.ID28       7   Identifier 28
C1UAR8.ID27       6   Identifier 27
C1UAR8.ID26       5   Identifier 26
C1UAR8.ID25       4   Identifier 25
C1UAR8.ID24       3   Identifier 24
C1UAR8.ID23       2   Identifier 23
C1UAR8.ID22       1   Identifier 22
C1UAR8.ID21       0   Identifier 21
C1LAR8           0xEF84   CAN1 Lower Arbitration Register (msg. )
C1LAR8.ID4        15  Identifier 4 
C1LAR8.ID3        14  Identifier 3 
C1LAR8.ID2        13  Identifier 2 
C1LAR8.ID1        12  Identifier 1 
C1LAR8.ID0        11  Identifier 0 
C1LAR8.ID12       7   Identifier 12
C1LAR8.ID11       6   Identifier 11
C1LAR8.ID10       5   Identifier 10
C1LAR8.ID9        4   Identifier 9 
C1LAR8.ID8        3   Identifier 8 
C1LAR8.ID7        2   Identifier 7 
C1LAR8.ID6        1   Identifier 6 
C1LAR8.ID5        0   Identifier 5 
C1MCFG8          0xEF86   CAN1 Message Configuration Register (msg. )
C1MCFG8.DLC_7     7   Data Length Code - bit 7
C1MCFG8.DLC_6     6   Data Length Code - bit 6
C1MCFG8.DLC_5     5   Data Length Code - bit 5
C1MCFG8.DLC_4     4   Data Length Code - bit 4
C1MCFG8.DIR       3   Message Direction
C1MCFG8.XTD       2   Extended Identifier
C1MCR9           0xEF91   CAN1 Message Ctrl. Reg. (msg. )
C1MCR9.RMTPND_15        15  Remote Pending - bit 15
C1MCR9.RMTPND_14        14  Remote Pending - bit 14
C1MCR9.TXRQ_13          13  Transmit Request - bit 13
C1MCR9.TXRQ_12          12  Transmit Request - bit 12
C1MCR9.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C1MCR9.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C1MCR9.NEWDAT_9         9   New Data - bit 9
C1MCR9.NEWDAT_8         8   New Data - bit 8
C1MCR9.MSGVAL_7         7   Message Valid - bit 7
C1MCR9.MSGVAL_6         6   Message Valid - bit 6
C1MCR9.TXIE_5           5   Transmit Interrupt Enable - bit 5
C1MCR9.TXIE_4           4   Transmit Interrupt Enable - bit 4
C1MCR9.RXIE_3           3   Receive Interrupt Enable - bit 3
C1MCR9.RXIE_2           2   Receive Interrupt Enable - bit 2
C1MCR9.INTPND_1         1   Interrupt Pending - bit 1
C1MCR9.INTPND_0         0   Interrupt Pending - bit 0
C1UAR9           0xEF92   CAN1 Upper Arbitration Reg. (msg. )
C1UAR9.ID20       15  Identifier 20
C1UAR9.ID19       14  Identifier 19
C1UAR9.ID18       13  Identifier 18
C1UAR9.ID17       12  Identifier 17
C1UAR9.ID16       11  Identifier 16
C1UAR9.ID15       10  Identifier 15
C1UAR9.ID14       9   Identifier 14
C1UAR9.ID13       8   Identifier 13
C1UAR9.ID28       7   Identifier 28
C1UAR9.ID27       6   Identifier 27
C1UAR9.ID26       5   Identifier 26
C1UAR9.ID25       4   Identifier 25
C1UAR9.ID24       3   Identifier 24
C1UAR9.ID23       2   Identifier 23
C1UAR9.ID22       1   Identifier 22
C1UAR9.ID21       0   Identifier 21
C1LAR9           0xEF94   CAN1 Lower Arbitration Register (msg. )
C1LAR9.ID4        15  Identifier 4 
C1LAR9.ID3        14  Identifier 3 
C1LAR9.ID2        13  Identifier 2 
C1LAR9.ID1        12  Identifier 1 
C1LAR9.ID0        11  Identifier 0 
C1LAR9.ID12       7   Identifier 12
C1LAR9.ID11       6   Identifier 11
C1LAR9.ID10       5   Identifier 10
C1LAR9.ID9        4   Identifier 9 
C1LAR9.ID8        3   Identifier 8 
C1LAR9.ID7        2   Identifier 7 
C1LAR9.ID6        1   Identifier 6 
C1LAR9.ID5        0   Identifier 5 
C1MCFG9          0xEF96   CAN1 Message Configuration Register (msg. )
C1MCFG9.DLC_7     7   Data Length Code - bit 7
C1MCFG9.DLC_6     6   Data Length Code - bit 6
C1MCFG9.DLC_5     5   Data Length Code - bit 5
C1MCFG9.DLC_4     4   Data Length Code - bit 4
C1MCFG9.DIR       3   Message Direction
C1MCFG9.XTD       2   Extended Identifier
C1MCR10          0xEFA1   CAN1 Message Ctrl. Reg. (msg. )
C1MCR10.RMTPND_15        15  Remote Pending - bit 15
C1MCR10.RMTPND_14        14  Remote Pending - bit 14
C1MCR10.TXRQ_13          13  Transmit Request - bit 13
C1MCR10.TXRQ_12          12  Transmit Request - bit 12
C1MCR10.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C1MCR10.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C1MCR10.NEWDAT_9         9   New Data - bit 9
C1MCR10.NEWDAT_8         8   New Data - bit 8
C1MCR10.MSGVAL_7         7   Message Valid - bit 7
C1MCR10.MSGVAL_6         6   Message Valid - bit 6
C1MCR10.TXIE_5           5   Transmit Interrupt Enable - bit 5
C1MCR10.TXIE_4           4   Transmit Interrupt Enable - bit 4
C1MCR10.RXIE_3           3   Receive Interrupt Enable - bit 3
C1MCR10.RXIE_2           2   Receive Interrupt Enable - bit 2
C1MCR10.INTPND_1         1   Interrupt Pending - bit 1
C1MCR10.INTPND_0         0   Interrupt Pending - bit 0
C1UAR10          0xEFA2   CAN1 Upper Arbitration Reg. (msg. )
C1UAR10.ID20      15  Identifier 20
C1UAR10.ID19      14  Identifier 19
C1UAR10.ID18      13  Identifier 18
C1UAR10.ID17      12  Identifier 17
C1UAR10.ID16      11  Identifier 16
C1UAR10.ID15      10  Identifier 15
C1UAR10.ID14      9   Identifier 14
C1UAR10.ID13      8   Identifier 13
C1UAR10.ID28      7   Identifier 28
C1UAR10.ID27      6   Identifier 27
C1UAR10.ID26      5   Identifier 26
C1UAR10.ID25      4   Identifier 25
C1UAR10.ID24      3   Identifier 24
C1UAR10.ID23      2   Identifier 23
C1UAR10.ID22      1   Identifier 22
C1UAR10.ID21      0   Identifier 21
C1LAR10          0xEFA4   CAN1 Lower Arbitration Register (msg. )
C1LAR10.ID4       15  Identifier 4
C1LAR10.ID3       14  Identifier 3
C1LAR10.ID2       13  Identifier 2
C1LAR10.ID1       12  Identifier 1
C1LAR10.ID0       11  Identifier 0
C1LAR10.ID12      7   Identifier 12
C1LAR10.ID11      6   Identifier 11
C1LAR10.ID10      5   Identifier 10
C1LAR10.ID9       4   Identifier 9
C1LAR10.ID8       3   Identifier 8
C1LAR10.ID7       2   Identifier 7
C1LAR10.ID6       1   Identifier 6
C1LAR10.ID5       0   Identifier 5
C1MCFG10         0xEFA6   CAN1 Message Configuration Register (msg. )
C1MCFG10.DLC_7    7   Data Length Code - bit 7
C1MCFG10.DLC_6    6   Data Length Code - bit 6
C1MCFG10.DLC_5    5   Data Length Code - bit 5
C1MCFG10.DLC_4    4   Data Length Code - bit 4
C1MCFG10.DIR      3   Message Direction
C1MCFG10.XTD      2   Extended Identifier
C1MCR11          0xEFB1   CAN1 Message Ctrl. Reg. (msg. )
C1MCR11.RMTPND_15        15  Remote Pending - bit 15
C1MCR11.RMTPND_14        14  Remote Pending - bit 14
C1MCR11.TXRQ_13          13  Transmit Request - bit 13
C1MCR11.TXRQ_12          12  Transmit Request - bit 12
C1MCR11.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C1MCR11.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C1MCR11.NEWDAT_9         9   New Data - bit 9
C1MCR11.NEWDAT_8         8   New Data - bit 8
C1MCR11.MSGVAL_7         7   Message Valid - bit 7
C1MCR11.MSGVAL_6         6   Message Valid - bit 6
C1MCR11.TXIE_5           5   Transmit Interrupt Enable - bit 5
C1MCR11.TXIE_4           4   Transmit Interrupt Enable - bit 4
C1MCR11.RXIE_3           3   Receive Interrupt Enable - bit 3
C1MCR11.RXIE_2           2   Receive Interrupt Enable - bit 2
C1MCR11.INTPND_1         1   Interrupt Pending - bit 1
C1MCR11.INTPND_0         0   Interrupt Pending - bit 0
C1UAR11          0xEFB2   CAN1 Upper Arbitration Reg. (msg. )
C1UAR11.ID20      15  Identifier 20
C1UAR11.ID19      14  Identifier 19
C1UAR11.ID18      13  Identifier 18
C1UAR11.ID17      12  Identifier 17
C1UAR11.ID16      11  Identifier 16
C1UAR11.ID15      10  Identifier 15
C1UAR11.ID14      9   Identifier 14
C1UAR11.ID13      8   Identifier 13
C1UAR11.ID28      7   Identifier 28
C1UAR11.ID27      6   Identifier 27
C1UAR11.ID26      5   Identifier 26
C1UAR11.ID25      4   Identifier 25
C1UAR11.ID24      3   Identifier 24
C1UAR11.ID23      2   Identifier 23
C1UAR11.ID22      1   Identifier 22
C1UAR11.ID21      0   Identifier 21
C1LAR11          0xEFB4   CAN1 Lower Arbitration Register (msg. )
C1LAR11.ID4       15  Identifier 4
C1LAR11.ID3       14  Identifier 3
C1LAR11.ID2       13  Identifier 2
C1LAR11.ID1       12  Identifier 1
C1LAR11.ID0       11  Identifier 0
C1LAR11.ID12      7   Identifier 12
C1LAR11.ID11      6   Identifier 11
C1LAR11.ID10      5   Identifier 10
C1LAR11.ID9       4   Identifier 9
C1LAR11.ID8       3   Identifier 8
C1LAR11.ID7       2   Identifier 7
C1LAR11.ID6       1   Identifier 6
C1LAR11.ID5       0   Identifier 5
C1MCFG11         0xEFB6   CAN1 Message Configuration Register (msg. )
C1MCFG11.DLC_7    7   Data Length Code - bit 7
C1MCFG11.DLC_6    6   Data Length Code - bit 6
C1MCFG11.DLC_5    5   Data Length Code - bit 5
C1MCFG11.DLC_4    4   Data Length Code - bit 4
C1MCFG11.DIR      3   Message Direction
C1MCFG11.XTD      2   Extended Identifier
C1MCR12          0xEFC1   CAN1 Message Ctrl. Reg. (msg. )
C1MCR12.RMTPND_15        15  Remote Pending - bit 15
C1MCR12.RMTPND_14        14  Remote Pending - bit 14
C1MCR12.TXRQ_13          13  Transmit Request - bit 13
C1MCR12.TXRQ_12          12  Transmit Request - bit 12
C1MCR12.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C1MCR12.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C1MCR12.NEWDAT_9         9   New Data - bit 9
C1MCR12.NEWDAT_8         8   New Data - bit 8
C1MCR12.MSGVAL_7         7   Message Valid - bit 7
C1MCR12.MSGVAL_6         6   Message Valid - bit 6
C1MCR12.TXIE_5           5   Transmit Interrupt Enable - bit 5
C1MCR12.TXIE_4           4   Transmit Interrupt Enable - bit 4
C1MCR12.RXIE_3           3   Receive Interrupt Enable - bit 3
C1MCR12.RXIE_2           2   Receive Interrupt Enable - bit 2
C1MCR12.INTPND_1         1   Interrupt Pending - bit 1
C1MCR12.INTPND_0         0   Interrupt Pending - bit 0
C1UAR12          0xEFC1   CAN1 Upper Arbitration Reg. (msg. )
C1UAR12.ID20      15  Identifier 20
C1UAR12.ID19      14  Identifier 19
C1UAR12.ID18      13  Identifier 18
C1UAR12.ID17      12  Identifier 17
C1UAR12.ID16      11  Identifier 16
C1UAR12.ID15      10  Identifier 15
C1UAR12.ID14      9   Identifier 14
C1UAR12.ID13      8   Identifier 13
C1UAR12.ID28      7   Identifier 28
C1UAR12.ID27      6   Identifier 27
C1UAR12.ID26      5   Identifier 26
C1UAR12.ID25      4   Identifier 25
C1UAR12.ID24      3   Identifier 24
C1UAR12.ID23      2   Identifier 23
C1UAR12.ID22      1   Identifier 22
C1UAR12.ID21      0   Identifier 21
C1LAR12          0xEFC4   CAN1 Lower Arbitration Register (msg. )
C1LAR12.ID4       15  Identifier 4
C1LAR12.ID3       14  Identifier 3
C1LAR12.ID2       13  Identifier 2
C1LAR12.ID1       12  Identifier 1
C1LAR12.ID0       11  Identifier 0
C1LAR12.ID12      7   Identifier 12
C1LAR12.ID11      6   Identifier 11
C1LAR12.ID10      5   Identifier 10
C1LAR12.ID9       4   Identifier 9
C1LAR12.ID8       3   Identifier 8
C1LAR12.ID7       2   Identifier 7
C1LAR12.ID6       1   Identifier 6
C1LAR12.ID5       0   Identifier 5
C1MCFG12         0xEFC6   CAN1 Message Configuration Register (msg. )
C1MCFG12.DLC_7    7   Data Length Code - bit 7
C1MCFG12.DLC_6    6   Data Length Code - bit 6
C1MCFG12.DLC_5    5   Data Length Code - bit 5
C1MCFG12.DLC_4    4   Data Length Code - bit 4
C1MCFG12.DIR      3   Message Direction
C1MCFG12.XTD      2   Extended Identifier
C1MCR13          0xEFD1   CAN1 Message Ctrl. Reg. (msg. )
C1MCR13.RMTPND_15        15  Remote Pending - bit 15
C1MCR13.RMTPND_14        14  Remote Pending - bit 14
C1MCR13.TXRQ_13          13  Transmit Request - bit 13
C1MCR13.TXRQ_12          12  Transmit Request - bit 12
C1MCR13.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C1MCR13.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C1MCR13.NEWDAT_9         9   New Data - bit 9
C1MCR13.NEWDAT_8         8   New Data - bit 8
C1MCR13.MSGVAL_7         7   Message Valid - bit 7
C1MCR13.MSGVAL_6         6   Message Valid - bit 6
C1MCR13.TXIE_5           5   Transmit Interrupt Enable - bit 5
C1MCR13.TXIE_4           4   Transmit Interrupt Enable - bit 4
C1MCR13.RXIE_3           3   Receive Interrupt Enable - bit 3
C1MCR13.RXIE_2           2   Receive Interrupt Enable - bit 2
C1MCR13.INTPND_1         1   Interrupt Pending - bit 1
C1MCR13.INTPND_0         0   Interrupt Pending - bit 0
C1UAR13          0xEFD2   CAN1 Upper Arbitration Reg. (msg. )
C1UAR13.ID20      15  Identifier 20
C1UAR13.ID19      14  Identifier 19
C1UAR13.ID18      13  Identifier 18
C1UAR13.ID17      12  Identifier 17
C1UAR13.ID16      11  Identifier 16
C1UAR13.ID15      10  Identifier 15
C1UAR13.ID14      9   Identifier 14
C1UAR13.ID13      8   Identifier 13
C1UAR13.ID28      7   Identifier 28
C1UAR13.ID27      6   Identifier 27
C1UAR13.ID26      5   Identifier 26
C1UAR13.ID25      4   Identifier 25
C1UAR13.ID24      3   Identifier 24
C1UAR13.ID23      2   Identifier 23
C1UAR13.ID22      1   Identifier 22
C1UAR13.ID21      0   Identifier 21
C1LAR13          0xEFD4   CAN1 Lower Arbitration Register (msg. )
C1LAR13.ID4       15  Identifier 4
C1LAR13.ID3       14  Identifier 3
C1LAR13.ID2       13  Identifier 2
C1LAR13.ID1       12  Identifier 1
C1LAR13.ID0       11  Identifier 0
C1LAR13.ID12      7   Identifier 12
C1LAR13.ID11      6   Identifier 11
C1LAR13.ID10      5   Identifier 10
C1LAR13.ID9       4   Identifier 9
C1LAR13.ID8       3   Identifier 8
C1LAR13.ID7       2   Identifier 7
C1LAR13.ID6       1   Identifier 6
C1LAR13.ID5       0   Identifier 5
C1MCFG13         0xEFD6   CAN1 Message Configuration Register (msg. )
C1MCFG13.DLC_7    7   Data Length Code - bit 7
C1MCFG13.DLC_6    6   Data Length Code - bit 6
C1MCFG13.DLC_5    5   Data Length Code - bit 5
C1MCFG13.DLC_4    4   Data Length Code - bit 4
C1MCFG13.DIR      3   Message Direction
C1MCFG13.XTD      2   Extended Identifier
C1MCR14          0xEFE1   CAN1 Message Ctrl. Reg. (msg. )
C1MCR14.RMTPND_15        15  Remote Pending - bit 15
C1MCR14.RMTPND_14        14  Remote Pending - bit 14
C1MCR14.TXRQ_13          13  Transmit Request - bit 13
C1MCR14.TXRQ_12          12  Transmit Request - bit 12
C1MCR14.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C1MCR14.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C1MCR14.NEWDAT_9         9   New Data - bit 9
C1MCR14.NEWDAT_8         8   New Data - bit 8
C1MCR14.MSGVAL_7         7   Message Valid - bit 7
C1MCR14.MSGVAL_6         6   Message Valid - bit 6
C1MCR14.TXIE_5           5   Transmit Interrupt Enable - bit 5
C1MCR14.TXIE_4           4   Transmit Interrupt Enable - bit 4
C1MCR14.RXIE_3           3   Receive Interrupt Enable - bit 3
C1MCR14.RXIE_2           2   Receive Interrupt Enable - bit 2
C1MCR14.INTPND_1         1   Interrupt Pending - bit 1
C1MCR14.INTPND_0         0   Interrupt Pending - bit 0
C1UAR14          0xEFE2   CAN1 Upper Arbitration Reg. (msg. )
C1UAR14.ID20      15  Identifier 20
C1UAR14.ID19      14  Identifier 19
C1UAR14.ID18      13  Identifier 18
C1UAR14.ID17      12  Identifier 17
C1UAR14.ID16      11  Identifier 16
C1UAR14.ID15      10  Identifier 15
C1UAR14.ID14      9   Identifier 14
C1UAR14.ID13      8   Identifier 13
C1UAR14.ID28      7   Identifier 28
C1UAR14.ID27      6   Identifier 27
C1UAR14.ID26      5   Identifier 26
C1UAR14.ID25      4   Identifier 25
C1UAR14.ID24      3   Identifier 24
C1UAR14.ID23      2   Identifier 23
C1UAR14.ID22      1   Identifier 22
C1UAR14.ID21      0   Identifier 21
C1LAR14          0xEFE4   CAN1 Lower Arbitration Register (msg. )
C1LAR14.ID4       15  Identifier 4
C1LAR14.ID3       14  Identifier 3
C1LAR14.ID2       13  Identifier 2
C1LAR14.ID1       12  Identifier 1
C1LAR14.ID0       11  Identifier 0
C1LAR14.ID12      7   Identifier 12
C1LAR14.ID11      6   Identifier 11
C1LAR14.ID10      5   Identifier 10
C1LAR14.ID9       4   Identifier 9
C1LAR14.ID8       3   Identifier 8
C1LAR14.ID7       2   Identifier 7
C1LAR14.ID6       1   Identifier 6
C1LAR14.ID5       0   Identifier 5
C1MCFG14         0xEFE6   CAN1 Message Configuration Register (msg. )
C1MCFG14.DLC_7    7   Data Length Code - bit 7
C1MCFG14.DLC_6    6   Data Length Code - bit 6
C1MCFG14.DLC_5    5   Data Length Code - bit 5
C1MCFG14.DLC_4    4   Data Length Code - bit 4
C1MCFG14.DIR      3   Message Direction
C1MCFG14.XTD      2   Extended Identifier
C1MCR15          0xEFF1   CAN1 Message Ctrl. Reg. (msg. )
C1MCR15.RMTPND_15        15  Remote Pending - bit 15
C1MCR15.RMTPND_14        14  Remote Pending - bit 14
C1MCR15.TXRQ_13          13  Transmit Request - bit 13
C1MCR15.TXRQ_12          12  Transmit Request - bit 12
C1MCR15.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C1MCR15.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C1MCR15.NEWDAT_9         9   New Data - bit 9
C1MCR15.NEWDAT_8         8   New Data - bit 8
C1MCR15.MSGVAL_7         7   Message Valid - bit 7
C1MCR15.MSGVAL_6         6   Message Valid - bit 6
C1MCR15.TXIE_5           5   Transmit Interrupt Enable - bit 5
C1MCR15.TXIE_4           4   Transmit Interrupt Enable - bit 4
C1MCR15.RXIE_3           3   Receive Interrupt Enable - bit 3
C1MCR15.RXIE_2           2   Receive Interrupt Enable - bit 2
C1MCR15.INTPND_1         1   Interrupt Pending - bit 1
C1MCR15.INTPND_0         0   Interrupt Pending - bit 0
C1UAR15          0xEFF2   CAN1 Upper Arbitration Reg. (msg. )
C1UAR15.ID20      15  Identifier 20
C1UAR15.ID19      14  Identifier 19
C1UAR15.ID18      13  Identifier 18
C1UAR15.ID17      12  Identifier 17
C1UAR15.ID16      11  Identifier 16
C1UAR15.ID15      10  Identifier 15
C1UAR15.ID14      9   Identifier 14
C1UAR15.ID13      8   Identifier 13
C1UAR15.ID28      7   Identifier 28
C1UAR15.ID27      6   Identifier 27
C1UAR15.ID26      5   Identifier 26
C1UAR15.ID25      4   Identifier 25
C1UAR15.ID24      3   Identifier 24
C1UAR15.ID23      2   Identifier 23
C1UAR15.ID22      1   Identifier 22
C1UAR15.ID21      0   Identifier 21
C1LAR15          0xEFF4   CAN1 Lower Arbitration Register (msg. )
C1LAR15.ID4       15  Identifier 4
C1LAR15.ID3       14  Identifier 3
C1LAR15.ID2       13  Identifier 2
C1LAR15.ID1       12  Identifier 1
C1LAR15.ID0       11  Identifier 0
C1LAR15.ID12      7   Identifier 12
C1LAR15.ID11      6   Identifier 11
C1LAR15.ID10      5   Identifier 10
C1LAR15.ID9       4   Identifier 9
C1LAR15.ID8       3   Identifier 8
C1LAR15.ID7       2   Identifier 7
C1LAR15.ID6       1   Identifier 6
C1LAR15.ID5       0   Identifier 5
C1MCFG15         0xEFF6   CAN1 Message Configuration Register (msg. )
C1MCFG15.DLC_7    7   Data Length Code - bit 7
C1MCFG15.DLC_6    6   Data Length Code - bit 6
C1MCFG15.DLC_5    5   Data Length Code - bit 5
C1MCFG15.DLC_4    4   Data Length Code - bit 4
C1MCFG15.DIR      3   Message Direction
C1MCFG15.XTD      2   Extended Identifier
T7               0xF050   CAPCOM Timer 7 Register
T8               0xF052   CAPCOM Timer 8 Register
T7REL            0xF054   CAPCOM Timer 7 Reload Register
T8REL            0xF056   CAPCOM Timer 8 Reload Register
IDPROG           0xF078   Identifier
IDMEM            0xF07A   Identifier
IDCHIP           0xF07C   Identifier
IDMANUF          0xF07E   Identifier
POCON0L          0xF080   Port P0L Output Control Register
POCON0L.PN3DC_15  15  Port Nibble 3 Driver Characteristic - bit 15
POCON0L.PN3DC_14  14  Port Nibble 3 Edge Characteristic - bit 14
POCON0L.PN3EC_13  13  Port Nibble 3 Driver Characteristic - bit 13
POCON0L.PN3EC_12  12  Port Nibble 3 Edge Characteristic - bit 12
POCON0L.PN2DC_11  11  Port Nibble 2 Driver Characteristic - bit 11
POCON0L.PN2DC_10  10  Port Nibble 2 Edge Characteristic - bit 10
POCON0L.PN2EC_9   9   Port Nibble 2 Driver Characteristic - bit 9 
POCON0L.PN2EC_8   8   Port Nibble 2 Edge Characteristic - bit 8 
POCON0L.PN1DC_7   7   Port Nibble 1 Driver Characteristic - bit 7 
POCON0L.PN1DC_6   6   Port Nibble 1 Edge Characteristic - bit 6 
POCON0L.PN1EC_5   5   Port Nibble 1 Driver Characteristic - bit 5 
POCON0L.PN1EC_4   4   Port Nibble 1 Edge Characteristic - bit 4 
POCON0L.PN0DC_3   3   Port Nibble 0 Driver Characteristic - bit 3 
POCON0L.PN0DC_2   2   Port Nibble 0 Edge Characteristic - bit 2 
POCON0L.PN0EC_1   1   Port Nibble 0 Driver Characteristic - bit 1 
POCON0L.PN0EC_0   0   Port Nibble 0 Edge Characteristic - bit 0 
POCON0H          0xF082   Port P0H Output Control Register
POCON0H.PN3DC_15  15  Port Nibble 3 Driver Characteristic - bit 15
POCON0H.PN3DC_14  14  Port Nibble 3 Edge Characteristic - bit 14
POCON0H.PN3EC_13  13  Port Nibble 3 Driver Characteristic - bit 13
POCON0H.PN3EC_12  12  Port Nibble 3 Edge Characteristic - bit 12
POCON0H.PN2DC_11  11  Port Nibble 2 Driver Characteristic - bit 11
POCON0H.PN2DC_10  10  Port Nibble 2 Edge Characteristic - bit 10
POCON0H.PN2EC_9   9   Port Nibble 2 Driver Characteristic - bit 9 
POCON0H.PN2EC_8   8   Port Nibble 2 Edge Characteristic - bit 8 
POCON0H.PN1DC_7   7   Port Nibble 1 Driver Characteristic - bit 7 
POCON0H.PN1DC_6   6   Port Nibble 1 Edge Characteristic - bit 6 
POCON0H.PN1EC_5   5   Port Nibble 1 Driver Characteristic - bit 5 
POCON0H.PN1EC_4   4   Port Nibble 1 Edge Characteristic - bit 4 
POCON0H.PN0DC_3   3   Port Nibble 0 Driver Characteristic - bit 3 
POCON0H.PN0DC_2   2   Port Nibble 0 Edge Characteristic - bit 2 
POCON0H.PN0EC_1   1   Port Nibble 0 Driver Characteristic - bit 1 
POCON0H.PN0EC_0   0   Port Nibble 0 Edge Characteristic - bit 0 
POCON1L          0xF084   Port P1L Output Control Register
POCON1L.PN3DC_15  15  Port Nibble 3 Driver Characteristic - bit 15
POCON1L.PN3DC_14  14  Port Nibble 3 Edge Characteristic - bit 14
POCON1L.PN3EC_13  13  Port Nibble 3 Driver Characteristic - bit 13
POCON1L.PN3EC_12  12  Port Nibble 3 Edge Characteristic - bit 12
POCON1L.PN2DC_11  11  Port Nibble 2 Driver Characteristic - bit 11
POCON1L.PN2DC_10  10  Port Nibble 2 Edge Characteristic - bit 10
POCON1L.PN2EC_9   9   Port Nibble 2 Driver Characteristic - bit 9 
POCON1L.PN2EC_8   8   Port Nibble 2 Edge Characteristic - bit 8 
POCON1L.PN1DC_7   7   Port Nibble 1 Driver Characteristic - bit 7 
POCON1L.PN1DC_6   6   Port Nibble 1 Edge Characteristic - bit 6 
POCON1L.PN1EC_5   5   Port Nibble 1 Driver Characteristic - bit 5 
POCON1L.PN1EC_4   4   Port Nibble 1 Edge Characteristic - bit 4 
POCON1L.PN0DC_3   3   Port Nibble 0 Driver Characteristic - bit 3 
POCON1L.PN0DC_2   2   Port Nibble 0 Edge Characteristic - bit 2 
POCON1L.PN0EC_1   1   Port Nibble 0 Driver Characteristic - bit 1 
POCON1L.PN0EC_0   0   Port Nibble 0 Edge Characteristic - bit 0 
POCON1H          0xF086   Port P1H Output Control Register
POCON1H.PN3DC_15  15  Port Nibble 3 Driver Characteristic - bit 15
POCON1H.PN3DC_14  14  Port Nibble 3 Edge Characteristic - bit 14
POCON1H.PN3EC_13  13  Port Nibble 3 Driver Characteristic - bit 13
POCON1H.PN3EC_12  12  Port Nibble 3 Edge Characteristic - bit 12
POCON1H.PN2DC_11  11  Port Nibble 2 Driver Characteristic - bit 11
POCON1H.PN2DC_10  10  Port Nibble 2 Edge Characteristic - bit 10
POCON1H.PN2EC_9   9   Port Nibble 2 Driver Characteristic - bit 9 
POCON1H.PN2EC_8   8   Port Nibble 2 Edge Characteristic - bit 8 
POCON1H.PN1DC_7   7   Port Nibble 1 Driver Characteristic - bit 7 
POCON1H.PN1DC_6   6   Port Nibble 1 Edge Characteristic - bit 6 
POCON1H.PN1EC_5   5   Port Nibble 1 Driver Characteristic - bit 5 
POCON1H.PN1EC_4   4   Port Nibble 1 Edge Characteristic - bit 4 
POCON1H.PN0DC_3   3   Port Nibble 0 Driver Characteristic - bit 3 
POCON1H.PN0DC_2   2   Port Nibble 0 Edge Characteristic - bit 2 
POCON1H.PN0EC_1   1   Port Nibble 0 Driver Characteristic - bit 1 
POCON1H.PN0EC_0   0   Port Nibble 0 Edge Characteristic - bit 0 
POCON2           0xF088   Port P2 Output Control Register
POCON2.PN3DC_15   15  Port Nibble 3 Driver Characteristic - bit 15
POCON2.PN3DC_14   14  Port Nibble 3 Edge Characteristic - bit 14
POCON2.PN3EC_13   13  Port Nibble 3 Driver Characteristic - bit 13
POCON2.PN3EC_12   12  Port Nibble 3 Edge Characteristic - bit 12
POCON2.PN2DC_11   11  Port Nibble 2 Driver Characteristic - bit 11
POCON2.PN2DC_10   10  Port Nibble 2 Edge Characteristic - bit 10
POCON2.PN2EC_9    9   Port Nibble 2 Driver Characteristic - bit 9
POCON2.PN2EC_8    8   Port Nibble 2 Edge Characteristic - bit 8
POCON2.PN1DC_7    7   Port Nibble 1 Driver Characteristic - bit 7
POCON2.PN1DC_6    6   Port Nibble 1 Edge Characteristic - bit 6
POCON2.PN1EC_5    5   Port Nibble 1 Driver Characteristic - bit 5
POCON2.PN1EC_4    4   Port Nibble 1 Edge Characteristic - bit 4
POCON2.PN0DC_3    3   Port Nibble 0 Driver Characteristic - bit 3
POCON2.PN0DC_2    2   Port Nibble 0 Edge Characteristic - bit 2
POCON2.PN0EC_1    1   Port Nibble 0 Driver Characteristic - bit 1
POCON2.PN0EC_0    0   Port Nibble 0 Edge Characteristic - bit 0
POCON3           0xF08A   Port P3 Output Control Register
POCON3.PN3DC_15   15  Port Nibble 3 Driver Characteristic - bit 15
POCON3.PN3DC_14   14  Port Nibble 3 Edge Characteristic - bit 14
POCON3.PN3EC_13   13  Port Nibble 3 Driver Characteristic - bit 13
POCON3.PN3EC_12   12  Port Nibble 3 Edge Characteristic - bit 12
POCON3.PN2DC_11   11  Port Nibble 2 Driver Characteristic - bit 11
POCON3.PN2DC_10   10  Port Nibble 2 Edge Characteristic - bit 10
POCON3.PN2EC_9    9   Port Nibble 2 Driver Characteristic - bit 9
POCON3.PN2EC_8    8   Port Nibble 2 Edge Characteristic - bit 8
POCON3.PN1DC_7    7   Port Nibble 1 Driver Characteristic - bit 7
POCON3.PN1DC_6    6   Port Nibble 1 Edge Characteristic - bit 6
POCON3.PN1EC_5    5   Port Nibble 1 Driver Characteristic - bit 5
POCON3.PN1EC_4    4   Port Nibble 1 Edge Characteristic - bit 4
POCON3.PN0DC_3    3   Port Nibble 0 Driver Characteristic - bit 3
POCON3.PN0DC_2    2   Port Nibble 0 Edge Characteristic - bit 2
POCON3.PN0EC_1    1   Port Nibble 0 Driver Characteristic - bit 1
POCON3.PN0EC_0    0   Port Nibble 0 Edge Characteristic - bit 0
POCON4           0xF08C   Port P4 Output Control Register
POCON4.PN3DC_15   15  Port Nibble 3 Driver Characteristic - bit 15
POCON4.PN3DC_14   14  Port Nibble 3 Edge Characteristic - bit 14
POCON4.PN3EC_13   13  Port Nibble 3 Driver Characteristic - bit 13
POCON4.PN3EC_12   12  Port Nibble 3 Edge Characteristic - bit 12
POCON4.PN2DC_11   11  Port Nibble 2 Driver Characteristic - bit 11
POCON4.PN2DC_10   10  Port Nibble 2 Edge Characteristic - bit 10
POCON4.PN2EC_9    9   Port Nibble 2 Driver Characteristic - bit 9
POCON4.PN2EC_8    8   Port Nibble 2 Edge Characteristic - bit 8
POCON4.PN1DC_7    7   Port Nibble 1 Driver Characteristic - bit 7
POCON4.PN1DC_6    6   Port Nibble 1 Edge Characteristic - bit 6
POCON4.PN1EC_5    5   Port Nibble 1 Driver Characteristic - bit 5
POCON4.PN1EC_4    4   Port Nibble 1 Edge Characteristic - bit 4
POCON4.PN0DC_3    3   Port Nibble 0 Driver Characteristic - bit 3
POCON4.PN0DC_2    2   Port Nibble 0 Edge Characteristic - bit 2
POCON4.PN0EC_1    1   Port Nibble 0 Driver Characteristic - bit 1
POCON4.PN0EC_0    0   Port Nibble 0 Edge Characteristic - bit 0
POCON6           0xF08E   Port P6 Output Control Register
POCON6.PN3DC_15   15  Port Nibble 3 Driver Characteristic - bit 15
POCON6.PN3DC_14   14  Port Nibble 3 Edge Characteristic - bit 14
POCON6.PN3EC_13   13  Port Nibble 3 Driver Characteristic - bit 13
POCON6.PN3EC_12   12  Port Nibble 3 Edge Characteristic - bit 12
POCON6.PN2DC_11   11  Port Nibble 2 Driver Characteristic - bit 11
POCON6.PN2DC_10   10  Port Nibble 2 Edge Characteristic - bit 10
POCON6.PN2EC_9    9   Port Nibble 2 Driver Characteristic - bit 9
POCON6.PN2EC_8    8   Port Nibble 2 Edge Characteristic - bit 8
POCON6.PN1DC_7    7   Port Nibble 1 Driver Characteristic - bit 7
POCON6.PN1DC_6    6   Port Nibble 1 Edge Characteristic - bit 6
POCON6.PN1EC_5    5   Port Nibble 1 Driver Characteristic - bit 5
POCON6.PN1EC_4    4   Port Nibble 1 Edge Characteristic - bit 4
POCON6.PN0DC_3    3   Port Nibble 0 Driver Characteristic - bit 3
POCON6.PN0DC_2    2   Port Nibble 0 Edge Characteristic - bit 2
POCON6.PN0EC_1    1   Port Nibble 0 Driver Characteristic - bit 1
POCON6.PN0EC_0    0   Port Nibble 0 Edge Characteristic - bit 0
POCON7           0xF090   Port P7 Output Control Register
POCON7.PN3DC_15   15  Port Nibble 3 Driver Characteristic - bit 15
POCON7.PN3DC_14   14  Port Nibble 3 Edge Characteristic - bit 14
POCON7.PN3EC_13   13  Port Nibble 3 Driver Characteristic - bit 13
POCON7.PN3EC_12   12  Port Nibble 3 Edge Characteristic - bit 12
POCON7.PN2DC_11   11  Port Nibble 2 Driver Characteristic - bit 11
POCON7.PN2DC_10   10  Port Nibble 2 Edge Characteristic - bit 10
POCON7.PN2EC_9    9   Port Nibble 2 Driver Characteristic - bit 9
POCON7.PN2EC_8    8   Port Nibble 2 Edge Characteristic - bit 8
POCON7.PN1DC_7    7   Port Nibble 1 Driver Characteristic - bit 7
POCON7.PN1DC_6    6   Port Nibble 1 Edge Characteristic - bit 6
POCON7.PN1EC_5    5   Port Nibble 1 Driver Characteristic - bit 5
POCON7.PN1EC_4    4   Port Nibble 1 Edge Characteristic - bit 4
POCON7.PN0DC_3    3   Port Nibble 0 Driver Characteristic - bit 3
POCON7.PN0DC_2    2   Port Nibble 0 Edge Characteristic - bit 2
POCON7.PN0EC_1    1   Port Nibble 0 Driver Characteristic - bit 1
POCON7.PN0EC_0    0   Port Nibble 0 Edge Characteristic - bit 0
ADDAT2           0xF0A0   A/D Converter 2 Result Register
ADDAT2.CHNR_15    15  Channel Number - bit 15
ADDAT2.CHNR_14    14  Channel Number - bit 14
ADDAT2.CHNR_13    13  Channel Number - bit 13
ADDAT2.CHNR_12    12  Channel Number - bit 12
ADDAT2.ADRES_9    9   A/D Conversion Result - bit 9
ADDAT2.ADRES_8    8   A/D Conversion Result - bit 8
ADDAT2.ADRES_7    7   A/D Conversion Result - bit 7
ADDAT2.ADRES_6    6   A/D Conversion Result - bit 6
ADDAT2.ADRES_5    5   A/D Conversion Result - bit 5
ADDAT2.ADRES_4    4   A/D Conversion Result - bit 4
ADDAT2.ADRES_3    3   A/D Conversion Result - bit 3
ADDAT2.ADRES_2    2   A/D Conversion Result - bit 2
ADDAT2.ADRES_1    1   A/D Conversion Result - bit 1
ADDAT2.ADRES_0    0   A/D Conversion Result - bit 0
POCON20          0xF0AA   Dedicated Pin Output Control Register
POCON20.PN3DC_15  15  Port Nibble 3 Driver Characteristic - bit 15
POCON20.PN3DC_14  14  Port Nibble 3 Edge Characteristic - bit 14
POCON20.PN3EC_13  13  Port Nibble 3 Driver Characteristic - bit 13
POCON20.PN3EC_12  12  Port Nibble 3 Edge Characteristic - bit 12
POCON20.PN2DC_11  11  Port Nibble 2 Driver Characteristic - bit 11
POCON20.PN2DC_10  10  Port Nibble 2 Edge Characteristic - bit 10
POCON20.PN2EC_9   9   Port Nibble 2 Driver Characteristic - bit 9
POCON20.PN2EC_8   8   Port Nibble 2 Edge Characteristic - bit 8
POCON20.PN1DC_7   7   Port Nibble 1 Driver Characteristic - bit 7
POCON20.PN1DC_6   6   Port Nibble 1 Edge Characteristic - bit 6
POCON20.PN1EC_5   5   Port Nibble 1 Driver Characteristic - bit 5
POCON20.PN1EC_4   4   Port Nibble 1 Edge Characteristic - bit 4
POCON20.PN0DC_3   3   Port Nibble 0 Driver Characteristic - bit 3
POCON20.PN0DC_2   2   Port Nibble 0 Edge Characteristic - bit 2
POCON20.PN0EC_1   1   Port Nibble 0 Driver Characteristic - bit 1
POCON20.PN0EC_0   0   Port Nibble 0 Edge Characteristic - bit 0
SSCTB            0xF0B0   SSC Transmit Buffer
SSCRB            0xF0B2   SSC Receive Buffer
SSCBR            0xF0B4   SSC Baudrate Register
T14REL           0xF0D0   RTC Timer 14 Reload Register
T14              0xF0D2   RTC Timer 14 Register
RTCL             0xF0D4   RTC Low Register
RTCH             0xF0D6   RTC High Register
DP0L             0xF100   P0L Direction Control Register
DP0L.DP0L7        7   Port direction register DP0L bit 7
DP0L.DP0L6        6   Port direction register DP0L bit 6
DP0L.DP0L5        5   Port direction register DP0L bit 5
DP0L.DP0L4        4   Port direction register DP0L bit 4
DP0L.DP0L3        3   Port direction register DP0L bit 3
DP0L.DP0L2        2   Port direction register DP0L bit 2
DP0L.DP0L1        1   Port direction register DP0L bit 1
DP0L.DP0L0        0   Port direction register DP0L bit 0
DP0H             0xF102   P0H Direction Control Register
DP0H.DP0H7        7   Port direction register DP0H bit 7
DP0H.DP0H6        6   Port direction register DP0H bit 6
DP0H.DP0H5        5   Port direction register DP0H bit 5
DP0H.DP0H4        4   Port direction register DP0H bit 4
DP0H.DP0H3        3   Port direction register DP0H bit 3
DP0H.DP0H2        2   Port direction register DP0H bit 2
DP0H.DP0H1        1   Port direction register DP0H bit 1
DP0H.DP0H0        0   Port direction register DP0H bit 0
DP1L             0xF104   P1L Direction Control Register
DP1L.DP1L7        7   Port direction register DP1L bit 7
DP1L.DP1L6        6   Port direction register DP1L bit 6
DP1L.DP1L5        5   Port direction register DP1L bit 5
DP1L.DP1L4        4   Port direction register DP1L bit 4
DP1L.DP1L3        3   Port direction register DP1L bit 3
DP1L.DP1L2        2   Port direction register DP1L bit 2
DP1L.DP1L1        1   Port direction register DP1L bit 1
DP1L.DP1L0        0   Port direction register DP1L bit 0
DP1H             0xF106   P1H Direction Control Register
DP1H.DP1H7        7   Port direction register DP1H bit 7
DP1H.DP1H6        6   Port direction register DP1H bit 6
DP1H.DP1H5        5   Port direction register DP1H bit 5
DP1H.DP1H4        4   Port direction register DP1H bit 4
DP1H.DP1H3        3   Port direction register DP1H bit 3
DP1H.DP1H2        2   Port direction register DP1H bit 2
DP1H.DP1H1        1   Port direction register DP1H bit 1
DP1H.DP1H0        0   Port direction register DP1L bit 0
RP0H             0xF108   System Startup Configuration Register (read only)
RP0H.CLKCFG_7     7   Clock Generation Mode Configuration - bit 7
RP0H.CLKCFG_6     6   Clock Generation Mode Configuration - bit 6
RP0H.CLKCFG_5     5   Clock Generation Mode Configuration - bit 5
RP0H.SALSEL_4     4   Segment Address Line Selection - bit 4
RP0H.SALSEL_3     3   Segment Address Line Selection - bit 3
RP0H.CSSEL_2      2   Chip Select Line Selection - bit 2
RP0H.CSSEL_1      1   Chip Select Line Selection - bit 1
RP0H.WRC          0   Write Configuration
CC16IC           0xF160   CAPCOM Register 16 Interrupt Ctrl. Reg.
CC16IC.CC16IR     7   Interrupt Request Flag
CC16IC.CC16IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC16IC.ILVL_5     5   Interrupt Priority Level - bit 5
CC16IC.ILVL_4     4   Interrupt Priority Level - bit 4
CC16IC.ILVL_3     3   Interrupt Priority Level - bit 3
CC16IC.ILVL_2     2   Interrupt Priority Level - bit 2
CC16IC.GLVL_1     1   Group Level - bit 1
CC16IC.GLVL_0     0   Group Level - bit 0
CC17IC           0xF162   CAPCOM Register 17 Interrupt Ctrl. Reg.
CC17IC.CC17IR     7   Interrupt Request Flag
CC17IC.CC17IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC17IC.ILVL_5     5   Interrupt Priority Level - bit 5
CC17IC.ILVL_4     4   Interrupt Priority Level - bit 4
CC17IC.ILVL_3     3   Interrupt Priority Level - bit 3
CC17IC.ILVL_2     2   Interrupt Priority Level - bit 2
CC17IC.GLVL_1     1   Group Level - bit 1
CC17IC.GLVL_0     0   Group Level - bit 0
CC18IC           0xF164   CAPCOM Register 18 Interrupt Ctrl. Reg.
CC18IC.CC18IR     7   Interrupt Request Flag
CC18IC.CC18IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC18IC.ILVL_5     5   Interrupt Priority Level - bit 5
CC18IC.ILVL_4     4   Interrupt Priority Level - bit 4
CC18IC.ILVL_3     3   Interrupt Priority Level - bit 3
CC18IC.ILVL_2     2   Interrupt Priority Level - bit 2
CC18IC.GLVL_1     1   Group Level - bit 1
CC18IC.GLVL_0     0   Group Level - bit 0
CC19IC           0xF166   CAPCOM Register 19 Interrupt Ctrl. Reg.
CC19IC.CC19IR     7   Interrupt Request Flag
CC19IC.CC19IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC19IC.ILVL_5     5   Interrupt Priority Level - bit 5
CC19IC.ILVL_4     4   Interrupt Priority Level - bit 4
CC19IC.ILVL_3     3   Interrupt Priority Level - bit 3
CC19IC.ILVL_2     2   Interrupt Priority Level - bit 2
CC19IC.GLVL_1     1   Group Level - bit 1
CC19IC.GLVL_0     0   Group Level - bit 0
CC20IC           0xF168   CAPCOM Register 20 Interrupt Ctrl. Reg.
CC20IC.CC20IR     7   Interrupt Request Flag
CC20IC.CC20IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC20IC.ILVL_5     5   Interrupt Priority Level - bit 5
CC20IC.ILVL_4     4   Interrupt Priority Level - bit 4
CC20IC.ILVL_3     3   Interrupt Priority Level - bit 3
CC20IC.ILVL_2     2   Interrupt Priority Level - bit 2
CC20IC.GLVL_1     1   Group Level - bit 1
CC20IC.GLVL_0     0   Group Level - bit 0
CC21IC           0xF16A   CAPCOM Register 21 Interrupt Ctrl. Reg.
CC21IC.CC21IR     7   Interrupt Request Flag
CC21IC.CC21IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC21IC.ILVL_5     5   Interrupt Priority Level - bit 5
CC21IC.ILVL_4     4   Interrupt Priority Level - bit 4
CC21IC.ILVL_3     3   Interrupt Priority Level - bit 3
CC21IC.ILVL_2     2   Interrupt Priority Level - bit 2
CC21IC.GLVL_1     1   Group Level - bit 1
CC21IC.GLVL_0     0   Group Level - bit 0
CC22IC           0xF16C   CAPCOM Register 22 Interrupt Ctrl. Reg.
CC22IC.CC22IR     7   Interrupt Request Flag
CC22IC.CC22IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC22IC.ILVL_5     5   Interrupt Priority Level - bit 5
CC22IC.ILVL_4     4   Interrupt Priority Level - bit 4
CC22IC.ILVL_3     3   Interrupt Priority Level - bit 3
CC22IC.ILVL_2     2   Interrupt Priority Level - bit 2
CC22IC.GLVL_1     1   Group Level - bit 1
CC22IC.GLVL_0     0   Group Level - bit 0
CC23IC           0xF16E   CAPCOM Register 23 Interrupt Ctrl. Reg.
CC23IC.CC23IR     7   Interrupt Request Flag
CC23IC.CC23IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC23IC.ILVL_5     5   Interrupt Priority Level - bit 5
CC23IC.ILVL_4     4   Interrupt Priority Level - bit 4
CC23IC.ILVL_3     3   Interrupt Priority Level - bit 3
CC23IC.ILVL_2     2   Interrupt Priority Level - bit 2
CC23IC.GLVL_1     1   Group Level - bit 1
CC23IC.GLVL_0     0   Group Level - bit 0
CC24IC           0xF170   CAPCOM Register 24 Interrupt Ctrl. Reg.
CC24IC.CC24IR     7   Interrupt Request Flag
CC24IC.CC24IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC24IC.ILVL_5     5   Interrupt Priority Level - bit 5
CC24IC.ILVL_4     4   Interrupt Priority Level - bit 4
CC24IC.ILVL_3     3   Interrupt Priority Level - bit 3
CC24IC.ILVL_2     2   Interrupt Priority Level - bit 2
CC24IC.GLVL_1     1   Group Level - bit 1
CC24IC.GLVL_0     0   Group Level - bit 0
CC25IC           0xF172   CAPCOM Register 25 Interrupt Ctrl. Reg.
CC25IC.CC25IR     7   Interrupt Request Flag
CC25IC.CC25IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC25IC.ILVL_5     5   Interrupt Priority Level - bit 5
CC25IC.ILVL_4     4   Interrupt Priority Level - bit 4
CC25IC.ILVL_3     3   Interrupt Priority Level - bit 3
CC25IC.ILVL_2     2   Interrupt Priority Level - bit 2
CC25IC.GLVL_1     1   Group Level - bit 1
CC25IC.GLVL_0     0   Group Level - bit 0
CC26IC           0xF174   CAPCOM Register 26 Interrupt Ctrl. Reg.
CC26IC.CC26IR     7   Interrupt Request Flag
CC26IC.CC26IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC26IC.ILVL_5     5   Interrupt Priority Level - bit 5
CC26IC.ILVL_4     4   Interrupt Priority Level - bit 4
CC26IC.ILVL_3     3   Interrupt Priority Level - bit 3
CC26IC.ILVL_2     2   Interrupt Priority Level - bit 2
CC26IC.GLVL_1     1   Group Level - bit 1
CC26IC.GLVL_0     0   Group Level - bit 0
CC27IC           0xF176   CAPCOM Register 27 Interrupt Ctrl. Reg.
CC27IC.CC27IR     7   Interrupt Request Flag
CC27IC.CC27IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC27IC.ILVL_5     5   Interrupt Priority Level - bit 5
CC27IC.ILVL_4     4   Interrupt Priority Level - bit 4
CC27IC.ILVL_3     3   Interrupt Priority Level - bit 3
CC27IC.ILVL_2     2   Interrupt Priority Level - bit 2
CC27IC.GLVL_1     1   Group Level - bit 1
CC27IC.GLVL_0     0   Group Level - bit 0
CC28IC           0xF178   CAPCOM Register 28 Interrupt Ctrl. Reg.
CC28IC.CC28IR     7   Interrupt Request Flag
CC28IC.CC28IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC28IC.ILVL_5     5   Interrupt Priority Level - bit 5
CC28IC.ILVL_4     4   Interrupt Priority Level - bit 4
CC28IC.ILVL_3     3   Interrupt Priority Level - bit 3
CC28IC.ILVL_2     2   Interrupt Priority Level - bit 2
CC28IC.GLVL_1     1   Group Level - bit 1
CC28IC.GLVL_0     0   Group Level - bit 0
T7IC             0xF17A   CAPCOM Timer 7 Interrupt Ctrl. Reg.
T7IC.T7IR         7   Interrupt Request Flag
T7IC.T7IE         6   Interrupt Enable Control Bit (individually enables/disables a specific source)
T7IC.ILVL_5       5   Interrupt Priority Level - bit 5
T7IC.ILVL_4       4   Interrupt Priority Level - bit 4
T7IC.ILVL_3       3   Interrupt Priority Level - bit 3
T7IC.ILVL_2       2   Interrupt Priority Level - bit 2
T7IC.GLVL_1       1   Group Level - bit 1
T7IC.GLVL_0       0   Group Level - bit 0
T8IC             0xF17C   CAPCOM Timer 8 Interrupt Ctrl. Reg.
T8IC.T8IR         7   Interrupt Request Flag
T8IC.T8IE         6   Interrupt Enable Control Bit (individually enables/disables a specific source)
T8IC.ILVL_5       5   Interrupt Priority Level - bit 5
T8IC.ILVL_4       4   Interrupt Priority Level - bit 4
T8IC.ILVL_3       3   Interrupt Priority Level - bit 3
T8IC.ILVL_2       2   Interrupt Priority Level - bit 2
T8IC.GLVL_1       1   Group Level - bit 1
T8IC.GLVL_0       0   Group Level - bit 0
XP4IC            0xF182   ASC1 Transmit Interrupt Control Register
XP4IC.XP4IR       7   Interrupt Request Flag
XP4IC.XP4IE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
XP4IC.ILVL_5      5   Interrupt Priority Level - bit 5
XP4IC.ILVL_4      4   Interrupt Priority Level - bit 4
XP4IC.ILVL_3      3   Interrupt Priority Level - bit 3
XP4IC.ILVL_2      2   Interrupt Priority Level - bit 2
XP4IC.GLVL_1      1   Group Level - bit 1
XP4IC.GLVL_0      0   Group Level - bit 0
CC29IC           0xF184   CAPCOM Register 29 Interrupt Ctrl. Reg.
CC29IC.CC29IR     7   Interrupt Request Flag
CC29IC.CC29IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC29IC.ILVL_5     5   Interrupt Priority Level - bit 5
CC29IC.ILVL_4     4   Interrupt Priority Level - bit 4
CC29IC.ILVL_3     3   Interrupt Priority Level - bit 3
CC29IC.ILVL_2     2   Interrupt Priority Level - bit 2
CC29IC.GLVL_1     1   Group Level - bit 1
CC29IC.GLVL_0     0   Group Level - bit 0
XP0IC            0xF186   IIC Data Interrupt Control Register
XP0IC.XP0IR       7   Interrupt Request Flag
XP0IC.XP0IE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
XP0IC.ILVL_5      5   Interrupt Priority Level - bit 5
XP0IC.ILVL_4      4   Interrupt Priority Level - bit 4
XP0IC.ILVL_3      3   Interrupt Priority Level - bit 3
XP0IC.ILVL_2      2   Interrupt Priority Level - bit 2
XP0IC.GLVL_1      1   Group Level - bit 1
XP0IC.GLVL_0      0   Group Level - bit 0
XP5IC            0xF18A   ASC1 Receive Interrupt Control Register
XP5IC.XP5IR       7   Interrupt Request Flag
XP5IC.XP5IE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
XP5IC.ILVL_5      5   Interrupt Priority Level - bit 5
XP5IC.ILVL_4      4   Interrupt Priority Level - bit 4
XP5IC.ILVL_3      3   Interrupt Priority Level - bit 3
XP5IC.ILVL_2      2   Interrupt Priority Level - bit 2
XP5IC.GLVL_1      1   Group Level - bit 1
XP5IC.GLVL_0      0   Group Level - bit 0
CC30IC           0xF18C   CAPCOM Register 30 Interrupt Ctrl. Reg.
CC30IC.CC30IR     7   Interrupt Request Flag
CC30IC.CC30IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC30IC.ILVL_5     5   Interrupt Priority Level - bit 5
CC30IC.ILVL_4     4   Interrupt Priority Level - bit 4
CC30IC.ILVL_3     3   Interrupt Priority Level - bit 3
CC30IC.ILVL_2     2   Interrupt Priority Level - bit 2
CC30IC.GLVL_1     1   Group Level - bit 1
CC30IC.GLVL_0     0   Group Level - bit 0
XP1IC            0xF18E   IIC Protocol Interrupt Control Register
XP1IC.XP1IR       7   Interrupt Request Flag
XP1IC.XP1IE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
XP1IC.ILVL_5      5   Interrupt Priority Level - bit 5
XP1IC.ILVL_4      4   Interrupt Priority Level - bit 4
XP1IC.ILVL_3      3   Interrupt Priority Level - bit 3
XP1IC.ILVL_2      2   Interrupt Priority Level - bit 2
XP1IC.GLVL_1      1   Group Level - bit 1
XP1IC.GLVL_0      0   Group Level - bit 0
XP6IC            0xF192   ASC1 Error Interrupt Control Register
XP6IC.XP6IR       7   Interrupt Request Flag
XP6IC.XP6IE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
XP6IC.ILVL_5      5   Interrupt Priority Level - bit 5
XP6IC.ILVL_4      4   Interrupt Priority Level - bit 4
XP6IC.ILVL_3      3   Interrupt Priority Level - bit 3
XP6IC.ILVL_2      2   Interrupt Priority Level - bit 2
XP6IC.GLVL_1      1   Group Level - bit 1
XP6IC.GLVL_0      0   Group Level - bit 0
CC31IC           0xF194   CAPCOM Register 31 Interrupt Ctrl. Reg.
CC31IC.CC31IR     7   Interrupt Request Flag
CC31IC.CC31IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC31IC.ILVL_5     5   Interrupt Priority Level - bit 5
CC31IC.ILVL_4     4   Interrupt Priority Level - bit 4
CC31IC.ILVL_3     3   Interrupt Priority Level - bit 3
CC31IC.ILVL_2     2   Interrupt Priority Level - bit 2
CC31IC.GLVL_1     1   Group Level - bit 1
CC31IC.GLVL_0     0   Group Level - bit 0
XP2IC            0xF196   CAN1 Interrupt Control Register
XP2IC.XP2IR       7   Interrupt Request Flag
XP2IC.XP2IE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
XP2IC.ILVL_5      5   Interrupt Priority Level - bit 5
XP2IC.ILVL_4      4   Interrupt Priority Level - bit 4
XP2IC.ILVL_3      3   Interrupt Priority Level - bit 3
XP2IC.ILVL_2      2   Interrupt Priority Level - bit 2
XP2IC.GLVL_1      1   Group Level - bit 1
XP2IC.GLVL_0      0   Group Level - bit 0
XP7IC            0xF19A   CAN2/SDLM Interrupt Control Register
XP7IC.XP7IR       7   Interrupt Request Flag
XP7IC.XP7IE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
XP7IC.ILVL_5      5   Interrupt Priority Level - bit 5
XP7IC.ILVL_4      4   Interrupt Priority Level - bit 4
XP7IC.ILVL_3      3   Interrupt Priority Level - bit 3
XP7IC.ILVL_2      2   Interrupt Priority Level - bit 2
XP7IC.GLVL_1      1   Group Level - bit 1
XP7IC.GLVL_0      0   Group Level - bit 0
S0TBIC           0xF19C   Serial Channel 0 Transmit Buffer Interrupt Control Register
S0TBIC.S0TBIR     7   Interrupt Request Flag
S0TBIC.S0TBIE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
S0TBIC.ILVL_5     5   Interrupt Priority Level - bit 5
S0TBIC.ILVL_4     4   Interrupt Priority Level - bit 4
S0TBIC.ILVL_3     3   Interrupt Priority Level - bit 3
S0TBIC.ILVL_2     2   Interrupt Priority Level - bit 2
S0TBIC.GLVL_1     1   Group Level - bit 1
S0TBIC.GLVL_0     0   Group Level - bit 0
XP3IC            0xF19E   RTC/PLL/OWD Interrupt Control Register
XP3IC.XP7IR       7   Interrupt Request Flag
XP3IC.XP7IE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
XP3IC.ILVL_5      5   Interrupt Priority Level - bit 5
XP3IC.ILVL_4      4   Interrupt Priority Level - bit 4
XP3IC.ILVL_3      3   Interrupt Priority Level - bit 3
XP3IC.ILVL_2      2   Interrupt Priority Level - bit 2
XP3IC.GLVL_1      1   Group Level - bit 1
XP3IC.GLVL_0      0   Group Level - bit 0
EXICON           0xF1C0   External Interrupt Control Register
EXICON.EXI7ES_15  15  External Interrupt 15 Edge Selection Field - bit 15
EXICON.EXI7ES_14  14  External Interrupt 14 Edge Selection Field - bit 14
EXICON.EXI6ES_13  13  External Interrupt 13 Edge Selection Field - bit 13
EXICON.EXI6ES_12  12  External Interrupt 12 Edge Selection Field - bit 12
EXICON.EXI5ES_11  11  External Interrupt 11 Edge Selection Field - bit 11
EXICON.EXI5ES_10  10  External Interrupt 10 Edge Selection Field - bit 10
EXICON.EXI4ES_9   9   External Interrupt 9 Edge Selection Field - bit 9 
EXICON.EXI4ES_8   8   External Interrupt 8 Edge Selection Field - bit 8 
EXICON.EXI3ES_7   7   External Interrupt 7 Edge Selection Field - bit 7 
EXICON.EXI3ES_6   6   External Interrupt 6 Edge Selection Field - bit 6 
EXICON.EXI2ES_5   5   External Interrupt 5 Edge Selection Field - bit 5 
EXICON.EXI2ES_4   4   External Interrupt 4 Edge Selection Field - bit 4 
EXICON.EXI1ES_3   3   External Interrupt 3 Edge Selection Field - bit 3 
EXICON.EXI1ES_2   2   External Interrupt 2 Edge Selection Field - bit 2 
EXICON.EXI0ES_1   1   External Interrupt 1 Edge Selection Field - bit 1 
EXICON.EXI0ES_0   0   External Interrupt 0 Edge Selection Field - bit 0 
ODP2             0xF1C2   Port 2 Open Drain Control Register
ODP2.ODP2_15      15  Port 2 Open Drain control register bit 15
ODP2.ODP2_14      14  Port 2 Open Drain control register bit 14
ODP2.ODP2_13      13  Port 2 Open Drain control register bit 13
ODP2.ODP2_12      12  Port 2 Open Drain control register bit 12
ODP2.ODP2_11      11  Port 2 Open Drain control register bit 11
ODP2.ODP2_10      10  Port 2 Open Drain control register bit 10
ODP2.ODP2_9       9   Port 2 Open Drain control register bit 9 
ODP2.ODP2_8       8   Port 2 Open Drain control register bit 8 
PICON            0xF1C4   Port Input Threshold Control Register
PICON.P7LIN       6   Port 7 Low Byte Input Level Selection
PICON.P6LIN       5   Port 6 Low Byte Input Level Selection
PICON.P5LIN       4   Port 5 Low Byte Input Level Selection
PICON.P3HIN       3   Port 3 High Byte Input Level Selection
PICON.P3LIN       2   Port 3 Low Byte Input Level Selection
PICON.P2HIN       1   Port 2 High Byte Input Level Selection
ODP3             0xF1C6   Port 3 Open Drain Control Register
ODP3.ODP3_13      13  Port 3 Open Drain control register bit 13
ODP3.ODP3_11      11  Port 3 Open Drain control register bit 11
ODP3.ODP3_10      10  Port 3 Open Drain control register bit 10
ODP3.ODP3_9       9   Port 3 Open Drain control register bit 9 
ODP3.ODP3_8       8   Port 3 Open Drain control register bit 8 
ODP3.ODP3_7       7   Port 3 Open Drain control register bit 7 
ODP3.ODP3_6       6   Port 3 Open Drain control register bit 6 
ODP3.ODP3_5       5   Port 3 Open Drain control register bit 5 
ODP3.ODP3_4       4   Port 3 Open Drain control register bit 4 
ODP3.ODP3_3       3   Port 3 Open Drain control register bit 3 
ODP3.ODP3_2       2   Port 3 Open Drain control register bit 2 
ODP3.ODP3_1       1   Port 3 Open Drain control register bit 1 
ODP3.ODP3_0       0   Port 3 Open Drain control register bit 0 
ODP4             0xF1CA   Port 4 Open Drain Control Register
ODP4.ODP4_7       7   Port 4 Open Drain control register bit 7 
ODP4.ODP4_6       6   Port 4 Open Drain control register bit 6 
ODP4.ODP4_5       5   Port 4 Open Drain control register bit 5 
ODP4.ODP4_4       4   Port 4 Open Drain control register bit 4 
ODP4.ODP4_3       3   Port 4 Open Drain control register bit 3 
ODP4.ODP4_2       2   Port 4 Open Drain control register bit 2 
ODP4.ODP4_1       1   Port 4 Open Drain control register bit 1 
ODP4.ODP4_0       0   Port 4 Open Drain control register bit 0 
ODP6             0xF1CE   Port 6 Open Drain Control Register
ODP6.ODP6_7       7   Port 6 Open Drain control register bit 7
ODP6.ODP6_6       6   Port 6 Open Drain control register bit 6
ODP6.ODP6_5       5   Port 6 Open Drain control register bit 5
ODP6.ODP6_4       4   Port 6 Open Drain control register bit 4
ODP6.ODP6_3       3   Port 6 Open Drain control register bit 3
ODP6.ODP6_2       2   Port 6 Open Drain control register bit 2
ODP6.ODP6_1       1   Port 6 Open Drain control register bit 1
ODP6.ODP6_0       0   Port 6 Open Drain control register bit 0
SYSCON2          0xF1D0   CPU System Configuration Register 2
SYSCON2.CLKLOCK   15  Clock Signal Status Bit
SYSCON2.CLKREL_14 14  Reload Counter Value for Slowdown Divider - 14
SYSCON2.CLKREL_13 13  Reload Counter Value for Slowdown Divider - 13
SYSCON2.CLKREL_12 12  Reload Counter Value for Slowdown Divider - 12
SYSCON2.CLKREL_11 11  Reload Counter Value for Slowdown Divider - 11
SYSCON2.CLKREL_10 10  Reload Counter Value for Slowdown Divider - 10
SYSCON2.CLKCON_9  9   Clock State Control - bit 9
SYSCON2.CLKCON_8  8   Clock State Control - bit 8
SYSCON2.SCS       7   SDD Clock Source
SYSCON2.RCS       6   RTC Clock Source
SYSCON2.PDCON_5   5   Power Down Control - bit 5
SYSCON2.PDCON_4   4   Power Down Control - bit 4
SYSCON2.SYSRLS_3  3   Register Release Function - bit 3
SYSCON2.SYSRLS_2  2   Register Release Function - bit 2
SYSCON2.SYSRLS_1  1   Register Release Function - bit 1
SYSCON2.SYSRLS_0  0   Register Release Function - bit 0
ODP7             0xF1D2   Port 7 Open Drain Control Register
ODP7.ODP7_7       7   Port 7 Open Drain control register bit 7
ODP7.ODP7_6       6   Port 7 Open Drain control register bit 6
ODP7.ODP7_5       5   Port 7 Open Drain control register bit 5
ODP7.ODP7_4       4   Port 7 Open Drain control register bit 4
SYSCON3          0xF1D4   CPU System Configuration Register 3
SYSCON3.PCDDIS    15  Peripheral Clock Driver
SYSCON3.CAN1DIS   13  On-chip CAN Module 1
SYSCON3.SDLMDIS   12  On-chip SDLM (J1850 Module) exists only in the C161JC and C161JI
SYSCON3.IICDIS    11  On-chip IIC Bus Module
SYSCON3.ASC1DIS   10  USART ASC1
SYSCON3.CC2DIS    7   CAPCOM Unit 2
SYSCON3.CC1DIS    6   CAPCOM Unit 1
SYSCON3.GPTDIS    3   General Purpose Timer Blocks
SYSCON3.SSCDIS    2   Synchronous Serial Channel SSC
SYSCON3.ASC0DIS   1   USART ASC0
SYSCON3.ADCDIS    0   Analog/Digital Converter
EXISEL           0xF1DA   External Interrupt Source Select Register
EXISEL.EXI7SS_15  15  External Interrupt 15 Source Selection Field - bit 15
EXISEL.EXI7SS_14  14  External Interrupt 14 Source Selection Field - bit 14
EXISEL.EXI6SS_13  13  External Interrupt 13 Source Selection Field - bit 13
EXISEL.EXI6SS_12  12  External Interrupt 12 Source Selection Field - bit 12
EXISEL.EXI5SS_11  11  External Interrupt 11 Source Selection Field - bit 11
EXISEL.EXI5SS_10  10  External Interrupt 10 Source Selection Field - bit 10
EXISEL.EXI4SS_9   9   External Interrupt 9 Source Selection Field - bit 9 
EXISEL.EXI4SS_8   8   External Interrupt 8 Source Selection Field - bit 8 
EXISEL.EXI3SS_7   7   External Interrupt 7 Source Selection Field - bit 7 
EXISEL.EXI3SS_6   6   External Interrupt 6 Source Selection Field - bit 6 
EXISEL.EXI2SS_5   5   External Interrupt 5 Source Selection Field - bit 5 
EXISEL.EXI2SS_4   4   External Interrupt 4 Source Selection Field - bit 4 
EXISEL.EXI1SS_3   3   External Interrupt 3 Source Selection Field - bit 3 
EXISEL.EXI1SS_2   2   External Interrupt 2 Source Selection Field - bit 2 
EXISEL.EXI0SS_1   1   External Interrupt 1 Source Selection Field - bit 1 
EXISEL.EXI0SS_0   0   External Interrupt 0 Source Selection Field - bit 0 
SYSCON1          0xF1DC   CPU System Configuration Register 1
SYSCON1.SLEEPCON_1 1  SLEEP Mode Configuration - bit 1
SYSCON1.SLEEPCON_0 0  SLEEP Mode Configuration - bit 0
ISNC             0xF1DE   Interrupt Subnode Control Register
ISNC.PLLIE        3   Interrupt Enable Control Bit for Source PLL
ISNC.PLLIR        2   Interrupt Request Flag for Source PLL
ISNC.RTCIE        1   Interrupt Enable Control Bit for Source RTC
ISNC.RTCIR        0   Interrupt Request Flag for Source RTC
RSTCON           0xF1E0   Reset Control Register
RSTCON.CLKCFG_15  15  Clock Generation Mode Configuration - bit 15
RSTCON.CLKCFG_14  14  Clock Generation Mode Configuration - bit 14
RSTCON.CLKCFG_13  13  Clock Generation Mode Configuration - bit 13
RSTCON.SALSEL_12  12  Segment Address Line Selection - bit 12
RSTCON.SALSEL_11  11  Segment Address Line Selection - bit 11
RSTCON.CSSEL_10   10  Chip Select Line Selection - bit 10
RSTCON.CSSEL_9    9   Chip Select Line Selection - bit 9
RSTCON.SUE        8   Software Update Enable
RSTCON.RSTLEN_1   1   Reset Length Control - bit 1
RSTCON.RSTLEN_0   0   Reset Length Control - bit 0
DPP0             0xFE00   CPU Data Page Pointer 0 Register (10 bits)
DPP0.DPP0PN_9     9   Data Page Number of DPP0 - bit 9
DPP0.DPP0PN_8     8   Data Page Number of DPP0 - bit 8
DPP0.DPP0PN_7     7   Data Page Number of DPP0 - bit 7
DPP0.DPP0PN_6     6   Data Page Number of DPP0 - bit 6
DPP0.DPP0PN_5     5   Data Page Number of DPP0 - bit 5
DPP0.DPP0PN_4     4   Data Page Number of DPP0 - bit 4
DPP0.DPP0PN_3     3   Data Page Number of DPP0 - bit 3
DPP0.DPP0PN_2     2   Data Page Number of DPP0 - bit 2
DPP0.DPP0PN_1     1   Data Page Number of DPP0 - bit 1
DPP0.DPP0PN_0     0   Data Page Number of DPP0 - bit 0
DPP1             0xFE02   CPU Data Page Pointer 1 Register (10 bits)
DPP1.DPP1PN_9     9   Data Page Number of DPP1 - bit 9
DPP1.DPP1PN_8     8   Data Page Number of DPP1 - bit 8
DPP1.DPP1PN_7     7   Data Page Number of DPP1 - bit 7
DPP1.DPP1PN_6     6   Data Page Number of DPP1 - bit 6
DPP1.DPP1PN_5     5   Data Page Number of DPP1 - bit 5
DPP1.DPP1PN_4     4   Data Page Number of DPP1 - bit 4
DPP1.DPP1PN_3     3   Data Page Number of DPP1 - bit 3
DPP1.DPP1PN_2     2   Data Page Number of DPP1 - bit 2
DPP1.DPP1PN_1     1   Data Page Number of DPP1 - bit 1
DPP1.DPP1PN_0     0   Data Page Number of DPP1 - bit 0
DPP2             0xFE04   CPU Data Page Pointer 2 Register (10 bits)
DPP2.DPP2PN_9     9   Data Page Number of DPP2 - bit 9
DPP2.DPP2PN_8     8   Data Page Number of DPP2 - bit 8
DPP2.DPP2PN_7     7   Data Page Number of DPP2 - bit 7
DPP2.DPP2PN_6     6   Data Page Number of DPP2 - bit 6
DPP2.DPP2PN_5     5   Data Page Number of DPP2 - bit 5
DPP2.DPP2PN_4     4   Data Page Number of DPP2 - bit 4
DPP2.DPP2PN_3     3   Data Page Number of DPP2 - bit 3
DPP2.DPP2PN_2     2   Data Page Number of DPP2 - bit 2
DPP2.DPP2PN_1     1   Data Page Number of DPP2 - bit 1
DPP2.DPP2PN_0     0   Data Page Number of DPP2 - bit 0
DPP3             0xFE06   CPU Data Page Pointer 3 Register (10 bits)
DPP3.DPP3PN_9     9   Data Page Number of DPP3 - bit 9
DPP3.DPP3PN_8     8   Data Page Number of DPP3 - bit 8
DPP3.DPP3PN_7     7   Data Page Number of DPP3 - bit 7
DPP3.DPP3PN_6     6   Data Page Number of DPP3 - bit 6
DPP3.DPP3PN_5     5   Data Page Number of DPP3 - bit 5
DPP3.DPP3PN_4     4   Data Page Number of DPP3 - bit 4
DPP3.DPP3PN_3     3   Data Page Number of DPP3 - bit 3
DPP3.DPP3PN_2     2   Data Page Number of DPP3 - bit 2
DPP3.DPP3PN_1     1   Data Page Number of DPP3 - bit 1
DPP3.DPP3PN_0     0   Data Page Number of DPP3 - bit 0
CSP              0xFE08   CPU Code Segment Pointer Register (8 bits, not directly writeable)
CSP.SEGNR_7       7   Segment Number - bit 7
CSP.SEGNR_6       6   Segment Number - bit 6
CSP.SEGNR_5       5   Segment Number - bit 5
CSP.SEGNR_4       4   Segment Number - bit 4
CSP.SEGNR_3       3   Segment Number - bit 3
CSP.SEGNR_2       2   Segment Number - bit 2
CSP.SEGNR_1       1   Segment Number - bit 1
CSP.SEGNR_0       0   Segment Number - bit 0
MDH              0xFE0C   CPU Multiply Divide Register ­ High Word
MDH.mdh_15        15
MDH.mdh_14        14
MDH.mdh_13        13
MDH.mdh_12        12
MDH.mdh_11        11
MDH.mdh_10        10
MDH.mdh_9         9 
MDH.mdh_8         8 
MDH.mdh_7         7 
MDH.mdh_6         6 
MDH.mdh_5         5 
MDH.mdh_4         4 
MDH.mdh_3         3 
MDH.mdh_2         2 
MDH.mdh_1         1 
MDH.mdh_0         0 
MDL              0xFE0E   CPU Multiply Divide Register ­ Low Word
MDL.MDL_15        15
MDL.MDL_14        14
MDL.MDL_13        13
MDL.MDL_12        12
MDL.MDL_11        11
MDL.MDL_10        10
MDL.MDL_9         9 
MDL.MDL_8         8 
MDL.MDL_7         7 
MDL.MDL_6         6 
MDL.MDL_5         5 
MDL.MDL_4         4 
MDL.MDL_3         3 
MDL.MDL_2         2 
MDL.MDL_1         1 
MDL.MDL_0         0 
CP               0xFE10   CPU Context Pointer Register
CP.cp_11          11  Modifiable portion of register CP - bit 11
CP.cp_10          10  Modifiable portion of register CP - bit 10
CP.cp_9           9   Modifiable portion of register CP - bit 9
CP.cp_8           8   Modifiable portion of register CP - bit 8
CP.cp_7           7   Modifiable portion of register CP - bit 7
CP.cp_6           6   Modifiable portion of register CP - bit 6
CP.cp_5           5   Modifiable portion of register CP - bit 5
CP.cp_4           4   Modifiable portion of register CP - bit 4
CP.cp_3           3   Modifiable portion of register CP - bit 3
CP.cp_2           2   Modifiable portion of register CP - bit 2
CP.cp_1           1   Modifiable portion of register CP - bit 1
SP               0xFE12   CPU System Stack Pointer Register
SP.sp_11          11  Modifiable portion of register SP - bit 11
SP.sp_10          10  Modifiable portion of register SP - bit 10
SP.sp_9           9   Modifiable portion of register SP - bit 9
SP.sp_8           8   Modifiable portion of register SP - bit 8
SP.sp_7           7   Modifiable portion of register SP - bit 7
SP.sp_6           6   Modifiable portion of register SP - bit 6
SP.sp_5           5   Modifiable portion of register SP - bit 5
SP.sp_4           4   Modifiable portion of register SP - bit 4
SP.sp_3           3   Modifiable portion of register SP - bit 3
SP.sp_2           2   Modifiable portion of register SP - bit 2
SP.sp_1           1   Modifiable portion of register SP - bit 1
STKOV            0xFE14   CPU Stack Overflow Pointer Register
STKOV.stkov_11    11  Modifiable portion of register STKOV - bit 11
STKOV.stkov_10    10  Modifiable portion of register STKOV - bit 10
STKOV.stkov_9     9   Modifiable portion of register STKOV - bit 9
STKOV.stkov_8     8   Modifiable portion of register STKOV - bit 8
STKOV.stkov_7     7   Modifiable portion of register STKOV - bit 7
STKOV.stkov_6     6   Modifiable portion of register STKOV - bit 6
STKOV.stkov_5     5   Modifiable portion of register STKOV - bit 5
STKOV.stkov_4     4   Modifiable portion of register STKOV - bit 4
STKOV.stkov_3     3   Modifiable portion of register STKOV - bit 3
STKOV.stkov_2     2   Modifiable portion of register STKOV - bit 2
STKOV.stkov_1     1   Modifiable portion of register STKOV - bit 1
STKUN            0xFE16   CPU Stack Underflow Pointer Register
STKUN.STKUN_11    11  Modifiable portion of register STKUN - bit 11
STKUN.STKUN_10    10  Modifiable portion of register STKUN - bit 10
STKUN.STKUN_9     9   Modifiable portion of register STKUN - bit 9
STKUN.STKUN_8     8   Modifiable portion of register STKUN - bit 8
STKUN.STKUN_7     7   Modifiable portion of register STKUN - bit 7
STKUN.STKUN_6     6   Modifiable portion of register STKUN - bit 6
STKUN.STKUN_5     5   Modifiable portion of register STKUN - bit 5
STKUN.STKUN_4     4   Modifiable portion of register STKUN - bit 4
STKUN.STKUN_3     3   Modifiable portion of register STKUN - bit 3
STKUN.STKUN_2     2   Modifiable portion of register STKUN - bit 2
STKUN.STKUN_1     1   Modifiable portion of register STKUN - bit 1
ADDRSEL1         0xFE18   Address Select Register 1
ADDRSEL1.RGSAD15  15  Range Start Address bit 15
ADDRSEL1.RGSAD14  14  Range Start Address bit 14
ADDRSEL1.RGSAD13  13  Range Start Address bit 13
ADDRSEL1.RGSAD12  12  Range Start Address bit 12
ADDRSEL1.RGSAD11  11  Range Start Address bit 11
ADDRSEL1.RGSAD10  10  Range Start Address bit 10
ADDRSEL1.RGSAD9   9   Range Start Address bit 9 
ADDRSEL1.RGSAD8   8   Range Start Address bit 8 
ADDRSEL1.RGSAD7   7   Range Start Address bit 7 
ADDRSEL1.RGSAD6   6   Range Start Address bit 6 
ADDRSEL1.RGSAD5   5   Range Start Address bit 5 
ADDRSEL1.RGSAD4   4   Range Start Address bit 4 
ADDRSEL1.RGSZ3    3   Range Size Selection bit 3
ADDRSEL1.RGSZ2    2   Range Size Selection bit 2
ADDRSEL1.RGSZ1    1   Range Size Selection bit 1
ADDRSEL1.RGSZ0    0   Range Size Selection bit 0
ADDRSEL2         0xFE1A   Address Select Register 2
ADDRSEL2.RGSAD15  15  Range Start Address bit 15
ADDRSEL2.RGSAD14  14  Range Start Address bit 14
ADDRSEL2.RGSAD13  13  Range Start Address bit 13
ADDRSEL2.RGSAD12  12  Range Start Address bit 12
ADDRSEL2.RGSAD11  11  Range Start Address bit 11
ADDRSEL2.RGSAD10  10  Range Start Address bit 10
ADDRSEL2.RGSAD9   9   Range Start Address bit 9 
ADDRSEL2.RGSAD8   8   Range Start Address bit 8 
ADDRSEL2.RGSAD7   7   Range Start Address bit 7 
ADDRSEL2.RGSAD6   6   Range Start Address bit 6 
ADDRSEL2.RGSAD5   5   Range Start Address bit 5 
ADDRSEL2.RGSAD4   4   Range Start Address bit 4 
ADDRSEL2.RGSZ3    3   Range Size Selection bit 3
ADDRSEL2.RGSZ2    2   Range Size Selection bit 2
ADDRSEL2.RGSZ1    1   Range Size Selection bit 1
ADDRSEL2.RGSZ0    0   Range Size Selection bit 0
ADDRSEL3         0xFE1C   Address Select Register 3
ADDRSEL3.RGSAD15  15  Range Start Address bit 15
ADDRSEL3.RGSAD14  14  Range Start Address bit 14
ADDRSEL3.RGSAD13  13  Range Start Address bit 13
ADDRSEL3.RGSAD12  12  Range Start Address bit 12
ADDRSEL3.RGSAD11  11  Range Start Address bit 11
ADDRSEL3.RGSAD10  10  Range Start Address bit 10
ADDRSEL3.RGSAD9   9   Range Start Address bit 9 
ADDRSEL3.RGSAD8   8   Range Start Address bit 8 
ADDRSEL3.RGSAD7   7   Range Start Address bit 7 
ADDRSEL3.RGSAD6   6   Range Start Address bit 6 
ADDRSEL3.RGSAD5   5   Range Start Address bit 5 
ADDRSEL3.RGSAD4   4   Range Start Address bit 4 
ADDRSEL3.RGSZ3    3   Range Size Selection bit 3
ADDRSEL3.RGSZ2    2   Range Size Selection bit 2
ADDRSEL3.RGSZ1    1   Range Size Selection bit 1
ADDRSEL3.RGSZ0    0   Range Size Selection bit 0
ADDRSEL4         0xFE1E   Address Select Register 4
ADDRSEL4.RGSAD15  15  Range Start Address bit 15
ADDRSEL4.RGSAD14  14  Range Start Address bit 14
ADDRSEL4.RGSAD13  13  Range Start Address bit 13
ADDRSEL4.RGSAD12  12  Range Start Address bit 12
ADDRSEL4.RGSAD11  11  Range Start Address bit 11
ADDRSEL4.RGSAD10  10  Range Start Address bit 10
ADDRSEL4.RGSAD9   9   Range Start Address bit 9 
ADDRSEL4.RGSAD8   8   Range Start Address bit 8 
ADDRSEL4.RGSAD7   7   Range Start Address bit 7 
ADDRSEL4.RGSAD6   6   Range Start Address bit 6 
ADDRSEL4.RGSAD5   5   Range Start Address bit 5 
ADDRSEL4.RGSAD4   4   Range Start Address bit 4 
ADDRSEL4.RGSZ3    3   Range Size Selection bit 3
ADDRSEL4.RGSZ2    2   Range Size Selection bit 2
ADDRSEL4.RGSZ1    1   Range Size Selection bit 1
ADDRSEL4.RGSZ0    0   Range Size Selection bit 0
T2               0xFE40   GPT1 Timer 2 Register
T3               0xFE42   GPT1 Timer 3 Register
T4               0xFE44   GPT1 Timer 4 Register
T5               0xFE46   GPT2 Timer 5 Register
T6               0xFE48   GPT2 Timer 6 Register
CAPREL           0xFE4A   GPT2 Capture/Reload Register
T0               0xFE50   CAPCOM Timer 0 Register
T1               0xFE52   CAPCOM Timer 1 Register
T0REL            0xFE54   CAPCOM Timer 0 Reload Register
T1REL            0xFE56   CAPCOM Timer 1 Reload Register
CC16             0xFE60   CAPCOM Register 16
CC17             0xFE62   CAPCOM Register 17
CC18             0xFE64   CAPCOM Register 18
CC19             0xFE66   CAPCOM Register 19
CC20             0xFE68   CAPCOM Register 20
CC21             0xFE6A   CAPCOM Register 21
CC22             0xFE6C   CAPCOM Register 22
CC23             0xFE6E   CAPCOM Register 23
CC24             0xFE70   CAPCOM Register 24
CC25             0xFE72   CAPCOM Register 25
CC26             0xFE74   CAPCOM Register 26
CC27             0xFE76   CAPCOM Register 27
CC28             0xFE78   CAPCOM Register 28
CC29             0xFE7A   CAPCOM Register 29
CC30             0xFE7C   CAPCOM Register 30
CC31             0xFE7E   CAPCOM Register 31
CC0              0xFE80   CAPCOM Register 0
CC1              0xFE82   CAPCOM Register 1
CC2              0xFE84   CAPCOM Register 2
CC3              0xFE86   CAPCOM Register 3
CC4              0xFE88   CAPCOM Register 4
CC5              0xFE8A   CAPCOM Register 5
CC6              0xFE8C   CAPCOM Register 6
CC7              0xFE8E   CAPCOM Register 7
CC8              0xFE90   CAPCOM Register 8
CC9              0xFE92   CAPCOM Register 9
CC10             0xFE94   CAPCOM Register 10
CC11             0xFE96   CAPCOM Register 11
CC12             0xFE98   CAPCOM Register 12
CC13             0xFE9A   CAPCOM Register 13
CC14             0xFE9C   CAPCOM Register 14
CC15             0xFE9E   CAPCOM Register 15
ADDAT            0xFEA0   A/D Converter Result Register
ADDAT.CHNR_15     15  Channel Number - bit 15      
ADDAT.CHNR_14     14  Channel Number - bit 14      
ADDAT.CHNR_13     13  Channel Number - bit 13      
ADDAT.CHNR_12     12  Channel Number - bit 12      
ADDAT.ADRES_9     9   A/D Conversion Result - bit 9
ADDAT.ADRES_8     8   A/D Conversion Result - bit 8
ADDAT.ADRES_7     7   A/D Conversion Result - bit 7
ADDAT.ADRES_6     6   A/D Conversion Result - bit 6
ADDAT.ADRES_5     5   A/D Conversion Result - bit 5
ADDAT.ADRES_4     4   A/D Conversion Result - bit 4
ADDAT.ADRES_3     3   A/D Conversion Result - bit 3
ADDAT.ADRES_2     2   A/D Conversion Result - bit 2
ADDAT.ADRES_1     1   A/D Conversion Result - bit 1
ADDAT.ADRES_0     0   A/D Conversion Result - bit 0
P1DIDIS          0xFEA4   PORT1 Digital Input Disable Register
WDT              0xFEAE   Watchdog Timer Register (read only)
S0TBUF           0xFEB0   Serial Channel 0 Transmit Buffer Register
S0RBUF           0xFEB2   Serial Channel 0 Receive Buffer Register (read only)
S0BG             0xFEB4   Serial Channel 0 Baud Rate Generator Reload Register
PECC0            0xFEC0   PEC Channel 0 Control Register             
PECC0.INC_10      10  Increment Control - bit 10
PECC0.INC_9       9   Increment Control - bit 9 
PECC0.BWT         8   Byte/Word Transfer Selection
PECC0.COUNT_7     7    PEC Transfer Count - bit 7
PECC0.COUNT_6     6    PEC Transfer Count - bit 6
PECC0.COUNT_5     5    PEC Transfer Count - bit 5
PECC0.COUNT_4     4    PEC Transfer Count - bit 4
PECC0.COUNT_3     3    PEC Transfer Count - bit 3
PECC0.COUNT_2     2    PEC Transfer Count - bit 2
PECC0.COUNT_1     1    PEC Transfer Count - bit 1
PECC0.COUNT_0     0    PEC Transfer Count - bit 0
PECC1            0xFEC2   PEC Channel 1 Control Register             
PECC1.INC_10      10  Increment Control - bit 10
PECC1.INC_9       9   Increment Control - bit 9 
PECC1.BWT         8   Byte/Word Transfer Selection
PECC1.COUNT_7     7    PEC Transfer Count - bit 7
PECC1.COUNT_6     6    PEC Transfer Count - bit 6
PECC1.COUNT_5     5    PEC Transfer Count - bit 5
PECC1.COUNT_4     4    PEC Transfer Count - bit 4
PECC1.COUNT_3     3    PEC Transfer Count - bit 3
PECC1.COUNT_2     2    PEC Transfer Count - bit 2
PECC1.COUNT_1     1    PEC Transfer Count - bit 1
PECC1.COUNT_0     0    PEC Transfer Count - bit 0
PECC2            0xFEC4   PEC Channel 2 Control Register             
PECC2.INC_10      10  Increment Control - bit 10
PECC2.INC_9       9   Increment Control - bit 9 
PECC2.BWT         8   Byte/Word Transfer Selection
PECC2.COUNT_7     7    PEC Transfer Count - bit 7
PECC2.COUNT_6     6    PEC Transfer Count - bit 6
PECC2.COUNT_5     5    PEC Transfer Count - bit 5
PECC2.COUNT_4     4    PEC Transfer Count - bit 4
PECC2.COUNT_3     3    PEC Transfer Count - bit 3
PECC2.COUNT_2     2    PEC Transfer Count - bit 2
PECC2.COUNT_1     1    PEC Transfer Count - bit 1
PECC2.COUNT_0     0    PEC Transfer Count - bit 0
PECC3            0xFEC6   PEC Channel 3 Control Register             
PECC3.INC_10      10  Increment Control - bit 10
PECC3.INC_9       9   Increment Control - bit 9 
PECC3.BWT         8   Byte/Word Transfer Selection
PECC3.COUNT_7     7    PEC Transfer Count - bit 7
PECC3.COUNT_6     6    PEC Transfer Count - bit 6
PECC3.COUNT_5     5    PEC Transfer Count - bit 5
PECC3.COUNT_4     4    PEC Transfer Count - bit 4
PECC3.COUNT_3     3    PEC Transfer Count - bit 3
PECC3.COUNT_2     2    PEC Transfer Count - bit 2
PECC3.COUNT_1     1    PEC Transfer Count - bit 1
PECC3.COUNT_0     0    PEC Transfer Count - bit 0
PECC4            0xFEC8   PEC Channel 4 Control Register             
PECC4.INC_10      10  Increment Control - bit 10
PECC4.INC_9       9   Increment Control - bit 9 
PECC4.BWT         8   Byte/Word Transfer Selection
PECC4.COUNT_7     7    PEC Transfer Count - bit 7
PECC4.COUNT_6     6    PEC Transfer Count - bit 6
PECC4.COUNT_5     5    PEC Transfer Count - bit 5
PECC4.COUNT_4     4    PEC Transfer Count - bit 4
PECC4.COUNT_3     3    PEC Transfer Count - bit 3
PECC4.COUNT_2     2    PEC Transfer Count - bit 2
PECC4.COUNT_1     1    PEC Transfer Count - bit 1
PECC4.COUNT_0     0    PEC Transfer Count - bit 0
PECC5            0xFECA   PEC Channel 5 Control Register             
PECC5.INC_10      10  Increment Control - bit 10
PECC5.INC_9       9   Increment Control - bit 9 
PECC5.BWT         8   Byte/Word Transfer Selection
PECC5.COUNT_7     7    PEC Transfer Count - bit 7
PECC5.COUNT_6     6    PEC Transfer Count - bit 6
PECC5.COUNT_5     5    PEC Transfer Count - bit 5
PECC5.COUNT_4     4    PEC Transfer Count - bit 4
PECC5.COUNT_3     3    PEC Transfer Count - bit 3
PECC5.COUNT_2     2    PEC Transfer Count - bit 2
PECC5.COUNT_1     1    PEC Transfer Count - bit 1
PECC5.COUNT_0     0    PEC Transfer Count - bit 0
PECC6            0xFECC   PEC Channel 6 Control Register             
PECC6.INC_10      10  Increment Control - bit 10
PECC6.INC_9       9   Increment Control - bit 9 
PECC6.BWT         8   Byte/Word Transfer Selection
PECC6.COUNT_7     7    PEC Transfer Count - bit 7
PECC6.COUNT_6     6    PEC Transfer Count - bit 6
PECC6.COUNT_5     5    PEC Transfer Count - bit 5
PECC6.COUNT_4     4    PEC Transfer Count - bit 4
PECC6.COUNT_3     3    PEC Transfer Count - bit 3
PECC6.COUNT_2     2    PEC Transfer Count - bit 2
PECC6.COUNT_1     1    PEC Transfer Count - bit 1
PECC6.COUNT_0     0    PEC Transfer Count - bit 0
PECC7            0xFECE   PEC Channel 7 Control Register             
PECC7.INC_10      10  Increment Control - bit 10
PECC7.INC_9       9   Increment Control - bit 9 
PECC7.BWT         8   Byte/Word Transfer Selection
PECC7.COUNT_7     7    PEC Transfer Count - bit 7
PECC7.COUNT_6     6    PEC Transfer Count - bit 6
PECC7.COUNT_5     5    PEC Transfer Count - bit 5
PECC7.COUNT_4     4    PEC Transfer Count - bit 4
PECC7.COUNT_3     3    PEC Transfer Count - bit 3
PECC7.COUNT_2     2    PEC Transfer Count - bit 2
PECC7.COUNT_1     1    PEC Transfer Count - bit 1
PECC7.COUNT_0     0    PEC Transfer Count - bit 0
P0L              0xFF00   Port 0 Low Register (Lower half of PORT0)
P0L.P0L7          7   Port data register P0L bit 7
P0L.P0L6          6   Port data register P0L bit 6
P0L.P0L5          5   Port data register P0L bit 5
P0L.P0L4          4   Port data register P0L bit 4
P0L.P0L3          3   Port data register P0L bit 3
P0L.P0L2          2   Port data register P0L bit 2
P0L.P0L1          1   Port data register P0L bit 1
P0L.P0L0          0   Port data register P0L bit 0
P0H              0xFF02   Port 0 High Register (Upper half of PORT0)
P0H.P0H7          7   Port data register P0H bit 7
P0H.P0H6          6   Port data register P0H bit 6
P0H.P0H5          5   Port data register P0H bit 5
P0H.P0H4          4   Port data register P0H bit 4
P0H.P0H3          3   Port data register P0H bit 3
P0H.P0H2          2   Port data register P0H bit 2
P0H.P0H1          1   Port data register P0H bit 1
P0H.P0H0          0   Port data register P0H bit 0
P1L              0xFF04   Port 1 Low Register (Lower half of PORT1)
P1L.P1L7          7   Port data register P1L bit 7
P1L.P1L6          6   Port data register P1L bit 6
P1L.P1L5          5   Port data register P1L bit 5
P1L.P1L4          4   Port data register P1L bit 4
P1L.P1L3          3   Port data register P1L bit 3
P1L.P1L2          2   Port data register P1L bit 2
P1L.P1L1          1   Port data register P1L bit 1
P1L.P1L0          0   Port data register P1L bit 0
P1H              0xFF06   Port 1 High Register (Upper half of PORT1)
P1H.P1H7          7   Port data register P1H bit 7
P1H.P1H6          6   Port data register P1H bit 6
P1H.P1H5          5   Port data register P1H bit 5
P1H.P1H4          4   Port data register P1H bit 4
P1H.P1H3          3   Port data register P1H bit 3
P1H.P1H2          2   Port data register P1H bit 2
P1H.P1H1          1   Port data register P1H bit 1
P1H.P1H0          0   Port data register P1H bit 0
BUSCON0          0xFF0C   Bus Configuration Register 0
BUSCON0.CSWEN0    15  Write Chip Select Enable
BUSCON0.CSREN0    14  Read Chip Select Enable
BUSCON0.RDYEN0    12  READY Input Enable
BUSCON0.BSWC0     11  BUSCON Switch Control
BUSCON0.BUSACT0   10  Bus Active Control
BUSCON0.ALECTL0   9   ALE Lengthening Control
BUSCON0.EWEN0     8   Early Write Enable
BUSCON0.BTYP_7    7   External Bus Configuration - bit 7
BUSCON0.BTYP_6    6   External Bus Configuration - bit 6
BUSCON0.MTTC0     5   Memory Tristate Time Control
BUSCON0.RWDC0     4   Read/Write Delay Control for BUSCON
BUSCON0.MCTC_3    3   Memory Cycle Time Control - bit 3
BUSCON0.MCTC_2    2   Memory Cycle Time Control - bit 2
BUSCON0.MCTC_1    1   Memory Cycle Time Control - bit 1
BUSCON0.MCTC_0    0   Memory Cycle Time Control - bit 0
MDC              0xFF0E   CPU Multiply Divide Control Register
MDC.MDRIU         4   Multiply/Divide Register In Use
PSW              0xFF10   CPU Program Status Word
PSW.ILVL_15       15  Interrupt and EBC Control Field - bit 15
PSW.ILVL_14       14  Interrupt and EBC Control Field - bit 14
PSW.ILVL_13       13  Interrupt and EBC Control Field - bit 13
PSW.ILVL_12       12  Interrupt and EBC Control Field - bit 12
PSW.IEN           11  Interrupt and EBC Control Field
PSW.HLDEN         10  Interrupt and EBC Control Field
PSW.USR0          6   User General Purpose Flag
PSW.MULIP         5   Multiplication/Division In Progress
PSW.E             4   End of Table Flag
PSW.Z             3   Zero F lag
PSW.V             2   Overflow Result
PSW.C             1   Carry Flag
PSW.N             0   Negative Result
SYSCON           0xFF12   CPU System Configuration Register
SYSCON.STKSZ_15   15  System Stack Size - bit 15
SYSCON.STKSZ_14   14  System Stack Size - bit 14
SYSCON.STKSZ_13   13  System Stack Size - bit 13
SYSCON.ROMS1      12  Internal ROM Mapping
SYSCON.SGTDIS     11  Segmentation Disable/Enable Control (Cleared after reset)
SYSCON.ROMEN      10  Internal ROM Enable (Set according to pin EA during reset)
SYSCON.BYTDIS     9   Disable/Enable Control for Pin BHE (Set according to data bus width)
SYSCON.CLKEN      8   System Clock Output Enable (CLKOUT, cleared after reset)
SYSCON.WRCFG      7   Write Configuration Control (Set according to pin P0H.0 during reset)
SYSCON.CSCFG      6   Chip Select Configuration Control (Cleared after reset)
SYSCON.OWDDIS     4   Oscillator Watchdog Disable Bit (Depending on reset configuration)
SYSCON.BDRSTEN    3   Bidirectional Reset Enable Bit
SYSCON.XPEN       2   Peripheral Enable Bit
SYSCON.VISIBLE    1   Visible Mode Control
SYSCON.XPER_SHARE 0   XBUS Peripheral Share Mode Control
BUSCON1          0xFF14   Bus Configuration Register 1
BUSCON1.CSWEN1    15  Write Chip Select Enable
BUSCON1.CSREN1    14  Read Chip Select Enable
BUSCON1.RDYEN1    12  READY Input Enable
BUSCON1.BSWC1     11  BUSCON Switch Control
BUSCON1.BUSACT1   10  Bus Active Control
BUSCON1.ALECTL1   9   ALE Lengthening Control
BUSCON1.EWEN1     8   Early Write Enable
BUSCON1.BTYP_7    7   External Bus Configuration - bit 7
BUSCON1.BTYP_6    6   External Bus Configuration - bit 6
BUSCON1.MTTC1     5   Memory Tristate Time Control
BUSCON1.RWDC1     4   Read/Write Delay Control for BUSCON
BUSCON1.MCTC_3    3   Memory Cycle Time Control - bit 3
BUSCON1.MCTC_2    2   Memory Cycle Time Control - bit 2
BUSCON1.MCTC_1    1   Memory Cycle Time Control - bit 1
BUSCON1.MCTC_0    0   Memory Cycle Time Control - bit 0
BUSCON2          0xFF16   Bus Configuration Register 2
BUSCON2.CSWEN2    15  Write Chip Select Enable
BUSCON2.CSREN2    14  Read Chip Select Enable
BUSCON2.RDYEN2    12  READY Input Enable
BUSCON2.BSWC2     11  BUSCON Switch Control
BUSCON2.BUSACT2   10  Bus Active Control
BUSCON2.ALECTL2   9   ALE Lengthening Control
BUSCON2.EWEN2     8   Early Write Enable
BUSCON2.BTYP_7    7   External Bus Configuration - bit 7
BUSCON2.BTYP_6    6   External Bus Configuration - bit 6
BUSCON2.MTTC2     5   Memory Tristate Time Control
BUSCON2.RWDC2     4   Read/Write Delay Control for BUSCON
BUSCON2.MCTC_3    3   Memory Cycle Time Control - bit 3
BUSCON2.MCTC_2    2   Memory Cycle Time Control - bit 2
BUSCON2.MCTC_1    1   Memory Cycle Time Control - bit 1
BUSCON2.MCTC_0    0   Memory Cycle Time Control - bit 0
BUSCON3          0xFF18   Bus Configuration Register 3
BUSCON3.CSWEN3    15  Write Chip Select Enable
BUSCON3.CSREN3    14  Read Chip Select Enable
BUSCON3.RDYEN3    12  READY Input Enable
BUSCON3.BSWC3     11  BUSCON Switch Control
BUSCON3.BUSACT3   10  Bus Active Control
BUSCON3.ALECTL3   9   ALE Lengthening Control
BUSCON3.EWEN3     8   Early Write Enable
BUSCON3.BTYP_7    7   External Bus Configuration - bit 7
BUSCON3.BTYP_6    6   External Bus Configuration - bit 6
BUSCON3.MTTC3     5   Memory Tristate Time Control
BUSCON3.RWDC3     4   Read/Write Delay Control for BUSCON
BUSCON3.MCTC_3    3   Memory Cycle Time Control - bit 3
BUSCON3.MCTC_2    2   Memory Cycle Time Control - bit 2
BUSCON3.MCTC_1    1   Memory Cycle Time Control - bit 1
BUSCON3.MCTC_0    0   Memory Cycle Time Control - bit 0
BUSCON4          0xFF1A   Bus Configuration Register 4
BUSCON4.CSWEN4    15  Write Chip Select Enable
BUSCON4.CSREN4    14  Read Chip Select Enable
BUSCON4.RDYEN4    12  READY Input Enable
BUSCON4.BSWC4     11  BUSCON Switch Control
BUSCON4.BUSACT4   10  Bus Active Control
BUSCON4.ALECTL4   9   ALE Lengthening Control
BUSCON4.EWEN4     8   Early Write Enable
BUSCON4.BTYP_7    7   External Bus Configuration - bit 7
BUSCON4.BTYP_6    6   External Bus Configuration - bit 6
BUSCON4.MTTC4     5   Memory Tristate Time Control
BUSCON4.RWDC4     4   Read/Write Delay Control for BUSCON
BUSCON4.MCTC_3    3   Memory Cycle Time Control - bit 3
BUSCON4.MCTC_2    2   Memory Cycle Time Control - bit 2
BUSCON4.MCTC_1    1   Memory Cycle Time Control - bit 1
BUSCON4.MCTC_0    0   Memory Cycle Time Control - bit 0
ZEROS            0xFF1C   Constant Value 0's Register (read only)
ONES             0xFF1E   Constant Value 1's Register (read only)
T78CON           0xFF20   CAPCOM Timer 7 and 8 Control Register      
T78CON.T8R        14  Timer/Counter 8 Run Control
T78CON.T8M        11  Timer/Counter 8 Mode Selection
T78CON.T8I_10     10  Timer/Counter 8 Input Selection - bit 10
T78CON.T8I_9      9   Timer/Counter 8 Input Selection - bit 9 
T78CON.T8I_8      8   Timer/Counter 8 Input Selection - bit 8 
T78CON.T7R        6   Timer/Counter 7 Run Control
T78CON.T7M        3   Timer/Counter 7 Mode Selection
T78CON.T7I_2      2   Timer/Counter 7 Input Selection - bit 2
T78CON.T7I_1      1   Timer/Counter 7 Input Selection - bit 1
T78CON.T7I_0      0   Timer/Counter 7 Input Selection - bit 0
CCM4             0xFF22   CAPCOM Mode Control Register 4
CCM4.ACC19        15  Allocation Bit for Capture/Compare Register CC4
CCM4.CCMOD19_14   14  Mode Selection for Capture/Compare Register CC4 bit 14
CCM4.CCMOD19_13   13  Mode Selection for Capture/Compare Register CC4 bit 13
CCM4.CCMOD19_12   12  Mode Selection for Capture/Compare Register CC4 bit 12
CCM4.ACC18        11  Allocation Bit for Capture/Compare Register CC4       
CCM4.CCMOD18_10   10  Mode Selection for Capture/Compare Register CC4 bit 10
CCM4.CCMOD18_9    9   Mode Selection for Capture/Compare Register CC4 bit 9 
CCM4.CCMOD18_8    8   Mode Selection for Capture/Compare Register CC4 bit 8 
CCM4.ACC17        7   Allocation Bit for Capture/Compare Register CC4       
CCM4.CCMOD17_6    6   Mode Selection for Capture/Compare Register CC4 bit 6 
CCM4.CCMOD17_5    5   Mode Selection for Capture/Compare Register CC4 bit 5 
CCM4.CCMOD17_4    4   Mode Selection for Capture/Compare Register CC4 bit 4 
CCM4.ACC16        3   Allocation Bit for Capture/Compare Register CC4       
CCM4.CCMOD16_2    2   Mode Selection for Capture/Compare Register CC4 bit 2 
CCM4.CCMOD16_1    1   Mode Selection for Capture/Compare Register CC4 bit 1 
CCM4.CCMOD16_0    0   Mode Selection for Capture/Compare Register CC4 bit 0 
CCM5             0xFF24 CAPCOM Mode Control Register 5
CCM5.ACC23        15  Allocation Bit for Capture/Compare Register CC4       
CCM5.CCMOD23_14   14  Mode Selection for Capture/Compare Register CC4 bit 14
CCM5.CCMOD23_13   13  Mode Selection for Capture/Compare Register CC4 bit 13
CCM5.CCMOD23_12   12  Mode Selection for Capture/Compare Register CC4 bit 12
CCM5.ACC22        11  Allocation Bit for Capture/Compare Register CC4       
CCM5.CCMOD22_10   10  Mode Selection for Capture/Compare Register CC4 bit 10
CCM5.CCMOD22_9    9   Mode Selection for Capture/Compare Register CC4 bit 9 
CCM5.CCMOD22_8    8   Mode Selection for Capture/Compare Register CC4 bit 8 
CCM5.ACC21        7   Allocation Bit for Capture/Compare Register CC4       
CCM5.CCMOD21_6    6   Mode Selection for Capture/Compare Register CC4 bit 6 
CCM5.CCMOD21_5    5   Mode Selection for Capture/Compare Register CC4 bit 5 
CCM5.CCMOD21_4    4   Mode Selection for Capture/Compare Register CC4 bit 4 
CCM5.ACC20        3   Allocation Bit for Capture/Compare Register CC4       
CCM5.CCMOD20_2    2   Mode Selection for Capture/Compare Register CC4 bit 2 
CCM5.CCMOD20_1    1   Mode Selection for Capture/Compare Register CC4 bit 1 
CCM5.CCMOD20_0    0   Mode Selection for Capture/Compare Register CC4 bit 0 
CCM6             0xFF26 CAPCOM Mode Control Register 6
CCM6.ACC27        15  Allocation Bit for Capture/Compare Register CC4       
CCM6.CCMOD27_14   14  Mode Selection for Capture/Compare Register CC4 bit 14
CCM6.CCMOD27_13   13  Mode Selection for Capture/Compare Register CC4 bit 13
CCM6.CCMOD27_12   12  Mode Selection for Capture/Compare Register CC4 bit 12
CCM6.ACC26        11  Allocation Bit for Capture/Compare Register CC4       
CCM6.CCMOD26_10   10  Mode Selection for Capture/Compare Register CC4 bit 10
CCM6.CCMOD26_9    9   Mode Selection for Capture/Compare Register CC4 bit 9 
CCM6.CCMOD26_8    8   Mode Selection for Capture/Compare Register CC4 bit 8 
CCM6.ACC25        7   Allocation Bit for Capture/Compare Register CC4       
CCM6.CCMOD25_6    6   Mode Selection for Capture/Compare Register CC4 bit 6 
CCM6.CCMOD25_5    5   Mode Selection for Capture/Compare Register CC4 bit 5 
CCM6.CCMOD25_4    4   Mode Selection for Capture/Compare Register CC4 bit 4 
CCM6.ACC24        3   Allocation Bit for Capture/Compare Register CC4       
CCM6.CCMOD24_2    2   Mode Selection for Capture/Compare Register CC4 bit 2 
CCM6.CCMOD24_1    1   Mode Selection for Capture/Compare Register CC4 bit 1 
CCM6.CCMOD24_0    0   Mode Selection for Capture/Compare Register CC4 bit 0 
CCM7             0xFF28 CAPCOM Mode Control Register 7
CCM7.ACC31        15  Allocation Bit for Capture/Compare Register CC4       
CCM7.CCMOD31_14   14  Mode Selection for Capture/Compare Register CC4 bit 14
CCM7.CCMOD31_13   13  Mode Selection for Capture/Compare Register CC4 bit 13
CCM7.CCMOD31_12   12  Mode Selection for Capture/Compare Register CC4 bit 12
CCM7.ACC30        11  Allocation Bit for Capture/Compare Register CC4       
CCM7.CCMOD30_10   10  Mode Selection for Capture/Compare Register CC4 bit 10
CCM7.CCMOD30_9    9   Mode Selection for Capture/Compare Register CC4 bit 9 
CCM7.CCMOD30_8    8   Mode Selection for Capture/Compare Register CC4 bit 8 
CCM7.ACC29        7   Allocation Bit for Capture/Compare Register CC4       
CCM7.CCMOD29_6    6   Mode Selection for Capture/Compare Register CC4 bit 6 
CCM7.CCMOD29_5    5   Mode Selection for Capture/Compare Register CC4 bit 5 
CCM7.CCMOD29_4    4   Mode Selection for Capture/Compare Register CC4 bit 4 
CCM7.ACC28        3   Allocation Bit for Capture/Compare Register CC4       
CCM7.CCMOD28_2    2   Mode Selection for Capture/Compare Register CC4 bit 2 
CCM7.CCMOD28_1    1   Mode Selection for Capture/Compare Register CC4 bit 1 
CCM7.CCMOD28_0    0   Mode Selection for Capture/Compare Register CC4 bit 0 
T2CON            0xFF40   GPT1 Timer 2 Control Register
T2CON.T2OTL       10  Timer 2 Output Toggle Latch
T2CON.T2OE        9   Alternate Output Function Enable
T2CON.T2UDE       8   Timer 2 External Up/Down Enable
T2CON.T2UD        7   Timer 2 Up / Down Control
T2CON.T2R         6   Timer 2 Run Bit
T2CON.T2M_5       5   Timer 2 Mode Control - bit 5
T2CON.T2M_4       4   Timer 2 Mode Control - bit 4
T2CON.T2M_3       3   Timer 2 Mode Control - bit 3
T2CON.T2I_2       2   Timer 2 Input Selection - bit 2
T2CON.T2I_1       1   Timer 2 Input Selection - bit 1
T2CON.T2I_0       0   Timer 2 Input Selection - bit 0
T3CON            0xFF42   GPT1 Timer 3 Control Register
T3CON.T3OTL       10  Timer 3 Output Toggle Latch
T3CON.T3OE        9   Alternate Output Function Enable
T3CON.T3UDE       8   Timer 3 External Up/Down Enable
T3CON.T3UD        7   Timer 3 Up / Down Control
T3CON.T3R         6   Timer 3 Run Bit
T3CON.T3M_5       5   Timer 3 Mode Control - bit 5
T3CON.T3M_4       4   Timer 3 Mode Control - bit 4
T3CON.T3M_3       3   Timer 3 Mode Control - bit 3
T3CON.T3I_2       2   Timer 3 Input Selection - bit 2
T3CON.T3I_1       1   Timer 3 Input Selection - bit 1
T3CON.T3I_0       0   Timer 3 Input Selection - bit 0
T4CON            0xFF44   GPT1 Timer 4 Control Register
T4CON.T4OTL       10  Timer 4 Output Toggle Latch
T4CON.T4OE        9   Alternate Output Function Enable
T4CON.T4UDE       8   Timer 4 External Up/Down Enable
T4CON.T4UD        7   Timer 4 Up / Down Control
T4CON.T4R         6   Timer 4 Run Bit
T4CON.T4M_5       5   Timer 4 Mode Control - bit 5
T4CON.T4M_4       4   Timer 4 Mode Control - bit 4
T4CON.T4M_3       3   Timer 4 Mode Control - bit 3
T4CON.T4I_2       2   Timer 4 Input Selection - bit 2
T4CON.T4I_1       1   Timer 4 Input Selection - bit 1
T4CON.T4I_0       0   Timer 4 Input Selection - bit 0
T5CON            0xFF46   GPT2 Timer 5 Control Register
T5CON.T5SR        15  Timer 5 Reload Mode Enable
T5CON.T5CLR       14  Timer 5 Clear Bit
T5CON.CI_13       13  Register CAPREL Capture Trigger Selection - bit 13
T5CON.CI_12       12  Register CAPREL Capture Trigger Selection - bit 12
T5CON.CT3         10  Timer 3 Capture Trigger Enable
T5CON.T5UD        7   Timer 5 Up / Down Control
T5CON.T5R         6   Timer 5 Run Bit
T5CON.T5M_5       5   Timer 5 Mode Control - bit 5
T5CON.T5M_4       4   Timer 5 Mode Control - bit 4
T5CON.T5M_3       3   Timer 5 Mode Control - bit 3
T5CON.T5I_2       2   Timer 5 Input Selection - bit 2
T5CON.T5I_1       1   Timer 5 Input Selection - bit 1
T5CON.T5I_0       0   Timer 5 Input Selection - bit 0
T6CON            0xFF48   GPT2 Timer 6 Control Register
T6CON.T6SR        15  Timer 6 Reload Mode Enable
T6CON.T6OTL       10  Timer 6 Output Toggle Latch
T6CON.T6OE        9   Alternate Output Function Enable
T6CON.T6UD        7   Timer 6 Up / Down Control
T6CON.T6R         6   Timer 6 Run Bit
T6CON.T6M_5       5   Timer 6 Mode Control - bit 5
T6CON.T6M_4       4   Timer 6 Mode Control - bit 4
T6CON.T6M_3       3   Timer 6 Mode Control - bit 3
T6CON.T6I_2       2   Timer 6 Input Selection - bit 2
T6CON.T6I_1       1   Timer 6 Input Selection - bit 1
T6CON.T6I_0       0   Timer 6 Input Selection - bit 0
T01CON           0xFF50   CAPCOM Timer 0 and Timer 1 Ctrl. Reg.
T01CON.T1R        14  Timer/Counter 1 Run Control
T01CON.T1M        11  Timer/Counter 1 Mode Selection
T01CON.T1I_10     10  Timer/Counter 1 Input Selection - bit 10
T01CON.T1I_9      9   Timer/Counter 1 Input Selection - bit 9 
T01CON.T1I_8      8   Timer/Counter 1 Input Selection - bit 8 
T01CON.T0R        6   Timer/Counter 0 Run Control
T01CON.T0M        3   Timer/Counter 0 Mode Selection
T01CON.T0I_2      2   Timer/Counter 0 Input Selection - bit 2
T01CON.T0I_1      1   Timer/Counter 0 Input Selection - bit 1
T01CON.T0I_0      0   Timer/Counter 0 Input Selection - bit 0
CCM0             0xFF52   CAPCOM Mode Control Register 0
CCM0.ACC3         15  Allocation Bit for Capture/Compare Register CC0       
CCM0.CCMOD3_14    14  Mode Selection for Capture/Compare Register CC0 bit 14
CCM0.CCMOD3_13    13  Mode Selection for Capture/Compare Register CC0 bit 13
CCM0.CCMOD3_12    12  Mode Selection for Capture/Compare Register CC0 bit 12
CCM0.ACC2         11  Allocation Bit for Capture/Compare Register CC0       
CCM0.CCMOD2_10    10  Mode Selection for Capture/Compare Register CC0 bit 10
CCM0.CCMOD2_9     9   Mode Selection for Capture/Compare Register CC0 bit 9 
CCM0.CCMOD2_8     8   Mode Selection for Capture/Compare Register CC0 bit 8 
CCM0.ACC1         7   Allocation Bit for Capture/Compare Register CC0       
CCM0.CCMOD1_6     6   Mode Selection for Capture/Compare Register CC0 bit 6 
CCM0.CCMOD1_5     5   Mode Selection for Capture/Compare Register CC0 bit 5 
CCM0.CCMOD1_4     4   Mode Selection for Capture/Compare Register CC0 bit 4 
CCM0.ACC0         3   Allocation Bit for Capture/Compare Register CC0       
CCM0.CCMOD0_2     2   Mode Selection for Capture/Compare Register CC0 bit 2 
CCM0.CCMOD0_1     1   Mode Selection for Capture/Compare Register CC0 bit 1 
CCM0.CCMOD0_0     0   Mode Selection for Capture/Compare Register CC0 bit 0 
CCM1             0xFF54   CAPCOM Mode Control Register 1
CCM1.ACC7         15  Allocation Bit for Capture/Compare Register CC1       
CCM1.CCMOD7_14    14  Mode Selection for Capture/Compare Register CC1 bit 14
CCM1.CCMOD7_13    13  Mode Selection for Capture/Compare Register CC1 bit 13
CCM1.CCMOD7_12    12  Mode Selection for Capture/Compare Register CC1 bit 12
CCM1.ACC6         11  Allocation Bit for Capture/Compare Register CC1       
CCM1.CCMOD6_10    10  Mode Selection for Capture/Compare Register CC1 bit 10
CCM1.CCMOD6_9     9   Mode Selection for Capture/Compare Register CC1 bit 9 
CCM1.CCMOD6_8     8   Mode Selection for Capture/Compare Register CC1 bit 8 
CCM1.ACC5         7   Allocation Bit for Capture/Compare Register CC1       
CCM1.CCMOD5_6     6   Mode Selection for Capture/Compare Register CC1 bit 6 
CCM1.CCMOD5_5     5   Mode Selection for Capture/Compare Register CC1 bit 5 
CCM1.CCMOD5_4     4   Mode Selection for Capture/Compare Register CC1 bit 4 
CCM1.ACC4         3   Allocation Bit for Capture/Compare Register CC1       
CCM1.CCMOD4_2     2   Mode Selection for Capture/Compare Register CC1 bit 2 
CCM1.CCMOD4_1     1   Mode Selection for Capture/Compare Register CC1 bit 1 
CCM1.CCMOD4_0     0   Mode Selection for Capture/Compare Register CC1 bit 0 
CCM2             0xFF56 CAPCOM Mode Control Register 2
CCM2.ACC11        15  Allocation Bit for Capture/Compare Register CC2
CCM2.CCMOD11_14   14  Mode Selection for Capture/Compare Register CC2 bit 14
CCM2.CCMOD11_13   13  Mode Selection for Capture/Compare Register CC2 bit 13
CCM2.CCMOD11_12   12  Mode Selection for Capture/Compare Register CC2 bit 12
CCM2.ACC10        11  Allocation Bit for Capture/Compare Register CC2     
CCM2.CCMOD10_10   10  Mode Selection for Capture/Compare Register CC2 bit 10
CCM2.CCMOD10_9    9   Mode Selection for Capture/Compare Register CC2 bit 9 
CCM2.CCMOD10_8    8   Mode Selection for Capture/Compare Register CC2 bit 8 
CCM2.ACC9         7   Allocation Bit for Capture/Compare Register CC2     
CCM2.CCMOD9_6     6   Mode Selection for Capture/Compare Register CC2 bit 6
CCM2.CCMOD9_5     5   Mode Selection for Capture/Compare Register CC2 bit 5
CCM2.CCMOD9_4     4   Mode Selection for Capture/Compare Register CC2 bit 4
CCM2.ACC8         3   Allocation Bit for Capture/Compare Register CC2      
CCM2.CCMOD8_2     2   Mode Selection for Capture/Compare Register CC2 bit 2
CCM2.CCMOD8_1     1   Mode Selection for Capture/Compare Register CC2 bit 1
CCM2.CCMOD8_0     0   Mode Selection for Capture/Compare Register CC2 bit 0
CCM3             0xFF58 CAPCOM Mode Control Register 3
CCM3.ACC15        15  Allocation Bit for Capture/Compare Register CC3       
CCM3.CCMOD15_14   14  Mode Selection for Capture/Compare Register CC3 bit 14
CCM3.CCMOD15_13   13  Mode Selection for Capture/Compare Register CC3 bit 13
CCM3.CCMOD15_12   12  Mode Selection for Capture/Compare Register CC3 bit 12
CCM3.ACC14        11  Allocation Bit for Capture/Compare Register CC3       
CCM3.CCMOD14_10   10  Mode Selection for Capture/Compare Register CC3 bit 10
CCM3.CCMOD14_9    9   Mode Selection for Capture/Compare Register CC3 bit 9 
CCM3.CCMOD14_8    8   Mode Selection for Capture/Compare Register CC3 bit 8 
CCM3.ACC13        7   Allocation Bit for Capture/Compare Register CC3       
CCM3.CCMOD13_6    6   Mode Selection for Capture/Compare Register CC3 bit 6 
CCM3.CCMOD13_5    5   Mode Selection for Capture/Compare Register CC3 bit 5 
CCM3.CCMOD13_4    4   Mode Selection for Capture/Compare Register CC3 bit 4 
CCM3.ACC12        3   Allocation Bit for Capture/Compare Register CC3       
CCM3.CCMOD12_2    2   Mode Selection for Capture/Compare Register CC3 bit 2 
CCM3.CCMOD12_1    1   Mode Selection for Capture/Compare Register CC3 bit 1 
CCM3.CCMOD12_0    0   Mode Selection for Capture/Compare Register CC3 bit 0 
T2IC             0xFF60   GPT1 Timer 2 Interrupt Control Register
T2IC.T2IR         7   Interrupt Request Flag
T2IC.T2IE         6   Interrupt Enable Control Bit (individually enables/disables a specific source)
T2IC.ILVL_5       5   Interrupt Priority Level - bit 5
T2IC.ILVL_4       4   Interrupt Priority Level - bit 4
T2IC.ILVL_3       3   Interrupt Priority Level - bit 3
T2IC.ILVL_2       2   Interrupt Priority Level - bit 2
T2IC.GLVL_1       1   Group Level - bit 1
T2IC.GLVL_0       0   Group Level - bit 0
T3IC             0xFF62   GPT1 Timer 3 Interrupt Control Register
T3IC.T3IR         7   Interrupt Request Flag
T3IC.T3IE         6   Interrupt Enable Control Bit (individually enables/disables a specific source)
T3IC.ILVL_5       5   Interrupt Priority Level - bit 5
T3IC.ILVL_4       4   Interrupt Priority Level - bit 4
T3IC.ILVL_3       3   Interrupt Priority Level - bit 3
T3IC.ILVL_2       2   Interrupt Priority Level - bit 2
T3IC.GLVL_1       1   Group Level - bit 1
T3IC.GLVL_0       0   Group Level - bit 0
T4IC             0xFF64   GPT1 Timer 4 Interrupt Control Register
T4IC.T4IR         7   Interrupt Request Flag
T4IC.T4IE         6   Interrupt Enable Control Bit (individually enables/disables a specific source)
T4IC.ILVL_5       5   Interrupt Priority Level - bit 5
T4IC.ILVL_4       4   Interrupt Priority Level - bit 4
T4IC.ILVL_3       3   Interrupt Priority Level - bit 3
T4IC.ILVL_2       2   Interrupt Priority Level - bit 2
T4IC.GLVL_1       1   Group Level - bit 1
T4IC.GLVL_0       0   Group Level - bit 0
T5IC             0xFF66   GPT2 Timer 5 Interrupt Control Register
T5IC.T5IR         7   Interrupt Request Flag
T5IC.T5IE         6   Interrupt Enable Control Bit (individually enables/disables a specific source)
T5IC.ILVL_5       5   Interrupt Priority Level - bit 5
T5IC.ILVL_4       4   Interrupt Priority Level - bit 4
T5IC.ILVL_3       3   Interrupt Priority Level - bit 3
T5IC.ILVL_2       2   Interrupt Priority Level - bit 2
T5IC.GLVL_1       1   Group Level - bit 1
T5IC.GLVL_0       0   Group Level - bit 0
T6IC             0xFF68   GPT2 Timer 6 Interrupt Control Register
T6IC.T2IR         7   Interrupt Request Flag
T6IC.T2IE         6   Interrupt Enable Control Bit (individually enables/disables a specific source)
T6IC.ILVL_5       5   Interrupt Priority Level - bit 5
T6IC.ILVL_4       4   Interrupt Priority Level - bit 4
T6IC.ILVL_3       3   Interrupt Priority Level - bit 3
T6IC.ILVL_2       2   Interrupt Priority Level - bit 2
T6IC.GLVL_1       1   Group Level - bit 1
T6IC.GLVL_0       0   Group Level - bit 0
CRIC             0xFF6A   GPT2 CAPREL Interrupt Control Register
CRIC.CRIR         7   Interrupt Request Flag
CRIC.CRIE         6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CRIC.ILVL_5       5   Interrupt Priority Level - bit 5
CRIC.ILVL_4       4   Interrupt Priority Level - bit 4
CRIC.ILVL_3       3   Interrupt Priority Level - bit 3
CRIC.ILVL_2       2   Interrupt Priority Level - bit 2
CRIC.GLVL_1       1   Group Level - bit 1
CRIC.GLVL_0       0   Group Level - bit 0
S0TIC            0xFF6C   Serial Channel 0 Transmit Interrupt Control Register
S0TIC.S0TIR       7   Interrupt Request Flag
S0TIC.S0TIE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
S0TIC.ILVL_5      5   Interrupt Priority Level - bit 5
S0TIC.ILVL_4      4   Interrupt Priority Level - bit 4
S0TIC.ILVL_3      3   Interrupt Priority Level - bit 3
S0TIC.ILVL_2      2   Interrupt Priority Level - bit 2
S0TIC.GLVL_1      1   Group Level - bit 1
S0TIC.GLVL_0      0   Group Level - bit 0
S0RIC            0xFF6E   Serial Channel 0 Receive Interrupt Control Register
S0RIC.S0RIR       7   Interrupt Request Flag
S0RIC.S0RIE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
S0RIC.ILVL_5      5   Interrupt Priority Level - bit 5
S0RIC.ILVL_4      4   Interrupt Priority Level - bit 4
S0RIC.ILVL_3      3   Interrupt Priority Level - bit 3
S0RIC.ILVL_2      2   Interrupt Priority Level - bit 2
S0RIC.GLVL_1      1   Group Level - bit 1
S0RIC.GLVL_0      0   Group Level - bit 0
S0EIC            0xFF70   Serial Channel 0 Error Interrupt Control Register
S0EIC.S0EIR       7   Interrupt Request Flag
S0EIC.S0EIE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
S0EIC.ILVL_5      5   Interrupt Priority Level - bit 5
S0EIC.ILVL_4      4   Interrupt Priority Level - bit 4
S0EIC.ILVL_3      3   Interrupt Priority Level - bit 3
S0EIC.ILVL_2      2   Interrupt Priority Level - bit 2
S0EIC.GLVL_1      1   Group Level - bit 1
S0EIC.GLVL_0      0   Group Level - bit 0
SSCTIC           0xFF72   SSC Transmit Interrupt Control Register
SSCTIC.SSCTIR     7   Interrupt Request Flag
SSCTIC.SSCTIE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
SSCTIC.ILVL_5     5   Interrupt Priority Level - bit 5
SSCTIC.ILVL_4     4   Interrupt Priority Level - bit 4
SSCTIC.ILVL_3     3   Interrupt Priority Level - bit 3
SSCTIC.ILVL_2     2   Interrupt Priority Level - bit 2
SSCTIC.GLVL_1     1   Group Level - bit 1
SSCTIC.GLVL_0     0   Group Level - bit 0
SSCRIC           0xFF74   SSC Receive Interrupt Control Register
SSCRIC.SSCRIR     7   Interrupt Request Flag
SSCRIC.SSCRIE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
SSCRIC.ILVL_5     5   Interrupt Priority Level - bit 5
SSCRIC.ILVL_4     4   Interrupt Priority Level - bit 4
SSCRIC.ILVL_3     3   Interrupt Priority Level - bit 3
SSCRIC.ILVL_2     2   Interrupt Priority Level - bit 2
SSCRIC.GLVL_1     1   Group Level - bit 1
SSCRIC.GLVL_0     0   Group Level - bit 0
SSCEIC           0xFF76   SSC Error Interrupt Control Register
SSCEIC.SSCEIR     7   Interrupt Request Flag
SSCEIC.SSCEIE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
SSCEIC.ILVL_5     5   Interrupt Priority Level - bit 5
SSCEIC.ILVL_4     4   Interrupt Priority Level - bit 4
SSCEIC.ILVL_3     3   Interrupt Priority Level - bit 3
SSCEIC.ILVL_2     2   Interrupt Priority Level - bit 2
SSCEIC.GLVL_1     1   Group Level - bit 1
SSCEIC.GLVL_0     0   Group Level - bit 0
CC0IC            0xFF78   CAPCOM Register 0 Interrupt Ctrl. Reg.
CC0IC.CC0IR       7   Interrupt Request Flag
CC0IC.CC0IE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC0IC.ILVL_5      5   Interrupt Priority Level - bit 5
CC0IC.ILVL_4      4   Interrupt Priority Level - bit 4
CC0IC.ILVL_3      3   Interrupt Priority Level - bit 3
CC0IC.ILVL_2      2   Interrupt Priority Level - bit 2
CC0IC.GLVL_1      1   Group Level - bit 1
CC0IC.GLVL_0      0   Group Level - bit 0
CC1IC            0xFF7A   CAPCOM Register 1 Interrupt Ctrl. Reg.
CC1IC.CC1IR       7   Interrupt Request Flag
CC1IC.CC1IE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC1IC.ILVL_5      5   Interrupt Priority Level - bit 5
CC1IC.ILVL_4      4   Interrupt Priority Level - bit 4
CC1IC.ILVL_3      3   Interrupt Priority Level - bit 3
CC1IC.ILVL_2      2   Interrupt Priority Level - bit 2
CC1IC.GLVL_1      1   Group Level - bit 1
CC1IC.GLVL_0      0   Group Level - bit 0
CC2IC            0xFF7C   CAPCOM Register 2 Interrupt Ctrl. Reg.
CC2IC.CC2IR       7   Interrupt Request Flag
CC2IC.CC2IE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC2IC.ILVL_5      5   Interrupt Priority Level - bit 5
CC2IC.ILVL_4      4   Interrupt Priority Level - bit 4
CC2IC.ILVL_3      3   Interrupt Priority Level - bit 3
CC2IC.ILVL_2      2   Interrupt Priority Level - bit 2
CC2IC.GLVL_1      1   Group Level - bit 1
CC2IC.GLVL_0      0   Group Level - bit 0
CC3IC            0xFF7E   CAPCOM Register 3 Interrupt Ctrl. Reg.
CC3IC.CC3IR       7   Interrupt Request Flag
CC3IC.CC3IE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC3IC.ILVL_5      5   Interrupt Priority Level - bit 5
CC3IC.ILVL_4      4   Interrupt Priority Level - bit 4
CC3IC.ILVL_3      3   Interrupt Priority Level - bit 3
CC3IC.ILVL_2      2   Interrupt Priority Level - bit 2
CC3IC.GLVL_1      1   Group Level - bit 1
CC3IC.GLVL_0      0   Group Level - bit 0
CC4IC            0xFF80   CAPCOM Register 4 Interrupt Ctrl. Reg.
CC4IC.CC4IR       7   Interrupt Request Flag
CC4IC.CC4IE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC4IC.ILVL_5      5   Interrupt Priority Level - bit 5
CC4IC.ILVL_4      4   Interrupt Priority Level - bit 4
CC4IC.ILVL_3      3   Interrupt Priority Level - bit 3
CC4IC.ILVL_2      2   Interrupt Priority Level - bit 2
CC4IC.GLVL_1      1   Group Level - bit 1
CC4IC.GLVL_0      0   Group Level - bit 0
CC5IC            0xFF82   CAPCOM Register 5 Interrupt Ctrl. Reg.
CC5IC.CC5IR       7   Interrupt Request Flag
CC5IC.CC5IE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC5IC.ILVL_5      5   Interrupt Priority Level - bit 5
CC5IC.ILVL_4      4   Interrupt Priority Level - bit 4
CC5IC.ILVL_3      3   Interrupt Priority Level - bit 3
CC5IC.ILVL_2      2   Interrupt Priority Level - bit 2
CC5IC.GLVL_1      1   Group Level - bit 1
CC5IC.GLVL_0      0   Group Level - bit 0
CC6IC            0xFF84   CAPCOM Register 6 Interrupt Ctrl. Reg.
CC6IC.CC6IR       7   Interrupt Request Flag
CC6IC.CC6IE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC6IC.ILVL_5      5   Interrupt Priority Level - bit 5
CC6IC.ILVL_4      4   Interrupt Priority Level - bit 4
CC6IC.ILVL_3      3   Interrupt Priority Level - bit 3
CC6IC.ILVL_2      2   Interrupt Priority Level - bit 2
CC6IC.GLVL_1      1   Group Level - bit 1
CC6IC.GLVL_0      0   Group Level - bit 0
CC7IC            0xFF86   CAPCOM Register 7 Interrupt Ctrl. Reg.
CC7IC.CC7IR       7   Interrupt Request Flag
CC7IC.CC7IE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC7IC.ILVL_5      5   Interrupt Priority Level - bit 5
CC7IC.ILVL_4      4   Interrupt Priority Level - bit 4
CC7IC.ILVL_3      3   Interrupt Priority Level - bit 3
CC7IC.ILVL_2      2   Interrupt Priority Level - bit 2
CC7IC.GLVL_1      1   Group Level - bit 1
CC7IC.GLVL_0      0   Group Level - bit 0
CC8IC            0xFF88   CAPCOM Register 8 Interrupt Ctrl. Reg.
CC8IC.CC8IR       7   Interrupt Request Flag
CC8IC.CC8IE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC8IC.ILVL_5      5   Interrupt Priority Level - bit 5
CC8IC.ILVL_4      4   Interrupt Priority Level - bit 4
CC8IC.ILVL_3      3   Interrupt Priority Level - bit 3
CC8IC.ILVL_2      2   Interrupt Priority Level - bit 2
CC8IC.GLVL_1      1   Group Level - bit 1
CC8IC.GLVL_0      0   Group Level - bit 0
CC9IC            0xFF8A   CAPCOM Register 9 Interrupt Ctrl. Reg.
CC9IC.CC9IR       7   Interrupt Request Flag
CC9IC.CC9IE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC9IC.ILVL_5      5   Interrupt Priority Level - bit 5
CC9IC.ILVL_4      4   Interrupt Priority Level - bit 4
CC9IC.ILVL_3      3   Interrupt Priority Level - bit 3
CC9IC.ILVL_2      2   Interrupt Priority Level - bit 2
CC9IC.GLVL_1      1   Group Level - bit 1
CC9IC.GLVL_0      0   Group Level - bit 0
CC10IC           0xFF8C   CAPCOM Register 10 Interrupt Ctrl. Reg.
CC10IC.CC10IR     7   Interrupt Request Flag
CC10IC.CC10IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC10IC.ILVL_5     5   Interrupt Priority Level - bit 5
CC10IC.ILVL_4     4   Interrupt Priority Level - bit 4
CC10IC.ILVL_3     3   Interrupt Priority Level - bit 3
CC10IC.ILVL_2     2   Interrupt Priority Level - bit 2
CC10IC.GLVL_1     1   Group Level - bit 1
CC10IC.GLVL_0     0   Group Level - bit 0
CC11IC           0xFF8E   CAPCOM Register 11 Interrupt Ctrl. Reg.
CC11IC.CC11IR     7   Interrupt Request Flag
CC11IC.CC11IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC11IC.ILVL_5     5   Interrupt Priority Level - bit 5
CC11IC.ILVL_4     4   Interrupt Priority Level - bit 4
CC11IC.ILVL_3     3   Interrupt Priority Level - bit 3
CC11IC.ILVL_2     2   Interrupt Priority Level - bit 2
CC11IC.GLVL_1     1   Group Level - bit 1
CC11IC.GLVL_0     0   Group Level - bit 0
CC12IC           0xFF90   CAPCOM Register 12 Interrupt Ctrl. Reg.
CC12IC.CC12IR     7   Interrupt Request Flag
CC12IC.CC12IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC12IC.ILVL_5     5   Interrupt Priority Level - bit 5
CC12IC.ILVL_4     4   Interrupt Priority Level - bit 4
CC12IC.ILVL_3     3   Interrupt Priority Level - bit 3
CC12IC.ILVL_2     2   Interrupt Priority Level - bit 2
CC12IC.GLVL_1     1   Group Level - bit 1
CC12IC.GLVL_0     0   Group Level - bit 0
CC13IC           0xFF92   CAPCOM Register 13 Interrupt Ctrl. Reg.
CC13IC.CC13IR     7   Interrupt Request Flag
CC13IC.CC13IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC13IC.ILVL_5     5   Interrupt Priority Level - bit 5
CC13IC.ILVL_4     4   Interrupt Priority Level - bit 4
CC13IC.ILVL_3     3   Interrupt Priority Level - bit 3
CC13IC.ILVL_2     2   Interrupt Priority Level - bit 2
CC13IC.GLVL_1     1   Group Level - bit 1
CC13IC.GLVL_0     0   Group Level - bit 0
CC14IC           0xFF94   CAH CAPCOM Register 14 Interrupt Ctrl. Reg.
CC14IC.CC14IR     7   Interrupt Request Flag
CC14IC.CC14IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC14IC.ILVL_5     5   Interrupt Priority Level - bit 5
CC14IC.ILVL_4     4   Interrupt Priority Level - bit 4
CC14IC.ILVL_3     3   Interrupt Priority Level - bit 3
CC14IC.ILVL_2     2   Interrupt Priority Level - bit 2
CC14IC.GLVL_1     1   Group Level - bit 1
CC14IC.GLVL_0     0   Group Level - bit 0
CC15IC           0xFF96   CBH CAPCOM Register 15 Interrupt Ctrl. Reg.
CC15IC.CC15IR     7   Interrupt Request Flag
CC15IC.CC15IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC15IC.ILVL_5     5   Interrupt Priority Level - bit 5
CC15IC.ILVL_4     4   Interrupt Priority Level - bit 4
CC15IC.ILVL_3     3   Interrupt Priority Level - bit 3
CC15IC.ILVL_2     2   Interrupt Priority Level - bit 2
CC15IC.GLVL_1     1   Group Level - bit 1
CC15IC.GLVL_0     0   Group Level - bit 0
ADCIC            0xFF98   CCH A/D Converter End of Conversion Interrupt Control Register
ADCIC.ADCIR       7   Interrupt Request Flag
ADCIC.ADCIE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
ADCIC.ILVL_5      5   Interrupt Priority Level - bit 5
ADCIC.ILVL_4      4   Interrupt Priority Level - bit 4
ADCIC.ILVL_3      3   Interrupt Priority Level - bit 3
ADCIC.ILVL_2      2   Interrupt Priority Level - bit 2
ADCIC.GLVL_1      1   Group Level - bit 1
ADCIC.GLVL_0      0   Group Level - bit 0
ADEIC            0xFF9A   CDH A/D Converter Overrun Error Interrupt Control Register
ADEIC.ADEIR       7   Interrupt Request Flag
ADEIC.ADEIE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
ADEIC.ILVL_5      5   Interrupt Priority Level - bit 5
ADEIC.ILVL_4      4   Interrupt Priority Level - bit 4
ADEIC.ILVL_3      3   Interrupt Priority Level - bit 3
ADEIC.ILVL_2      2   Interrupt Priority Level - bit 2
ADEIC.GLVL_1      1   Group Level - bit 1
ADEIC.GLVL_0      0   Group Level - bit 0
T0IC             0xFF9C   CEH CAPCOM Timer 0 Interrupt Ctrl. Reg.
T0IC.T0IR         7   Interrupt Request Flag
T0IC.T0IE         6   Interrupt Enable Control Bit (individually enables/disables a specific source)
T0IC.ILVL_5       5   Interrupt Priority Level - bit 5
T0IC.ILVL_4       4   Interrupt Priority Level - bit 4
T0IC.ILVL_3       3   Interrupt Priority Level - bit 3
T0IC.ILVL_2       2   Interrupt Priority Level - bit 2
T0IC.GLVL_1       1   Group Level - bit 1
T0IC.GLVL_0       0   Group Level - bit 0
T1IC             0xFF9E   CFH CAPCOM Timer 1 Interrupt Ctrl. Reg.
T1IC.T1IR         7   Interrupt Request Flag
T1IC.T1IE         6   Interrupt Enable Control Bit (individually enables/disables a specific source)
T1IC.ILVL_5       5   Interrupt Priority Level - bit 5
T1IC.ILVL_4       4   Interrupt Priority Level - bit 4
T1IC.ILVL_3       3   Interrupt Priority Level - bit 3
T1IC.ILVL_2       2   Interrupt Priority Level - bit 2
T1IC.GLVL_1       1   Group Level - bit 1
T1IC.GLVL_0       0   Group Level - bit 0
ADCON            0xFFA0   A/D Converter Control Register
ADCON.ADCTC_15    15  ADC Conversion Time Control - bit 15
ADCON.ADCTC_14    14  ADC Conversion Time Control - bit 14
ADCON.ADSTC_13    13  ADC Sample Time Control - bit 13
ADCON.ADSTC_12    12  ADC Sample Time Control - bit 12
ADCON.ADCRQ       11  ADC Channel Injection Request Flag
ADCON.ADCIN       10  ADC Channel Injection Enable
ADCON.ADWR        9   ADC Wait for Read Control
ADCON.ADBSY       8   ADC Busy Flag
ADCON.ADST        7   ADC Start Bit
ADCON.ADM_5       5   ADC Mode Selection - bit 5
ADCON.ADM_4       4   ADC Mode Selection - bit 4
ADCON.ADCH_3      3   ADC Analog Channel Input Selection - bit 3
ADCON.ADCH_2      2   ADC Analog Channel Input Selection - bit 2
ADCON.ADCH_1      1   ADC Analog Channel Input Selection - bit 1
ADCON.ADCH_0      0   ADC Analog Channel Input Selection - bit 0
P5               0xFFA2   Port 5 Register (read only)
P5.P5_15          15  Port data register P5 bit 15
P5.P5_14          14  Port data register P5 bit 14
P5.P5_13          13  Port data register P5 bit 13
P5.P5_12          12  Port data register P5 bit 12
P5.P5_7           7   Port data register P5 bit 7 
P5.P5_6           6   Port data register P5 bit 6 
P5.P5_5           5   Port data register P5 bit 5 
P5.P5_4           4   Port data register P5 bit 4 
P5.P5_3           3   Port data register P5 bit 3 
P5.P5_2           2   Port data register P5 bit 2 
P5.P5_1           1   Port data register P5 bit 1 
P5.P5_0           0   Port data register P5 bit 0 
P5DIDIS          0xFFA4   Port 5 Digital Input Disable Register
P5DIDIS.P5D_15    15  Port 5 Bit 15 Digital Input Control
P5DIDIS.P5D_14    14  Port 5 Bit 14 Digital Input Control
P5DIDIS.P5D_13    13  Port 5 Bit 13 Digital Input Control
P5DIDIS.P5D_12    12  Port 5 Bit 12 Digital Input Control
P5DIDIS.P5D_7     7   Port 5 Bit 7  Digital Input Control
P5DIDIS.P5D_6     6   Port 5 Bit 6  Digital Input Control
P5DIDIS.P5D_5     5   Port 5 Bit 5  Digital Input Control
P5DIDIS.P5D_4     4   Port 5 Bit 4  Digital Input Control
P5DIDIS.P5D_3     3   Port 5 Bit 3  Digital Input Control
P5DIDIS.P5D_2     2   Port 5 Bit 2  Digital Input Control
P5DIDIS.P5D_1     1   Port 5 Bit 1  Digital Input Control
P5DIDIS.P5D_0     0   Port 5 Bit 0  Digital Input Control
FOCON            0xFFAA   Frequency Output Control Register
FOCON.FOEN        15  Frequency Output Enable
FOCON.FOSS        14  Frequency Output Signal Select
FOCON.FORV_13     13  Frequency Output Reload Value - bit 13
FOCON.FORV_12     12  Frequency Output Reload Value - bit 12
FOCON.FORV_11     11  Frequency Output Reload Value - bit 11
FOCON.FORV_10     10  Frequency Output Reload Value - bit 10
FOCON.FORV_9      9   Frequency Output Reload Value - bit 9 
FOCON.FORV_8      8   Frequency Output Reload Value - bit 8 
FOCON.FOTL        6   Frequency Output Toggle Latch
FOCON.FOCNT_5     5   Frequency Output Counter - bit 5
FOCON.FOCNT_4     4   Frequency Output Counter - bit 4
FOCON.FOCNT_3     3   Frequency Output Counter - bit 3
FOCON.FOCNT_2     2   Frequency Output Counter - bit 2
FOCON.FOCNT_1     1   Frequency Output Counter - bit 1
FOCON.FOCNT_0     0   Frequency Output Counter - bit 0
TFR              0xFFAC   Trap Flag Register
TFR.NMI           15  Non Maskable Interrupt Flag
TFR.STKOF         14  Stack Overflow Flag
TFR.STKUF         13  Stack Underflow Flag
TFR.UNDOPC        7   Undefined Opcode Flag
TFR.PRTFLT        3   Protection Fault Flag
TFR.ILLOPA        2   Illegal Word Operand Access Flag
TFR.ILLINA        1   Illegal Instruction Access Flag
TFR.ILLBUS        0   Illegal External Bus Access Flag
WDTCON           0xFFAE   Watchdog Timer Control Register      
WDTCON.WDTREL_15  15  Watchdog Timer Reload Value - bit 15
WDTCON.WDTREL_14  14  Watchdog Timer Reload Value - bit 14
WDTCON.WDTREL_13  13  Watchdog Timer Reload Value - bit 13
WDTCON.WDTREL_12  12  Watchdog Timer Reload Value - bit 12
WDTCON.WDTREL_11  11  Watchdog Timer Reload Value - bit 11
WDTCON.WDTREL_10  10  Watchdog Timer Reload Value - bit 10
WDTCON.WDTREL_9   9   Watchdog Timer Reload Value - bit 9 
WDTCON.WDTREL_8   8   Watchdog Timer Reload Value - bit 8 
WDTCON.WDTPRE     7   Watchdog Timer Input Prescaler Control
WDTCON.LHWR       4   Long Hardware Reset Indication Flag
WDTCON.SHWR       3   Short Hardware Reset Indication Flag
WDTCON.SWR        2   Software Reset Indication Flag
WDTCON.WDTR       1   Watchdog Timer Reset Indication Flag
WDTCON.WDTIN      0   Watchdog Timer Input Frequency Select
S0CON            0xFFB0   Serial Channel 0 Control Register    
S0CON.S0R         15  Baudrate Generator Run Bit
S0CON.S0LB        14  LoopBack Mode Enable Bit
S0CON.S0BRS       13  Baudrate Selection Bit
S0CON.S0ODD       12  Parity Selection Bit
S0CON.S0OE        10  Overrun Error Flag
S0CON.S0FE        9   Framing Error Flag
S0CON.S0PE        8   Parity Error Flag
S0CON.S0OEN       7   Overrun Check Enable Bit
S0CON.S0FEN       6   Framing Check Enable Bit
S0CON.S0PEN       5   Parity Check Enable Bit
S0CON.S0REN       4   Receiver Enable Bit
S0CON.S0STP       3   Number of Stop Bits Selection
S0CON.S0M_2       2   ASC0 Mode Control - bit 2
S0CON.S0M_1       1   ASC0 Mode Control - bit 1
S0CON.S0M_0       0   ASC0 Mode Control - bit 0
SSCCON           0xFFB2   SSC Control Register                 
P2               0xFFC0   Port 2 Register
P2.P2_15          15  Port data register P2 bit 15
P2.P2_14          14  Port data register P2 bit 14
P2.P2_13          13  Port data register P2 bit 13
P2.P2_12          12  Port data register P2 bit 12
P2.P2_11          11  Port data register P2 bit 11
P2.P2_10          10  Port data register P2 bit 10
P2.P2_9           9   Port data register P2 bit 9 
P2.P2_8           8   Port data register P2 bit 8 
DP2              0xFFC2   Port 2 Direction Control Register
DP2.DP2_15        15  Port direction register DP2 bit 15
DP2.DP2_14        14  Port direction register DP2 bit 14
DP2.DP2_13        13  Port direction register DP2 bit 13
DP2.DP2_12        12  Port direction register DP2 bit 12
DP2.DP2_11        11  Port direction register DP2 bit 11
DP2.DP2_10        10  Port direction register DP2 bit 10
DP2.DP2_9         9   Port direction register DP2 bit 9 
DP2.DP2_8         8   Port direction register DP2 bit 8 
P3               0xFFC4   Port 3 Register
P3.P3_15          15  Port data register P3 bit 15
P3.P3_13          13  Port data register P3 bit 13
P3.P3_12          12  Port data register P3 bit 12
P3.P3_11          11  Port data register P3 bit 11
P3.P3_10          10  Port data register P3 bit 10
P3.P3_9           9   Port data register P3 bit 9 
P3.P3_8           8   Port data register P3 bit 8 
P3.P3_7           7   Port data register P3 bit 7 
P3.P3_6           6   Port data register P3 bit 6 
P3.P3_5           5   Port data register P3 bit 5 
P3.P3_4           4   Port data register P3 bit 4 
P3.P3_3           3   Port data register P3 bit 3 
P3.P3_2           2   Port data register P3 bit 2 
P3.P3_1           1   Port data register P3 bit 1 
P3.P3_0           0   Port data register P3 bit 0 
DP3              0xFFC6   Port 3 Direction Control Register
DP3.DP3_15        15  Port direction register DP3 bit 15
DP3.DP3_13        13  Port direction register DP3 bit 13
DP3.DP3_12        12  Port direction register DP3 bit 12
DP3.DP3_11        11  Port direction register DP3 bit 11
DP3.DP3_10        10  Port direction register DP3 bit 10
DP3.DP3_9         9   Port direction register DP3 bit 9 
DP3.DP3_8         8   Port direction register DP3 bit 8 
DP3.DP3_7         7   Port direction register DP3 bit 7 
DP3.DP3_6         6   Port direction register DP3 bit 6 
DP3.DP3_5         5   Port direction register DP3 bit 5 
DP3.DP3_4         4   Port direction register DP3 bit 4 
DP3.DP3_3         3   Port direction register DP3 bit 3 
DP3.DP3_2         2   Port direction register DP3 bit 2 
DP3.DP3_1         1   Port direction register DP3 bit 1 
DP3.DP3_0         0   Port direction register DP3 bit 0 
P4               0xFFC8   Port 4 Register (7 bits)
P4.P4_7           7   Port data register P4 bit 7 
P4.P4_6           6   Port data register P4 bit 6 
P4.P4_5           5   Port data register P4 bit 5 
P4.P4_4           4   Port data register P4 bit 4 
P4.P4_3           3   Port data register P4 bit 3 
P4.P4_2           2   Port data register P4 bit 2 
P4.P4_1           1   Port data register P4 bit 1 
P4.P4_0           0   Port data register P4 bit 0 
DP4              0xFFCA   Port 4 Direction Control Register
DP4.DP4_7         7   Port direction register DP4 bit 7 
DP4.DP4_6         6   Port direction register DP4 bit 6 
DP4.DP4_5         5   Port direction register DP4 bit 5 
DP4.DP4_4         4   Port direction register DP4 bit 4 
DP4.DP4_3         3   Port direction register DP4 bit 3 
DP4.DP4_2         2   Port direction register DP4 bit 2 
DP4.DP4_1         1   Port direction register DP4 bit 1 
DP4.DP4_0         0   Port direction register DP4 bit 0 
P6               0xFFCC   Port 6 Register (8 bits)
P6.P6_7           7   Port data register P6 bit 7 
P6.P6_6           6   Port data register P6 bit 6 
P6.P6_5           5   Port data register P6 bit 5 
P6.P6_4           4   Port data register P6 bit 4 
P6.P6_3           3   Port data register P6 bit 3 
P6.P6_2           2   Port data register P6 bit 2 
P6.P6_1           1   Port data register P6 bit 1 
P6.P6_0           0   Port data register P6 bit 0 
DP6              0xFFCE   Port 6 Direction Control Register
DP6.DP6_7         7   Port direction register DP6 bit 7 
DP6.DP6_6         6   Port direction register DP6 bit 6 
DP6.DP6_5         5   Port direction register DP6 bit 5 
DP6.DP6_4         4   Port direction register DP6 bit 4 
DP6.DP6_3         3   Port direction register DP6 bit 3 
DP6.DP6_2         2   Port direction register DP6 bit 2 
DP6.DP6_1         1   Port direction register DP6 bit 1 
DP6.DP6_0         0   Port direction register DP6 bit 0 
P7               0xFFD0   Port 7 Register (8 bits)
P7.P7_7           7   Port data register P7 bit 7 
P7.P7_6           6   Port data register P7 bit 6 
P7.P7_5           5   Port data register P7 bit 5 
P7.P7_4           4   Port data register P7 bit 4 
DP7              0xFFD2   Port 7 Direction Control Register
DP7.DP7_7         7   Port direction register DP7 bit 7 
DP7.DP7_6         6   Port direction register DP7 bit 6 
DP7.DP7_5         5   Port direction register DP7 bit 5 
DP7.DP7_4         4   Port direction register DP7 bit 4 
P9               0xFFD8   Port 9 Register (8 bits)
P9.P9_5           5   Port data register P9 bit 5 
P9.P9_4           4   Port data register P9 bit 4 
P9.P9_3           3   Port data register P9 bit 3 
P9.P9_2           2   Port data register P9 bit 2 
P9.P9_1           1   Port data register P9 bit 1 
P9.P9_0           0   Port data register P9 bit 0 
DP9              0xFFDA   Port 9 Direction Control Register
DP9.DP9_5         5   Port direction register DP9 bit 5 
DP9.DP9_4         4   Port direction register DP9 bit 4 
DP9.DP9_3         3   Port direction register DP9 bit 3 
DP9.DP9_2         2   Port direction register DP9 bit 2 
DP9.DP9_1         1   Port direction register DP9 bit 1 
DP9.DP9_0         0   Port direction register DP9 bit 0 


.C161JI
; http://www.infineon.com/cgi/ecrm.dll/ecrm/scripts/public_download.jsp?oid=18695&parent_oid=13740


; MEMORY MAP
area DATA ROM_           0x0000:0x8000   Internal ROM Area
area DATA MEM_EXT        0x8000:0xC000   External Memory
area DATA XRAM           0xC000:0xE000
area BSS  RESERVED       0xE000:0xEB00
area DATA SDLM_          0xEB00:0xEC00
area BSS  RESERVED       0xEC00:0xED00
area DATA IIC_ASC1       0xED00:0xEE00   IIC/ASC1
area BSS  RESERVED       0xEE00:0xEF00
area DATA CAN1_          0xEF00:0xF000
area DATA ESFR_          0xF000:0xF200   ESFR Area
area BSS  RESERVED       0xF200:0xF600   
area DATA IRAM_          0xF600:0xFE00   IRAM
area DATA SFR_           0xFE00:0x10000  SFR Area


; Interrupt and reset vector assignments
entry RESET     0x0000    RESET
entry NMITRAP   0x0008    NMITRAP Non-Maskable Interrupt (Class A Hardware Traps)
entry STOTRAP   0x0010    STOTRAP Stack Overflow (Class A Hardware Traps)
entry STUTRAP   0x0018    STUTRAP Stack Underflow (Class A Hardware Traps)
entry BTRAP     0x0028    BTRAP Class B Hardware Traps
entry CC0INT    0x0040    CAPCOM Register 0
entry CC1INT    0x0044    CAPCOM Register 1
entry CC2INT    0x0048    CAPCOM Register 2
entry CC3INT    0x004C    CAPCOM Register 3
entry CC4INT    0x0050    CAPCOM Register 4
entry CC5INT    0x0054    CAPCOM Register 5
entry CC6INT    0x0058    CAPCOM Register 6
entry CC7INT    0x005C    CAPCOM Register 7
entry CC8INT    0x0060    CAPCOM Register 8
entry CC9INT    0x0064    CAPCOM Register 9
entry CC10INT   0x0068    CAPCOM Register 10
entry CC11INT   0x006C    CAPCOM Register 11
entry CC12INT   0x0070    CAPCOM Register 12
entry CC13INT   0x0074    CAPCOM Register 13
entry CC14INT   0x0078    CAPCOM Register 14
entry CC15INT   0x007C    CAPCOM Register 15
entry T0INT     0x0080    CAPCOM Timer 0
entry T1INT     0x0084    CAPCOM Timer 1
entry T2INT     0x0088    GPT1 Timer 2
entry T3INT     0x008C    GPT1 Timer 3
entry T4INT     0x0090    GPT1 Timer 4
entry T5INT     0x0094    GPT2 Timer 5
entry T6INT     0x0098    GPT2 Timer 6
entry CRINT     0x009C    GPT2 CAPREL Register
entry ADCINT    0x00A0    A/D Conversion Complete
entry ADEINT    0x00A4    A/D Overrun Error
entry S0TINT    0x00A8    ASC0 Transmit
entry S0RINT    0x00AC    ASC0 Receive
entry S0EINT    0x00B0    ASC0 Error
entry SCTINT    0x00B4    SSC Transmit
entry SCRINT    0x00B8    SSC Receive
entry SCEINT    0x00BC    SSC Error
entry CC16INT   0x00C0    CAPCOM Register 16
entry CC17INT   0x00C4    CAPCOM Register 17
entry CC18INT   0x00C8    CAPCOM Register 18
entry CC19INT   0x00CC    CAPCOM Register 19
entry CC20INT   0x00D0    CAPCOM Register 20
entry CC21INT   0x00D4    CAPCOM Register 21
entry CC22INT   0x00D8    CAPCOM Register 22
entry CC23INT   0x00DC    CAPCOM Register 23
entry CC24INT   0x00E0    CAPCOM Register 24
entry CC25INT   0x00E4    CAPCOM Register 25
entry CC26INT   0x00E8    CAPCOM Register 26
entry CC27INT   0x00EC    CAPCOM Register 27
entry CC28INT   0x00F0    CAPCOM Register 28
entry T7INT     0x00F4    CAPCOM Timer 7
entry T8INT     0x00F8    CAPCOM Timer 8
entry XP0INT    0x0100    IIC Data Transfer Event
entry XP1INT    0x0104    IIC Protocol Event
entry XP3INT    0x010C    PLL/RTC (via ISNC)
entry CC29INT   0x0110    CAPCOM Register 29
entry CC30INT   0x0114    CAPCOM Register 30
entry CC31INT   0x0118    CAPCOM Register 31
entry S0TBINT   0x011C    ASC0 Transmit Buffer
entry XP4INT    0x0120    ASC1 Transmit
entry XP5INT    0x0124    ASC1 Receive
entry XP6INT    0x0128    ASC1 Error
entry XP7INT    0x012C    SDLM (C161JC/JI)


; INPUT/OUTPUT PORTS
IPCR             0xEB04   SDLM Interface Port Connect Register           
IPCR.IPC_2        2   Interface Port Connection - bit 2
IPCR.IPC_1        1   Interface Port Connection - bit 1
IPCR.IPC_0        0   Interface Port Connection - bit 0
GLOBCON          0xEB10   SDLM Global Control Register                   
GLOBCON.ARIFR     6   Automatic Retry of IFR
GLOBCON.OVWR      5   Overwrite Enable
GLOBCON.NB        4   Normalization Bit Polarity
GLOBCON.HDT       3   Header Type
GLOBCON.BMEN      2   Block Mode Enable
GLOBCON.EN4X      1   High Speed Transfer Enable (4x)
GLOBCON.GMEN      0   Global Module Enable
CLKDIV           0xEB14   SDLM Clock Divider Register                    
CLKDIV.CLKEN      7   Clock Enable
CLKDIV.CLKSEL     6   Clock Select
CLKDIV.CD_5       5   Clock Divider - bit 5
CLKDIV.CD_4       4   Clock Divider - bit 4
CLKDIV.CD_3       3   Clock Divider - bit 3
CLKDIV.CD_2       2   Clock Divider - bit 2
CLKDIV.CD_1       1   Clock Divider - bit 1
CLKDIV.CD_0       0   Clock Divider - bit 0
TxDELAY          0xEB16   SDLM Trabsceiver Delay Register                
TxDELAY.RINV      6   Invert Receive Input
TxDELAY.TD_5      5   Transceiver Delay - bit 5
TxDELAY.TD_4      4   Transceiver Delay - bit 4
TxDELAY.TD_3      3   Transceiver Delay - bit 3
TxDELAY.TD_2      2   Transceiver Delay - bit 2
TxDELAY.TD_1      1   Transceiver Delay - bit 1
TxDELAY.TD_0      0   Transceiver Delay - bit 0
IFR              0xEB18   SDLM In-Frame Response Value Register          
IFR.IFRVAL_7      7   In-Frame Response Value - bit 7
IFR.IFRVAL_6      6   In-Frame Response Value - bit 6
IFR.IFRVAL_5      5   In-Frame Response Value - bit 5
IFR.IFRVAL_4      4   In-Frame Response Value - bit 4
IFR.IFRVAL_3      3   In-Frame Response Value - bit 3
IFR.IFRVAL_2      2   In-Frame Response Value - bit 2
IFR.IFRVAL_1      1   In-Frame Response Value - bit 1
IFR.IFRVAL_0      0   In-Frame Response Value - bit 0
BUFFSTAT         0xEB1C   SDLM Buffer Status Register                    
BUFFSTAT.RBC      4   Receive Buffer on CPU Side Full
BUFFSTAT.RBB      3   Receive Buffer on Bus Side Full
BUFFSTAT.MSGLST   2   Message Lost
BUFFSTAT.RIP      1   Reception in Progress
BUFFSTAT.TIP      0   Transmission In Progress
TRANSSTAT        0xEB1E   SDLM Transmission Status Register              
TRANSSTAT.Y       7   Y Bit in 3 Byte Consolidated Headers
TRANSSTAT.K       6   K Bit in 3 Byte Consolidated Headers
TRANSSTAT.H       5   H Bit in Consolidated Headers
TRANSSTAT.ARL     4   Arbitration Lost
TRANSSTAT.BREAK   3   Break Received
TRANSSTAT.HEADER  2   Header Received
TRANSSTAT.MSGREC  1   Message Received
TRANSSTAT.MSGTRA  0   Message Transmitted
BUSSTAT          0xEB20   SDLM Bus Status Register                       
BUSSTAT.IDLE      3   Bus Idle
BUSSTAT.ENDF      2   End Of Frame Detected
BUSSTAT.EOD       1   End Of Data Detected
BUSSTAT.SOF       0   Start Of Frame Detected
ERRSTAT          0xEB22   SDLM Error Status Register                     
ERRSTAT.CRCER     4   CRC Error
ERRSTAT.COL       3   Collision Detected (lost arbitration)
ERRSTAT.SHORTH    2   Bus Shorted High
ERRSTAT.SHORTL    1   Bus Shorted Low
ERRSTAT.FORMAT    0   Format Error
BUFFCON          0xEB24   SDLM Buffer Control Register                   
BUFFCON.RXINCE    7   Receive Buffer Increment Enable
BUFFCON.TXINCE    6   Transmit Buffer Increment Enable
BUFFCON.IFREN     5   In-Frame Response Enable
BUFFCON.CRCEN     4   CRC Enable
BUFFCON.SBRK      3   Send Break
BUFFCON.DONE      2   Receive Buffer on CPU Side Read Out Done
BUFFCON.TXRQ      1   Transmit Request
BUFFCON.TXIFR     0   Transmit In-Frame Response
FLAGRST          0xEB28   SDLM Flag Reset Register                       
FLAGRST.ERRST     5   Reset Error
FLAGRST.BUSRST    4   Reset Bus Status
FLAGRST.RXRST     3   Reset Buffer Status
FLAGRST.TXRST     2   Reset Buffer Status
FLAGRST.ARLRST    1   Reset Buffer Status
FLAGRST.BRKRST    0   Reset Buffer Status
INTCON           0xEB2C   SDLM Interrupt Control Register                
INTCON.ERRIE      7   Enable Error Interrupt
INTCON.CRCIE      6   Enable CRC Error Interrupt
INTCON.ARLIE      5   Enable Arbitration Lost Interrupt
INTCON.BRKIE      4   Enable Break Received Interrupt
INTCON.ENDFIE     3   Enable End of Frame Detection
INTCON.HDIE       2   Enable Header Received Interrupt
INTCON.RECIE      1   Enable Receive Interrupt
INTCON.TRAIE      0   Enable Transmit Interrupt
TXD0             0xEB30   SDLM Transmit Data Register 0 
TXD0.TXDATA1_15   15  Transmit Buffer Data Byte 1 - bit 15
TXD0.TXDATA1_14   14  Transmit Buffer Data Byte 1 - bit 14
TXD0.TXDATA1_13   13  Transmit Buffer Data Byte 1 - bit 13
TXD0.TXDATA1_12   12  Transmit Buffer Data Byte 1 - bit 12
TXD0.TXDATA1_11   11  Transmit Buffer Data Byte 1 - bit 11
TXD0.TXDATA1_10   10  Transmit Buffer Data Byte 1 - bit 10
TXD0.TXDATA1_9    9   Transmit Buffer Data Byte 1 - bit 9 
TXD0.TXDATA1_8    8   Transmit Buffer Data Byte 1 - bit 8 
TXD0.TXDATA0_7    7   Transmit Buffer Data Byte 0 - bit 7 
TXD0.TXDATA0_6    6   Transmit Buffer Data Byte 0 - bit 6 
TXD0.TXDATA0_5    5   Transmit Buffer Data Byte 0 - bit 5 
TXD0.TXDATA0_4    4   Transmit Buffer Data Byte 0 - bit 4 
TXD0.TXDATA0_3    3   Transmit Buffer Data Byte 0 - bit 3 
TXD0.TXDATA0_2    2   Transmit Buffer Data Byte 0 - bit 2 
TXD0.TXDATA0_1    1   Transmit Buffer Data Byte 0 - bit 1 
TXD0.TXDATA0_0    0   Transmit Buffer Data Byte 0 - bit 0 
TXD2             0xEB32   SDLM Transmit Data Register 2 
TXD2.TXDATA3_15   15  Transmit Buffer Data Byte 3 - bit 15
TXD2.TXDATA3_14   14  Transmit Buffer Data Byte 3 - bit 14
TXD2.TXDATA3_13   13  Transmit Buffer Data Byte 3 - bit 13
TXD2.TXDATA3_12   12  Transmit Buffer Data Byte 3 - bit 12
TXD2.TXDATA3_11   11  Transmit Buffer Data Byte 3 - bit 11
TXD2.TXDATA3_10   10  Transmit Buffer Data Byte 3 - bit 10
TXD2.TXDATA3_9    9   Transmit Buffer Data Byte 3 - bit 9 
TXD2.TXDATA3_8    8   Transmit Buffer Data Byte 3 - bit 8 
TXD2.TXDATA2_7    7   Transmit Buffer Data Byte 2 - bit 7 
TXD2.TXDATA2_6    6   Transmit Buffer Data Byte 2 - bit 6 
TXD2.TXDATA2_5    5   Transmit Buffer Data Byte 2 - bit 5 
TXD2.TXDATA2_4    4   Transmit Buffer Data Byte 2 - bit 4 
TXD2.TXDATA2_3    3   Transmit Buffer Data Byte 2 - bit 3 
TXD2.TXDATA2_2    2   Transmit Buffer Data Byte 2 - bit 2 
TXD2.TXDATA2_1    1   Transmit Buffer Data Byte 2 - bit 1 
TXD2.TXDATA2_0    0   Transmit Buffer Data Byte 2 - bit 0 
TXD4             0xEB34   SDLM Transmit Data Register 4 
TXD4.TXDATA5_15   15  Transmit Buffer Data Byte 5 - bit 15
TXD4.TXDATA5_14   14  Transmit Buffer Data Byte 5 - bit 14
TXD4.TXDATA5_13   13  Transmit Buffer Data Byte 5 - bit 13
TXD4.TXDATA5_12   12  Transmit Buffer Data Byte 5 - bit 12
TXD4.TXDATA5_11   11  Transmit Buffer Data Byte 5 - bit 11
TXD4.TXDATA5_10   10  Transmit Buffer Data Byte 5 - bit 10
TXD4.TXDATA5_9    9   Transmit Buffer Data Byte 5 - bit 9 
TXD4.TXDATA5_8    8   Transmit Buffer Data Byte 5 - bit 8 
TXD4.TXDATA4_7    7   Transmit Buffer Data Byte 4 - bit 7 
TXD4.TXDATA4_6    6   Transmit Buffer Data Byte 4 - bit 6 
TXD4.TXDATA4_5    5   Transmit Buffer Data Byte 4 - bit 5 
TXD4.TXDATA4_4    4   Transmit Buffer Data Byte 4 - bit 4 
TXD4.TXDATA4_3    3   Transmit Buffer Data Byte 4 - bit 3 
TXD4.TXDATA4_2    2   Transmit Buffer Data Byte 4 - bit 2 
TXD4.TXDATA4_1    1   Transmit Buffer Data Byte 4 - bit 1 
TXD4.TXDATA4_0    0   Transmit Buffer Data Byte 4 - bit 0 
TXD6             0xEB36   SDLM Transmit Data Register 6 
TXD6.TXDATA7_15   15  Transmit Buffer Data Byte 7 - bit 15
TXD6.TXDATA7_14   14  Transmit Buffer Data Byte 7 - bit 14
TXD6.TXDATA7_13   13  Transmit Buffer Data Byte 7 - bit 13
TXD6.TXDATA7_12   12  Transmit Buffer Data Byte 7 - bit 12
TXD6.TXDATA7_11   11  Transmit Buffer Data Byte 7 - bit 11
TXD6.TXDATA7_10   10  Transmit Buffer Data Byte 7 - bit 10
TXD6.TXDATA7_9    9   Transmit Buffer Data Byte 7 - bit 9 
TXD6.TXDATA7_8    8   Transmit Buffer Data Byte 7 - bit 8 
TXD6.TXDATA6_7    7   Transmit Buffer Data Byte 6 - bit 7 
TXD6.TXDATA6_6    6   Transmit Buffer Data Byte 6 - bit 6 
TXD6.TXDATA6_5    5   Transmit Buffer Data Byte 6 - bit 5 
TXD6.TXDATA6_4    4   Transmit Buffer Data Byte 6 - bit 4 
TXD6.TXDATA6_3    3   Transmit Buffer Data Byte 6 - bit 3 
TXD6.TXDATA6_2    2   Transmit Buffer Data Byte 6 - bit 2 
TXD6.TXDATA6_1    1   Transmit Buffer Data Byte 6 - bit 1 
TXD6.TXDATA6_0    0   Transmit Buffer Data Byte 6 - bit 0 
TXD8             0xEB38   SDLM Transmit Data Register 8 
TXD8.TXDATA9_15   15  Transmit Buffer Data Byte 9 - bit 15
TXD8.TXDATA9_14   14  Transmit Buffer Data Byte 9 - bit 14
TXD8.TXDATA9_13   13  Transmit Buffer Data Byte 9 - bit 13
TXD8.TXDATA9_12   12  Transmit Buffer Data Byte 9 - bit 12
TXD8.TXDATA9_11   11  Transmit Buffer Data Byte 9 - bit 11
TXD8.TXDATA9_10   10  Transmit Buffer Data Byte 9 - bit 10
TXD8.TXDATA9_9    9   Transmit Buffer Data Byte 9 - bit 9 
TXD8.TXDATA9_8    8   Transmit Buffer Data Byte 9 - bit 8 
TXD8.TXDATA8_7    7   Transmit Buffer Data Byte 8 - bit 7 
TXD8.TXDATA8_6    6   Transmit Buffer Data Byte 8 - bit 6 
TXD8.TXDATA8_5    5   Transmit Buffer Data Byte 8 - bit 5 
TXD8.TXDATA8_4    4   Transmit Buffer Data Byte 8 - bit 4 
TXD8.TXDATA8_3    3   Transmit Buffer Data Byte 8 - bit 3 
TXD8.TXDATA8_2    2   Transmit Buffer Data Byte 8 - bit 2 
TXD8.TXDATA8_1    1   Transmit Buffer Data Byte 8 - bit 1 
TXD8.TXDATA8_0    0   Transmit Buffer Data Byte 8 - bit 0 
TXD10            0xEB3A   SDLM Transmit Data Register 10
TXD10.TXDATA10_7  7   Transmit Buffer Data Byte 10 - bit 7 
TXD10.TXDATA10_6  6   Transmit Buffer Data Byte 10 - bit 6 
TXD10.TXDATA10_5  5   Transmit Buffer Data Byte 10 - bit 5 
TXD10.TXDATA10_4  4   Transmit Buffer Data Byte 10 - bit 4 
TXD10.TXDATA10_3  3   Transmit Buffer Data Byte 10 - bit 3 
TXD10.TXDATA10_2  2   Transmit Buffer Data Byte 10 - bit 2 
TXD10.TXDATA10_1  1   Transmit Buffer Data Byte 10 - bit 1 
TXD10.TXDATA10_0  0   Transmit Buffer Data Byte 10 - bit 0 
TXCNT            0xEB3C   SDLM Bus Transmit Byte Counter                 
TXCNT.TxCNT_3     3   Bus Transmit Byte Counter bit - 3
TXCNT.TxCNT_2     2   Bus Transmit Byte Counter bit - 2
TXCNT.TxCNT_1     1   Bus Transmit Byte Counter bit - 1
TXCNT.TxCNT_0     0   Bus Transmit Byte Counter bit - 0
TXCPU            0xEB3E   SDLM CPU Transmit Byte Counter                 
TXCPU.TxCPU_3     3   CPU Transmit Byte Counter bit - 3
TXCPU.TxCPU_2     2   CPU Transmit Byte Counter bit - 2
TXCPU.TxCPU_1     1   CPU Transmit Byte Counter bit - 1
TXCPU.TxCPU_0     0   CPU Transmit Byte Counter bit - 0
RXD00            0xEB40   SDLM Receive Data Register 0
RXD00.RXDATA01_15 15  Receive Buffer 0 Data Byte 1 - bit 15
RXD00.RXDATA01_14 14  Receive Buffer 0 Data Byte 1 - bit 14
RXD00.RXDATA01_13 13  Receive Buffer 0 Data Byte 1 - bit 13
RXD00.RXDATA01_12 12  Receive Buffer 0 Data Byte 1 - bit 12
RXD00.RXDATA01_11 11  Receive Buffer 0 Data Byte 1 - bit 11
RXD00.RXDATA01_10 10  Receive Buffer 0 Data Byte 1 - bit 10
RXD00.RXDATA01_9  9   Receive Buffer 0 Data Byte 1 - bit 9 
RXD00.RXDATA01_8  8   Receive Buffer 0 Data Byte 1 - bit 8 
RXD00.RXDATA00_7  7   Receive Buffer 0 Data Byte 0 - bit 7 
RXD00.RXDATA00_6  6   Receive Buffer 0 Data Byte 0 - bit 6 
RXD00.RXDATA00_5  5   Receive Buffer 0 Data Byte 0 - bit 5 
RXD00.RXDATA00_4  4   Receive Buffer 0 Data Byte 0 - bit 4 
RXD00.RXDATA00_3  3   Receive Buffer 0 Data Byte 0 - bit 3 
RXD00.RXDATA00_2  2   Receive Buffer 0 Data Byte 0 - bit 2 
RXD00.RXDATA00_1  1   Receive Buffer 0 Data Byte 0 - bit 1 
RXD00.RXDATA00_0  0   Receive Buffer 0 Data Byte 0 - bit 0 
RXD02            0xEB42   SDLM Receive Data Register 2
RXD02.RXDATA03_15 15  Receive Buffer 0 Data Byte 3 - bit 15
RXD02.RXDATA03_14 14  Receive Buffer 0 Data Byte 3 - bit 14
RXD02.RXDATA03_13 13  Receive Buffer 0 Data Byte 3 - bit 13
RXD02.RXDATA03_12 12  Receive Buffer 0 Data Byte 3 - bit 12
RXD02.RXDATA03_11 11  Receive Buffer 0 Data Byte 3 - bit 11
RXD02.RXDATA03_10 10  Receive Buffer 0 Data Byte 3 - bit 10
RXD02.RXDATA03_9  9   Receive Buffer 0 Data Byte 3 - bit 9 
RXD02.RXDATA03_8  8   Receive Buffer 0 Data Byte 3 - bit 8 
RXD02.RXDATA02_7  7   Receive Buffer 0 Data Byte 2 - bit 7 
RXD02.RXDATA02_6  6   Receive Buffer 0 Data Byte 2 - bit 6 
RXD02.RXDATA02_5  5   Receive Buffer 0 Data Byte 2 - bit 5 
RXD02.RXDATA02_4  4   Receive Buffer 0 Data Byte 2 - bit 4 
RXD02.RXDATA02_3  3   Receive Buffer 0 Data Byte 2 - bit 3 
RXD02.RXDATA02_2  2   Receive Buffer 0 Data Byte 2 - bit 2 
RXD02.RXDATA02_1  1   Receive Buffer 0 Data Byte 2 - bit 1 
RXD02.RXDATA02_0  0   Receive Buffer 0 Data Byte 2 - bit 0 
RXD04            0xEB44   SDLM Receive Data Register 4
RXD04.RXDATA05_15 15  Receive Buffer 0 Data Byte 5 - bit 15
RXD04.RXDATA05_14 14  Receive Buffer 0 Data Byte 5 - bit 14
RXD04.RXDATA05_13 13  Receive Buffer 0 Data Byte 5 - bit 13
RXD04.RXDATA05_12 12  Receive Buffer 0 Data Byte 5 - bit 12
RXD04.RXDATA05_11 11  Receive Buffer 0 Data Byte 5 - bit 11
RXD04.RXDATA05_10 10  Receive Buffer 0 Data Byte 5 - bit 10
RXD04.RXDATA05_9  9   Receive Buffer 0 Data Byte 5 - bit 9 
RXD04.RXDATA05_8  8   Receive Buffer 0 Data Byte 5 - bit 8 
RXD04.RXDATA04_7  7   Receive Buffer 0 Data Byte 4 - bit 7 
RXD04.RXDATA04_6  6   Receive Buffer 0 Data Byte 4 - bit 6 
RXD04.RXDATA04_5  5   Receive Buffer 0 Data Byte 4 - bit 5 
RXD04.RXDATA04_4  4   Receive Buffer 0 Data Byte 4 - bit 4 
RXD04.RXDATA04_3  3   Receive Buffer 0 Data Byte 4 - bit 3 
RXD04.RXDATA04_2  2   Receive Buffer 0 Data Byte 4 - bit 2 
RXD04.RXDATA04_1  1   Receive Buffer 0 Data Byte 4 - bit 1 
RXD04.RXDATA04_0  0   Receive Buffer 0 Data Byte 4 - bit 0 
RXD06            0xEB46   SDLM Receive Data Register 6
RXD06.RXDATA07_15 15  Receive Buffer 0 Data Byte 7 - bit 15
RXD06.RXDATA07_14 14  Receive Buffer 0 Data Byte 7 - bit 14
RXD06.RXDATA07_13 13  Receive Buffer 0 Data Byte 7 - bit 13
RXD06.RXDATA07_12 12  Receive Buffer 0 Data Byte 7 - bit 12
RXD06.RXDATA07_11 11  Receive Buffer 0 Data Byte 7 - bit 11
RXD06.RXDATA07_10 10  Receive Buffer 0 Data Byte 7 - bit 10
RXD06.RXDATA07_9  9   Receive Buffer 0 Data Byte 7 - bit 9 
RXD06.RXDATA07_8  8   Receive Buffer 0 Data Byte 7 - bit 8 
RXD06.RXDATA06_7  7   Receive Buffer 0 Data Byte 6 - bit 7 
RXD06.RXDATA06_6  6   Receive Buffer 0 Data Byte 6 - bit 6 
RXD06.RXDATA06_5  5   Receive Buffer 0 Data Byte 6 - bit 5 
RXD06.RXDATA06_4  4   Receive Buffer 0 Data Byte 6 - bit 4 
RXD06.RXDATA06_3  3   Receive Buffer 0 Data Byte 6 - bit 3 
RXD06.RXDATA06_2  2   Receive Buffer 0 Data Byte 6 - bit 2 
RXD06.RXDATA06_1  1   Receive Buffer 0 Data Byte 6 - bit 1 
RXD06.RXDATA06_0  0   Receive Buffer 0 Data Byte 6 - bit 0 
RXD08            0xEB48   SDLM Receive Data Register 8
RXD08.RXDATA09_15 15  Receive Buffer 0 Data Byte 9 - bit 15
RXD08.RXDATA09_14 14  Receive Buffer 0 Data Byte 9 - bit 14
RXD08.RXDATA09_13 13  Receive Buffer 0 Data Byte 9 - bit 13
RXD08.RXDATA09_12 12  Receive Buffer 0 Data Byte 9 - bit 12
RXD08.RXDATA09_11 11  Receive Buffer 0 Data Byte 9 - bit 11
RXD08.RXDATA09_10 10  Receive Buffer 0 Data Byte 9 - bit 10
RXD08.RXDATA09_9  9   Receive Buffer 0 Data Byte 9 - bit 9 
RXD08.RXDATA09_8  8   Receive Buffer 0 Data Byte 9 - bit 8 
RXD08.RXDATA08_7  7   Receive Buffer 0 Data Byte 8 - bit 7 
RXD08.RXDATA08_6  6   Receive Buffer 0 Data Byte 8 - bit 6 
RXD08.RXDATA08_5  5   Receive Buffer 0 Data Byte 8 - bit 5 
RXD08.RXDATA08_4  4   Receive Buffer 0 Data Byte 8 - bit 4 
RXD08.RXDATA08_3  3   Receive Buffer 0 Data Byte 8 - bit 3 
RXD08.RXDATA08_2  2   Receive Buffer 0 Data Byte 8 - bit 2 
RXD08.RXDATA08_1  1   Receive Buffer 0 Data Byte 8 - bit 1 
RXD08.RXDATA08_0  0   Receive Buffer 0 Data Byte 8 - bit 0 
RXD010           0xEB4A   SDLM Receive Data Register 10
RXD010.RXDATA010_7  7 Receive Buffer 0 Data Byte 10 - bit 7 
RXD010.RXDATA010_6  6 Receive Buffer 0 Data Byte 10 - bit 6 
RXD010.RXDATA010_5  5 Receive Buffer 0 Data Byte 10 - bit 5 
RXD010.RXDATA010_4  4 Receive Buffer 0 Data Byte 10 - bit 4 
RXD010.RXDATA010_3  3 Receive Buffer 0 Data Byte 10 - bit 3 
RXD010.RXDATA010_2  2 Receive Buffer 0 Data Byte 10 - bit 2 
RXD010.RXDATA010_1  1 Receive Buffer 0 Data Byte 10 - bit 1 
RXD010.RXDATA010_0  0 Receive Buffer 0 Data Byte 10 - bit 0 
RXCNT            0xEB4C   SDLM Bus Receive Byte Counter (CPU)            
RXCNT.RxCNT_3     3   Receive Byte Count - bit 3
RXCNT.RxCNT_2     2   Receive Byte Count - bit 2
RXCNT.RxCNT_1     1   Receive Byte Count - bit 1
RXCNT.RxCNT_0     0   Receive Byte Count - bit 0
RXCPU            0xEB4E   SDLM CPU Receive Byte Counter (CPU)            
RXCPU.RxCPU_3     3   CPU Receive Byte Count - bit 3
RXCPU.RxCPU_2     2   CPU Receive Byte Count - bit 2
RXCPU.RxCPU_1     1   CPU Receive Byte Count - bit 1
RXCPU.RxCPU_0     0   CPU Receive Byte Count - bit 0
RXD10            0xEB50   Receive Data Register 10 (bus)
RXD10.RXDATA11_15 15  Receive Buffer 1 Data Byte 1 - bit 15
RXD10.RXDATA11_14 14  Receive Buffer 1 Data Byte 1 - bit 14
RXD10.RXDATA11_13 13  Receive Buffer 1 Data Byte 1 - bit 13
RXD10.RXDATA11_12 12  Receive Buffer 1 Data Byte 1 - bit 12
RXD10.RXDATA11_11 11  Receive Buffer 1 Data Byte 1 - bit 11
RXD10.RXDATA11_10 10  Receive Buffer 1 Data Byte 1 - bit 10
RXD10.RXDATA11_9  9   Receive Buffer 1 Data Byte 1 - bit 9 
RXD10.RXDATA11_8  8   Receive Buffer 1 Data Byte 1 - bit 8 
RXD10.RXDATA10_7  7   Receive Buffer 1 Data Byte 0 - bit 7 
RXD10.RXDATA10_6  6   Receive Buffer 1 Data Byte 0 - bit 6 
RXD10.RXDATA10_5  5   Receive Buffer 1 Data Byte 0 - bit 5 
RXD10.RXDATA10_4  4   Receive Buffer 1 Data Byte 0 - bit 4 
RXD10.RXDATA10_3  3   Receive Buffer 1 Data Byte 0 - bit 3 
RXD10.RXDATA10_2  2   Receive Buffer 1 Data Byte 0 - bit 2 
RXD10.RXDATA10_1  1   Receive Buffer 1 Data Byte 0 - bit 1 
RXD10.RXDATA10_0  0   Receive Buffer 1 Data Byte 0 - bit 0 
RXD12            0xEB52   Receive Data Register 12 (bus)
RXD12.RXDATA13_15 15  Receive Buffer 1 Data Byte 3 - bit 15
RXD12.RXDATA13_14 14  Receive Buffer 1 Data Byte 3 - bit 14
RXD12.RXDATA13_13 13  Receive Buffer 1 Data Byte 3 - bit 13
RXD12.RXDATA13_12 12  Receive Buffer 1 Data Byte 3 - bit 12
RXD12.RXDATA13_11 11  Receive Buffer 1 Data Byte 3 - bit 11
RXD12.RXDATA13_10 10  Receive Buffer 1 Data Byte 3 - bit 10
RXD12.RXDATA13_9  9   Receive Buffer 1 Data Byte 3 - bit 9 
RXD12.RXDATA12_8  8   Receive Buffer 1 Data Byte 2 - bit 8 
RXD12.RXDATA12_7  7   Receive Buffer 1 Data Byte 2 - bit 7 
RXD12.RXDATA12_6  6   Receive Buffer 1 Data Byte 2 - bit 6 
RXD12.RXDATA12_5  5   Receive Buffer 1 Data Byte 2 - bit 5 
RXD12.RXDATA12_4  4   Receive Buffer 1 Data Byte 2 - bit 4 
RXD12.RXDATA12_3  3   Receive Buffer 1 Data Byte 2 - bit 3 
RXD12.RXDATA12_2  2   Receive Buffer 1 Data Byte 2 - bit 2 
RXD12.RXDATA12_1  1   Receive Buffer 1 Data Byte 2 - bit 1 
RXD12.RXDATA12_0  0   Receive Buffer 1 Data Byte 2 - bit 0 
RXD14            0xEB54   Receive Data Register 14 (bus)
RXD14.RXDATA15_15 15  Receive Buffer 1 Data Byte 5 - bit 15
RXD14.RXDATA15_14 14  Receive Buffer 1 Data Byte 5 - bit 14
RXD14.RXDATA15_13 13  Receive Buffer 1 Data Byte 5 - bit 13
RXD14.RXDATA15_12 12  Receive Buffer 1 Data Byte 5 - bit 12
RXD14.RXDATA15_11 11  Receive Buffer 1 Data Byte 5 - bit 11
RXD14.RXDATA15_10 10  Receive Buffer 1 Data Byte 5 - bit 10
RXD14.RXDATA15_9  9   Receive Buffer 1 Data Byte 5 - bit 9 
RXD14.RXDATA15_8  8   Receive Buffer 1 Data Byte 5 - bit 8 
RXD14.RXDATA14_7  7   Receive Buffer 1 Data Byte 4 - bit 7 
RXD14.RXDATA14_6  6   Receive Buffer 1 Data Byte 4 - bit 6 
RXD14.RXDATA14_5  5   Receive Buffer 1 Data Byte 4 - bit 5 
RXD14.RXDATA14_4  4   Receive Buffer 1 Data Byte 4 - bit 4 
RXD14.RXDATA14_3  3   Receive Buffer 1 Data Byte 4 - bit 3 
RXD14.RXDATA14_2  2   Receive Buffer 1 Data Byte 4 - bit 2 
RXD14.RXDATA14_1  1   Receive Buffer 1 Data Byte 4 - bit 1 
RXD14.RXDATA14_0  0   Receive Buffer 1 Data Byte 4 - bit 0 
RXD16            0xEB56   Receive Data Register 16 (bus)
RXD16.RXDATA17_15 15  Receive Buffer 1 Data Byte 7 - bit 15
RXD16.RXDATA17_14 14  Receive Buffer 1 Data Byte 7 - bit 14
RXD16.RXDATA17_13 13  Receive Buffer 1 Data Byte 7 - bit 13
RXD16.RXDATA17_12 12  Receive Buffer 1 Data Byte 7 - bit 12
RXD16.RXDATA17_11 11  Receive Buffer 1 Data Byte 7 - bit 11
RXD16.RXDATA17_10 10  Receive Buffer 1 Data Byte 7 - bit 10
RXD16.RXDATA17_9  9   Receive Buffer 1 Data Byte 7 - bit 9 
RXD16.RXDATA17_8  8   Receive Buffer 1 Data Byte 7 - bit 8 
RXD16.RXDATA16_7  7   Receive Buffer 1 Data Byte 6 - bit 7 
RXD16.RXDATA16_6  6   Receive Buffer 1 Data Byte 6 - bit 6 
RXD16.RXDATA16_5  5   Receive Buffer 1 Data Byte 6 - bit 5 
RXD16.RXDATA16_4  4   Receive Buffer 1 Data Byte 6 - bit 4 
RXD16.RXDATA16_3  3   Receive Buffer 1 Data Byte 6 - bit 3 
RXD16.RXDATA16_2  2   Receive Buffer 1 Data Byte 6 - bit 2 
RXD16.RXDATA16_1  1   Receive Buffer 1 Data Byte 6 - bit 1 
RXD16.RXDATA16_0  0   Receive Buffer 1 Data Byte 6 - bit 0 
RXD18            0xEB58   Receive Data Register 18 (bus)
RXD18.RXDATA19_15 15  Receive Buffer 1 Data Byte 9 - bit 15
RXD18.RXDATA19_14 14  Receive Buffer 1 Data Byte 9 - bit 14
RXD18.RXDATA19_13 13  Receive Buffer 1 Data Byte 9 - bit 13
RXD18.RXDATA19_12 12  Receive Buffer 1 Data Byte 9 - bit 12
RXD18.RXDATA19_11 11  Receive Buffer 1 Data Byte 9 - bit 11
RXD18.RXDATA19_10 10  Receive Buffer 1 Data Byte 9 - bit 10
RXD18.RXDATA19_9  9   Receive Buffer 1 Data Byte 9 - bit 9 
RXD18.RXDATA19_8  8   Receive Buffer 1 Data Byte 9 - bit 8 
RXD18.RXDATA18_7  7   Receive Buffer 1 Data Byte 8 - bit 7 
RXD18.RXDATA18_6  6   Receive Buffer 1 Data Byte 8 - bit 6 
RXD18.RXDATA18_5  5   Receive Buffer 1 Data Byte 8 - bit 5 
RXD18.RXDATA18_4  4   Receive Buffer 1 Data Byte 8 - bit 4 
RXD18.RXDATA18_3  3   Receive Buffer 1 Data Byte 8 - bit 3 
RXD18.RXDATA18_2  2   Receive Buffer 1 Data Byte 8 - bit 2 
RXD18.RXDATA18_1  1   Receive Buffer 1 Data Byte 8 - bit 1 
RXD18.RXDATA18_0  0   Receive Buffer 1 Data Byte 8 - bit 0 
RXD110           0xEB5A   Receive Data Register 110 (bus)
RXD110.RXDATA110_7  7 Receive Buffer 1 Data Byte 10 - bit 7 
RXD110.RXDATA110_6  6 Receive Buffer 1 Data Byte 10 - bit 6 
RXD110.RXDATA110_5  5 Receive Buffer 1 Data Byte 10 - bit 5 
RXD110.RXDATA110_4  4 Receive Buffer 1 Data Byte 10 - bit 4 
RXD110.RXDATA110_3  3 Receive Buffer 1 Data Byte 10 - bit 3 
RXD110.RXDATA110_2  2 Receive Buffer 1 Data Byte 10 - bit 2 
RXD110.RXDATA110_1  1 Receive Buffer 1 Data Byte 10 - bit 1 
RXD110.RXDATA110_0  0 Receive Buffer 1 Data Byte 10 - bit 0 
RXCNTB           0xEB5C   SDLM Bus Receive Byte Counter (Bus)            
RXCNTB.RxCNTB_3   3   Receive Byte Counter - bit 3
RXCNTB.RxCNTB_2   2   Receive Byte Counter - bit 2
RXCNTB.RxCNTB_1   1   Receive Byte Counter - bit 1
RXCNTB.RxCNTB_0   0   Receive Byte Counter - bit 0
SOFPTR           0xEB60   SDLM Start-of-frame Pointer Register           
SOFPTR.SOFCNT_3   3   Start-of-Frame Counter for Block Mode - bit 3
SOFPTR.SOFCNT_2   2   Start-of-Frame Counter for Block Mode - bit 2
SOFPTR.SOFCNT_1   1   Start-of-Frame Counter for Block Mode - bit 1
SOFPTR.SOFCNT_0   0   Start-of-Frame Counter for Block Mode - bit 0
ICCFG            0xED00   IIC Configuration Register                     
ICCFG.BRP_15      15  Baudrate Prescaler  - bit 15
ICCFG.BRP_14      14  Baudrate Prescaler  - bit 14
ICCFG.BRP_13      13  Baudrate Prescaler  - bit 13
ICCFG.BRP_12      12  Baudrate Prescaler  - bit 12
ICCFG.BRP_11      11  Baudrate Prescaler  - bit 11
ICCFG.BRP_10      10  Baudrate Prescaler  - bit 10
ICCFG.BRP_9       9   Baudrate Prescaler  - bit 9 
ICCFG.BRP_8       8   Baudrate Prescaler  - bit 8 
ICCFG.SCLSEL1     5   SCL Pin Selection 1
ICCFG.SCLSEL0     4   SCL Pin Selection 0
ICCFG.SDASEL2     2   SDA Pin Selection 2
ICCFG.SDASEL1     1   SDA Pin Selection 1
ICCFG.SDASEL0     0   SDA Pin Selection 0
ICCON            0xED02   IIC Control Register                           
ICCON.TRX         7   Transmit Select
ICCON.AIRDIS      6   Auto Interrupt Reset Disable
ICCON.ACKDIS      5   Acknowledge Pulse Disable
ICCON.BUM         4   Busy Master
ICCON.MOD_3       3   Basic Operating Mode - bit 3 
ICCON.MOD_2       2   Basic Operating Mode - bit 2 
ICCON.RSC         1   Repeated Start Condition
ICCON.M10         0   Address Mode
ICST             0xED04   IIC Status Register                            
ICST.IRQP         6  IIC Interrupt Request Bit for Protocol Events
ICST.IRQD         5  IIC Interrupt Request Bit for Data Transfer Events
ICST.BB           4  Bus Busy
ICST.LRB          3  Last Received Bit
ICST.SLA          2  Slave
ICST.AL           1  Arbitration Lost
ICST.ADR          0  Address
ICADR            0xED06   IIC Address Register                           
ICADR.ICA9        9
ICADR.ICA8        8
ICADR.ICA7        7
ICADR.ICA6        6
ICADR.ICA5        5
ICADR.ICA4        4
ICADR.ICA3        3
ICADR.ICA2        2
ICADR.ICA1        1
ICADR.ICA0        0
ICRTB            0xED08   IIC Receive/Transmit Buffer                    
ICRTB.ICData_7    7   Transmit and shift data - bit 7
ICRTB.ICData_6    6   Transmit and shift data - bit 6
ICRTB.ICData_5    5   Transmit and shift data - bit 5
ICRTB.ICData_4    4   Transmit and shift data - bit 4
ICRTB.ICData_3    3   Transmit and shift data - bit 3
ICRTB.ICData_2    2   Transmit and shift data - bit 2
ICRTB.ICData_1    1   Transmit and shift data - bit 1
ICRTB.ICData_0    0   Transmit and shift data - bit 0
S1TBUF           0xEDA0   Serial Channel 1 Transmit Buffer Register      
S1RBUF           0xEDA2   Serial Channel 1 Receive Buffer Register (read only)
S1BG             0xEDA4   Serial Channel 1 Baud Rate Generator Reload Register
S1CON            0xEDA6   Serial Channel 1 Control Register              
S1CON.S1R         15  Baudrate Generator Run Bit
S1CON.S1LB        14  LoopBack Mode Enable Bit
S1CON.S1BRS       13  Baudrate Selection Bit
S1CON.S1ODD       12  Parity Selection Bit
S1CON.S1OE        10  Overrun Error Flag
S1CON.S1FE        9   Framing Error Flag
S1CON.S1PE        8   Parity Error Flag
S1CON.S1OEN       7   Overrun Check Enable Bit
S1CON.S1FEN       6   Framing Check Enable Bit
S1CON.S1PEN       5   Parity Check Enable Bit
S1CON.S1REN       4   Receiver Enable Bit
S1CON.S1STP       3   Number of Stop Bits Selection
S1CON.S1M_2       2   ASC1 Mode Control - bit 2
S1CON.S1M_1       1   ASC1 Mode Control - bit 1
S1CON.S1M_0       0   ASC1 Mode Control - bit 0
C2CSR            0xEE00   CAN2 Control/Status Register                   
C2CSR.BOFF        15  Busoff Status
C2CSR.EWRN        14  Error Warning Status
C2CSR.RXOK        12  Received Message Successfully
C2CSR.TXOK        11  Transmitted Message Successfully
C2CSR.LEC_10      10  Last Error Code - bit 10
C2CSR.LEC_9       9   Last Error Code - bit 9 
C2CSR.LEC_8       8   Last Error Code - bit 8 
C2CSR.TM          7   Test Mode
C2CSR.CCE         6   Configuration Change Enable
C2CSR.CPS         4   Clock Prescaler Control Bit
C2CSR.EIE         3   Error Interrupt Enable
C2CSR.SIE         2   Status Change Interrupt Enable
C2CSR.IE          1   Interrupt Enable
C2CSR.INIT        0   Initialization
C2PCIR           0xEE02   CAN2Port Control and Interrupt Register        
C2PCIR.IPC_10     10  Interface Port Control - bit 10
C2PCIR.IPC_9      9   Interface Port Control - bit 9 
C2PCIR.IPC_8      8   Interface Port Control - bit 8 
C2PCIR.INTID_7    7   Interrupt Identifier - bit 7
C2PCIR.INTID_6    6   Interrupt Identifier - bit 6
C2PCIR.INTID_5    5   Interrupt Identifier - bit 5
C2PCIR.INTID_4    4   Interrupt Identifier - bit 4
C2PCIR.INTID_3    3   Interrupt Identifier - bit 3
C2PCIR.INTID_2    2   Interrupt Identifier - bit 2
C2PCIR.INTID_1    1   Interrupt Identifier - bit 1
C2PCIR.INTID_0    0   Interrupt Identifier - bit 0
C2BTR            0xEE04   CAN2 Bit Timing Register                       
C2BTR.TSEG2_14    14  Time Segment after sample point - bit 14
C2BTR.TSEG2_13    13  Time Segment after sample point - bit 13
C2BTR.TSEG2_12    12  Time Segment after sample point - bit 12
C2BTR.TSEG1_11    11  Time Segment before sample point - bit 11
C2BTR.TSEG1_10    10  Time Segment before sample point - bit 10
C2BTR.TSEG1_9     9   Time Segment before sample point - bit 9 
C2BTR.TSEG1_8     8   Time Segment before sample point - bit 8 
C2BTR.SJW_7       7   (Re)Synchronization Jump Width - bit 7
C2BTR.SJW_6       6   (Re)Synchronization Jump Width - bit 6
C2BTR.BRP_5       5   Baud Rate Prescaler - bit 5
C2BTR.BRP_4       4   Baud Rate Prescaler - bit 4
C2BTR.BRP_3       3   Baud Rate Prescaler - bit 3
C2BTR.BRP_2       2   Baud Rate Prescaler - bit 2
C2BTR.BRP_1       1   Baud Rate Prescaler - bit 1
C2BTR.BRP_0       0   Baud Rate Prescaler - bit 0
C2GMS            0xEE06   CAN2 Global Mask Short                         
C2GMS.ID20        15  Identifier 20
C2GMS.ID19        14  Identifier 19
C2GMS.ID18        13  Identifier 18
C2GMS.ID28        7   Identifier 28
C2GMS.ID27        6   Identifier 27
C2GMS.ID26        5   Identifier 26
C2GMS.ID25        4   Identifier 25
C2GMS.ID24        3   Identifier 24
C2GMS.ID23        2   Identifier 23
C2GMS.ID22        1   Identifier 22
C2GMS.ID21        0   Identifier 21
C2UGML           0xEE08   CAN2 Upper Global Mask Long                    
C2UGML.ID20       15  Identifier 20
C2UGML.ID19       14  Identifier 19
C2UGML.ID18       13  Identifier 18
C2UGML.ID17       12  Identifier 17
C2UGML.ID16       11  Identifier 16
C2UGML.ID15       10  Identifier 15
C2UGML.ID14       9   Identifier 14
C2UGML.ID13       8   Identifier 13
C2UGML.ID28       7   Identifier 28
C2UGML.ID27       6   Identifier 27
C2UGML.ID26       5   Identifier 26
C2UGML.ID25       4   Identifier 25
C2UGML.ID24       3   Identifier 24
C2UGML.ID23       2   Identifier 23
C2UGML.ID22       1   Identifier 22
C2UGML.ID21       0   Identifier 21
C2LGML           0xEE0A   CAN2 Lower Global Mask Long                    
C2LGML.ID4        15  Identifier 4 
C2LGML.ID3        14  Identifier 3 
C2LGML.ID2        13  Identifier 2 
C2LGML.ID1        12  Identifier 1 
C2LGML.ID0        11  Identifier 0 
C2LGML.ID12       7   Identifier 12
C2LGML.ID11       6   Identifier 11
C2LGML.ID10       5   Identifier 10
C2LGML.ID9        4   Identifier 9 
C2LGML.ID8        3   Identifier 8 
C2LGML.ID7        2   Identifier 7 
C2LGML.ID6        1   Identifier 6 
C2LGML.ID5        0   Identifier 5 
C2UMLM           0xEE0C   CAN2 Upper Mask of Last Message                
C2UMLM.ID20       15  Identifier 20
C2UMLM.ID19       14  Identifier 19
C2UMLM.ID18       13  Identifier 18
C2UMLM.ID17       12  Identifier 17
C2UMLM.ID16       11  Identifier 16
C2UMLM.ID15       10  Identifier 15
C2UMLM.ID14       9   Identifier 14
C2UMLM.ID13       8   Identifier 13
C2UMLM.ID28       7   Identifier 28
C2UMLM.ID27       6   Identifier 27
C2UMLM.ID26       5   Identifier 26
C2UMLM.ID25       4   Identifier 25
C2UMLM.ID24       3   Identifier 24
C2UMLM.ID23       2   Identifier 23
C2UMLM.ID22       1   Identifier 22
C2UMLM.ID21       0   Identifier 21
C2LMLM           0xEE0E   CAN2 Lower Mask of Last Message                
C2LMLM.ID4        15  Identifier 4 
C2LMLM.ID3        14  Identifier 3 
C2LMLM.ID2        13  Identifier 2 
C2LMLM.ID1        12  Identifier 1 
C2LMLM.ID0        11  Identifier 0 
C2LMLM.ID12       7   Identifier 12
C2LMLM.ID11       6   Identifier 11
C2LMLM.ID10       5   Identifier 10
C2LMLM.ID9        4   Identifier 9 
C2LMLM.ID8        3   Identifier 8 
C2LMLM.ID7        2   Identifier 7 
C2LMLM.ID6        1   Identifier 6 
C2LMLM.ID5        0   Identifier 5 
C2MCR1           0xEE11   CAN2 Message Ctrl. Reg. (msg. )
C2MCR1.RMTPND_15        15  Remote Pending - bit 15
C2MCR1.RMTPND_14        14  Remote Pending - bit 14
C2MCR1.TXRQ_13          13  Transmit Request - bit 13
C2MCR1.TXRQ_12          12  Transmit Request - bit 12
C2MCR1.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C2MCR1.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C2MCR1.NEWDAT_9         9   New Data - bit 9
C2MCR1.NEWDAT_8         8   New Data - bit 8
C2MCR1.MSGVAL_7         7   Message Valid - bit 7
C2MCR1.MSGVAL_6         6   Message Valid - bit 6
C2MCR1.TXIE_5           5   Transmit Interrupt Enable - bit 5
C2MCR1.TXIE_4           4   Transmit Interrupt Enable - bit 4
C2MCR1.RXIE_3           3   Receive Interrupt Enable - bit 3
C2MCR1.RXIE_2           2   Receive Interrupt Enable - bit 2
C2MCR1.INTPND_1         1   Interrupt Pending - bit 1
C2MCR1.INTPND_0         0   Interrupt Pending - bit 0
C2UAR1           0xEE12   CAN2 Upper Arbitration Reg. (msg. )           
C2UAR1.ID20       15  Identifier 20
C2UAR1.ID19       14  Identifier 19
C2UAR1.ID18       13  Identifier 18
C2UAR1.ID17       12  Identifier 17
C2UAR1.ID16       11  Identifier 16
C2UAR1.ID15       10  Identifier 15
C2UAR1.ID14       9   Identifier 14
C2UAR1.ID13       8   Identifier 13
C2UAR1.ID28       7   Identifier 28
C2UAR1.ID27       6   Identifier 27
C2UAR1.ID26       5   Identifier 26
C2UAR1.ID25       4   Identifier 25
C2UAR1.ID24       3   Identifier 24
C2UAR1.ID23       2   Identifier 23
C2UAR1.ID22       1   Identifier 22
C2UAR1.ID21       0   Identifier 21
C2LAR1           0xEE14   CAN2 Lower Arbitration Register (msg. )       
C2LAR1.ID4        15  Identifier 4 
C2LAR1.ID3        14  Identifier 3 
C2LAR1.ID2        13  Identifier 2 
C2LAR1.ID1        12  Identifier 1 
C2LAR1.ID0        11  Identifier 0 
C2LAR1.ID12       7   Identifier 12
C2LAR1.ID11       6   Identifier 11
C2LAR1.ID10       5   Identifier 10
C2LAR1.ID9        4   Identifier 9 
C2LAR1.ID8        3   Identifier 8 
C2LAR1.ID7        2   Identifier 7 
C2LAR1.ID6        1   Identifier 6 
C2LAR1.ID5        0   Identifier 5 
C2MCFG1          0xEE16   CAN2 Message Configuration Register (msg. )
C2MCFG1.DLC_7     7   Data Length Code - bit 7
C2MCFG1.DLC_6     6   Data Length Code - bit 6
C2MCFG1.DLC_5     5   Data Length Code - bit 5
C2MCFG1.DLC_4     4   Data Length Code - bit 4
C2MCFG1.DIR       3   Message Direction
C2MCFG1.XTD       2   Extended Identifier
C2MCR2           0xEE21   CAN2 Message Ctrl. Reg. (msg. )
C2MCR2.RMTPND_15        15  Remote Pending - bit 15
C2MCR2.RMTPND_14        14  Remote Pending - bit 14
C2MCR2.TXRQ_13          13  Transmit Request - bit 13
C2MCR2.TXRQ_12          12  Transmit Request - bit 12
C2MCR2.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C2MCR2.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C2MCR2.NEWDAT_9         9   New Data - bit 9
C2MCR2.NEWDAT_8         8   New Data - bit 8
C2MCR2.MSGVAL_7         7   Message Valid - bit 7
C2MCR2.MSGVAL_6         6   Message Valid - bit 6
C2MCR2.TXIE_5           5   Transmit Interrupt Enable - bit 5
C2MCR2.TXIE_4           4   Transmit Interrupt Enable - bit 4
C2MCR2.RXIE_3           3   Receive Interrupt Enable - bit 3
C2MCR2.RXIE_2           2   Receive Interrupt Enable - bit 2
C2MCR2.INTPND_1         1   Interrupt Pending - bit 1
C2MCR2.INTPND_0         0   Interrupt Pending - bit 0
C2UAR2           0xEE22   CAN2 Upper Arbitration Reg. (msg. )           
C2UAR2.ID20       15  Identifier 20
C2UAR2.ID19       14  Identifier 19
C2UAR2.ID18       13  Identifier 18
C2UAR2.ID17       12  Identifier 17
C2UAR2.ID16       11  Identifier 16
C2UAR2.ID15       10  Identifier 15
C2UAR2.ID14       9   Identifier 14
C2UAR2.ID13       8   Identifier 13
C2UAR2.ID28       7   Identifier 28
C2UAR2.ID27       6   Identifier 27
C2UAR2.ID26       5   Identifier 26
C2UAR2.ID25       4   Identifier 25
C2UAR2.ID24       3   Identifier 24
C2UAR2.ID23       2   Identifier 23
C2UAR2.ID22       1   Identifier 22
C2UAR2.ID21       0   Identifier 21
C2LAR2           0xEE24   CAN2 Lower Arbitration Register (msg. )       
C2LAR2.ID4        15  Identifier 4 
C2LAR2.ID3        14  Identifier 3 
C2LAR2.ID2        13  Identifier 2 
C2LAR2.ID1        12  Identifier 1 
C2LAR2.ID0        11  Identifier 0 
C2LAR2.ID12       7   Identifier 12
C2LAR2.ID11       6   Identifier 11
C2LAR2.ID10       5   Identifier 10
C2LAR2.ID9        4   Identifier 9 
C2LAR2.ID8        3   Identifier 8 
C2LAR2.ID7        2   Identifier 7 
C2LAR2.ID6        1   Identifier 6 
C2LAR2.ID5        0   Identifier 5 
C2MCFG2          0xEE26   CAN2 Message Configuration Register (msg. )
C2MCFG2.DLC_7     7   Data Length Code - bit 7
C2MCFG2.DLC_6     6   Data Length Code - bit 6
C2MCFG2.DLC_5     5   Data Length Code - bit 5
C2MCFG2.DLC_4     4   Data Length Code - bit 4
C2MCFG2.DIR       3   Message Direction
C2MCFG2.XTD       2   Extended Identifier
C2MCR3           0xEE31   CAN2 Message Ctrl. Reg. (msg. )
C2MCR3.RMTPND_15        15  Remote Pending - bit 15
C2MCR3.RMTPND_14        14  Remote Pending - bit 14
C2MCR3.TXRQ_13          13  Transmit Request - bit 13
C2MCR3.TXRQ_12          12  Transmit Request - bit 12
C2MCR3.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C2MCR3.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C2MCR3.NEWDAT_9         9   New Data - bit 9
C2MCR3.NEWDAT_8         8   New Data - bit 8
C2MCR3.MSGVAL_7         7   Message Valid - bit 7
C2MCR3.MSGVAL_6         6   Message Valid - bit 6
C2MCR3.TXIE_5           5   Transmit Interrupt Enable - bit 5
C2MCR3.TXIE_4           4   Transmit Interrupt Enable - bit 4
C2MCR3.RXIE_3           3   Receive Interrupt Enable - bit 3
C2MCR3.RXIE_2           2   Receive Interrupt Enable - bit 2
C2MCR3.INTPND_1         1   Interrupt Pending - bit 1
C2MCR3.INTPND_0         0   Interrupt Pending - bit 0
C2UAR3           0xEE32   CAN2 Upper Arbitration Reg. (msg. )           
C2UAR3.ID20       15  Identifier 20
C2UAR3.ID19       14  Identifier 19
C2UAR3.ID18       13  Identifier 18
C2UAR3.ID17       12  Identifier 17
C2UAR3.ID16       11  Identifier 16
C2UAR3.ID15       10  Identifier 15
C2UAR3.ID14       9   Identifier 14
C2UAR3.ID13       8   Identifier 13
C2UAR3.ID28       7   Identifier 28
C2UAR3.ID27       6   Identifier 27
C2UAR3.ID26       5   Identifier 26
C2UAR3.ID25       4   Identifier 25
C2UAR3.ID24       3   Identifier 24
C2UAR3.ID23       2   Identifier 23
C2UAR3.ID22       1   Identifier 22
C2UAR3.ID21       0   Identifier 21
C2LAR3           0xEE34   CAN2 Lower Arbitration Register (msg. )       
C2LAR3.ID4        15  Identifier 4 
C2LAR3.ID3        14  Identifier 3 
C2LAR3.ID2        13  Identifier 2 
C2LAR3.ID1        12  Identifier 1 
C2LAR3.ID0        11  Identifier 0 
C2LAR3.ID12       7   Identifier 12
C2LAR3.ID11       6   Identifier 11
C2LAR3.ID10       5   Identifier 10
C2LAR3.ID9        4   Identifier 9 
C2LAR3.ID8        3   Identifier 8 
C2LAR3.ID7        2   Identifier 7 
C2LAR3.ID6        1   Identifier 6 
C2LAR3.ID5        0   Identifier 5 
C2MCFG3          0xEE36   CAN2 Message Configuration Register (msg. )
C2MCFG3.DLC_7     7   Data Length Code - bit 7
C2MCFG3.DLC_6     6   Data Length Code - bit 6
C2MCFG3.DLC_5     5   Data Length Code - bit 5
C2MCFG3.DLC_4     4   Data Length Code - bit 4
C2MCFG3.DIR       3   Message Direction
C2MCFG3.XTD       2   Extended Identifier
C2MCR4           0xEE41   CAN2 Message Ctrl. Reg. (msg. )
C2MCR4.RMTPND_15        15  Remote Pending - bit 15
C2MCR4.RMTPND_14        14  Remote Pending - bit 14
C2MCR4.TXRQ_13          13  Transmit Request - bit 13
C2MCR4.TXRQ_12          12  Transmit Request - bit 12
C2MCR4.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C2MCR4.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C2MCR4.NEWDAT_9         9   New Data - bit 9
C2MCR4.NEWDAT_8         8   New Data - bit 8
C2MCR4.MSGVAL_7         7   Message Valid - bit 7
C2MCR4.MSGVAL_6         6   Message Valid - bit 6
C2MCR4.TXIE_5           5   Transmit Interrupt Enable - bit 5
C2MCR4.TXIE_4           4   Transmit Interrupt Enable - bit 4
C2MCR4.RXIE_3           3   Receive Interrupt Enable - bit 3
C2MCR4.RXIE_2           2   Receive Interrupt Enable - bit 2
C2MCR4.INTPND_1         1   Interrupt Pending - bit 1
C2MCR4.INTPND_0         0   Interrupt Pending - bit 0
C2UAR4           0xEE42   CAN2 Upper Arbitration Reg. (msg. )           
C2UAR4.ID20       15  Identifier 20
C2UAR4.ID19       14  Identifier 19
C2UAR4.ID18       13  Identifier 18
C2UAR4.ID17       12  Identifier 17
C2UAR4.ID16       11  Identifier 16
C2UAR4.ID15       10  Identifier 15
C2UAR4.ID14       9   Identifier 14
C2UAR4.ID13       8   Identifier 13
C2UAR4.ID28       7   Identifier 28
C2UAR4.ID27       6   Identifier 27
C2UAR4.ID26       5   Identifier 26
C2UAR4.ID25       4   Identifier 25
C2UAR4.ID24       3   Identifier 24
C2UAR4.ID23       2   Identifier 23
C2UAR4.ID22       1   Identifier 22
C2UAR4.ID21       0   Identifier 21
C2LAR4           0xEE44   CAN2 Lower Arbitration Register (msg. )       
C2LAR4.ID4        15  Identifier 4 
C2LAR4.ID3        14  Identifier 3 
C2LAR4.ID2        13  Identifier 2 
C2LAR4.ID1        12  Identifier 1 
C2LAR4.ID0        11  Identifier 0 
C2LAR4.ID12       7   Identifier 12
C2LAR4.ID11       6   Identifier 11
C2LAR4.ID10       5   Identifier 10
C2LAR4.ID9        4   Identifier 9 
C2LAR4.ID8        3   Identifier 8 
C2LAR4.ID7        2   Identifier 7 
C2LAR4.ID6        1   Identifier 6 
C2LAR4.ID5        0   Identifier 5 
C2MCFG4          0xEE46   CAN2 Message Configuration Register (msg. )
C2MCFG4.DLC_7     7   Data Length Code - bit 7
C2MCFG4.DLC_6     6   Data Length Code - bit 6
C2MCFG4.DLC_5     5   Data Length Code - bit 5
C2MCFG4.DLC_4     4   Data Length Code - bit 4
C2MCFG4.DIR       3   Message Direction
C2MCFG4.XTD       2   Extended Identifier
C2MCR5           0xEE51   CAN2 Message Ctrl. Reg. (msg. )
C2MCR5.RMTPND_15        15  Remote Pending - bit 15
C2MCR5.RMTPND_14        14  Remote Pending - bit 14
C2MCR5.TXRQ_13          13  Transmit Request - bit 13
C2MCR5.TXRQ_12          12  Transmit Request - bit 12
C2MCR5.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C2MCR5.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C2MCR5.NEWDAT_9         9   New Data - bit 9
C2MCR5.NEWDAT_8         8   New Data - bit 8
C2MCR5.MSGVAL_7         7   Message Valid - bit 7
C2MCR5.MSGVAL_6         6   Message Valid - bit 6
C2MCR5.TXIE_5           5   Transmit Interrupt Enable - bit 5
C2MCR5.TXIE_4           4   Transmit Interrupt Enable - bit 4
C2MCR5.RXIE_3           3   Receive Interrupt Enable - bit 3
C2MCR5.RXIE_2           2   Receive Interrupt Enable - bit 2
C2MCR5.INTPND_1         1   Interrupt Pending - bit 1
C2MCR5.INTPND_0         0   Interrupt Pending - bit 0
C2UAR5           0xEE52   CAN2 Upper Arbitration Reg. (msg. )           
C2UAR5.ID20       15  Identifier 20
C2UAR5.ID19       14  Identifier 19
C2UAR5.ID18       13  Identifier 18
C2UAR5.ID17       12  Identifier 17
C2UAR5.ID16       11  Identifier 16
C2UAR5.ID15       10  Identifier 15
C2UAR5.ID14       9   Identifier 14
C2UAR5.ID13       8   Identifier 13
C2UAR5.ID28       7   Identifier 28
C2UAR5.ID27       6   Identifier 27
C2UAR5.ID26       5   Identifier 26
C2UAR5.ID25       4   Identifier 25
C2UAR5.ID24       3   Identifier 24
C2UAR5.ID23       2   Identifier 23
C2UAR5.ID22       1   Identifier 22
C2UAR5.ID21       0   Identifier 21
C2LAR5           0xEE54   CAN2 Lower Arbitration Register (msg. )       
C2LAR5.ID4        15  Identifier 4 
C2LAR5.ID3        14  Identifier 3 
C2LAR5.ID2        13  Identifier 2 
C2LAR5.ID1        12  Identifier 1 
C2LAR5.ID0        11  Identifier 0 
C2LAR5.ID12       7   Identifier 12
C2LAR5.ID11       6   Identifier 11
C2LAR5.ID10       5   Identifier 10
C2LAR5.ID9        4   Identifier 9 
C2LAR5.ID8        3   Identifier 8 
C2LAR5.ID7        2   Identifier 7 
C2LAR5.ID6        1   Identifier 6 
C2LAR5.ID5        0   Identifier 5 
C2MCFG5          0xEE56   CAN2 Message Configuration Register (msg. )
C2MCFG5.DLC_7     7   Data Length Code - bit 7
C2MCFG5.DLC_6     6   Data Length Code - bit 6
C2MCFG5.DLC_5     5   Data Length Code - bit 5
C2MCFG5.DLC_4     4   Data Length Code - bit 4
C2MCFG5.DIR       3   Message Direction
C2MCFG5.XTD       2   Extended Identifier
C2MCR6           0xEE61   CAN2 Message Ctrl. Reg. (msg. )
C2MCR6.RMTPND_15        15  Remote Pending - bit 15
C2MCR6.RMTPND_14        14  Remote Pending - bit 14
C2MCR6.TXRQ_13          13  Transmit Request - bit 13
C2MCR6.TXRQ_12          12  Transmit Request - bit 12
C2MCR6.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C2MCR6.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C2MCR6.NEWDAT_9         9   New Data - bit 9
C2MCR6.NEWDAT_8         8   New Data - bit 8
C2MCR6.MSGVAL_7         7   Message Valid - bit 7
C2MCR6.MSGVAL_6         6   Message Valid - bit 6
C2MCR6.TXIE_5           5   Transmit Interrupt Enable - bit 5
C2MCR6.TXIE_4           4   Transmit Interrupt Enable - bit 4
C2MCR6.RXIE_3           3   Receive Interrupt Enable - bit 3
C2MCR6.RXIE_2           2   Receive Interrupt Enable - bit 2
C2MCR6.INTPND_1         1   Interrupt Pending - bit 1
C2MCR6.INTPND_0         0   Interrupt Pending - bit 0
C2UAR6           0xEE62   CAN2 Upper Arbitration Reg. (msg. )           
C2UAR6.ID20       15  Identifier 20
C2UAR6.ID19       14  Identifier 19
C2UAR6.ID18       13  Identifier 18
C2UAR6.ID17       12  Identifier 17
C2UAR6.ID16       11  Identifier 16
C2UAR6.ID15       10  Identifier 15
C2UAR6.ID14       9   Identifier 14
C2UAR6.ID13       8   Identifier 13
C2UAR6.ID28       7   Identifier 28
C2UAR6.ID27       6   Identifier 27
C2UAR6.ID26       5   Identifier 26
C2UAR6.ID25       4   Identifier 25
C2UAR6.ID24       3   Identifier 24
C2UAR6.ID23       2   Identifier 23
C2UAR6.ID22       1   Identifier 22
C2UAR6.ID21       0   Identifier 21
C2LAR6           0xEE64   CAN2 Lower Arbitration Register (msg. )       
C2LAR6.ID4        15  Identifier 4 
C2LAR6.ID3        14  Identifier 3 
C2LAR6.ID2        13  Identifier 2 
C2LAR6.ID1        12  Identifier 1 
C2LAR6.ID0        11  Identifier 0 
C2LAR6.ID12       7   Identifier 12
C2LAR6.ID11       6   Identifier 11
C2LAR6.ID10       5   Identifier 10
C2LAR6.ID9        4   Identifier 9 
C2LAR6.ID8        3   Identifier 8 
C2LAR6.ID7        2   Identifier 7 
C2LAR6.ID6        1   Identifier 6 
C2LAR6.ID5        0   Identifier 5 
C2MCFG6          0xEE66   CAN2 Message Configuration Register (msg. )
C2MCFG6.DLC_7     7   Data Length Code - bit 7
C2MCFG6.DLC_6     6   Data Length Code - bit 6
C2MCFG6.DLC_5     5   Data Length Code - bit 5
C2MCFG6.DLC_4     4   Data Length Code - bit 4
C2MCFG6.DIR       3   Message Direction
C2MCFG6.XTD       2   Extended Identifier
C2MCR7           0xEE71   CAN2 Message Ctrl. Reg. (msg. )
C2MCR7.RMTPND_15        15  Remote Pending - bit 15
C2MCR7.RMTPND_14        14  Remote Pending - bit 14
C2MCR7.TXRQ_13          13  Transmit Request - bit 13
C2MCR7.TXRQ_12          12  Transmit Request - bit 12
C2MCR7.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C2MCR7.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C2MCR7.NEWDAT_9         9   New Data - bit 9
C2MCR7.NEWDAT_8         8   New Data - bit 8
C2MCR7.MSGVAL_7         7   Message Valid - bit 7
C2MCR7.MSGVAL_6         6   Message Valid - bit 6
C2MCR7.TXIE_5           5   Transmit Interrupt Enable - bit 5
C2MCR7.TXIE_4           4   Transmit Interrupt Enable - bit 4
C2MCR7.RXIE_3           3   Receive Interrupt Enable - bit 3
C2MCR7.RXIE_2           2   Receive Interrupt Enable - bit 2
C2MCR7.INTPND_1         1   Interrupt Pending - bit 1
C2MCR7.INTPND_0         0   Interrupt Pending - bit 0
C2UAR7           0xEE72   CAN2 Upper Arbitration Reg. (msg. )           
C2UAR7.ID20       15  Identifier 20
C2UAR7.ID19       14  Identifier 19
C2UAR7.ID18       13  Identifier 18
C2UAR7.ID17       12  Identifier 17
C2UAR7.ID16       11  Identifier 16
C2UAR7.ID15       10  Identifier 15
C2UAR7.ID14       9   Identifier 14
C2UAR7.ID13       8   Identifier 13
C2UAR7.ID28       7   Identifier 28
C2UAR7.ID27       6   Identifier 27
C2UAR7.ID26       5   Identifier 26
C2UAR7.ID25       4   Identifier 25
C2UAR7.ID24       3   Identifier 24
C2UAR7.ID23       2   Identifier 23
C2UAR7.ID22       1   Identifier 22
C2UAR7.ID21       0   Identifier 21
C2LAR7           0xEE74   CAN2 Lower Arbitration Register (msg. )       
C2LAR7.ID4        15  Identifier 4 
C2LAR7.ID3        14  Identifier 3 
C2LAR7.ID2        13  Identifier 2 
C2LAR7.ID1        12  Identifier 1 
C2LAR7.ID0        11  Identifier 0 
C2LAR7.ID12       7   Identifier 12
C2LAR7.ID11       6   Identifier 11
C2LAR7.ID10       5   Identifier 10
C2LAR7.ID9        4   Identifier 9 
C2LAR7.ID8        3   Identifier 8 
C2LAR7.ID7        2   Identifier 7 
C2LAR7.ID6        1   Identifier 6 
C2LAR7.ID5        0   Identifier 5 
C2MCFG7          0xEE76   CAN2 Message Configuration Register (msg. )
C2MCFG7.DLC_7     7   Data Length Code - bit 7
C2MCFG7.DLC_6     6   Data Length Code - bit 6
C2MCFG7.DLC_5     5   Data Length Code - bit 5
C2MCFG7.DLC_4     4   Data Length Code - bit 4
C2MCFG7.DIR       3   Message Direction
C2MCFG7.XTD       2   Extended Identifier
C2MCR8           0xEE81   CAN2 Message Ctrl. Reg. (msg. )
C2MCR8.RMTPND_15        15  Remote Pending - bit 15
C2MCR8.RMTPND_14        14  Remote Pending - bit 14
C2MCR8.TXRQ_13          13  Transmit Request - bit 13
C2MCR8.TXRQ_12          12  Transmit Request - bit 12
C2MCR8.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C2MCR8.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C2MCR8.NEWDAT_9         9   New Data - bit 9
C2MCR8.NEWDAT_8         8   New Data - bit 8
C2MCR8.MSGVAL_7         7   Message Valid - bit 7
C2MCR8.MSGVAL_6         6   Message Valid - bit 6
C2MCR8.TXIE_5           5   Transmit Interrupt Enable - bit 5
C2MCR8.TXIE_4           4   Transmit Interrupt Enable - bit 4
C2MCR8.RXIE_3           3   Receive Interrupt Enable - bit 3
C2MCR8.RXIE_2           2   Receive Interrupt Enable - bit 2
C2MCR8.INTPND_1         1   Interrupt Pending - bit 1
C2MCR8.INTPND_0         0   Interrupt Pending - bit 0
C2UAR8           0xEE82   CAN2 Upper Arbitration Reg. (msg. )           
C2UAR8.ID20       15  Identifier 20
C2UAR8.ID19       14  Identifier 19
C2UAR8.ID18       13  Identifier 18
C2UAR8.ID17       12  Identifier 17
C2UAR8.ID16       11  Identifier 16
C2UAR8.ID15       10  Identifier 15
C2UAR8.ID14       9   Identifier 14
C2UAR8.ID13       8   Identifier 13
C2UAR8.ID28       7   Identifier 28
C2UAR8.ID27       6   Identifier 27
C2UAR8.ID26       5   Identifier 26
C2UAR8.ID25       4   Identifier 25
C2UAR8.ID24       3   Identifier 24
C2UAR8.ID23       2   Identifier 23
C2UAR8.ID22       1   Identifier 22
C2UAR8.ID21       0   Identifier 21
C2LAR8           0xEE84   CAN2 Lower Arbitration Register (msg. )       
C2LAR8.ID4        15  Identifier 4 
C2LAR8.ID3        14  Identifier 3 
C2LAR8.ID2        13  Identifier 2 
C2LAR8.ID1        12  Identifier 1 
C2LAR8.ID0        11  Identifier 0 
C2LAR8.ID12       7   Identifier 12
C2LAR8.ID11       6   Identifier 11
C2LAR8.ID10       5   Identifier 10
C2LAR8.ID9        4   Identifier 9 
C2LAR8.ID8        3   Identifier 8 
C2LAR8.ID7        2   Identifier 7 
C2LAR8.ID6        1   Identifier 6 
C2LAR8.ID5        0   Identifier 5 
C2MCFG8          0xEE86   CAN2 Message Configuration Register (msg. )
C2MCFG8.DLC_7     7   Data Length Code - bit 7
C2MCFG8.DLC_6     6   Data Length Code - bit 6
C2MCFG8.DLC_5     5   Data Length Code - bit 5
C2MCFG8.DLC_4     4   Data Length Code - bit 4
C2MCFG8.DIR       3   Message Direction
C2MCFG8.XTD       2   Extended Identifier
C2MCR9           0xEE91   CAN2 Message Ctrl. Reg. (msg. )
C2MCR9.RMTPND_15        15  Remote Pending - bit 15
C2MCR9.RMTPND_14        14  Remote Pending - bit 14
C2MCR9.TXRQ_13          13  Transmit Request - bit 13
C2MCR9.TXRQ_12          12  Transmit Request - bit 12
C2MCR9.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C2MCR9.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C2MCR9.NEWDAT_9         9   New Data - bit 9
C2MCR9.NEWDAT_8         8   New Data - bit 8
C2MCR9.MSGVAL_7         7   Message Valid - bit 7
C2MCR9.MSGVAL_6         6   Message Valid - bit 6
C2MCR9.TXIE_5           5   Transmit Interrupt Enable - bit 5
C2MCR9.TXIE_4           4   Transmit Interrupt Enable - bit 4
C2MCR9.RXIE_3           3   Receive Interrupt Enable - bit 3
C2MCR9.RXIE_2           2   Receive Interrupt Enable - bit 2
C2MCR9.INTPND_1         1   Interrupt Pending - bit 1
C2MCR9.INTPND_0         0   Interrupt Pending - bit 0
C2UAR9           0xEE92   CAN2 Upper Arbitration Reg. (msg. )           
C2UAR9.ID20       15  Identifier 20
C2UAR9.ID19       14  Identifier 19
C2UAR9.ID18       13  Identifier 18
C2UAR9.ID17       12  Identifier 17
C2UAR9.ID16       11  Identifier 16
C2UAR9.ID15       10  Identifier 15
C2UAR9.ID14       9   Identifier 14
C2UAR9.ID13       8   Identifier 13
C2UAR9.ID28       7   Identifier 28
C2UAR9.ID27       6   Identifier 27
C2UAR9.ID26       5   Identifier 26
C2UAR9.ID25       4   Identifier 25
C2UAR9.ID24       3   Identifier 24
C2UAR9.ID23       2   Identifier 23
C2UAR9.ID22       1   Identifier 22
C2UAR9.ID21       0   Identifier 21
C2LAR9           0xEE94   CAN2 Lower Arbitration Register (msg. )       
C2LAR9.ID4        15  Identifier 4 
C2LAR9.ID3        14  Identifier 3 
C2LAR9.ID2        13  Identifier 2 
C2LAR9.ID1        12  Identifier 1 
C2LAR9.ID0        11  Identifier 0 
C2LAR9.ID12       7   Identifier 12
C2LAR9.ID11       6   Identifier 11
C2LAR9.ID10       5   Identifier 10
C2LAR9.ID9        4   Identifier 9 
C2LAR9.ID8        3   Identifier 8 
C2LAR9.ID7        2   Identifier 7 
C2LAR9.ID6        1   Identifier 6 
C2LAR9.ID5        0   Identifier 5 
C2MCFG9          0xEE96   CAN2 Message Configuration Register (msg. )
C2MCFG9.DLC_7     7   Data Length Code - bit 7
C2MCFG9.DLC_6     6   Data Length Code - bit 6
C2MCFG9.DLC_5     5   Data Length Code - bit 5
C2MCFG9.DLC_4     4   Data Length Code - bit 4
C2MCFG9.DIR       3   Message Direction
C2MCFG9.XTD       2   Extended Identifier
C2MCR10          0xEEA1   CAN2 Message Ctrl. Reg. (msg. )
C2MCR10.RMTPND_15        15  Remote Pending - bit 15
C2MCR10.RMTPND_14        14  Remote Pending - bit 14
C2MCR10.TXRQ_13          13  Transmit Request - bit 13
C2MCR10.TXRQ_12          12  Transmit Request - bit 12
C2MCR10.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C2MCR10.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C2MCR10.NEWDAT_9         9   New Data - bit 9
C2MCR10.NEWDAT_8         8   New Data - bit 8
C2MCR10.MSGVAL_7         7   Message Valid - bit 7
C2MCR10.MSGVAL_6         6   Message Valid - bit 6
C2MCR10.TXIE_5           5   Transmit Interrupt Enable - bit 5
C2MCR10.TXIE_4           4   Transmit Interrupt Enable - bit 4
C2MCR10.RXIE_3           3   Receive Interrupt Enable - bit 3
C2MCR10.RXIE_2           2   Receive Interrupt Enable - bit 2
C2MCR10.INTPND_1         1   Interrupt Pending - bit 1
C2MCR10.INTPND_0         0   Interrupt Pending - bit 0
C2UAR10          0xEEA2   CAN2 Upper Arbitration Reg. (msg. )
C2UAR10.ID20      15  Identifier 20
C2UAR10.ID19      14  Identifier 19
C2UAR10.ID18      13  Identifier 18
C2UAR10.ID17      12  Identifier 17
C2UAR10.ID16      11  Identifier 16
C2UAR10.ID15      10  Identifier 15
C2UAR10.ID14      9   Identifier 14
C2UAR10.ID13      8   Identifier 13
C2UAR10.ID28      7   Identifier 28
C2UAR10.ID27      6   Identifier 27
C2UAR10.ID26      5   Identifier 26
C2UAR10.ID25      4   Identifier 25
C2UAR10.ID24      3   Identifier 24
C2UAR10.ID23      2   Identifier 23
C2UAR10.ID22      1   Identifier 22
C2UAR10.ID21      0   Identifier 21
C2LAR10          0xEEA4   CAN2 Lower Arbitration Register (msg. )
C2LAR10.ID4       15  Identifier 4 
C2LAR10.ID3       14  Identifier 3 
C2LAR10.ID2       13  Identifier 2 
C2LAR10.ID1       12  Identifier 1 
C2LAR10.ID0       11  Identifier 0 
C2LAR10.ID12      7   Identifier 12
C2LAR10.ID11      6   Identifier 11
C2LAR10.ID10      5   Identifier 10
C2LAR10.ID9       4   Identifier 9 
C2LAR10.ID8       3   Identifier 8 
C2LAR10.ID7       2   Identifier 7 
C2LAR10.ID6       1   Identifier 6 
C2LAR10.ID5       0   Identifier 5 
C2MCFG10         0xEEA6   CAN2 Message Configuration Register (msg. )
C2MCFG10.DLC_7     7   Data Length Code - bit 7
C2MCFG10.DLC_6     6   Data Length Code - bit 6
C2MCFG10.DLC_5     5   Data Length Code - bit 5
C2MCFG10.DLC_4     4   Data Length Code - bit 4
C2MCFG10.DIR       3   Message Direction
C2MCFG10.XTD       2   Extended Identifier
C2MCR11          0xEEB1   CAN2 Message Ctrl. Reg. (msg. )
C2MCR11.RMTPND_15        15  Remote Pending - bit 15
C2MCR11.RMTPND_14        14  Remote Pending - bit 14
C2MCR11.TXRQ_13          13  Transmit Request - bit 13
C2MCR11.TXRQ_12          12  Transmit Request - bit 12
C2MCR11.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C2MCR11.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C2MCR11.NEWDAT_9         9   New Data - bit 9
C2MCR11.NEWDAT_8         8   New Data - bit 8
C2MCR11.MSGVAL_7         7   Message Valid - bit 7
C2MCR11.MSGVAL_6         6   Message Valid - bit 6
C2MCR11.TXIE_5           5   Transmit Interrupt Enable - bit 5
C2MCR11.TXIE_4           4   Transmit Interrupt Enable - bit 4
C2MCR11.RXIE_3           3   Receive Interrupt Enable - bit 3
C2MCR11.RXIE_2           2   Receive Interrupt Enable - bit 2
C2MCR11.INTPND_1         1   Interrupt Pending - bit 1
C2MCR11.INTPND_0         0   Interrupt Pending - bit 
C2UAR11          0xEEB2   CAN2 Upper Arbitration Reg. (msg. )
C2UAR11.ID20      15  Identifier 20
C2UAR11.ID19      14  Identifier 19
C2UAR11.ID18      13  Identifier 18
C2UAR11.ID17      12  Identifier 17
C2UAR11.ID16      11  Identifier 16
C2UAR11.ID15      10  Identifier 15
C2UAR11.ID14      9   Identifier 14
C2UAR11.ID13      8   Identifier 13
C2UAR11.ID28      7   Identifier 28
C2UAR11.ID27      6   Identifier 27
C2UAR11.ID26      5   Identifier 26
C2UAR11.ID25      4   Identifier 25
C2UAR11.ID24      3   Identifier 24
C2UAR11.ID23      2   Identifier 23
C2UAR11.ID22      1   Identifier 22
C2UAR11.ID21      0   Identifier 21
C2LAR11          0xEEB4   CAN2 Lower Arbitration Register (msg. )
C2LAR11.ID4       15  Identifier 4 
C2LAR11.ID3       14  Identifier 3 
C2LAR11.ID2       13  Identifier 2 
C2LAR11.ID1       12  Identifier 1 
C2LAR11.ID0       11  Identifier 0 
C2LAR11.ID12      7   Identifier 12
C2LAR11.ID11      6   Identifier 11
C2LAR11.ID10      5   Identifier 10
C2LAR11.ID9       4   Identifier 9 
C2LAR11.ID8       3   Identifier 8 
C2LAR11.ID7       2   Identifier 7 
C2LAR11.ID6       1   Identifier 6 
C2LAR11.ID5       0   Identifier 5 
C2MCFG11         0xEEB6   CAN2 Message Configuration Register (msg. )
C2MCFG11.DLC_7     7   Data Length Code - bit 7
C2MCFG11.DLC_6     6   Data Length Code - bit 6
C2MCFG11.DLC_5     5   Data Length Code - bit 5
C2MCFG11.DLC_4     4   Data Length Code - bit 4
C2MCFG11.DIR       3   Message Direction
C2MCFG11.XTD       2   Extended Identifier
C2MCR12          0xEEC1   CAN2 Message Ctrl. Reg. (msg. )
C2MCR12.RMTPND_15        15  Remote Pending - bit 15
C2MCR12.RMTPND_14        14  Remote Pending - bit 14
C2MCR12.TXRQ_13          13  Transmit Request - bit 13
C2MCR12.TXRQ_12          12  Transmit Request - bit 12
C2MCR12.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C2MCR12.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C2MCR12.NEWDAT_9         9   New Data - bit 9
C2MCR12.NEWDAT_8         8   New Data - bit 8
C2MCR12.MSGVAL_7         7   Message Valid - bit 7
C2MCR12.MSGVAL_6         6   Message Valid - bit 6
C2MCR12.TXIE_5           5   Transmit Interrupt Enable - bit 5
C2MCR12.TXIE_4           4   Transmit Interrupt Enable - bit 4
C2MCR12.RXIE_3           3   Receive Interrupt Enable - bit 3
C2MCR12.RXIE_2           2   Receive Interrupt Enable - bit 2
C2MCR12.INTPND_1         1   Interrupt Pending - bit 1
C2MCR12.INTPND_0         0   Interrupt Pending - bit 
C2UAR12          0xEEC2   CAN2 Upper Arbitration Reg. (msg. )
C2UAR12.ID20      15  Identifier 20
C2UAR12.ID19      14  Identifier 19
C2UAR12.ID18      13  Identifier 18
C2UAR12.ID17      12  Identifier 17
C2UAR12.ID16      11  Identifier 16
C2UAR12.ID15      10  Identifier 15
C2UAR12.ID14      9   Identifier 14
C2UAR12.ID13      8   Identifier 13
C2UAR12.ID28      7   Identifier 28
C2UAR12.ID27      6   Identifier 27
C2UAR12.ID26      5   Identifier 26
C2UAR12.ID25      4   Identifier 25
C2UAR12.ID24      3   Identifier 24
C2UAR12.ID23      2   Identifier 23
C2UAR12.ID22      1   Identifier 22
C2UAR12.ID21      0   Identifier 21
C2LAR12          0xEEC4   CAN2 Lower Arbitration Register (msg. )
C2LAR12.ID4       15  Identifier 4 
C2LAR12.ID3       14  Identifier 3 
C2LAR12.ID2       13  Identifier 2 
C2LAR12.ID1       12  Identifier 1 
C2LAR12.ID0       11  Identifier 0 
C2LAR12.ID12      7   Identifier 12
C2LAR12.ID11      6   Identifier 11
C2LAR12.ID10      5   Identifier 10
C2LAR12.ID9       4   Identifier 9 
C2LAR12.ID8       3   Identifier 8 
C2LAR12.ID7       2   Identifier 7 
C2LAR12.ID6       1   Identifier 6 
C2LAR12.ID5       0   Identifier 5 
C2MCFG12         0xEEC6   CAN2 Message Configuration Register (msg. )
C2MCFG12.DLC_7     7   Data Length Code - bit 7
C2MCFG12.DLC_6     6   Data Length Code - bit 6
C2MCFG12.DLC_5     5   Data Length Code - bit 5
C2MCFG12.DLC_4     4   Data Length Code - bit 4
C2MCFG12.DIR       3   Message Direction
C2MCFG12.XTD       2   Extended Identifier
C2MCR13          0xEED1   CAN2 Message Ctrl. Reg. (msg. )
C2MCR13.RMTPND_15        15  Remote Pending - bit 15
C2MCR13.RMTPND_14        14  Remote Pending - bit 14
C2MCR13.TXRQ_13          13  Transmit Request - bit 13
C2MCR13.TXRQ_12          12  Transmit Request - bit 12
C2MCR13.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C2MCR13.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C2MCR13.NEWDAT_9         9   New Data - bit 9
C2MCR13.NEWDAT_8         8   New Data - bit 8
C2MCR13.MSGVAL_7         7   Message Valid - bit 7
C2MCR13.MSGVAL_6         6   Message Valid - bit 6
C2MCR13.TXIE_5           5   Transmit Interrupt Enable - bit 5
C2MCR13.TXIE_4           4   Transmit Interrupt Enable - bit 4
C2MCR13.RXIE_3           3   Receive Interrupt Enable - bit 3
C2MCR13.RXIE_2           2   Receive Interrupt Enable - bit 2
C2MCR13.INTPND_1         1   Interrupt Pending - bit 1
C2MCR13.INTPND_0         0   Interrupt Pending - bit 
C2UAR13          0xEED2   CAN2 Upper Arbitration Reg. (msg. )
C2UAR14.ID20      15  Identifier 20
C2UAR14.ID19      14  Identifier 19
C2UAR14.ID18      13  Identifier 18
C2UAR14.ID17      12  Identifier 17
C2UAR14.ID16      11  Identifier 16
C2UAR14.ID15      10  Identifier 15
C2UAR14.ID14      9   Identifier 14
C2UAR14.ID13      8   Identifier 13
C2UAR14.ID28      7   Identifier 28
C2UAR14.ID27      6   Identifier 27
C2UAR14.ID26      5   Identifier 26
C2UAR14.ID25      4   Identifier 25
C2UAR14.ID24      3   Identifier 24
C2UAR14.ID23      2   Identifier 23
C2UAR14.ID22      1   Identifier 22
C2UAR14.ID21      0   Identifier 21
C2LAR13          0xEED4   CAN2 Lower Arbitration Register (msg. )
C2LAR13.ID4       15  Identifier 4 
C2LAR13.ID3       14  Identifier 3 
C2LAR13.ID2       13  Identifier 2 
C2LAR13.ID1       12  Identifier 1 
C2LAR13.ID0       11  Identifier 0 
C2LAR13.ID12      7   Identifier 12
C2LAR13.ID11      6   Identifier 11
C2LAR13.ID10      5   Identifier 10
C2LAR13.ID9       4   Identifier 9 
C2LAR13.ID8       3   Identifier 8 
C2LAR13.ID7       2   Identifier 7 
C2LAR13.ID6       1   Identifier 6 
C2LAR13.ID5       0   Identifier 5 
C2MCFG13         0xEED6   CAN2 Message Configuration Register (msg. )
C2MCFG13.DLC_7     7   Data Length Code - bit 7
C2MCFG13.DLC_6     6   Data Length Code - bit 6
C2MCFG13.DLC_5     5   Data Length Code - bit 5
C2MCFG13.DLC_4     4   Data Length Code - bit 4
C2MCFG13.DIR       3   Message Direction
C2MCFG13.XTD       2   Extended Identifier
C2MCR14          0xEEE1   CAN2 Message Ctrl. Reg. (msg. )
C2MCR14.RMTPND_15        15  Remote Pending - bit 15
C2MCR14.RMTPND_14        14  Remote Pending - bit 14
C2MCR14.TXRQ_13          13  Transmit Request - bit 13
C2MCR14.TXRQ_12          12  Transmit Request - bit 12
C2MCR14.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C2MCR14.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C2MCR14.NEWDAT_9         9   New Data - bit 9
C2MCR14.NEWDAT_8         8   New Data - bit 8
C2MCR14.MSGVAL_7         7   Message Valid - bit 7
C2MCR14.MSGVAL_6         6   Message Valid - bit 6
C2MCR14.TXIE_5           5   Transmit Interrupt Enable - bit 5
C2MCR14.TXIE_4           4   Transmit Interrupt Enable - bit 4
C2MCR14.RXIE_3           3   Receive Interrupt Enable - bit 3
C2MCR14.RXIE_2           2   Receive Interrupt Enable - bit 2
C2MCR14.INTPND_1         1   Interrupt Pending - bit 1
C2MCR14.INTPND_0         0   Interrupt Pending - bit 
C2UAR14          0xEEE2   CAN2 Upper Arbitration Reg. (msg. )
C2LAR14          0xEEE4   CAN2 Lower Arbitration Register (msg. )
C2LAR14.ID4       15  Identifier 4 
C2LAR14.ID3       14  Identifier 3 
C2LAR14.ID2       13  Identifier 2 
C2LAR14.ID1       12  Identifier 1 
C2LAR14.ID0       11  Identifier 0 
C2LAR14.ID12      7   Identifier 12
C2LAR14.ID11      6   Identifier 11
C2LAR14.ID10      5   Identifier 10
C2LAR14.ID9       4   Identifier 9 
C2LAR14.ID8       3   Identifier 8 
C2LAR14.ID7       2   Identifier 7 
C2LAR14.ID6       1   Identifier 6 
C2LAR14.ID5       0   Identifier 5 
C2MCFG14         0xEEE6   CAN2 Message Configuration Register (msg. )
C2MCFG14.DLC_7     7   Data Length Code - bit 7
C2MCFG14.DLC_6     6   Data Length Code - bit 6
C2MCFG14.DLC_5     5   Data Length Code - bit 5
C2MCFG14.DLC_4     4   Data Length Code - bit 4
C2MCFG14.DIR       3   Message Direction
C2MCFG14.XTD       2   Extended Identifier
C2MCR15          0xEEF1   CAN2 Message Ctrl. Reg. (msg. )
C2MCR15.RMTPND_15        15  Remote Pending - bit 15
C2MCR15.RMTPND_14        14  Remote Pending - bit 14
C2MCR15.TXRQ_13          13  Transmit Request - bit 13
C2MCR15.TXRQ_12          12  Transmit Request - bit 12
C2MCR15.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C2MCR15.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C2MCR15.NEWDAT_9         9   New Data - bit 9
C2MCR15.NEWDAT_8         8   New Data - bit 8
C2MCR15.MSGVAL_7         7   Message Valid - bit 7
C2MCR15.MSGVAL_6         6   Message Valid - bit 6
C2MCR15.TXIE_5           5   Transmit Interrupt Enable - bit 5
C2MCR15.TXIE_4           4   Transmit Interrupt Enable - bit 4
C2MCR15.RXIE_3           3   Receive Interrupt Enable - bit 3
C2MCR15.RXIE_2           2   Receive Interrupt Enable - bit 2
C2MCR15.INTPND_1         1   Interrupt Pending - bit 1
C2MCR15.INTPND_0         0   Interrupt Pending - bit 
C2UAR15          0xEEF2   CAN2 Upper Arbitration Reg. (msg. )
C2UAR15.ID20      15  Identifier 20
C2UAR15.ID19      14  Identifier 19
C2UAR15.ID18      13  Identifier 18
C2UAR15.ID17      12  Identifier 17
C2UAR15.ID16      11  Identifier 16
C2UAR15.ID15      10  Identifier 15
C2UAR15.ID14      9   Identifier 14
C2UAR15.ID13      8   Identifier 13
C2UAR15.ID28      7   Identifier 28
C2UAR15.ID27      6   Identifier 27
C2UAR15.ID26      5   Identifier 26
C2UAR15.ID25      4   Identifier 25
C2UAR15.ID24      3   Identifier 24
C2UAR15.ID23      2   Identifier 23
C2UAR15.ID22      1   Identifier 22
C2UAR15.ID21      0   Identifier 21
C2LAR15          0xEEF4   CAN2 Lower Arbitration Register (msg. )
C2LAR15.ID4       15  Identifier 4 
C2LAR15.ID3       14  Identifier 3 
C2LAR15.ID2       13  Identifier 2 
C2LAR15.ID1       12  Identifier 1 
C2LAR15.ID0       11  Identifier 0 
C2LAR15.ID12      7   Identifier 12
C2LAR15.ID11      6   Identifier 11
C2LAR15.ID10      5   Identifier 10
C2LAR15.ID9       4   Identifier 9 
C2LAR15.ID8       3   Identifier 8 
C2LAR15.ID7       2   Identifier 7 
C2LAR15.ID6       1   Identifier 6 
C2LAR15.ID5       0   Identifier 5 
C2MCFG15         0xEEF6   CAN2 Message Configuration Register (msg. )
C2MCFG15.DLC_7     7   Data Length Code - bit 7
C2MCFG15.DLC_6     6   Data Length Code - bit 6
C2MCFG15.DLC_5     5   Data Length Code - bit 5
C2MCFG15.DLC_4     4   Data Length Code - bit 4
C2MCFG15.DIR       3   Message Direction
C2MCFG15.XTD       2   Extended Identifier
C1CSR            0xEF00   CAN1 Control/Status Register                   
C1CSR.BOFF        15  Busoff Status
C1CSR.EWRN        14  Error Warning Status
C1CSR.RXOK        12  Received Message Successfully
C1CSR.TXOK        11  Transmitted Message Successfully
C1CSR.LEC_10      10  Last Error Code - bit 10
C1CSR.LEC_9       9   Last Error Code - bit 9 
C1CSR.LEC_8       8   Last Error Code - bit 8 
C1CSR.TM          7   Test Mode
C1CSR.CCE         6   Configuration Change Enable
C1CSR.CPS         4   Clock Prescaler Control Bit
C1CSR.EIE         3   Error Interrupt Enable
C1CSR.SIE         2   Status Change Interrupt Enable
C1CSR.IE          1   Interrupt Enable
C1CSR.INIT        0   Initialization
C1PCIR           0xEF02   CAN1 Port Control and Interrupt Register       
C1PCIR.IPC_10     10  Interface Port Control - bit 10
C1PCIR.IPC_9      9   Interface Port Control - bit 9 
C1PCIR.IPC_8      8   Interface Port Control - bit 8 
C1PCIR.INTID_7    7   Interrupt Identifier - bit 7
C1PCIR.INTID_6    6   Interrupt Identifier - bit 6
C1PCIR.INTID_5    5   Interrupt Identifier - bit 5
C1PCIR.INTID_4    4   Interrupt Identifier - bit 4
C1PCIR.INTID_3    3   Interrupt Identifier - bit 3
C1PCIR.INTID_2    2   Interrupt Identifier - bit 2
C1PCIR.INTID_1    1   Interrupt Identifier - bit 1
C1PCIR.INTID_0    0   Interrupt Identifier - bit 0
C1BTR            0xEF04   CAN1 Bit Timing Register                       
C1BTR.TSEG2_14    14  Time Segment after sample point - bit 14
C1BTR.TSEG2_13    13  Time Segment after sample point - bit 13
C1BTR.TSEG2_12    12  Time Segment after sample point - bit 12
C1BTR.TSEG1_11    11  Time Segment before sample point - bit 11
C1BTR.TSEG1_10    10  Time Segment before sample point - bit 10
C1BTR.TSEG1_9     9   Time Segment before sample point - bit 9 
C1BTR.TSEG1_8     8   Time Segment before sample point - bit 8 
C1BTR.SJW_7       7   (Re)Synchronization Jump Width - bit 7
C1BTR.SJW_6       6   (Re)Synchronization Jump Width - bit 6
C1BTR.BRP_5       5   Baud Rate Prescaler - bit 5
C1BTR.BRP_4       4   Baud Rate Prescaler - bit 4
C1BTR.BRP_3       3   Baud Rate Prescaler - bit 3
C1BTR.BRP_2       2   Baud Rate Prescaler - bit 2
C1BTR.BRP_1       1   Baud Rate Prescaler - bit 1
C1BTR.BRP_0       0   Baud Rate Prescaler - bit 0
C1GMS            0xEF06   CAN1 Global Mask Short                         
C1GMS.ID20        15  Identifier 20
C1GMS.ID19        14  Identifier 19
C1GMS.ID18        13  Identifier 18
C1GMS.ID28        7   Identifier 28
C1GMS.ID27        6   Identifier 27
C1GMS.ID26        5   Identifier 26
C1GMS.ID25        4   Identifier 25
C1GMS.ID24        3   Identifier 24
C1GMS.ID23        2   Identifier 23
C1GMS.ID22        1   Identifier 22
C1GMS.ID21        0   Identifier 21
C1UGML           0xEF08   CAN1 Upper Global Mask Long                    
C1UGML.ID20       15  Identifier 20
C1UGML.ID19       14  Identifier 19
C1UGML.ID18       13  Identifier 18
C1UGML.ID17       12  Identifier 17
C1UGML.ID16       11  Identifier 16
C1UGML.ID15       10  Identifier 15
C1UGML.ID14       9   Identifier 14
C1UGML.ID13       8   Identifier 13
C1UGML.ID28       7   Identifier 28
C1UGML.ID27       6   Identifier 27
C1UGML.ID26       5   Identifier 26
C1UGML.ID25       4   Identifier 25
C1UGML.ID24       3   Identifier 24
C1UGML.ID23       2   Identifier 23
C1UGML.ID22       1   Identifier 22
C1UGML.ID21       0   Identifier 21
C1LGML           0xEF0A   CAN1 Lower Global Mask Long                    
C1LGML.ID4        15  Identifier 4 
C1LGML.ID3        14  Identifier 3 
C1LGML.ID2        13  Identifier 2 
C1LGML.ID1        12  Identifier 1 
C1LGML.ID0        11  Identifier 0 
C1LGML.ID12       7   Identifier 12
C1LGML.ID11       6   Identifier 11
C1LGML.ID10       5   Identifier 10
C1LGML.ID9        4   Identifier 9 
C1LGML.ID8        3   Identifier 8 
C1LGML.ID7        2   Identifier 7 
C1LGML.ID6        1   Identifier 6 
C1LGML.ID5        0   Identifier 5 
C1UMLM           0xEF0C   CAN1 Upper Mask of Last Message                
C1UMLM.ID20       15  Identifier 20
C1UMLM.ID19       14  Identifier 19
C1UMLM.ID18       13  Identifier 18
C1UMLM.ID17       12  Identifier 17
C1UMLM.ID16       11  Identifier 16
C1UMLM.ID15       10  Identifier 15
C1UMLM.ID14       9   Identifier 14
C1UMLM.ID13       8   Identifier 13
C1UMLM.ID28       7   Identifier 28
C1UMLM.ID27       6   Identifier 27
C1UMLM.ID26       5   Identifier 26
C1UMLM.ID25       4   Identifier 25
C1UMLM.ID24       3   Identifier 24
C1UMLM.ID23       2   Identifier 23
C1UMLM.ID22       1   Identifier 22
C1UMLM.ID21       0   Identifier 21
C1LMLM           0xEF0E   CAN1 Lower Mask of Last Message                
C1LMLM.ID4        15  Identifier 4 
C1LMLM.ID3        14  Identifier 3 
C1LMLM.ID2        13  Identifier 2 
C1LMLM.ID1        12  Identifier 1 
C1LMLM.ID0        11  Identifier 0 
C1LMLM.ID12       7   Identifier 12
C1LMLM.ID11       6   Identifier 11
C1LMLM.ID10       5   Identifier 10
C1LMLM.ID9        4   Identifier 9 
C1LMLM.ID8        3   Identifier 8 
C1LMLM.ID7        2   Identifier 7 
C1LMLM.ID6        1   Identifier 6 
C1LMLM.ID5        0   Identifier 5 
C1MCR1           0xEF11   CAN1 Message Ctrl. Reg. (msg. )
C1MCR1.RMTPND_15        15  Remote Pending - bit 15
C1MCR1.RMTPND_14        14  Remote Pending - bit 14
C1MCR1.TXRQ_13          13  Transmit Request - bit 13
C1MCR1.TXRQ_12          12  Transmit Request - bit 12
C1MCR1.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C1MCR1.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C1MCR1.NEWDAT_9         9   New Data - bit 9
C1MCR1.NEWDAT_8         8   New Data - bit 8
C1MCR1.MSGVAL_7         7   Message Valid - bit 7
C1MCR1.MSGVAL_6         6   Message Valid - bit 6
C1MCR1.TXIE_5           5   Transmit Interrupt Enable - bit 5
C1MCR1.TXIE_4           4   Transmit Interrupt Enable - bit 4
C1MCR1.RXIE_3           3   Receive Interrupt Enable - bit 3
C1MCR1.RXIE_2           2   Receive Interrupt Enable - bit 2
C1MCR1.INTPND_1         1   Interrupt Pending - bit 1
C1MCR1.INTPND_0         0   Interrupt Pending - bit 0
C1UAR1           0xEF12   CAN1 Upper Arbitration Reg. (msg. )
C1UAR1.ID20       15  Identifier 20
C1UAR1.ID19       14  Identifier 19
C1UAR1.ID18       13  Identifier 18
C1UAR1.ID17       12  Identifier 17
C1UAR1.ID16       11  Identifier 16
C1UAR1.ID15       10  Identifier 15
C1UAR1.ID14       9   Identifier 14
C1UAR1.ID13       8   Identifier 13
C1UAR1.ID28       7   Identifier 28
C1UAR1.ID27       6   Identifier 27
C1UAR1.ID26       5   Identifier 26
C1UAR1.ID25       4   Identifier 25
C1UAR1.ID24       3   Identifier 24
C1UAR1.ID23       2   Identifier 23
C1UAR1.ID22       1   Identifier 22
C1UAR1.ID21       0   Identifier 21
C1LAR1           0xEF14   CAN1 Lower Arbitration Register (msg. )
C1LAR1.ID4        15  Identifier 4 
C1LAR1.ID3        14  Identifier 3 
C1LAR1.ID2        13  Identifier 2 
C1LAR1.ID1        12  Identifier 1 
C1LAR1.ID0        11  Identifier 0 
C1LAR1.ID12       7   Identifier 12
C1LAR1.ID11       6   Identifier 11
C1LAR1.ID10       5   Identifier 10
C1LAR1.ID9        4   Identifier 9 
C1LAR1.ID8        3   Identifier 8 
C1LAR1.ID7        2   Identifier 7 
C1LAR1.ID6        1   Identifier 6 
C1LAR1.ID5        0   Identifier 5 
C1MCFG1          0xEF16   CAN1 Message Configuration Register (msg. )
C1MCFG1.DLC_7     7   Data Length Code - bit 7
C1MCFG1.DLC_6     6   Data Length Code - bit 6
C1MCFG1.DLC_5     5   Data Length Code - bit 5
C1MCFG1.DLC_4     4   Data Length Code - bit 4
C1MCFG1.DIR       3   Message Direction
C1MCFG1.XTD       2   Extended Identifier
C1MCR2           0xEF21   CAN1 Message Ctrl. Reg. (msg. )
C1MCR2.RMTPND_15        15  Remote Pending - bit 15
C1MCR2.RMTPND_14        14  Remote Pending - bit 14
C1MCR2.TXRQ_13          13  Transmit Request - bit 13
C1MCR2.TXRQ_12          12  Transmit Request - bit 12
C1MCR2.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C1MCR2.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C1MCR2.NEWDAT_9         9   New Data - bit 9
C1MCR2.NEWDAT_8         8   New Data - bit 8
C1MCR2.MSGVAL_7         7   Message Valid - bit 7
C1MCR2.MSGVAL_6         6   Message Valid - bit 6
C1MCR2.TXIE_5           5   Transmit Interrupt Enable - bit 5
C1MCR2.TXIE_4           4   Transmit Interrupt Enable - bit 4
C1MCR2.RXIE_3           3   Receive Interrupt Enable - bit 3
C1MCR2.RXIE_2           2   Receive Interrupt Enable - bit 2
C1MCR2.INTPND_1         1   Interrupt Pending - bit 1
C1MCR2.INTPND_0         0   Interrupt Pending - bit 0
C1UAR2           0xEF22   CAN1 Upper Arbitration Reg. (msg. )
C1UAR2.ID20       15  Identifier 20
C1UAR2.ID19       14  Identifier 19
C1UAR2.ID18       13  Identifier 18
C1UAR2.ID17       12  Identifier 17
C1UAR2.ID16       11  Identifier 16
C1UAR2.ID15       10  Identifier 15
C1UAR2.ID14       9   Identifier 14
C1UAR2.ID13       8   Identifier 13
C1UAR2.ID28       7   Identifier 28
C1UAR2.ID27       6   Identifier 27
C1UAR2.ID26       5   Identifier 26
C1UAR2.ID25       4   Identifier 25
C1UAR2.ID24       3   Identifier 24
C1UAR2.ID23       2   Identifier 23
C1UAR2.ID22       1   Identifier 22
C1UAR2.ID21       0   Identifier 21
C1LAR2           0xEF24   CAN1 Lower Arbitration Register (msg. )
C1LAR2.ID4        15  Identifier 4 
C1LAR2.ID3        14  Identifier 3 
C1LAR2.ID2        13  Identifier 2 
C1LAR2.ID1        12  Identifier 1 
C1LAR2.ID0        11  Identifier 0 
C1LAR2.ID12       7   Identifier 12
C1LAR2.ID11       6   Identifier 11
C1LAR2.ID10       5   Identifier 10
C1LAR2.ID9        4   Identifier 9 
C1LAR2.ID8        3   Identifier 8 
C1LAR2.ID7        2   Identifier 7 
C1LAR2.ID6        1   Identifier 6 
C1LAR2.ID5        0   Identifier 5 
C1MCFG2          0xEF26   CAN1 Message Configuration Register (msg. )
C1MCFG2.DLC_7     7   Data Length Code - bit 7
C1MCFG2.DLC_6     6   Data Length Code - bit 6
C1MCFG2.DLC_5     5   Data Length Code - bit 5
C1MCFG2.DLC_4     4   Data Length Code - bit 4
C1MCFG2.DIR       3   Message Direction
C1MCFG2.XTD       2   Extended Identifier
C1MCR3           0xEF31   CAN1 Message Ctrl. Reg. (msg. )
C1MCR3.RMTPND_15        15  Remote Pending - bit 15
C1MCR3.RMTPND_14        14  Remote Pending - bit 14
C1MCR3.TXRQ_13          13  Transmit Request - bit 13
C1MCR3.TXRQ_12          12  Transmit Request - bit 12
C1MCR3.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C1MCR3.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C1MCR3.NEWDAT_9         9   New Data - bit 9
C1MCR3.NEWDAT_8         8   New Data - bit 8
C1MCR3.MSGVAL_7         7   Message Valid - bit 7
C1MCR3.MSGVAL_6         6   Message Valid - bit 6
C1MCR3.TXIE_5           5   Transmit Interrupt Enable - bit 5
C1MCR3.TXIE_4           4   Transmit Interrupt Enable - bit 4
C1MCR3.RXIE_3           3   Receive Interrupt Enable - bit 3
C1MCR3.RXIE_2           2   Receive Interrupt Enable - bit 2
C1MCR3.INTPND_1         1   Interrupt Pending - bit 1
C1MCR3.INTPND_0         0   Interrupt Pending - bit 0
C1UAR3           0xEF32   CAN1 Upper Arbitration Reg. (msg. )
C1UAR3.ID20       15  Identifier 20
C1UAR3.ID19       14  Identifier 19
C1UAR3.ID18       13  Identifier 18
C1UAR3.ID17       12  Identifier 17
C1UAR3.ID16       11  Identifier 16
C1UAR3.ID15       10  Identifier 15
C1UAR3.ID14       9   Identifier 14
C1UAR3.ID13       8   Identifier 13
C1UAR3.ID28       7   Identifier 28
C1UAR3.ID27       6   Identifier 27
C1UAR3.ID26       5   Identifier 26
C1UAR3.ID25       4   Identifier 25
C1UAR3.ID24       3   Identifier 24
C1UAR3.ID23       2   Identifier 23
C1UAR3.ID22       1   Identifier 22
C1UAR3.ID21       0   Identifier 21
C1LAR3           0xEF34   CAN1 Lower Arbitration Register (msg. )
C1LAR1.ID4        15  Identifier 4 
C1LAR1.ID3        14  Identifier 3 
C1LAR1.ID2        13  Identifier 2 
C1LAR1.ID1        12  Identifier 1 
C1LAR1.ID0        11  Identifier 0 
C1LAR1.ID12       7   Identifier 12
C1LAR1.ID11       6   Identifier 11
C1LAR1.ID10       5   Identifier 10
C1LAR1.ID9        4   Identifier 9 
C1LAR1.ID8        3   Identifier 8 
C1LAR1.ID7        2   Identifier 7 
C1LAR1.ID6        1   Identifier 6 
C1LAR1.ID5        0   Identifier 5 
C1MCFG3          0xEF36   CAN1 Message Configuration Register (msg. )
C1MCFG3.DLC_7     7   Data Length Code - bit 7
C1MCFG3.DLC_6     6   Data Length Code - bit 6
C1MCFG3.DLC_5     5   Data Length Code - bit 5
C1MCFG3.DLC_4     4   Data Length Code - bit 4
C1MCFG3.DIR       3   Message Direction
C1MCFG3.XTD       2   Extended Identifier
C1MCR4           0xEF41   CAN1 Message Ctrl. Reg. (msg. )
C1MCR4.RMTPND_15        15  Remote Pending - bit 15
C1MCR4.RMTPND_14        14  Remote Pending - bit 14
C1MCR4.TXRQ_13          13  Transmit Request - bit 13
C1MCR4.TXRQ_12          12  Transmit Request - bit 12
C1MCR4.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C1MCR4.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C1MCR4.NEWDAT_9         9   New Data - bit 9
C1MCR4.NEWDAT_8         8   New Data - bit 8
C1MCR4.MSGVAL_7         7   Message Valid - bit 7
C1MCR4.MSGVAL_6         6   Message Valid - bit 6
C1MCR4.TXIE_5           5   Transmit Interrupt Enable - bit 5
C1MCR4.TXIE_4           4   Transmit Interrupt Enable - bit 4
C1MCR4.RXIE_3           3   Receive Interrupt Enable - bit 3
C1MCR4.RXIE_2           2   Receive Interrupt Enable - bit 2
C1MCR4.INTPND_1         1   Interrupt Pending - bit 1
C1MCR4.INTPND_0         0   Interrupt Pending - bit 0
C1UAR4           0xEF42   CAN1 Upper Arbitration Reg. (msg. )
C1UAR4.ID20       15  Identifier 20
C1UAR4.ID19       14  Identifier 19
C1UAR4.ID18       13  Identifier 18
C1UAR4.ID17       12  Identifier 17
C1UAR4.ID16       11  Identifier 16
C1UAR4.ID15       10  Identifier 15
C1UAR4.ID14       9   Identifier 14
C1UAR4.ID13       8   Identifier 13
C1UAR4.ID28       7   Identifier 28
C1UAR4.ID27       6   Identifier 27
C1UAR4.ID26       5   Identifier 26
C1UAR4.ID25       4   Identifier 25
C1UAR4.ID24       3   Identifier 24
C1UAR4.ID23       2   Identifier 23
C1UAR4.ID22       1   Identifier 22
C1UAR4.ID21       0   Identifier 21
C1LAR4           0xEF44   CAN1 Lower Arbitration Register (msg. )
C1LAR4.ID4        15  Identifier 4 
C1LAR4.ID3        14  Identifier 3 
C1LAR4.ID2        13  Identifier 2 
C1LAR4.ID1        12  Identifier 1 
C1LAR4.ID0        11  Identifier 0 
C1LAR4.ID12       7   Identifier 12
C1LAR4.ID11       6   Identifier 11
C1LAR4.ID10       5   Identifier 10
C1LAR4.ID9        4   Identifier 9 
C1LAR4.ID8        3   Identifier 8 
C1LAR4.ID7        2   Identifier 7 
C1LAR4.ID6        1   Identifier 6 
C1LAR4.ID5        0   Identifier 5 
C1MCFG4          0xEF46   CAN1 Message Configuration Register (msg. )
C1MCFG4.DLC_7     7   Data Length Code - bit 7
C1MCFG4.DLC_6     6   Data Length Code - bit 6
C1MCFG4.DLC_5     5   Data Length Code - bit 5
C1MCFG4.DLC_4     4   Data Length Code - bit 4
C1MCFG4.DIR       3   Message Direction
C1MCFG4.XTD       2   Extended Identifier
C1MCR5           0xEF51   CAN1 Message Ctrl. Reg. (msg. )
C1MCR5.RMTPND_15        15  Remote Pending - bit 15
C1MCR5.RMTPND_14        14  Remote Pending - bit 14
C1MCR5.TXRQ_13          13  Transmit Request - bit 13
C1MCR5.TXRQ_12          12  Transmit Request - bit 12
C1MCR5.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C1MCR5.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C1MCR5.NEWDAT_9         9   New Data - bit 9
C1MCR5.NEWDAT_8         8   New Data - bit 8
C1MCR5.MSGVAL_7         7   Message Valid - bit 7
C1MCR5.MSGVAL_6         6   Message Valid - bit 6
C1MCR5.TXIE_5           5   Transmit Interrupt Enable - bit 5
C1MCR5.TXIE_4           4   Transmit Interrupt Enable - bit 4
C1MCR5.RXIE_3           3   Receive Interrupt Enable - bit 3
C1MCR5.RXIE_2           2   Receive Interrupt Enable - bit 2
C1MCR5.INTPND_1         1   Interrupt Pending - bit 1
C1MCR5.INTPND_0         0   Interrupt Pending - bit 0
C1UAR5           0xEF52   CAN1 Upper Arbitration Reg. (msg. )
C1UAR5.ID20       15  Identifier 20
C1UAR5.ID19       14  Identifier 19
C1UAR5.ID18       13  Identifier 18
C1UAR5.ID17       12  Identifier 17
C1UAR5.ID16       11  Identifier 16
C1UAR5.ID15       10  Identifier 15
C1UAR5.ID14       9   Identifier 14
C1UAR5.ID13       8   Identifier 13
C1UAR5.ID28       7   Identifier 28
C1UAR5.ID27       6   Identifier 27
C1UAR5.ID26       5   Identifier 26
C1UAR5.ID25       4   Identifier 25
C1UAR5.ID24       3   Identifier 24
C1UAR5.ID23       2   Identifier 23
C1UAR5.ID22       1   Identifier 22
C1UAR5.ID21       0   Identifier 21
C1LAR5           0xEF54   CAN1 Lower Arbitration Register (msg. )
C1LAR5.ID4        15  Identifier 4 
C1LAR5.ID3        14  Identifier 3 
C1LAR5.ID2        13  Identifier 2 
C1LAR5.ID1        12  Identifier 1 
C1LAR5.ID0        11  Identifier 0 
C1LAR5.ID12       7   Identifier 12
C1LAR5.ID11       6   Identifier 11
C1LAR5.ID10       5   Identifier 10
C1LAR5.ID9        4   Identifier 9 
C1LAR5.ID8        3   Identifier 8 
C1LAR5.ID7        2   Identifier 7 
C1LAR5.ID6        1   Identifier 6 
C1LAR5.ID5        0   Identifier 5 
C1MCFG5          0xEF56   CAN1 Message Configuration Register (msg. )
C1MCFG5.DLC_7     7   Data Length Code - bit 7
C1MCFG5.DLC_6     6   Data Length Code - bit 6
C1MCFG5.DLC_5     5   Data Length Code - bit 5
C1MCFG5.DLC_4     4   Data Length Code - bit 4
C1MCFG5.DIR       3   Message Direction
C1MCFG5.XTD       2   Extended Identifier
C1MCR6           0xEF61   CAN1 Message Ctrl. Reg. (msg. )
C1MCR6.RMTPND_15        15  Remote Pending - bit 15
C1MCR6.RMTPND_14        14  Remote Pending - bit 14
C1MCR6.TXRQ_13          13  Transmit Request - bit 13
C1MCR6.TXRQ_12          12  Transmit Request - bit 12
C1MCR6.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C1MCR6.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C1MCR6.NEWDAT_9         9   New Data - bit 9
C1MCR6.NEWDAT_8         8   New Data - bit 8
C1MCR6.MSGVAL_7         7   Message Valid - bit 7
C1MCR6.MSGVAL_6         6   Message Valid - bit 6
C1MCR6.TXIE_5           5   Transmit Interrupt Enable - bit 5
C1MCR6.TXIE_4           4   Transmit Interrupt Enable - bit 4
C1MCR6.RXIE_3           3   Receive Interrupt Enable - bit 3
C1MCR6.RXIE_2           2   Receive Interrupt Enable - bit 2
C1MCR6.INTPND_1         1   Interrupt Pending - bit 1
C1MCR6.INTPND_0         0   Interrupt Pending - bit 0
C1UAR6           0xEF62   CAN1 Upper Arbitration Reg. (msg. )
C1UAR6.ID20       15  Identifier 20
C1UAR6.ID19       14  Identifier 19
C1UAR6.ID18       13  Identifier 18
C1UAR6.ID17       12  Identifier 17
C1UAR6.ID16       11  Identifier 16
C1UAR6.ID15       10  Identifier 15
C1UAR6.ID14       9   Identifier 14
C1UAR6.ID13       8   Identifier 13
C1UAR6.ID28       7   Identifier 28
C1UAR6.ID27       6   Identifier 27
C1UAR6.ID26       5   Identifier 26
C1UAR6.ID25       4   Identifier 25
C1UAR6.ID24       3   Identifier 24
C1UAR6.ID23       2   Identifier 23
C1UAR6.ID22       1   Identifier 22
C1UAR6.ID21       0   Identifier 21
C1LAR6           0xEF64   CAN1 Lower Arbitration Register (msg. )
C1LAR6.ID4        15  Identifier 4 
C1LAR6.ID3        14  Identifier 3 
C1LAR6.ID2        13  Identifier 2 
C1LAR6.ID1        12  Identifier 1 
C1LAR6.ID0        11  Identifier 0 
C1LAR6.ID12       7   Identifier 12
C1LAR6.ID11       6   Identifier 11
C1LAR6.ID10       5   Identifier 10
C1LAR6.ID9        4   Identifier 9 
C1LAR6.ID8        3   Identifier 8 
C1LAR6.ID7        2   Identifier 7 
C1LAR6.ID6        1   Identifier 6 
C1LAR6.ID5        0   Identifier 5 
C1MCFG6          0xEF66   CAN1 Message Configuration Register (msg. )
C1MCFG6.DLC_7     7   Data Length Code - bit 7
C1MCFG6.DLC_6     6   Data Length Code - bit 6
C1MCFG6.DLC_5     5   Data Length Code - bit 5
C1MCFG6.DLC_4     4   Data Length Code - bit 4
C1MCFG6.DIR       3   Message Direction
C1MCFG6.XTD       2   Extended Identifier
C1MCR7           0xEF71   CAN1 Message Ctrl. Reg. (msg. )
C1MCR7.RMTPND_15        15  Remote Pending - bit 15
C1MCR7.RMTPND_14        14  Remote Pending - bit 14
C1MCR7.TXRQ_13          13  Transmit Request - bit 13
C1MCR7.TXRQ_12          12  Transmit Request - bit 12
C1MCR7.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C1MCR7.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C1MCR7.NEWDAT_9         9   New Data - bit 9
C1MCR7.NEWDAT_8         8   New Data - bit 8
C1MCR7.MSGVAL_7         7   Message Valid - bit 7
C1MCR7.MSGVAL_6         6   Message Valid - bit 6
C1MCR7.TXIE_5           5   Transmit Interrupt Enable - bit 5
C1MCR7.TXIE_4           4   Transmit Interrupt Enable - bit 4
C1MCR7.RXIE_3           3   Receive Interrupt Enable - bit 3
C1MCR7.RXIE_2           2   Receive Interrupt Enable - bit 2
C1MCR7.INTPND_1         1   Interrupt Pending - bit 1
C1MCR7.INTPND_0         0   Interrupt Pending - bit 0
C1UAR7           0xEF72   CAN1 Upper Arbitration Reg. (msg. )
C1UAR7.ID20       15  Identifier 20
C1UAR7.ID19       14  Identifier 19
C1UAR7.ID18       13  Identifier 18
C1UAR7.ID17       12  Identifier 17
C1UAR7.ID16       11  Identifier 16
C1UAR7.ID15       10  Identifier 15
C1UAR7.ID14       9   Identifier 14
C1UAR7.ID13       8   Identifier 13
C1UAR7.ID28       7   Identifier 28
C1UAR7.ID27       6   Identifier 27
C1UAR7.ID26       5   Identifier 26
C1UAR7.ID25       4   Identifier 25
C1UAR7.ID24       3   Identifier 24
C1UAR7.ID23       2   Identifier 23
C1UAR7.ID22       1   Identifier 22
C1UAR7.ID21       0   Identifier 21
C1LAR7           0xEF74   CAN1 Lower Arbitration Register (msg. )
C1LAR7.ID4        15  Identifier 4 
C1LAR7.ID3        14  Identifier 3 
C1LAR7.ID2        13  Identifier 2 
C1LAR7.ID1        12  Identifier 1 
C1LAR7.ID0        11  Identifier 0 
C1LAR7.ID12       7   Identifier 12
C1LAR7.ID11       6   Identifier 11
C1LAR7.ID10       5   Identifier 10
C1LAR7.ID9        4   Identifier 9 
C1LAR7.ID8        3   Identifier 8 
C1LAR7.ID7        2   Identifier 7 
C1LAR7.ID6        1   Identifier 6 
C1LAR7.ID5        0   Identifier 5 
C1MCFG7          0xEF76   CAN1 Message Configuration Register (msg. )
C1MCFG7.DLC_7     7   Data Length Code - bit 7
C1MCFG7.DLC_6     6   Data Length Code - bit 6
C1MCFG7.DLC_5     5   Data Length Code - bit 5
C1MCFG7.DLC_4     4   Data Length Code - bit 4
C1MCFG7.DIR       3   Message Direction
C1MCFG7.XTD       2   Extended Identifier
C1MCR8           0xEF81   CAN1 Message Ctrl. Reg. (msg. )
C1MCR8.RMTPND_15        15  Remote Pending - bit 15
C1MCR8.RMTPND_14        14  Remote Pending - bit 14
C1MCR8.TXRQ_13          13  Transmit Request - bit 13
C1MCR8.TXRQ_12          12  Transmit Request - bit 12
C1MCR8.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C1MCR8.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C1MCR8.NEWDAT_9         9   New Data - bit 9
C1MCR8.NEWDAT_8         8   New Data - bit 8
C1MCR8.MSGVAL_7         7   Message Valid - bit 7
C1MCR8.MSGVAL_6         6   Message Valid - bit 6
C1MCR8.TXIE_5           5   Transmit Interrupt Enable - bit 5
C1MCR8.TXIE_4           4   Transmit Interrupt Enable - bit 4
C1MCR8.RXIE_3           3   Receive Interrupt Enable - bit 3
C1MCR8.RXIE_2           2   Receive Interrupt Enable - bit 2
C1MCR8.INTPND_1         1   Interrupt Pending - bit 1
C1MCR8.INTPND_0         0   Interrupt Pending - bit 0
C1UAR8           0xEF82   CAN1 Upper Arbitration Reg. (msg. )
C1UAR8.ID20       15  Identifier 20
C1UAR8.ID19       14  Identifier 19
C1UAR8.ID18       13  Identifier 18
C1UAR8.ID17       12  Identifier 17
C1UAR8.ID16       11  Identifier 16
C1UAR8.ID15       10  Identifier 15
C1UAR8.ID14       9   Identifier 14
C1UAR8.ID13       8   Identifier 13
C1UAR8.ID28       7   Identifier 28
C1UAR8.ID27       6   Identifier 27
C1UAR8.ID26       5   Identifier 26
C1UAR8.ID25       4   Identifier 25
C1UAR8.ID24       3   Identifier 24
C1UAR8.ID23       2   Identifier 23
C1UAR8.ID22       1   Identifier 22
C1UAR8.ID21       0   Identifier 21
C1LAR8           0xEF84   CAN1 Lower Arbitration Register (msg. )
C1LAR8.ID4        15  Identifier 4 
C1LAR8.ID3        14  Identifier 3 
C1LAR8.ID2        13  Identifier 2 
C1LAR8.ID1        12  Identifier 1 
C1LAR8.ID0        11  Identifier 0 
C1LAR8.ID12       7   Identifier 12
C1LAR8.ID11       6   Identifier 11
C1LAR8.ID10       5   Identifier 10
C1LAR8.ID9        4   Identifier 9 
C1LAR8.ID8        3   Identifier 8 
C1LAR8.ID7        2   Identifier 7 
C1LAR8.ID6        1   Identifier 6 
C1LAR8.ID5        0   Identifier 5 
C1MCFG8          0xEF86   CAN1 Message Configuration Register (msg. )
C1MCFG8.DLC_7     7   Data Length Code - bit 7
C1MCFG8.DLC_6     6   Data Length Code - bit 6
C1MCFG8.DLC_5     5   Data Length Code - bit 5
C1MCFG8.DLC_4     4   Data Length Code - bit 4
C1MCFG8.DIR       3   Message Direction
C1MCFG8.XTD       2   Extended Identifier
C1MCR9           0xEF91   CAN1 Message Ctrl. Reg. (msg. )
C1MCR9.RMTPND_15        15  Remote Pending - bit 15
C1MCR9.RMTPND_14        14  Remote Pending - bit 14
C1MCR9.TXRQ_13          13  Transmit Request - bit 13
C1MCR9.TXRQ_12          12  Transmit Request - bit 12
C1MCR9.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C1MCR9.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C1MCR9.NEWDAT_9         9   New Data - bit 9
C1MCR9.NEWDAT_8         8   New Data - bit 8
C1MCR9.MSGVAL_7         7   Message Valid - bit 7
C1MCR9.MSGVAL_6         6   Message Valid - bit 6
C1MCR9.TXIE_5           5   Transmit Interrupt Enable - bit 5
C1MCR9.TXIE_4           4   Transmit Interrupt Enable - bit 4
C1MCR9.RXIE_3           3   Receive Interrupt Enable - bit 3
C1MCR9.RXIE_2           2   Receive Interrupt Enable - bit 2
C1MCR9.INTPND_1         1   Interrupt Pending - bit 1
C1MCR9.INTPND_0         0   Interrupt Pending - bit 0
C1UAR9           0xEF92   CAN1 Upper Arbitration Reg. (msg. )
C1UAR9.ID20       15  Identifier 20
C1UAR9.ID19       14  Identifier 19
C1UAR9.ID18       13  Identifier 18
C1UAR9.ID17       12  Identifier 17
C1UAR9.ID16       11  Identifier 16
C1UAR9.ID15       10  Identifier 15
C1UAR9.ID14       9   Identifier 14
C1UAR9.ID13       8   Identifier 13
C1UAR9.ID28       7   Identifier 28
C1UAR9.ID27       6   Identifier 27
C1UAR9.ID26       5   Identifier 26
C1UAR9.ID25       4   Identifier 25
C1UAR9.ID24       3   Identifier 24
C1UAR9.ID23       2   Identifier 23
C1UAR9.ID22       1   Identifier 22
C1UAR9.ID21       0   Identifier 21
C1LAR9           0xEF94   CAN1 Lower Arbitration Register (msg. )
C1LAR9.ID4        15  Identifier 4 
C1LAR9.ID3        14  Identifier 3 
C1LAR9.ID2        13  Identifier 2 
C1LAR9.ID1        12  Identifier 1 
C1LAR9.ID0        11  Identifier 0 
C1LAR9.ID12       7   Identifier 12
C1LAR9.ID11       6   Identifier 11
C1LAR9.ID10       5   Identifier 10
C1LAR9.ID9        4   Identifier 9 
C1LAR9.ID8        3   Identifier 8 
C1LAR9.ID7        2   Identifier 7 
C1LAR9.ID6        1   Identifier 6 
C1LAR9.ID5        0   Identifier 5 
C1MCFG9          0xEF96   CAN1 Message Configuration Register (msg. )
C1MCFG9.DLC_7     7   Data Length Code - bit 7
C1MCFG9.DLC_6     6   Data Length Code - bit 6
C1MCFG9.DLC_5     5   Data Length Code - bit 5
C1MCFG9.DLC_4     4   Data Length Code - bit 4
C1MCFG9.DIR       3   Message Direction
C1MCFG9.XTD       2   Extended Identifier
C1MCR10          0xEFA1   CAN1 Message Ctrl. Reg. (msg. )
C1MCR10.RMTPND_15        15  Remote Pending - bit 15
C1MCR10.RMTPND_14        14  Remote Pending - bit 14
C1MCR10.TXRQ_13          13  Transmit Request - bit 13
C1MCR10.TXRQ_12          12  Transmit Request - bit 12
C1MCR10.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C1MCR10.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C1MCR10.NEWDAT_9         9   New Data - bit 9
C1MCR10.NEWDAT_8         8   New Data - bit 8
C1MCR10.MSGVAL_7         7   Message Valid - bit 7
C1MCR10.MSGVAL_6         6   Message Valid - bit 6
C1MCR10.TXIE_5           5   Transmit Interrupt Enable - bit 5
C1MCR10.TXIE_4           4   Transmit Interrupt Enable - bit 4
C1MCR10.RXIE_3           3   Receive Interrupt Enable - bit 3
C1MCR10.RXIE_2           2   Receive Interrupt Enable - bit 2
C1MCR10.INTPND_1         1   Interrupt Pending - bit 1
C1MCR10.INTPND_0         0   Interrupt Pending - bit 0
C1UAR10          0xEFA2   CAN1 Upper Arbitration Reg. (msg. )
C1UAR10.ID20      15  Identifier 20
C1UAR10.ID19      14  Identifier 19
C1UAR10.ID18      13  Identifier 18
C1UAR10.ID17      12  Identifier 17
C1UAR10.ID16      11  Identifier 16
C1UAR10.ID15      10  Identifier 15
C1UAR10.ID14      9   Identifier 14
C1UAR10.ID13      8   Identifier 13
C1UAR10.ID28      7   Identifier 28
C1UAR10.ID27      6   Identifier 27
C1UAR10.ID26      5   Identifier 26
C1UAR10.ID25      4   Identifier 25
C1UAR10.ID24      3   Identifier 24
C1UAR10.ID23      2   Identifier 23
C1UAR10.ID22      1   Identifier 22
C1UAR10.ID21      0   Identifier 21
C1LAR10          0xEFA4   CAN1 Lower Arbitration Register (msg. )
C1LAR10.ID4       15  Identifier 4
C1LAR10.ID3       14  Identifier 3
C1LAR10.ID2       13  Identifier 2
C1LAR10.ID1       12  Identifier 1
C1LAR10.ID0       11  Identifier 0
C1LAR10.ID12      7   Identifier 12
C1LAR10.ID11      6   Identifier 11
C1LAR10.ID10      5   Identifier 10
C1LAR10.ID9       4   Identifier 9
C1LAR10.ID8       3   Identifier 8
C1LAR10.ID7       2   Identifier 7
C1LAR10.ID6       1   Identifier 6
C1LAR10.ID5       0   Identifier 5
C1MCFG10         0xEFA6   CAN1 Message Configuration Register (msg. )
C1MCFG10.DLC_7    7   Data Length Code - bit 7
C1MCFG10.DLC_6    6   Data Length Code - bit 6
C1MCFG10.DLC_5    5   Data Length Code - bit 5
C1MCFG10.DLC_4    4   Data Length Code - bit 4
C1MCFG10.DIR      3   Message Direction
C1MCFG10.XTD      2   Extended Identifier
C1MCR11          0xEFB1   CAN1 Message Ctrl. Reg. (msg. )
C1MCR11.RMTPND_15        15  Remote Pending - bit 15
C1MCR11.RMTPND_14        14  Remote Pending - bit 14
C1MCR11.TXRQ_13          13  Transmit Request - bit 13
C1MCR11.TXRQ_12          12  Transmit Request - bit 12
C1MCR11.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C1MCR11.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C1MCR11.NEWDAT_9         9   New Data - bit 9
C1MCR11.NEWDAT_8         8   New Data - bit 8
C1MCR11.MSGVAL_7         7   Message Valid - bit 7
C1MCR11.MSGVAL_6         6   Message Valid - bit 6
C1MCR11.TXIE_5           5   Transmit Interrupt Enable - bit 5
C1MCR11.TXIE_4           4   Transmit Interrupt Enable - bit 4
C1MCR11.RXIE_3           3   Receive Interrupt Enable - bit 3
C1MCR11.RXIE_2           2   Receive Interrupt Enable - bit 2
C1MCR11.INTPND_1         1   Interrupt Pending - bit 1
C1MCR11.INTPND_0         0   Interrupt Pending - bit 0
C1UAR11          0xEFB2   CAN1 Upper Arbitration Reg. (msg. )
C1UAR11.ID20      15  Identifier 20
C1UAR11.ID19      14  Identifier 19
C1UAR11.ID18      13  Identifier 18
C1UAR11.ID17      12  Identifier 17
C1UAR11.ID16      11  Identifier 16
C1UAR11.ID15      10  Identifier 15
C1UAR11.ID14      9   Identifier 14
C1UAR11.ID13      8   Identifier 13
C1UAR11.ID28      7   Identifier 28
C1UAR11.ID27      6   Identifier 27
C1UAR11.ID26      5   Identifier 26
C1UAR11.ID25      4   Identifier 25
C1UAR11.ID24      3   Identifier 24
C1UAR11.ID23      2   Identifier 23
C1UAR11.ID22      1   Identifier 22
C1UAR11.ID21      0   Identifier 21
C1LAR11          0xEFB4   CAN1 Lower Arbitration Register (msg. )
C1LAR11.ID4       15  Identifier 4
C1LAR11.ID3       14  Identifier 3
C1LAR11.ID2       13  Identifier 2
C1LAR11.ID1       12  Identifier 1
C1LAR11.ID0       11  Identifier 0
C1LAR11.ID12      7   Identifier 12
C1LAR11.ID11      6   Identifier 11
C1LAR11.ID10      5   Identifier 10
C1LAR11.ID9       4   Identifier 9
C1LAR11.ID8       3   Identifier 8
C1LAR11.ID7       2   Identifier 7
C1LAR11.ID6       1   Identifier 6
C1LAR11.ID5       0   Identifier 5
C1MCFG11         0xEFB6   CAN1 Message Configuration Register (msg. )
C1MCFG11.DLC_7    7   Data Length Code - bit 7
C1MCFG11.DLC_6    6   Data Length Code - bit 6
C1MCFG11.DLC_5    5   Data Length Code - bit 5
C1MCFG11.DLC_4    4   Data Length Code - bit 4
C1MCFG11.DIR      3   Message Direction
C1MCFG11.XTD      2   Extended Identifier
C1MCR12          0xEFC1   CAN1 Message Ctrl. Reg. (msg. )
C1MCR12.RMTPND_15        15  Remote Pending - bit 15
C1MCR12.RMTPND_14        14  Remote Pending - bit 14
C1MCR12.TXRQ_13          13  Transmit Request - bit 13
C1MCR12.TXRQ_12          12  Transmit Request - bit 12
C1MCR12.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C1MCR12.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C1MCR12.NEWDAT_9         9   New Data - bit 9
C1MCR12.NEWDAT_8         8   New Data - bit 8
C1MCR12.MSGVAL_7         7   Message Valid - bit 7
C1MCR12.MSGVAL_6         6   Message Valid - bit 6
C1MCR12.TXIE_5           5   Transmit Interrupt Enable - bit 5
C1MCR12.TXIE_4           4   Transmit Interrupt Enable - bit 4
C1MCR12.RXIE_3           3   Receive Interrupt Enable - bit 3
C1MCR12.RXIE_2           2   Receive Interrupt Enable - bit 2
C1MCR12.INTPND_1         1   Interrupt Pending - bit 1
C1MCR12.INTPND_0         0   Interrupt Pending - bit 0
C1UAR12          0xEFC1   CAN1 Upper Arbitration Reg. (msg. )
C1UAR12.ID20      15  Identifier 20
C1UAR12.ID19      14  Identifier 19
C1UAR12.ID18      13  Identifier 18
C1UAR12.ID17      12  Identifier 17
C1UAR12.ID16      11  Identifier 16
C1UAR12.ID15      10  Identifier 15
C1UAR12.ID14      9   Identifier 14
C1UAR12.ID13      8   Identifier 13
C1UAR12.ID28      7   Identifier 28
C1UAR12.ID27      6   Identifier 27
C1UAR12.ID26      5   Identifier 26
C1UAR12.ID25      4   Identifier 25
C1UAR12.ID24      3   Identifier 24
C1UAR12.ID23      2   Identifier 23
C1UAR12.ID22      1   Identifier 22
C1UAR12.ID21      0   Identifier 21
C1LAR12          0xEFC4   CAN1 Lower Arbitration Register (msg. )
C1LAR12.ID4       15  Identifier 4
C1LAR12.ID3       14  Identifier 3
C1LAR12.ID2       13  Identifier 2
C1LAR12.ID1       12  Identifier 1
C1LAR12.ID0       11  Identifier 0
C1LAR12.ID12      7   Identifier 12
C1LAR12.ID11      6   Identifier 11
C1LAR12.ID10      5   Identifier 10
C1LAR12.ID9       4   Identifier 9
C1LAR12.ID8       3   Identifier 8
C1LAR12.ID7       2   Identifier 7
C1LAR12.ID6       1   Identifier 6
C1LAR12.ID5       0   Identifier 5
C1MCFG12         0xEFC6   CAN1 Message Configuration Register (msg. )
C1MCFG12.DLC_7    7   Data Length Code - bit 7
C1MCFG12.DLC_6    6   Data Length Code - bit 6
C1MCFG12.DLC_5    5   Data Length Code - bit 5
C1MCFG12.DLC_4    4   Data Length Code - bit 4
C1MCFG12.DIR      3   Message Direction
C1MCFG12.XTD      2   Extended Identifier
C1MCR13          0xEFD1   CAN1 Message Ctrl. Reg. (msg. )
C1MCR13.RMTPND_15        15  Remote Pending - bit 15
C1MCR13.RMTPND_14        14  Remote Pending - bit 14
C1MCR13.TXRQ_13          13  Transmit Request - bit 13
C1MCR13.TXRQ_12          12  Transmit Request - bit 12
C1MCR13.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C1MCR13.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C1MCR13.NEWDAT_9         9   New Data - bit 9
C1MCR13.NEWDAT_8         8   New Data - bit 8
C1MCR13.MSGVAL_7         7   Message Valid - bit 7
C1MCR13.MSGVAL_6         6   Message Valid - bit 6
C1MCR13.TXIE_5           5   Transmit Interrupt Enable - bit 5
C1MCR13.TXIE_4           4   Transmit Interrupt Enable - bit 4
C1MCR13.RXIE_3           3   Receive Interrupt Enable - bit 3
C1MCR13.RXIE_2           2   Receive Interrupt Enable - bit 2
C1MCR13.INTPND_1         1   Interrupt Pending - bit 1
C1MCR13.INTPND_0         0   Interrupt Pending - bit 0
C1UAR13          0xEFD2   CAN1 Upper Arbitration Reg. (msg. )
C1UAR13.ID20      15  Identifier 20
C1UAR13.ID19      14  Identifier 19
C1UAR13.ID18      13  Identifier 18
C1UAR13.ID17      12  Identifier 17
C1UAR13.ID16      11  Identifier 16
C1UAR13.ID15      10  Identifier 15
C1UAR13.ID14      9   Identifier 14
C1UAR13.ID13      8   Identifier 13
C1UAR13.ID28      7   Identifier 28
C1UAR13.ID27      6   Identifier 27
C1UAR13.ID26      5   Identifier 26
C1UAR13.ID25      4   Identifier 25
C1UAR13.ID24      3   Identifier 24
C1UAR13.ID23      2   Identifier 23
C1UAR13.ID22      1   Identifier 22
C1UAR13.ID21      0   Identifier 21
C1LAR13          0xEFD4   CAN1 Lower Arbitration Register (msg. )
C1LAR13.ID4       15  Identifier 4
C1LAR13.ID3       14  Identifier 3
C1LAR13.ID2       13  Identifier 2
C1LAR13.ID1       12  Identifier 1
C1LAR13.ID0       11  Identifier 0
C1LAR13.ID12      7   Identifier 12
C1LAR13.ID11      6   Identifier 11
C1LAR13.ID10      5   Identifier 10
C1LAR13.ID9       4   Identifier 9
C1LAR13.ID8       3   Identifier 8
C1LAR13.ID7       2   Identifier 7
C1LAR13.ID6       1   Identifier 6
C1LAR13.ID5       0   Identifier 5
C1MCFG13         0xEFD6   CAN1 Message Configuration Register (msg. )
C1MCFG13.DLC_7    7   Data Length Code - bit 7
C1MCFG13.DLC_6    6   Data Length Code - bit 6
C1MCFG13.DLC_5    5   Data Length Code - bit 5
C1MCFG13.DLC_4    4   Data Length Code - bit 4
C1MCFG13.DIR      3   Message Direction
C1MCFG13.XTD      2   Extended Identifier
C1MCR14          0xEFE1   CAN1 Message Ctrl. Reg. (msg. )
C1MCR14.RMTPND_15        15  Remote Pending - bit 15
C1MCR14.RMTPND_14        14  Remote Pending - bit 14
C1MCR14.TXRQ_13          13  Transmit Request - bit 13
C1MCR14.TXRQ_12          12  Transmit Request - bit 12
C1MCR14.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C1MCR14.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C1MCR14.NEWDAT_9         9   New Data - bit 9
C1MCR14.NEWDAT_8         8   New Data - bit 8
C1MCR14.MSGVAL_7         7   Message Valid - bit 7
C1MCR14.MSGVAL_6         6   Message Valid - bit 6
C1MCR14.TXIE_5           5   Transmit Interrupt Enable - bit 5
C1MCR14.TXIE_4           4   Transmit Interrupt Enable - bit 4
C1MCR14.RXIE_3           3   Receive Interrupt Enable - bit 3
C1MCR14.RXIE_2           2   Receive Interrupt Enable - bit 2
C1MCR14.INTPND_1         1   Interrupt Pending - bit 1
C1MCR14.INTPND_0         0   Interrupt Pending - bit 0
C1UAR14          0xEFE2   CAN1 Upper Arbitration Reg. (msg. )
C1UAR14.ID20      15  Identifier 20
C1UAR14.ID19      14  Identifier 19
C1UAR14.ID18      13  Identifier 18
C1UAR14.ID17      12  Identifier 17
C1UAR14.ID16      11  Identifier 16
C1UAR14.ID15      10  Identifier 15
C1UAR14.ID14      9   Identifier 14
C1UAR14.ID13      8   Identifier 13
C1UAR14.ID28      7   Identifier 28
C1UAR14.ID27      6   Identifier 27
C1UAR14.ID26      5   Identifier 26
C1UAR14.ID25      4   Identifier 25
C1UAR14.ID24      3   Identifier 24
C1UAR14.ID23      2   Identifier 23
C1UAR14.ID22      1   Identifier 22
C1UAR14.ID21      0   Identifier 21
C1LAR14          0xEFE4   CAN1 Lower Arbitration Register (msg. )
C1LAR14.ID4       15  Identifier 4
C1LAR14.ID3       14  Identifier 3
C1LAR14.ID2       13  Identifier 2
C1LAR14.ID1       12  Identifier 1
C1LAR14.ID0       11  Identifier 0
C1LAR14.ID12      7   Identifier 12
C1LAR14.ID11      6   Identifier 11
C1LAR14.ID10      5   Identifier 10
C1LAR14.ID9       4   Identifier 9
C1LAR14.ID8       3   Identifier 8
C1LAR14.ID7       2   Identifier 7
C1LAR14.ID6       1   Identifier 6
C1LAR14.ID5       0   Identifier 5
C1MCFG14         0xEFE6   CAN1 Message Configuration Register (msg. )
C1MCFG14.DLC_7    7   Data Length Code - bit 7
C1MCFG14.DLC_6    6   Data Length Code - bit 6
C1MCFG14.DLC_5    5   Data Length Code - bit 5
C1MCFG14.DLC_4    4   Data Length Code - bit 4
C1MCFG14.DIR      3   Message Direction
C1MCFG14.XTD      2   Extended Identifier
C1MCR15          0xEFF1   CAN1 Message Ctrl. Reg. (msg. )
C1MCR15.RMTPND_15        15  Remote Pending - bit 15
C1MCR15.RMTPND_14        14  Remote Pending - bit 14
C1MCR15.TXRQ_13          13  Transmit Request - bit 13
C1MCR15.TXRQ_12          12  Transmit Request - bit 12
C1MCR15.CPUUPD_MSGLST_11 11  CPU Update / Message Lost- bit 11
C1MCR15.CPUUPD_MSGLST_10 10  CPU Update / Message Lost- bit 10
C1MCR15.NEWDAT_9         9   New Data - bit 9
C1MCR15.NEWDAT_8         8   New Data - bit 8
C1MCR15.MSGVAL_7         7   Message Valid - bit 7
C1MCR15.MSGVAL_6         6   Message Valid - bit 6
C1MCR15.TXIE_5           5   Transmit Interrupt Enable - bit 5
C1MCR15.TXIE_4           4   Transmit Interrupt Enable - bit 4
C1MCR15.RXIE_3           3   Receive Interrupt Enable - bit 3
C1MCR15.RXIE_2           2   Receive Interrupt Enable - bit 2
C1MCR15.INTPND_1         1   Interrupt Pending - bit 1
C1MCR15.INTPND_0         0   Interrupt Pending - bit 0
C1UAR15          0xEFF2   CAN1 Upper Arbitration Reg. (msg. )
C1UAR15.ID20      15  Identifier 20
C1UAR15.ID19      14  Identifier 19
C1UAR15.ID18      13  Identifier 18
C1UAR15.ID17      12  Identifier 17
C1UAR15.ID16      11  Identifier 16
C1UAR15.ID15      10  Identifier 15
C1UAR15.ID14      9   Identifier 14
C1UAR15.ID13      8   Identifier 13
C1UAR15.ID28      7   Identifier 28
C1UAR15.ID27      6   Identifier 27
C1UAR15.ID26      5   Identifier 26
C1UAR15.ID25      4   Identifier 25
C1UAR15.ID24      3   Identifier 24
C1UAR15.ID23      2   Identifier 23
C1UAR15.ID22      1   Identifier 22
C1UAR15.ID21      0   Identifier 21
C1LAR15          0xEFF4   CAN1 Lower Arbitration Register (msg. )
C1LAR15.ID4       15  Identifier 4
C1LAR15.ID3       14  Identifier 3
C1LAR15.ID2       13  Identifier 2
C1LAR15.ID1       12  Identifier 1
C1LAR15.ID0       11  Identifier 0
C1LAR15.ID12      7   Identifier 12
C1LAR15.ID11      6   Identifier 11
C1LAR15.ID10      5   Identifier 10
C1LAR15.ID9       4   Identifier 9
C1LAR15.ID8       3   Identifier 8
C1LAR15.ID7       2   Identifier 7
C1LAR15.ID6       1   Identifier 6
C1LAR15.ID5       0   Identifier 5
C1MCFG15         0xEFF6   CAN1 Message Configuration Register (msg. )
C1MCFG15.DLC_7    7   Data Length Code - bit 7
C1MCFG15.DLC_6    6   Data Length Code - bit 6
C1MCFG15.DLC_5    5   Data Length Code - bit 5
C1MCFG15.DLC_4    4   Data Length Code - bit 4
C1MCFG15.DIR      3   Message Direction
C1MCFG15.XTD      2   Extended Identifier
T7               0xF050   CAPCOM Timer 7 Register
T8               0xF052   CAPCOM Timer 8 Register
T7REL            0xF054   CAPCOM Timer 7 Reload Register
T8REL            0xF056   CAPCOM Timer 8 Reload Register
IDPROG           0xF078   Identifier
IDMEM            0xF07A   Identifier
IDCHIP           0xF07C   Identifier
IDMANUF          0xF07E   Identifier
POCON0L          0xF080   Port P0L Output Control Register
POCON0L.PN3DC_15  15  Port Nibble 3 Driver Characteristic - bit 15
POCON0L.PN3DC_14  14  Port Nibble 3 Edge Characteristic - bit 14
POCON0L.PN3EC_13  13  Port Nibble 3 Driver Characteristic - bit 13
POCON0L.PN3EC_12  12  Port Nibble 3 Edge Characteristic - bit 12
POCON0L.PN2DC_11  11  Port Nibble 2 Driver Characteristic - bit 11
POCON0L.PN2DC_10  10  Port Nibble 2 Edge Characteristic - bit 10
POCON0L.PN2EC_9   9   Port Nibble 2 Driver Characteristic - bit 9 
POCON0L.PN2EC_8   8   Port Nibble 2 Edge Characteristic - bit 8 
POCON0L.PN1DC_7   7   Port Nibble 1 Driver Characteristic - bit 7 
POCON0L.PN1DC_6   6   Port Nibble 1 Edge Characteristic - bit 6 
POCON0L.PN1EC_5   5   Port Nibble 1 Driver Characteristic - bit 5 
POCON0L.PN1EC_4   4   Port Nibble 1 Edge Characteristic - bit 4 
POCON0L.PN0DC_3   3   Port Nibble 0 Driver Characteristic - bit 3 
POCON0L.PN0DC_2   2   Port Nibble 0 Edge Characteristic - bit 2 
POCON0L.PN0EC_1   1   Port Nibble 0 Driver Characteristic - bit 1 
POCON0L.PN0EC_0   0   Port Nibble 0 Edge Characteristic - bit 0 
POCON0H          0xF082   Port P0H Output Control Register
POCON0H.PN3DC_15  15  Port Nibble 3 Driver Characteristic - bit 15
POCON0H.PN3DC_14  14  Port Nibble 3 Edge Characteristic - bit 14
POCON0H.PN3EC_13  13  Port Nibble 3 Driver Characteristic - bit 13
POCON0H.PN3EC_12  12  Port Nibble 3 Edge Characteristic - bit 12
POCON0H.PN2DC_11  11  Port Nibble 2 Driver Characteristic - bit 11
POCON0H.PN2DC_10  10  Port Nibble 2 Edge Characteristic - bit 10
POCON0H.PN2EC_9   9   Port Nibble 2 Driver Characteristic - bit 9 
POCON0H.PN2EC_8   8   Port Nibble 2 Edge Characteristic - bit 8 
POCON0H.PN1DC_7   7   Port Nibble 1 Driver Characteristic - bit 7 
POCON0H.PN1DC_6   6   Port Nibble 1 Edge Characteristic - bit 6 
POCON0H.PN1EC_5   5   Port Nibble 1 Driver Characteristic - bit 5 
POCON0H.PN1EC_4   4   Port Nibble 1 Edge Characteristic - bit 4 
POCON0H.PN0DC_3   3   Port Nibble 0 Driver Characteristic - bit 3 
POCON0H.PN0DC_2   2   Port Nibble 0 Edge Characteristic - bit 2 
POCON0H.PN0EC_1   1   Port Nibble 0 Driver Characteristic - bit 1 
POCON0H.PN0EC_0   0   Port Nibble 0 Edge Characteristic - bit 0 
POCON1L          0xF084   Port P1L Output Control Register
POCON1L.PN3DC_15  15  Port Nibble 3 Driver Characteristic - bit 15
POCON1L.PN3DC_14  14  Port Nibble 3 Edge Characteristic - bit 14
POCON1L.PN3EC_13  13  Port Nibble 3 Driver Characteristic - bit 13
POCON1L.PN3EC_12  12  Port Nibble 3 Edge Characteristic - bit 12
POCON1L.PN2DC_11  11  Port Nibble 2 Driver Characteristic - bit 11
POCON1L.PN2DC_10  10  Port Nibble 2 Edge Characteristic - bit 10
POCON1L.PN2EC_9   9   Port Nibble 2 Driver Characteristic - bit 9 
POCON1L.PN2EC_8   8   Port Nibble 2 Edge Characteristic - bit 8 
POCON1L.PN1DC_7   7   Port Nibble 1 Driver Characteristic - bit 7 
POCON1L.PN1DC_6   6   Port Nibble 1 Edge Characteristic - bit 6 
POCON1L.PN1EC_5   5   Port Nibble 1 Driver Characteristic - bit 5 
POCON1L.PN1EC_4   4   Port Nibble 1 Edge Characteristic - bit 4 
POCON1L.PN0DC_3   3   Port Nibble 0 Driver Characteristic - bit 3 
POCON1L.PN0DC_2   2   Port Nibble 0 Edge Characteristic - bit 2 
POCON1L.PN0EC_1   1   Port Nibble 0 Driver Characteristic - bit 1 
POCON1L.PN0EC_0   0   Port Nibble 0 Edge Characteristic - bit 0 
POCON1H          0xF086   Port P1H Output Control Register
POCON1H.PN3DC_15  15  Port Nibble 3 Driver Characteristic - bit 15
POCON1H.PN3DC_14  14  Port Nibble 3 Edge Characteristic - bit 14
POCON1H.PN3EC_13  13  Port Nibble 3 Driver Characteristic - bit 13
POCON1H.PN3EC_12  12  Port Nibble 3 Edge Characteristic - bit 12
POCON1H.PN2DC_11  11  Port Nibble 2 Driver Characteristic - bit 11
POCON1H.PN2DC_10  10  Port Nibble 2 Edge Characteristic - bit 10
POCON1H.PN2EC_9   9   Port Nibble 2 Driver Characteristic - bit 9 
POCON1H.PN2EC_8   8   Port Nibble 2 Edge Characteristic - bit 8 
POCON1H.PN1DC_7   7   Port Nibble 1 Driver Characteristic - bit 7 
POCON1H.PN1DC_6   6   Port Nibble 1 Edge Characteristic - bit 6 
POCON1H.PN1EC_5   5   Port Nibble 1 Driver Characteristic - bit 5 
POCON1H.PN1EC_4   4   Port Nibble 1 Edge Characteristic - bit 4 
POCON1H.PN0DC_3   3   Port Nibble 0 Driver Characteristic - bit 3 
POCON1H.PN0DC_2   2   Port Nibble 0 Edge Characteristic - bit 2 
POCON1H.PN0EC_1   1   Port Nibble 0 Driver Characteristic - bit 1 
POCON1H.PN0EC_0   0   Port Nibble 0 Edge Characteristic - bit 0 
POCON2           0xF088   Port P2 Output Control Register
POCON2.PN3DC_15   15  Port Nibble 3 Driver Characteristic - bit 15
POCON2.PN3DC_14   14  Port Nibble 3 Edge Characteristic - bit 14
POCON2.PN3EC_13   13  Port Nibble 3 Driver Characteristic - bit 13
POCON2.PN3EC_12   12  Port Nibble 3 Edge Characteristic - bit 12
POCON2.PN2DC_11   11  Port Nibble 2 Driver Characteristic - bit 11
POCON2.PN2DC_10   10  Port Nibble 2 Edge Characteristic - bit 10
POCON2.PN2EC_9    9   Port Nibble 2 Driver Characteristic - bit 9
POCON2.PN2EC_8    8   Port Nibble 2 Edge Characteristic - bit 8
POCON2.PN1DC_7    7   Port Nibble 1 Driver Characteristic - bit 7
POCON2.PN1DC_6    6   Port Nibble 1 Edge Characteristic - bit 6
POCON2.PN1EC_5    5   Port Nibble 1 Driver Characteristic - bit 5
POCON2.PN1EC_4    4   Port Nibble 1 Edge Characteristic - bit 4
POCON2.PN0DC_3    3   Port Nibble 0 Driver Characteristic - bit 3
POCON2.PN0DC_2    2   Port Nibble 0 Edge Characteristic - bit 2
POCON2.PN0EC_1    1   Port Nibble 0 Driver Characteristic - bit 1
POCON2.PN0EC_0    0   Port Nibble 0 Edge Characteristic - bit 0
POCON3           0xF08A   Port P3 Output Control Register
POCON3.PN3DC_15   15  Port Nibble 3 Driver Characteristic - bit 15
POCON3.PN3DC_14   14  Port Nibble 3 Edge Characteristic - bit 14
POCON3.PN3EC_13   13  Port Nibble 3 Driver Characteristic - bit 13
POCON3.PN3EC_12   12  Port Nibble 3 Edge Characteristic - bit 12
POCON3.PN2DC_11   11  Port Nibble 2 Driver Characteristic - bit 11
POCON3.PN2DC_10   10  Port Nibble 2 Edge Characteristic - bit 10
POCON3.PN2EC_9    9   Port Nibble 2 Driver Characteristic - bit 9
POCON3.PN2EC_8    8   Port Nibble 2 Edge Characteristic - bit 8
POCON3.PN1DC_7    7   Port Nibble 1 Driver Characteristic - bit 7
POCON3.PN1DC_6    6   Port Nibble 1 Edge Characteristic - bit 6
POCON3.PN1EC_5    5   Port Nibble 1 Driver Characteristic - bit 5
POCON3.PN1EC_4    4   Port Nibble 1 Edge Characteristic - bit 4
POCON3.PN0DC_3    3   Port Nibble 0 Driver Characteristic - bit 3
POCON3.PN0DC_2    2   Port Nibble 0 Edge Characteristic - bit 2
POCON3.PN0EC_1    1   Port Nibble 0 Driver Characteristic - bit 1
POCON3.PN0EC_0    0   Port Nibble 0 Edge Characteristic - bit 0
POCON4           0xF08C   Port P4 Output Control Register
POCON4.PN3DC_15   15  Port Nibble 3 Driver Characteristic - bit 15
POCON4.PN3DC_14   14  Port Nibble 3 Edge Characteristic - bit 14
POCON4.PN3EC_13   13  Port Nibble 3 Driver Characteristic - bit 13
POCON4.PN3EC_12   12  Port Nibble 3 Edge Characteristic - bit 12
POCON4.PN2DC_11   11  Port Nibble 2 Driver Characteristic - bit 11
POCON4.PN2DC_10   10  Port Nibble 2 Edge Characteristic - bit 10
POCON4.PN2EC_9    9   Port Nibble 2 Driver Characteristic - bit 9
POCON4.PN2EC_8    8   Port Nibble 2 Edge Characteristic - bit 8
POCON4.PN1DC_7    7   Port Nibble 1 Driver Characteristic - bit 7
POCON4.PN1DC_6    6   Port Nibble 1 Edge Characteristic - bit 6
POCON4.PN1EC_5    5   Port Nibble 1 Driver Characteristic - bit 5
POCON4.PN1EC_4    4   Port Nibble 1 Edge Characteristic - bit 4
POCON4.PN0DC_3    3   Port Nibble 0 Driver Characteristic - bit 3
POCON4.PN0DC_2    2   Port Nibble 0 Edge Characteristic - bit 2
POCON4.PN0EC_1    1   Port Nibble 0 Driver Characteristic - bit 1
POCON4.PN0EC_0    0   Port Nibble 0 Edge Characteristic - bit 0
POCON6           0xF08E   Port P6 Output Control Register
POCON6.PN3DC_15   15  Port Nibble 3 Driver Characteristic - bit 15
POCON6.PN3DC_14   14  Port Nibble 3 Edge Characteristic - bit 14
POCON6.PN3EC_13   13  Port Nibble 3 Driver Characteristic - bit 13
POCON6.PN3EC_12   12  Port Nibble 3 Edge Characteristic - bit 12
POCON6.PN2DC_11   11  Port Nibble 2 Driver Characteristic - bit 11
POCON6.PN2DC_10   10  Port Nibble 2 Edge Characteristic - bit 10
POCON6.PN2EC_9    9   Port Nibble 2 Driver Characteristic - bit 9
POCON6.PN2EC_8    8   Port Nibble 2 Edge Characteristic - bit 8
POCON6.PN1DC_7    7   Port Nibble 1 Driver Characteristic - bit 7
POCON6.PN1DC_6    6   Port Nibble 1 Edge Characteristic - bit 6
POCON6.PN1EC_5    5   Port Nibble 1 Driver Characteristic - bit 5
POCON6.PN1EC_4    4   Port Nibble 1 Edge Characteristic - bit 4
POCON6.PN0DC_3    3   Port Nibble 0 Driver Characteristic - bit 3
POCON6.PN0DC_2    2   Port Nibble 0 Edge Characteristic - bit 2
POCON6.PN0EC_1    1   Port Nibble 0 Driver Characteristic - bit 1
POCON6.PN0EC_0    0   Port Nibble 0 Edge Characteristic - bit 0
POCON7           0xF090   Port P7 Output Control Register
POCON7.PN3DC_15   15  Port Nibble 3 Driver Characteristic - bit 15
POCON7.PN3DC_14   14  Port Nibble 3 Edge Characteristic - bit 14
POCON7.PN3EC_13   13  Port Nibble 3 Driver Characteristic - bit 13
POCON7.PN3EC_12   12  Port Nibble 3 Edge Characteristic - bit 12
POCON7.PN2DC_11   11  Port Nibble 2 Driver Characteristic - bit 11
POCON7.PN2DC_10   10  Port Nibble 2 Edge Characteristic - bit 10
POCON7.PN2EC_9    9   Port Nibble 2 Driver Characteristic - bit 9
POCON7.PN2EC_8    8   Port Nibble 2 Edge Characteristic - bit 8
POCON7.PN1DC_7    7   Port Nibble 1 Driver Characteristic - bit 7
POCON7.PN1DC_6    6   Port Nibble 1 Edge Characteristic - bit 6
POCON7.PN1EC_5    5   Port Nibble 1 Driver Characteristic - bit 5
POCON7.PN1EC_4    4   Port Nibble 1 Edge Characteristic - bit 4
POCON7.PN0DC_3    3   Port Nibble 0 Driver Characteristic - bit 3
POCON7.PN0DC_2    2   Port Nibble 0 Edge Characteristic - bit 2
POCON7.PN0EC_1    1   Port Nibble 0 Driver Characteristic - bit 1
POCON7.PN0EC_0    0   Port Nibble 0 Edge Characteristic - bit 0
ADDAT2           0xF0A0   A/D Converter 2 Result Register
ADDAT2.CHNR_15    15  Channel Number - bit 15
ADDAT2.CHNR_14    14  Channel Number - bit 14
ADDAT2.CHNR_13    13  Channel Number - bit 13
ADDAT2.CHNR_12    12  Channel Number - bit 12
ADDAT2.ADRES_9    9   A/D Conversion Result - bit 9
ADDAT2.ADRES_8    8   A/D Conversion Result - bit 8
ADDAT2.ADRES_7    7   A/D Conversion Result - bit 7
ADDAT2.ADRES_6    6   A/D Conversion Result - bit 6
ADDAT2.ADRES_5    5   A/D Conversion Result - bit 5
ADDAT2.ADRES_4    4   A/D Conversion Result - bit 4
ADDAT2.ADRES_3    3   A/D Conversion Result - bit 3
ADDAT2.ADRES_2    2   A/D Conversion Result - bit 2
ADDAT2.ADRES_1    1   A/D Conversion Result - bit 1
ADDAT2.ADRES_0    0   A/D Conversion Result - bit 0
POCON20          0xF0AA   Dedicated Pin Output Control Register
POCON20.PN3DC_15  15  Port Nibble 3 Driver Characteristic - bit 15
POCON20.PN3DC_14  14  Port Nibble 3 Edge Characteristic - bit 14
POCON20.PN3EC_13  13  Port Nibble 3 Driver Characteristic - bit 13
POCON20.PN3EC_12  12  Port Nibble 3 Edge Characteristic - bit 12
POCON20.PN2DC_11  11  Port Nibble 2 Driver Characteristic - bit 11
POCON20.PN2DC_10  10  Port Nibble 2 Edge Characteristic - bit 10
POCON20.PN2EC_9   9   Port Nibble 2 Driver Characteristic - bit 9
POCON20.PN2EC_8   8   Port Nibble 2 Edge Characteristic - bit 8
POCON20.PN1DC_7   7   Port Nibble 1 Driver Characteristic - bit 7
POCON20.PN1DC_6   6   Port Nibble 1 Edge Characteristic - bit 6
POCON20.PN1EC_5   5   Port Nibble 1 Driver Characteristic - bit 5
POCON20.PN1EC_4   4   Port Nibble 1 Edge Characteristic - bit 4
POCON20.PN0DC_3   3   Port Nibble 0 Driver Characteristic - bit 3
POCON20.PN0DC_2   2   Port Nibble 0 Edge Characteristic - bit 2
POCON20.PN0EC_1   1   Port Nibble 0 Driver Characteristic - bit 1
POCON20.PN0EC_0   0   Port Nibble 0 Edge Characteristic - bit 0
SSCTB            0xF0B0   SSC Transmit Buffer
SSCRB            0xF0B2   SSC Receive Buffer
SSCBR            0xF0B4   SSC Baudrate Register
T14REL           0xF0D0   RTC Timer 14 Reload Register
T14              0xF0D2   RTC Timer 14 Register
RTCL             0xF0D4   RTC Low Register
RTCH             0xF0D6   RTC High Register
DP0L             0xF100   P0L Direction Control Register
DP0L.DP0L7        7   Port direction register DP0L bit 7
DP0L.DP0L6        6   Port direction register DP0L bit 6
DP0L.DP0L5        5   Port direction register DP0L bit 5
DP0L.DP0L4        4   Port direction register DP0L bit 4
DP0L.DP0L3        3   Port direction register DP0L bit 3
DP0L.DP0L2        2   Port direction register DP0L bit 2
DP0L.DP0L1        1   Port direction register DP0L bit 1
DP0L.DP0L0        0   Port direction register DP0L bit 0
DP0H             0xF102   P0H Direction Control Register
DP0H.DP0H7        7   Port direction register DP0H bit 7
DP0H.DP0H6        6   Port direction register DP0H bit 6
DP0H.DP0H5        5   Port direction register DP0H bit 5
DP0H.DP0H4        4   Port direction register DP0H bit 4
DP0H.DP0H3        3   Port direction register DP0H bit 3
DP0H.DP0H2        2   Port direction register DP0H bit 2
DP0H.DP0H1        1   Port direction register DP0H bit 1
DP0H.DP0H0        0   Port direction register DP0H bit 0
DP1L             0xF104   P1L Direction Control Register
DP1L.DP1L7        7   Port direction register DP1L bit 7
DP1L.DP1L6        6   Port direction register DP1L bit 6
DP1L.DP1L5        5   Port direction register DP1L bit 5
DP1L.DP1L4        4   Port direction register DP1L bit 4
DP1L.DP1L3        3   Port direction register DP1L bit 3
DP1L.DP1L2        2   Port direction register DP1L bit 2
DP1L.DP1L1        1   Port direction register DP1L bit 1
DP1L.DP1L0        0   Port direction register DP1L bit 0
DP1H             0xF106   P1H Direction Control Register
DP1H.DP1H7        7   Port direction register DP1H bit 7
DP1H.DP1H6        6   Port direction register DP1H bit 6
DP1H.DP1H5        5   Port direction register DP1H bit 5
DP1H.DP1H4        4   Port direction register DP1H bit 4
DP1H.DP1H3        3   Port direction register DP1H bit 3
DP1H.DP1H2        2   Port direction register DP1H bit 2
DP1H.DP1H1        1   Port direction register DP1H bit 1
DP1H.DP1H0        0   Port direction register DP1L bit 0
RP0H             0xF108   System Startup Configuration Register (read only)
RP0H.CLKCFG_7     7   Clock Generation Mode Configuration - bit 7
RP0H.CLKCFG_6     6   Clock Generation Mode Configuration - bit 6
RP0H.CLKCFG_5     5   Clock Generation Mode Configuration - bit 5
RP0H.SALSEL_4     4   Segment Address Line Selection - bit 4
RP0H.SALSEL_3     3   Segment Address Line Selection - bit 3
RP0H.CSSEL_2      2   Chip Select Line Selection - bit 2
RP0H.CSSEL_1      1   Chip Select Line Selection - bit 1
RP0H.WRC          0   Write Configuration
CC16IC           0xF160   CAPCOM Register 16 Interrupt Ctrl. Reg.
CC16IC.CC16IR     7   Interrupt Request Flag
CC16IC.CC16IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC16IC.ILVL_5     5   Interrupt Priority Level - bit 5
CC16IC.ILVL_4     4   Interrupt Priority Level - bit 4
CC16IC.ILVL_3     3   Interrupt Priority Level - bit 3
CC16IC.ILVL_2     2   Interrupt Priority Level - bit 2
CC16IC.GLVL_1     1   Group Level - bit 1
CC16IC.GLVL_0     0   Group Level - bit 0
CC17IC           0xF162   CAPCOM Register 17 Interrupt Ctrl. Reg.
CC17IC.CC17IR     7   Interrupt Request Flag
CC17IC.CC17IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC17IC.ILVL_5     5   Interrupt Priority Level - bit 5
CC17IC.ILVL_4     4   Interrupt Priority Level - bit 4
CC17IC.ILVL_3     3   Interrupt Priority Level - bit 3
CC17IC.ILVL_2     2   Interrupt Priority Level - bit 2
CC17IC.GLVL_1     1   Group Level - bit 1
CC17IC.GLVL_0     0   Group Level - bit 0
CC18IC           0xF164   CAPCOM Register 18 Interrupt Ctrl. Reg.
CC18IC.CC18IR     7   Interrupt Request Flag
CC18IC.CC18IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC18IC.ILVL_5     5   Interrupt Priority Level - bit 5
CC18IC.ILVL_4     4   Interrupt Priority Level - bit 4
CC18IC.ILVL_3     3   Interrupt Priority Level - bit 3
CC18IC.ILVL_2     2   Interrupt Priority Level - bit 2
CC18IC.GLVL_1     1   Group Level - bit 1
CC18IC.GLVL_0     0   Group Level - bit 0
CC19IC           0xF166   CAPCOM Register 19 Interrupt Ctrl. Reg.
CC19IC.CC19IR     7   Interrupt Request Flag
CC19IC.CC19IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC19IC.ILVL_5     5   Interrupt Priority Level - bit 5
CC19IC.ILVL_4     4   Interrupt Priority Level - bit 4
CC19IC.ILVL_3     3   Interrupt Priority Level - bit 3
CC19IC.ILVL_2     2   Interrupt Priority Level - bit 2
CC19IC.GLVL_1     1   Group Level - bit 1
CC19IC.GLVL_0     0   Group Level - bit 0
CC20IC           0xF168   CAPCOM Register 20 Interrupt Ctrl. Reg.
CC20IC.CC20IR     7   Interrupt Request Flag
CC20IC.CC20IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC20IC.ILVL_5     5   Interrupt Priority Level - bit 5
CC20IC.ILVL_4     4   Interrupt Priority Level - bit 4
CC20IC.ILVL_3     3   Interrupt Priority Level - bit 3
CC20IC.ILVL_2     2   Interrupt Priority Level - bit 2
CC20IC.GLVL_1     1   Group Level - bit 1
CC20IC.GLVL_0     0   Group Level - bit 0
CC21IC           0xF16A   CAPCOM Register 21 Interrupt Ctrl. Reg.
CC21IC.CC21IR     7   Interrupt Request Flag
CC21IC.CC21IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC21IC.ILVL_5     5   Interrupt Priority Level - bit 5
CC21IC.ILVL_4     4   Interrupt Priority Level - bit 4
CC21IC.ILVL_3     3   Interrupt Priority Level - bit 3
CC21IC.ILVL_2     2   Interrupt Priority Level - bit 2
CC21IC.GLVL_1     1   Group Level - bit 1
CC21IC.GLVL_0     0   Group Level - bit 0
CC22IC           0xF16C   CAPCOM Register 22 Interrupt Ctrl. Reg.
CC22IC.CC22IR     7   Interrupt Request Flag
CC22IC.CC22IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC22IC.ILVL_5     5   Interrupt Priority Level - bit 5
CC22IC.ILVL_4     4   Interrupt Priority Level - bit 4
CC22IC.ILVL_3     3   Interrupt Priority Level - bit 3
CC22IC.ILVL_2     2   Interrupt Priority Level - bit 2
CC22IC.GLVL_1     1   Group Level - bit 1
CC22IC.GLVL_0     0   Group Level - bit 0
CC23IC           0xF16E   CAPCOM Register 23 Interrupt Ctrl. Reg.
CC23IC.CC23IR     7   Interrupt Request Flag
CC23IC.CC23IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC23IC.ILVL_5     5   Interrupt Priority Level - bit 5
CC23IC.ILVL_4     4   Interrupt Priority Level - bit 4
CC23IC.ILVL_3     3   Interrupt Priority Level - bit 3
CC23IC.ILVL_2     2   Interrupt Priority Level - bit 2
CC23IC.GLVL_1     1   Group Level - bit 1
CC23IC.GLVL_0     0   Group Level - bit 0
CC24IC           0xF170   CAPCOM Register 24 Interrupt Ctrl. Reg.
CC24IC.CC24IR     7   Interrupt Request Flag
CC24IC.CC24IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC24IC.ILVL_5     5   Interrupt Priority Level - bit 5
CC24IC.ILVL_4     4   Interrupt Priority Level - bit 4
CC24IC.ILVL_3     3   Interrupt Priority Level - bit 3
CC24IC.ILVL_2     2   Interrupt Priority Level - bit 2
CC24IC.GLVL_1     1   Group Level - bit 1
CC24IC.GLVL_0     0   Group Level - bit 0
CC25IC           0xF172   CAPCOM Register 25 Interrupt Ctrl. Reg.
CC25IC.CC25IR     7   Interrupt Request Flag
CC25IC.CC25IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC25IC.ILVL_5     5   Interrupt Priority Level - bit 5
CC25IC.ILVL_4     4   Interrupt Priority Level - bit 4
CC25IC.ILVL_3     3   Interrupt Priority Level - bit 3
CC25IC.ILVL_2     2   Interrupt Priority Level - bit 2
CC25IC.GLVL_1     1   Group Level - bit 1
CC25IC.GLVL_0     0   Group Level - bit 0
CC26IC           0xF174   CAPCOM Register 26 Interrupt Ctrl. Reg.
CC26IC.CC26IR     7   Interrupt Request Flag
CC26IC.CC26IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC26IC.ILVL_5     5   Interrupt Priority Level - bit 5
CC26IC.ILVL_4     4   Interrupt Priority Level - bit 4
CC26IC.ILVL_3     3   Interrupt Priority Level - bit 3
CC26IC.ILVL_2     2   Interrupt Priority Level - bit 2
CC26IC.GLVL_1     1   Group Level - bit 1
CC26IC.GLVL_0     0   Group Level - bit 0
CC27IC           0xF176   CAPCOM Register 27 Interrupt Ctrl. Reg.
CC27IC.CC27IR     7   Interrupt Request Flag
CC27IC.CC27IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC27IC.ILVL_5     5   Interrupt Priority Level - bit 5
CC27IC.ILVL_4     4   Interrupt Priority Level - bit 4
CC27IC.ILVL_3     3   Interrupt Priority Level - bit 3
CC27IC.ILVL_2     2   Interrupt Priority Level - bit 2
CC27IC.GLVL_1     1   Group Level - bit 1
CC27IC.GLVL_0     0   Group Level - bit 0
CC28IC           0xF178   CAPCOM Register 28 Interrupt Ctrl. Reg.
CC28IC.CC28IR     7   Interrupt Request Flag
CC28IC.CC28IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC28IC.ILVL_5     5   Interrupt Priority Level - bit 5
CC28IC.ILVL_4     4   Interrupt Priority Level - bit 4
CC28IC.ILVL_3     3   Interrupt Priority Level - bit 3
CC28IC.ILVL_2     2   Interrupt Priority Level - bit 2
CC28IC.GLVL_1     1   Group Level - bit 1
CC28IC.GLVL_0     0   Group Level - bit 0
T7IC             0xF17A   CAPCOM Timer 7 Interrupt Ctrl. Reg.
T7IC.T7IR         7   Interrupt Request Flag
T7IC.T7IE         6   Interrupt Enable Control Bit (individually enables/disables a specific source)
T7IC.ILVL_5       5   Interrupt Priority Level - bit 5
T7IC.ILVL_4       4   Interrupt Priority Level - bit 4
T7IC.ILVL_3       3   Interrupt Priority Level - bit 3
T7IC.ILVL_2       2   Interrupt Priority Level - bit 2
T7IC.GLVL_1       1   Group Level - bit 1
T7IC.GLVL_0       0   Group Level - bit 0
T8IC             0xF17C   CAPCOM Timer 8 Interrupt Ctrl. Reg.
T8IC.T8IR         7   Interrupt Request Flag
T8IC.T8IE         6   Interrupt Enable Control Bit (individually enables/disables a specific source)
T8IC.ILVL_5       5   Interrupt Priority Level - bit 5
T8IC.ILVL_4       4   Interrupt Priority Level - bit 4
T8IC.ILVL_3       3   Interrupt Priority Level - bit 3
T8IC.ILVL_2       2   Interrupt Priority Level - bit 2
T8IC.GLVL_1       1   Group Level - bit 1
T8IC.GLVL_0       0   Group Level - bit 0
XP4IC            0xF182   ASC1 Transmit Interrupt Control Register
XP4IC.XP4IR       7   Interrupt Request Flag
XP4IC.XP4IE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
XP4IC.ILVL_5      5   Interrupt Priority Level - bit 5
XP4IC.ILVL_4      4   Interrupt Priority Level - bit 4
XP4IC.ILVL_3      3   Interrupt Priority Level - bit 3
XP4IC.ILVL_2      2   Interrupt Priority Level - bit 2
XP4IC.GLVL_1      1   Group Level - bit 1
XP4IC.GLVL_0      0   Group Level - bit 0
CC29IC           0xF184   CAPCOM Register 29 Interrupt Ctrl. Reg.
CC29IC.CC29IR     7   Interrupt Request Flag
CC29IC.CC29IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC29IC.ILVL_5     5   Interrupt Priority Level - bit 5
CC29IC.ILVL_4     4   Interrupt Priority Level - bit 4
CC29IC.ILVL_3     3   Interrupt Priority Level - bit 3
CC29IC.ILVL_2     2   Interrupt Priority Level - bit 2
CC29IC.GLVL_1     1   Group Level - bit 1
CC29IC.GLVL_0     0   Group Level - bit 0
XP0IC            0xF186   IIC Data Interrupt Control Register
XP0IC.XP0IR       7   Interrupt Request Flag
XP0IC.XP0IE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
XP0IC.ILVL_5      5   Interrupt Priority Level - bit 5
XP0IC.ILVL_4      4   Interrupt Priority Level - bit 4
XP0IC.ILVL_3      3   Interrupt Priority Level - bit 3
XP0IC.ILVL_2      2   Interrupt Priority Level - bit 2
XP0IC.GLVL_1      1   Group Level - bit 1
XP0IC.GLVL_0      0   Group Level - bit 0
XP5IC            0xF18A   ASC1 Receive Interrupt Control Register
XP5IC.XP5IR       7   Interrupt Request Flag
XP5IC.XP5IE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
XP5IC.ILVL_5      5   Interrupt Priority Level - bit 5
XP5IC.ILVL_4      4   Interrupt Priority Level - bit 4
XP5IC.ILVL_3      3   Interrupt Priority Level - bit 3
XP5IC.ILVL_2      2   Interrupt Priority Level - bit 2
XP5IC.GLVL_1      1   Group Level - bit 1
XP5IC.GLVL_0      0   Group Level - bit 0
CC30IC           0xF18C   CAPCOM Register 30 Interrupt Ctrl. Reg.
CC30IC.CC30IR     7   Interrupt Request Flag
CC30IC.CC30IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC30IC.ILVL_5     5   Interrupt Priority Level - bit 5
CC30IC.ILVL_4     4   Interrupt Priority Level - bit 4
CC30IC.ILVL_3     3   Interrupt Priority Level - bit 3
CC30IC.ILVL_2     2   Interrupt Priority Level - bit 2
CC30IC.GLVL_1     1   Group Level - bit 1
CC30IC.GLVL_0     0   Group Level - bit 0
XP1IC            0xF18E   IIC Protocol Interrupt Control Register
XP1IC.XP1IR       7   Interrupt Request Flag
XP1IC.XP1IE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
XP1IC.ILVL_5      5   Interrupt Priority Level - bit 5
XP1IC.ILVL_4      4   Interrupt Priority Level - bit 4
XP1IC.ILVL_3      3   Interrupt Priority Level - bit 3
XP1IC.ILVL_2      2   Interrupt Priority Level - bit 2
XP1IC.GLVL_1      1   Group Level - bit 1
XP1IC.GLVL_0      0   Group Level - bit 0
XP6IC            0xF192   ASC1 Error Interrupt Control Register
XP6IC.XP6IR       7   Interrupt Request Flag
XP6IC.XP6IE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
XP6IC.ILVL_5      5   Interrupt Priority Level - bit 5
XP6IC.ILVL_4      4   Interrupt Priority Level - bit 4
XP6IC.ILVL_3      3   Interrupt Priority Level - bit 3
XP6IC.ILVL_2      2   Interrupt Priority Level - bit 2
XP6IC.GLVL_1      1   Group Level - bit 1
XP6IC.GLVL_0      0   Group Level - bit 0
CC31IC           0xF194   CAPCOM Register 31 Interrupt Ctrl. Reg.
CC31IC.CC31IR     7   Interrupt Request Flag
CC31IC.CC31IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC31IC.ILVL_5     5   Interrupt Priority Level - bit 5
CC31IC.ILVL_4     4   Interrupt Priority Level - bit 4
CC31IC.ILVL_3     3   Interrupt Priority Level - bit 3
CC31IC.ILVL_2     2   Interrupt Priority Level - bit 2
CC31IC.GLVL_1     1   Group Level - bit 1
CC31IC.GLVL_0     0   Group Level - bit 0
XP2IC            0xF196   CAN1 Interrupt Control Register
XP2IC.XP2IR       7   Interrupt Request Flag
XP2IC.XP2IE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
XP2IC.ILVL_5      5   Interrupt Priority Level - bit 5
XP2IC.ILVL_4      4   Interrupt Priority Level - bit 4
XP2IC.ILVL_3      3   Interrupt Priority Level - bit 3
XP2IC.ILVL_2      2   Interrupt Priority Level - bit 2
XP2IC.GLVL_1      1   Group Level - bit 1
XP2IC.GLVL_0      0   Group Level - bit 0
XP7IC            0xF19A   CAN2/SDLM Interrupt Control Register
XP7IC.XP7IR       7   Interrupt Request Flag
XP7IC.XP7IE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
XP7IC.ILVL_5      5   Interrupt Priority Level - bit 5
XP7IC.ILVL_4      4   Interrupt Priority Level - bit 4
XP7IC.ILVL_3      3   Interrupt Priority Level - bit 3
XP7IC.ILVL_2      2   Interrupt Priority Level - bit 2
XP7IC.GLVL_1      1   Group Level - bit 1
XP7IC.GLVL_0      0   Group Level - bit 0
S0TBIC           0xF19C   Serial Channel 0 Transmit Buffer Interrupt Control Register
S0TBIC.S0TBIR     7   Interrupt Request Flag
S0TBIC.S0TBIE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
S0TBIC.ILVL_5     5   Interrupt Priority Level - bit 5
S0TBIC.ILVL_4     4   Interrupt Priority Level - bit 4
S0TBIC.ILVL_3     3   Interrupt Priority Level - bit 3
S0TBIC.ILVL_2     2   Interrupt Priority Level - bit 2
S0TBIC.GLVL_1     1   Group Level - bit 1
S0TBIC.GLVL_0     0   Group Level - bit 0
XP3IC            0xF19E   RTC/PLL/OWD Interrupt Control Register
XP3IC.XP7IR       7   Interrupt Request Flag
XP3IC.XP7IE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
XP3IC.ILVL_5      5   Interrupt Priority Level - bit 5
XP3IC.ILVL_4      4   Interrupt Priority Level - bit 4
XP3IC.ILVL_3      3   Interrupt Priority Level - bit 3
XP3IC.ILVL_2      2   Interrupt Priority Level - bit 2
XP3IC.GLVL_1      1   Group Level - bit 1
XP3IC.GLVL_0      0   Group Level - bit 0
EXICON           0xF1C0   External Interrupt Control Register
EXICON.EXI7ES_15  15  External Interrupt 15 Edge Selection Field - bit 15
EXICON.EXI7ES_14  14  External Interrupt 14 Edge Selection Field - bit 14
EXICON.EXI6ES_13  13  External Interrupt 13 Edge Selection Field - bit 13
EXICON.EXI6ES_12  12  External Interrupt 12 Edge Selection Field - bit 12
EXICON.EXI5ES_11  11  External Interrupt 11 Edge Selection Field - bit 11
EXICON.EXI5ES_10  10  External Interrupt 10 Edge Selection Field - bit 10
EXICON.EXI4ES_9   9   External Interrupt 9 Edge Selection Field - bit 9 
EXICON.EXI4ES_8   8   External Interrupt 8 Edge Selection Field - bit 8 
EXICON.EXI3ES_7   7   External Interrupt 7 Edge Selection Field - bit 7 
EXICON.EXI3ES_6   6   External Interrupt 6 Edge Selection Field - bit 6 
EXICON.EXI2ES_5   5   External Interrupt 5 Edge Selection Field - bit 5 
EXICON.EXI2ES_4   4   External Interrupt 4 Edge Selection Field - bit 4 
EXICON.EXI1ES_3   3   External Interrupt 3 Edge Selection Field - bit 3 
EXICON.EXI1ES_2   2   External Interrupt 2 Edge Selection Field - bit 2 
EXICON.EXI0ES_1   1   External Interrupt 1 Edge Selection Field - bit 1 
EXICON.EXI0ES_0   0   External Interrupt 0 Edge Selection Field - bit 0 
ODP2             0xF1C2   Port 2 Open Drain Control Register
ODP2.ODP2_15      15  Port 2 Open Drain control register bit 15
ODP2.ODP2_14      14  Port 2 Open Drain control register bit 14
ODP2.ODP2_13      13  Port 2 Open Drain control register bit 13
ODP2.ODP2_12      12  Port 2 Open Drain control register bit 12
ODP2.ODP2_11      11  Port 2 Open Drain control register bit 11
ODP2.ODP2_10      10  Port 2 Open Drain control register bit 10
ODP2.ODP2_9       9   Port 2 Open Drain control register bit 9 
ODP2.ODP2_8       8   Port 2 Open Drain control register bit 8 
PICON            0xF1C4   Port Input Threshold Control Register
PICON.P7LIN       6   Port 7 Low Byte Input Level Selection
PICON.P6LIN       5   Port 6 Low Byte Input Level Selection
PICON.P5LIN       4   Port 5 Low Byte Input Level Selection
PICON.P3HIN       3   Port 3 High Byte Input Level Selection
PICON.P3LIN       2   Port 3 Low Byte Input Level Selection
PICON.P2HIN       1   Port 2 High Byte Input Level Selection
ODP3             0xF1C6   Port 3 Open Drain Control Register
ODP3.ODP3_13      13  Port 3 Open Drain control register bit 13
ODP3.ODP3_11      11  Port 3 Open Drain control register bit 11
ODP3.ODP3_10      10  Port 3 Open Drain control register bit 10
ODP3.ODP3_9       9   Port 3 Open Drain control register bit 9 
ODP3.ODP3_8       8   Port 3 Open Drain control register bit 8 
ODP3.ODP3_7       7   Port 3 Open Drain control register bit 7 
ODP3.ODP3_6       6   Port 3 Open Drain control register bit 6 
ODP3.ODP3_5       5   Port 3 Open Drain control register bit 5 
ODP3.ODP3_4       4   Port 3 Open Drain control register bit 4 
ODP3.ODP3_3       3   Port 3 Open Drain control register bit 3 
ODP3.ODP3_2       2   Port 3 Open Drain control register bit 2 
ODP3.ODP3_1       1   Port 3 Open Drain control register bit 1 
ODP3.ODP3_0       0   Port 3 Open Drain control register bit 0 
ODP4             0xF1CA   Port 4 Open Drain Control Register
ODP4.ODP4_7       7   Port 4 Open Drain control register bit 7 
ODP4.ODP4_6       6   Port 4 Open Drain control register bit 6 
ODP4.ODP4_5       5   Port 4 Open Drain control register bit 5 
ODP4.ODP4_4       4   Port 4 Open Drain control register bit 4 
ODP4.ODP4_3       3   Port 4 Open Drain control register bit 3 
ODP4.ODP4_2       2   Port 4 Open Drain control register bit 2 
ODP4.ODP4_1       1   Port 4 Open Drain control register bit 1 
ODP4.ODP4_0       0   Port 4 Open Drain control register bit 0 
ODP6             0xF1CE   Port 6 Open Drain Control Register
ODP6.ODP6_7       7   Port 6 Open Drain control register bit 7
ODP6.ODP6_6       6   Port 6 Open Drain control register bit 6
ODP6.ODP6_5       5   Port 6 Open Drain control register bit 5
ODP6.ODP6_4       4   Port 6 Open Drain control register bit 4
ODP6.ODP6_3       3   Port 6 Open Drain control register bit 3
ODP6.ODP6_2       2   Port 6 Open Drain control register bit 2
ODP6.ODP6_1       1   Port 6 Open Drain control register bit 1
ODP6.ODP6_0       0   Port 6 Open Drain control register bit 0
SYSCON2          0xF1D0   CPU System Configuration Register 2
SYSCON2.CLKLOCK   15  Clock Signal Status Bit
SYSCON2.CLKREL_14 14  Reload Counter Value for Slowdown Divider - 14
SYSCON2.CLKREL_13 13  Reload Counter Value for Slowdown Divider - 13
SYSCON2.CLKREL_12 12  Reload Counter Value for Slowdown Divider - 12
SYSCON2.CLKREL_11 11  Reload Counter Value for Slowdown Divider - 11
SYSCON2.CLKREL_10 10  Reload Counter Value for Slowdown Divider - 10
SYSCON2.CLKCON_9  9   Clock State Control - bit 9
SYSCON2.CLKCON_8  8   Clock State Control - bit 8
SYSCON2.SCS       7   SDD Clock Source
SYSCON2.RCS       6   RTC Clock Source
SYSCON2.PDCON_5   5   Power Down Control - bit 5
SYSCON2.PDCON_4   4   Power Down Control - bit 4
SYSCON2.SYSRLS_3  3   Register Release Function - bit 3
SYSCON2.SYSRLS_2  2   Register Release Function - bit 2
SYSCON2.SYSRLS_1  1   Register Release Function - bit 1
SYSCON2.SYSRLS_0  0   Register Release Function - bit 0
ODP7             0xF1D2   Port 7 Open Drain Control Register
ODP7.ODP7_7       7   Port 7 Open Drain control register bit 7
ODP7.ODP7_6       6   Port 7 Open Drain control register bit 6
ODP7.ODP7_5       5   Port 7 Open Drain control register bit 5
ODP7.ODP7_4       4   Port 7 Open Drain control register bit 4
SYSCON3          0xF1D4   CPU System Configuration Register 3
SYSCON3.PCDDIS    15  Peripheral Clock Driver
SYSCON3.CAN1DIS   13  On-chip CAN Module 1
SYSCON3.SDLMDIS   12  On-chip SDLM (J1850 Module) exists only in the C161JC and C161JI
SYSCON3.IICDIS    11  On-chip IIC Bus Module
SYSCON3.ASC1DIS   10  USART ASC1
SYSCON3.CC2DIS    7   CAPCOM Unit 2
SYSCON3.CC1DIS    6   CAPCOM Unit 1
SYSCON3.GPTDIS    3   General Purpose Timer Blocks
SYSCON3.SSCDIS    2   Synchronous Serial Channel SSC
SYSCON3.ASC0DIS   1   USART ASC0
SYSCON3.ADCDIS    0   Analog/Digital Converter
EXISEL           0xF1DA   External Interrupt Source Select Register
EXISEL.EXI7SS_15  15  External Interrupt 15 Source Selection Field - bit 15
EXISEL.EXI7SS_14  14  External Interrupt 14 Source Selection Field - bit 14
EXISEL.EXI6SS_13  13  External Interrupt 13 Source Selection Field - bit 13
EXISEL.EXI6SS_12  12  External Interrupt 12 Source Selection Field - bit 12
EXISEL.EXI5SS_11  11  External Interrupt 11 Source Selection Field - bit 11
EXISEL.EXI5SS_10  10  External Interrupt 10 Source Selection Field - bit 10
EXISEL.EXI4SS_9   9   External Interrupt 9 Source Selection Field - bit 9 
EXISEL.EXI4SS_8   8   External Interrupt 8 Source Selection Field - bit 8 
EXISEL.EXI3SS_7   7   External Interrupt 7 Source Selection Field - bit 7 
EXISEL.EXI3SS_6   6   External Interrupt 6 Source Selection Field - bit 6 
EXISEL.EXI2SS_5   5   External Interrupt 5 Source Selection Field - bit 5 
EXISEL.EXI2SS_4   4   External Interrupt 4 Source Selection Field - bit 4 
EXISEL.EXI1SS_3   3   External Interrupt 3 Source Selection Field - bit 3 
EXISEL.EXI1SS_2   2   External Interrupt 2 Source Selection Field - bit 2 
EXISEL.EXI0SS_1   1   External Interrupt 1 Source Selection Field - bit 1 
EXISEL.EXI0SS_0   0   External Interrupt 0 Source Selection Field - bit 0 
SYSCON1          0xF1DC   CPU System Configuration Register 1
SYSCON1.SLEEPCON_1 1  SLEEP Mode Configuration - bit 1
SYSCON1.SLEEPCON_0 0  SLEEP Mode Configuration - bit 0
ISNC             0xF1DE   Interrupt Subnode Control Register
ISNC.PLLIE        3   Interrupt Enable Control Bit for Source PLL
ISNC.PLLIR        2   Interrupt Request Flag for Source PLL
ISNC.RTCIE        1   Interrupt Enable Control Bit for Source RTC
ISNC.RTCIR        0   Interrupt Request Flag for Source RTC
RSTCON           0xF1E0   Reset Control Register
RSTCON.CLKCFG_15  15  Clock Generation Mode Configuration - bit 15
RSTCON.CLKCFG_14  14  Clock Generation Mode Configuration - bit 14
RSTCON.CLKCFG_13  13  Clock Generation Mode Configuration - bit 13
RSTCON.SALSEL_12  12  Segment Address Line Selection - bit 12
RSTCON.SALSEL_11  11  Segment Address Line Selection - bit 11
RSTCON.CSSEL_10   10  Chip Select Line Selection - bit 10
RSTCON.CSSEL_9    9   Chip Select Line Selection - bit 9
RSTCON.SUE        8   Software Update Enable
RSTCON.RSTLEN_1   1   Reset Length Control - bit 1
RSTCON.RSTLEN_0   0   Reset Length Control - bit 0
DPP0             0xFE00   CPU Data Page Pointer 0 Register (10 bits)
DPP0.DPP0PN_9     9   Data Page Number of DPP0 - bit 9
DPP0.DPP0PN_8     8   Data Page Number of DPP0 - bit 8
DPP0.DPP0PN_7     7   Data Page Number of DPP0 - bit 7
DPP0.DPP0PN_6     6   Data Page Number of DPP0 - bit 6
DPP0.DPP0PN_5     5   Data Page Number of DPP0 - bit 5
DPP0.DPP0PN_4     4   Data Page Number of DPP0 - bit 4
DPP0.DPP0PN_3     3   Data Page Number of DPP0 - bit 3
DPP0.DPP0PN_2     2   Data Page Number of DPP0 - bit 2
DPP0.DPP0PN_1     1   Data Page Number of DPP0 - bit 1
DPP0.DPP0PN_0     0   Data Page Number of DPP0 - bit 0
DPP1             0xFE02   CPU Data Page Pointer 1 Register (10 bits)
DPP1.DPP1PN_9     9   Data Page Number of DPP1 - bit 9
DPP1.DPP1PN_8     8   Data Page Number of DPP1 - bit 8
DPP1.DPP1PN_7     7   Data Page Number of DPP1 - bit 7
DPP1.DPP1PN_6     6   Data Page Number of DPP1 - bit 6
DPP1.DPP1PN_5     5   Data Page Number of DPP1 - bit 5
DPP1.DPP1PN_4     4   Data Page Number of DPP1 - bit 4
DPP1.DPP1PN_3     3   Data Page Number of DPP1 - bit 3
DPP1.DPP1PN_2     2   Data Page Number of DPP1 - bit 2
DPP1.DPP1PN_1     1   Data Page Number of DPP1 - bit 1
DPP1.DPP1PN_0     0   Data Page Number of DPP1 - bit 0
DPP2             0xFE04   CPU Data Page Pointer 2 Register (10 bits)
DPP2.DPP2PN_9     9   Data Page Number of DPP2 - bit 9
DPP2.DPP2PN_8     8   Data Page Number of DPP2 - bit 8
DPP2.DPP2PN_7     7   Data Page Number of DPP2 - bit 7
DPP2.DPP2PN_6     6   Data Page Number of DPP2 - bit 6
DPP2.DPP2PN_5     5   Data Page Number of DPP2 - bit 5
DPP2.DPP2PN_4     4   Data Page Number of DPP2 - bit 4
DPP2.DPP2PN_3     3   Data Page Number of DPP2 - bit 3
DPP2.DPP2PN_2     2   Data Page Number of DPP2 - bit 2
DPP2.DPP2PN_1     1   Data Page Number of DPP2 - bit 1
DPP2.DPP2PN_0     0   Data Page Number of DPP2 - bit 0
DPP3             0xFE06   CPU Data Page Pointer 3 Register (10 bits)
DPP3.DPP3PN_9     9   Data Page Number of DPP3 - bit 9
DPP3.DPP3PN_8     8   Data Page Number of DPP3 - bit 8
DPP3.DPP3PN_7     7   Data Page Number of DPP3 - bit 7
DPP3.DPP3PN_6     6   Data Page Number of DPP3 - bit 6
DPP3.DPP3PN_5     5   Data Page Number of DPP3 - bit 5
DPP3.DPP3PN_4     4   Data Page Number of DPP3 - bit 4
DPP3.DPP3PN_3     3   Data Page Number of DPP3 - bit 3
DPP3.DPP3PN_2     2   Data Page Number of DPP3 - bit 2
DPP3.DPP3PN_1     1   Data Page Number of DPP3 - bit 1
DPP3.DPP3PN_0     0   Data Page Number of DPP3 - bit 0
CSP              0xFE08   CPU Code Segment Pointer Register (8 bits, not directly writeable)
CSP.SEGNR_7       7   Segment Number - bit 7
CSP.SEGNR_6       6   Segment Number - bit 6
CSP.SEGNR_5       5   Segment Number - bit 5
CSP.SEGNR_4       4   Segment Number - bit 4
CSP.SEGNR_3       3   Segment Number - bit 3
CSP.SEGNR_2       2   Segment Number - bit 2
CSP.SEGNR_1       1   Segment Number - bit 1
CSP.SEGNR_0       0   Segment Number - bit 0
MDH              0xFE0C   CPU Multiply Divide Register ­ High Word
MDH.mdh_15        15
MDH.mdh_14        14
MDH.mdh_13        13
MDH.mdh_12        12
MDH.mdh_11        11
MDH.mdh_10        10
MDH.mdh_9         9 
MDH.mdh_8         8 
MDH.mdh_7         7 
MDH.mdh_6         6 
MDH.mdh_5         5 
MDH.mdh_4         4 
MDH.mdh_3         3 
MDH.mdh_2         2 
MDH.mdh_1         1 
MDH.mdh_0         0 
MDL              0xFE0E   CPU Multiply Divide Register ­ Low Word
MDL.MDL_15        15
MDL.MDL_14        14
MDL.MDL_13        13
MDL.MDL_12        12
MDL.MDL_11        11
MDL.MDL_10        10
MDL.MDL_9         9 
MDL.MDL_8         8 
MDL.MDL_7         7 
MDL.MDL_6         6 
MDL.MDL_5         5 
MDL.MDL_4         4 
MDL.MDL_3         3 
MDL.MDL_2         2 
MDL.MDL_1         1 
MDL.MDL_0         0 
CP               0xFE10   CPU Context Pointer Register
CP.cp_11          11  Modifiable portion of register CP - bit 11
CP.cp_10          10  Modifiable portion of register CP - bit 10
CP.cp_9           9   Modifiable portion of register CP - bit 9
CP.cp_8           8   Modifiable portion of register CP - bit 8
CP.cp_7           7   Modifiable portion of register CP - bit 7
CP.cp_6           6   Modifiable portion of register CP - bit 6
CP.cp_5           5   Modifiable portion of register CP - bit 5
CP.cp_4           4   Modifiable portion of register CP - bit 4
CP.cp_3           3   Modifiable portion of register CP - bit 3
CP.cp_2           2   Modifiable portion of register CP - bit 2
CP.cp_1           1   Modifiable portion of register CP - bit 1
SP               0xFE12   CPU System Stack Pointer Register
SP.sp_11          11  Modifiable portion of register SP - bit 11
SP.sp_10          10  Modifiable portion of register SP - bit 10
SP.sp_9           9   Modifiable portion of register SP - bit 9
SP.sp_8           8   Modifiable portion of register SP - bit 8
SP.sp_7           7   Modifiable portion of register SP - bit 7
SP.sp_6           6   Modifiable portion of register SP - bit 6
SP.sp_5           5   Modifiable portion of register SP - bit 5
SP.sp_4           4   Modifiable portion of register SP - bit 4
SP.sp_3           3   Modifiable portion of register SP - bit 3
SP.sp_2           2   Modifiable portion of register SP - bit 2
SP.sp_1           1   Modifiable portion of register SP - bit 1
STKOV            0xFE14   CPU Stack Overflow Pointer Register
STKOV.stkov_11    11  Modifiable portion of register STKOV - bit 11
STKOV.stkov_10    10  Modifiable portion of register STKOV - bit 10
STKOV.stkov_9     9   Modifiable portion of register STKOV - bit 9
STKOV.stkov_8     8   Modifiable portion of register STKOV - bit 8
STKOV.stkov_7     7   Modifiable portion of register STKOV - bit 7
STKOV.stkov_6     6   Modifiable portion of register STKOV - bit 6
STKOV.stkov_5     5   Modifiable portion of register STKOV - bit 5
STKOV.stkov_4     4   Modifiable portion of register STKOV - bit 4
STKOV.stkov_3     3   Modifiable portion of register STKOV - bit 3
STKOV.stkov_2     2   Modifiable portion of register STKOV - bit 2
STKOV.stkov_1     1   Modifiable portion of register STKOV - bit 1
STKUN            0xFE16   CPU Stack Underflow Pointer Register
STKUN.STKUN_11    11  Modifiable portion of register STKUN - bit 11
STKUN.STKUN_10    10  Modifiable portion of register STKUN - bit 10
STKUN.STKUN_9     9   Modifiable portion of register STKUN - bit 9
STKUN.STKUN_8     8   Modifiable portion of register STKUN - bit 8
STKUN.STKUN_7     7   Modifiable portion of register STKUN - bit 7
STKUN.STKUN_6     6   Modifiable portion of register STKUN - bit 6
STKUN.STKUN_5     5   Modifiable portion of register STKUN - bit 5
STKUN.STKUN_4     4   Modifiable portion of register STKUN - bit 4
STKUN.STKUN_3     3   Modifiable portion of register STKUN - bit 3
STKUN.STKUN_2     2   Modifiable portion of register STKUN - bit 2
STKUN.STKUN_1     1   Modifiable portion of register STKUN - bit 1
ADDRSEL1         0xFE18   Address Select Register 1
ADDRSEL1.RGSAD15  15  Range Start Address bit 15
ADDRSEL1.RGSAD14  14  Range Start Address bit 14
ADDRSEL1.RGSAD13  13  Range Start Address bit 13
ADDRSEL1.RGSAD12  12  Range Start Address bit 12
ADDRSEL1.RGSAD11  11  Range Start Address bit 11
ADDRSEL1.RGSAD10  10  Range Start Address bit 10
ADDRSEL1.RGSAD9   9   Range Start Address bit 9 
ADDRSEL1.RGSAD8   8   Range Start Address bit 8 
ADDRSEL1.RGSAD7   7   Range Start Address bit 7 
ADDRSEL1.RGSAD6   6   Range Start Address bit 6 
ADDRSEL1.RGSAD5   5   Range Start Address bit 5 
ADDRSEL1.RGSAD4   4   Range Start Address bit 4 
ADDRSEL1.RGSZ3    3   Range Size Selection bit 3
ADDRSEL1.RGSZ2    2   Range Size Selection bit 2
ADDRSEL1.RGSZ1    1   Range Size Selection bit 1
ADDRSEL1.RGSZ0    0   Range Size Selection bit 0
ADDRSEL2         0xFE1A   Address Select Register 2
ADDRSEL2.RGSAD15  15  Range Start Address bit 15
ADDRSEL2.RGSAD14  14  Range Start Address bit 14
ADDRSEL2.RGSAD13  13  Range Start Address bit 13
ADDRSEL2.RGSAD12  12  Range Start Address bit 12
ADDRSEL2.RGSAD11  11  Range Start Address bit 11
ADDRSEL2.RGSAD10  10  Range Start Address bit 10
ADDRSEL2.RGSAD9   9   Range Start Address bit 9 
ADDRSEL2.RGSAD8   8   Range Start Address bit 8 
ADDRSEL2.RGSAD7   7   Range Start Address bit 7 
ADDRSEL2.RGSAD6   6   Range Start Address bit 6 
ADDRSEL2.RGSAD5   5   Range Start Address bit 5 
ADDRSEL2.RGSAD4   4   Range Start Address bit 4 
ADDRSEL2.RGSZ3    3   Range Size Selection bit 3
ADDRSEL2.RGSZ2    2   Range Size Selection bit 2
ADDRSEL2.RGSZ1    1   Range Size Selection bit 1
ADDRSEL2.RGSZ0    0   Range Size Selection bit 0
ADDRSEL3         0xFE1C   Address Select Register 3
ADDRSEL3.RGSAD15  15  Range Start Address bit 15
ADDRSEL3.RGSAD14  14  Range Start Address bit 14
ADDRSEL3.RGSAD13  13  Range Start Address bit 13
ADDRSEL3.RGSAD12  12  Range Start Address bit 12
ADDRSEL3.RGSAD11  11  Range Start Address bit 11
ADDRSEL3.RGSAD10  10  Range Start Address bit 10
ADDRSEL3.RGSAD9   9   Range Start Address bit 9 
ADDRSEL3.RGSAD8   8   Range Start Address bit 8 
ADDRSEL3.RGSAD7   7   Range Start Address bit 7 
ADDRSEL3.RGSAD6   6   Range Start Address bit 6 
ADDRSEL3.RGSAD5   5   Range Start Address bit 5 
ADDRSEL3.RGSAD4   4   Range Start Address bit 4 
ADDRSEL3.RGSZ3    3   Range Size Selection bit 3
ADDRSEL3.RGSZ2    2   Range Size Selection bit 2
ADDRSEL3.RGSZ1    1   Range Size Selection bit 1
ADDRSEL3.RGSZ0    0   Range Size Selection bit 0
ADDRSEL4         0xFE1E   Address Select Register 4
ADDRSEL4.RGSAD15  15  Range Start Address bit 15
ADDRSEL4.RGSAD14  14  Range Start Address bit 14
ADDRSEL4.RGSAD13  13  Range Start Address bit 13
ADDRSEL4.RGSAD12  12  Range Start Address bit 12
ADDRSEL4.RGSAD11  11  Range Start Address bit 11
ADDRSEL4.RGSAD10  10  Range Start Address bit 10
ADDRSEL4.RGSAD9   9   Range Start Address bit 9 
ADDRSEL4.RGSAD8   8   Range Start Address bit 8 
ADDRSEL4.RGSAD7   7   Range Start Address bit 7 
ADDRSEL4.RGSAD6   6   Range Start Address bit 6 
ADDRSEL4.RGSAD5   5   Range Start Address bit 5 
ADDRSEL4.RGSAD4   4   Range Start Address bit 4 
ADDRSEL4.RGSZ3    3   Range Size Selection bit 3
ADDRSEL4.RGSZ2    2   Range Size Selection bit 2
ADDRSEL4.RGSZ1    1   Range Size Selection bit 1
ADDRSEL4.RGSZ0    0   Range Size Selection bit 0
T2               0xFE40   GPT1 Timer 2 Register
T3               0xFE42   GPT1 Timer 3 Register
T4               0xFE44   GPT1 Timer 4 Register
T5               0xFE46   GPT2 Timer 5 Register
T6               0xFE48   GPT2 Timer 6 Register
CAPREL           0xFE4A   GPT2 Capture/Reload Register
T0               0xFE50   CAPCOM Timer 0 Register
T1               0xFE52   CAPCOM Timer 1 Register
T0REL            0xFE54   CAPCOM Timer 0 Reload Register
T1REL            0xFE56   CAPCOM Timer 1 Reload Register
CC16             0xFE60   CAPCOM Register 16
CC17             0xFE62   CAPCOM Register 17
CC18             0xFE64   CAPCOM Register 18
CC19             0xFE66   CAPCOM Register 19
CC20             0xFE68   CAPCOM Register 20
CC21             0xFE6A   CAPCOM Register 21
CC22             0xFE6C   CAPCOM Register 22
CC23             0xFE6E   CAPCOM Register 23
CC24             0xFE70   CAPCOM Register 24
CC25             0xFE72   CAPCOM Register 25
CC26             0xFE74   CAPCOM Register 26
CC27             0xFE76   CAPCOM Register 27
CC28             0xFE78   CAPCOM Register 28
CC29             0xFE7A   CAPCOM Register 29
CC30             0xFE7C   CAPCOM Register 30
CC31             0xFE7E   CAPCOM Register 31
CC0              0xFE80   CAPCOM Register 0
CC1              0xFE82   CAPCOM Register 1
CC2              0xFE84   CAPCOM Register 2
CC3              0xFE86   CAPCOM Register 3
CC4              0xFE88   CAPCOM Register 4
CC5              0xFE8A   CAPCOM Register 5
CC6              0xFE8C   CAPCOM Register 6
CC7              0xFE8E   CAPCOM Register 7
CC8              0xFE90   CAPCOM Register 8
CC9              0xFE92   CAPCOM Register 9
CC10             0xFE94   CAPCOM Register 10
CC11             0xFE96   CAPCOM Register 11
CC12             0xFE98   CAPCOM Register 12
CC13             0xFE9A   CAPCOM Register 13
CC14             0xFE9C   CAPCOM Register 14
CC15             0xFE9E   CAPCOM Register 15
ADDAT            0xFEA0   A/D Converter Result Register
ADDAT.CHNR_15     15  Channel Number - bit 15      
ADDAT.CHNR_14     14  Channel Number - bit 14      
ADDAT.CHNR_13     13  Channel Number - bit 13      
ADDAT.CHNR_12     12  Channel Number - bit 12      
ADDAT.ADRES_9     9   A/D Conversion Result - bit 9
ADDAT.ADRES_8     8   A/D Conversion Result - bit 8
ADDAT.ADRES_7     7   A/D Conversion Result - bit 7
ADDAT.ADRES_6     6   A/D Conversion Result - bit 6
ADDAT.ADRES_5     5   A/D Conversion Result - bit 5
ADDAT.ADRES_4     4   A/D Conversion Result - bit 4
ADDAT.ADRES_3     3   A/D Conversion Result - bit 3
ADDAT.ADRES_2     2   A/D Conversion Result - bit 2
ADDAT.ADRES_1     1   A/D Conversion Result - bit 1
ADDAT.ADRES_0     0   A/D Conversion Result - bit 0
P1DIDIS          0xFEA4   PORT1 Digital Input Disable Register
WDT              0xFEAE   Watchdog Timer Register (read only)
S0TBUF           0xFEB0   Serial Channel 0 Transmit Buffer Register
S0RBUF           0xFEB2   Serial Channel 0 Receive Buffer Register (read only)
S0BG             0xFEB4   Serial Channel 0 Baud Rate Generator Reload Register
PECC0            0xFEC0   PEC Channel 0 Control Register             
PECC0.INC_10      10  Increment Control - bit 10
PECC0.INC_9       9   Increment Control - bit 9 
PECC0.BWT         8   Byte/Word Transfer Selection
PECC0.COUNT_7     7    PEC Transfer Count - bit 7
PECC0.COUNT_6     6    PEC Transfer Count - bit 6
PECC0.COUNT_5     5    PEC Transfer Count - bit 5
PECC0.COUNT_4     4    PEC Transfer Count - bit 4
PECC0.COUNT_3     3    PEC Transfer Count - bit 3
PECC0.COUNT_2     2    PEC Transfer Count - bit 2
PECC0.COUNT_1     1    PEC Transfer Count - bit 1
PECC0.COUNT_0     0    PEC Transfer Count - bit 0
PECC1            0xFEC2   PEC Channel 1 Control Register             
PECC1.INC_10      10  Increment Control - bit 10
PECC1.INC_9       9   Increment Control - bit 9 
PECC1.BWT         8   Byte/Word Transfer Selection
PECC1.COUNT_7     7    PEC Transfer Count - bit 7
PECC1.COUNT_6     6    PEC Transfer Count - bit 6
PECC1.COUNT_5     5    PEC Transfer Count - bit 5
PECC1.COUNT_4     4    PEC Transfer Count - bit 4
PECC1.COUNT_3     3    PEC Transfer Count - bit 3
PECC1.COUNT_2     2    PEC Transfer Count - bit 2
PECC1.COUNT_1     1    PEC Transfer Count - bit 1
PECC1.COUNT_0     0    PEC Transfer Count - bit 0
PECC2            0xFEC4   PEC Channel 2 Control Register             
PECC2.INC_10      10  Increment Control - bit 10
PECC2.INC_9       9   Increment Control - bit 9 
PECC2.BWT         8   Byte/Word Transfer Selection
PECC2.COUNT_7     7    PEC Transfer Count - bit 7
PECC2.COUNT_6     6    PEC Transfer Count - bit 6
PECC2.COUNT_5     5    PEC Transfer Count - bit 5
PECC2.COUNT_4     4    PEC Transfer Count - bit 4
PECC2.COUNT_3     3    PEC Transfer Count - bit 3
PECC2.COUNT_2     2    PEC Transfer Count - bit 2
PECC2.COUNT_1     1    PEC Transfer Count - bit 1
PECC2.COUNT_0     0    PEC Transfer Count - bit 0
PECC3            0xFEC6   PEC Channel 3 Control Register             
PECC3.INC_10      10  Increment Control - bit 10
PECC3.INC_9       9   Increment Control - bit 9 
PECC3.BWT         8   Byte/Word Transfer Selection
PECC3.COUNT_7     7    PEC Transfer Count - bit 7
PECC3.COUNT_6     6    PEC Transfer Count - bit 6
PECC3.COUNT_5     5    PEC Transfer Count - bit 5
PECC3.COUNT_4     4    PEC Transfer Count - bit 4
PECC3.COUNT_3     3    PEC Transfer Count - bit 3
PECC3.COUNT_2     2    PEC Transfer Count - bit 2
PECC3.COUNT_1     1    PEC Transfer Count - bit 1
PECC3.COUNT_0     0    PEC Transfer Count - bit 0
PECC4            0xFEC8   PEC Channel 4 Control Register             
PECC4.INC_10      10  Increment Control - bit 10
PECC4.INC_9       9   Increment Control - bit 9 
PECC4.BWT         8   Byte/Word Transfer Selection
PECC4.COUNT_7     7    PEC Transfer Count - bit 7
PECC4.COUNT_6     6    PEC Transfer Count - bit 6
PECC4.COUNT_5     5    PEC Transfer Count - bit 5
PECC4.COUNT_4     4    PEC Transfer Count - bit 4
PECC4.COUNT_3     3    PEC Transfer Count - bit 3
PECC4.COUNT_2     2    PEC Transfer Count - bit 2
PECC4.COUNT_1     1    PEC Transfer Count - bit 1
PECC4.COUNT_0     0    PEC Transfer Count - bit 0
PECC5            0xFECA   PEC Channel 5 Control Register             
PECC5.INC_10      10  Increment Control - bit 10
PECC5.INC_9       9   Increment Control - bit 9 
PECC5.BWT         8   Byte/Word Transfer Selection
PECC5.COUNT_7     7    PEC Transfer Count - bit 7
PECC5.COUNT_6     6    PEC Transfer Count - bit 6
PECC5.COUNT_5     5    PEC Transfer Count - bit 5
PECC5.COUNT_4     4    PEC Transfer Count - bit 4
PECC5.COUNT_3     3    PEC Transfer Count - bit 3
PECC5.COUNT_2     2    PEC Transfer Count - bit 2
PECC5.COUNT_1     1    PEC Transfer Count - bit 1
PECC5.COUNT_0     0    PEC Transfer Count - bit 0
PECC6            0xFECC   PEC Channel 6 Control Register             
PECC6.INC_10      10  Increment Control - bit 10
PECC6.INC_9       9   Increment Control - bit 9 
PECC6.BWT         8   Byte/Word Transfer Selection
PECC6.COUNT_7     7    PEC Transfer Count - bit 7
PECC6.COUNT_6     6    PEC Transfer Count - bit 6
PECC6.COUNT_5     5    PEC Transfer Count - bit 5
PECC6.COUNT_4     4    PEC Transfer Count - bit 4
PECC6.COUNT_3     3    PEC Transfer Count - bit 3
PECC6.COUNT_2     2    PEC Transfer Count - bit 2
PECC6.COUNT_1     1    PEC Transfer Count - bit 1
PECC6.COUNT_0     0    PEC Transfer Count - bit 0
PECC7            0xFECE   PEC Channel 7 Control Register             
PECC7.INC_10      10  Increment Control - bit 10
PECC7.INC_9       9   Increment Control - bit 9 
PECC7.BWT         8   Byte/Word Transfer Selection
PECC7.COUNT_7     7    PEC Transfer Count - bit 7
PECC7.COUNT_6     6    PEC Transfer Count - bit 6
PECC7.COUNT_5     5    PEC Transfer Count - bit 5
PECC7.COUNT_4     4    PEC Transfer Count - bit 4
PECC7.COUNT_3     3    PEC Transfer Count - bit 3
PECC7.COUNT_2     2    PEC Transfer Count - bit 2
PECC7.COUNT_1     1    PEC Transfer Count - bit 1
PECC7.COUNT_0     0    PEC Transfer Count - bit 0
P0L              0xFF00   Port 0 Low Register (Lower half of PORT0)
P0L.P0L7          7   Port data register P0L bit 7
P0L.P0L6          6   Port data register P0L bit 6
P0L.P0L5          5   Port data register P0L bit 5
P0L.P0L4          4   Port data register P0L bit 4
P0L.P0L3          3   Port data register P0L bit 3
P0L.P0L2          2   Port data register P0L bit 2
P0L.P0L1          1   Port data register P0L bit 1
P0L.P0L0          0   Port data register P0L bit 0
P0H              0xFF02   Port 0 High Register (Upper half of PORT0)
P0H.P0H7          7   Port data register P0H bit 7
P0H.P0H6          6   Port data register P0H bit 6
P0H.P0H5          5   Port data register P0H bit 5
P0H.P0H4          4   Port data register P0H bit 4
P0H.P0H3          3   Port data register P0H bit 3
P0H.P0H2          2   Port data register P0H bit 2
P0H.P0H1          1   Port data register P0H bit 1
P0H.P0H0          0   Port data register P0H bit 0
P1L              0xFF04   Port 1 Low Register (Lower half of PORT1)
P1L.P1L7          7   Port data register P1L bit 7
P1L.P1L6          6   Port data register P1L bit 6
P1L.P1L5          5   Port data register P1L bit 5
P1L.P1L4          4   Port data register P1L bit 4
P1L.P1L3          3   Port data register P1L bit 3
P1L.P1L2          2   Port data register P1L bit 2
P1L.P1L1          1   Port data register P1L bit 1
P1L.P1L0          0   Port data register P1L bit 0
P1H              0xFF06   Port 1 High Register (Upper half of PORT1)
P1H.P1H7          7   Port data register P1H bit 7
P1H.P1H6          6   Port data register P1H bit 6
P1H.P1H5          5   Port data register P1H bit 5
P1H.P1H4          4   Port data register P1H bit 4
P1H.P1H3          3   Port data register P1H bit 3
P1H.P1H2          2   Port data register P1H bit 2
P1H.P1H1          1   Port data register P1H bit 1
P1H.P1H0          0   Port data register P1H bit 0
BUSCON0          0xFF0C   Bus Configuration Register 0
BUSCON0.CSWEN0    15  Write Chip Select Enable
BUSCON0.CSREN0    14  Read Chip Select Enable
BUSCON0.RDYEN0    12  READY Input Enable
BUSCON0.BSWC0     11  BUSCON Switch Control
BUSCON0.BUSACT0   10  Bus Active Control
BUSCON0.ALECTL0   9   ALE Lengthening Control
BUSCON0.EWEN0     8   Early Write Enable
BUSCON0.BTYP_7    7   External Bus Configuration - bit 7
BUSCON0.BTYP_6    6   External Bus Configuration - bit 6
BUSCON0.MTTC0     5   Memory Tristate Time Control
BUSCON0.RWDC0     4   Read/Write Delay Control for BUSCON
BUSCON0.MCTC_3    3   Memory Cycle Time Control - bit 3
BUSCON0.MCTC_2    2   Memory Cycle Time Control - bit 2
BUSCON0.MCTC_1    1   Memory Cycle Time Control - bit 1
BUSCON0.MCTC_0    0   Memory Cycle Time Control - bit 0
MDC              0xFF0E   CPU Multiply Divide Control Register
MDC.MDRIU         4   Multiply/Divide Register In Use
PSW              0xFF10   CPU Program Status Word
PSW.ILVL_15       15  Interrupt and EBC Control Field - bit 15
PSW.ILVL_14       14  Interrupt and EBC Control Field - bit 14
PSW.ILVL_13       13  Interrupt and EBC Control Field - bit 13
PSW.ILVL_12       12  Interrupt and EBC Control Field - bit 12
PSW.IEN           11  Interrupt and EBC Control Field
PSW.HLDEN         10  Interrupt and EBC Control Field
PSW.USR0          6   User General Purpose Flag
PSW.MULIP         5   Multiplication/Division In Progress
PSW.E             4   End of Table Flag
PSW.Z             3   Zero F lag
PSW.V             2   Overflow Result
PSW.C             1   Carry Flag
PSW.N             0   Negative Result
SYSCON           0xFF12   CPU System Configuration Register
SYSCON.STKSZ_15   15  System Stack Size - bit 15
SYSCON.STKSZ_14   14  System Stack Size - bit 14
SYSCON.STKSZ_13   13  System Stack Size - bit 13
SYSCON.ROMS1      12  Internal ROM Mapping
SYSCON.SGTDIS     11  Segmentation Disable/Enable Control (Cleared after reset)
SYSCON.ROMEN      10  Internal ROM Enable (Set according to pin EA during reset)
SYSCON.BYTDIS     9   Disable/Enable Control for Pin BHE (Set according to data bus width)
SYSCON.CLKEN      8   System Clock Output Enable (CLKOUT, cleared after reset)
SYSCON.WRCFG      7   Write Configuration Control (Set according to pin P0H.0 during reset)
SYSCON.CSCFG      6   Chip Select Configuration Control (Cleared after reset)
SYSCON.OWDDIS     4   Oscillator Watchdog Disable Bit (Depending on reset configuration)
SYSCON.BDRSTEN    3   Bidirectional Reset Enable Bit
SYSCON.XPEN       2   Peripheral Enable Bit
SYSCON.VISIBLE    1   Visible Mode Control
SYSCON.XPER_SHARE 0   XBUS Peripheral Share Mode Control
BUSCON1          0xFF14   Bus Configuration Register 1
BUSCON1.CSWEN1    15  Write Chip Select Enable
BUSCON1.CSREN1    14  Read Chip Select Enable
BUSCON1.RDYEN1    12  READY Input Enable
BUSCON1.BSWC1     11  BUSCON Switch Control
BUSCON1.BUSACT1   10  Bus Active Control
BUSCON1.ALECTL1   9   ALE Lengthening Control
BUSCON1.EWEN1     8   Early Write Enable
BUSCON1.BTYP_7    7   External Bus Configuration - bit 7
BUSCON1.BTYP_6    6   External Bus Configuration - bit 6
BUSCON1.MTTC1     5   Memory Tristate Time Control
BUSCON1.RWDC1     4   Read/Write Delay Control for BUSCON
BUSCON1.MCTC_3    3   Memory Cycle Time Control - bit 3
BUSCON1.MCTC_2    2   Memory Cycle Time Control - bit 2
BUSCON1.MCTC_1    1   Memory Cycle Time Control - bit 1
BUSCON1.MCTC_0    0   Memory Cycle Time Control - bit 0
BUSCON2          0xFF16   Bus Configuration Register 2
BUSCON2.CSWEN2    15  Write Chip Select Enable
BUSCON2.CSREN2    14  Read Chip Select Enable
BUSCON2.RDYEN2    12  READY Input Enable
BUSCON2.BSWC2     11  BUSCON Switch Control
BUSCON2.BUSACT2   10  Bus Active Control
BUSCON2.ALECTL2   9   ALE Lengthening Control
BUSCON2.EWEN2     8   Early Write Enable
BUSCON2.BTYP_7    7   External Bus Configuration - bit 7
BUSCON2.BTYP_6    6   External Bus Configuration - bit 6
BUSCON2.MTTC2     5   Memory Tristate Time Control
BUSCON2.RWDC2     4   Read/Write Delay Control for BUSCON
BUSCON2.MCTC_3    3   Memory Cycle Time Control - bit 3
BUSCON2.MCTC_2    2   Memory Cycle Time Control - bit 2
BUSCON2.MCTC_1    1   Memory Cycle Time Control - bit 1
BUSCON2.MCTC_0    0   Memory Cycle Time Control - bit 0
BUSCON3          0xFF18   Bus Configuration Register 3
BUSCON3.CSWEN3    15  Write Chip Select Enable
BUSCON3.CSREN3    14  Read Chip Select Enable
BUSCON3.RDYEN3    12  READY Input Enable
BUSCON3.BSWC3     11  BUSCON Switch Control
BUSCON3.BUSACT3   10  Bus Active Control
BUSCON3.ALECTL3   9   ALE Lengthening Control
BUSCON3.EWEN3     8   Early Write Enable
BUSCON3.BTYP_7    7   External Bus Configuration - bit 7
BUSCON3.BTYP_6    6   External Bus Configuration - bit 6
BUSCON3.MTTC3     5   Memory Tristate Time Control
BUSCON3.RWDC3     4   Read/Write Delay Control for BUSCON
BUSCON3.MCTC_3    3   Memory Cycle Time Control - bit 3
BUSCON3.MCTC_2    2   Memory Cycle Time Control - bit 2
BUSCON3.MCTC_1    1   Memory Cycle Time Control - bit 1
BUSCON3.MCTC_0    0   Memory Cycle Time Control - bit 0
BUSCON4          0xFF1A   Bus Configuration Register 4
BUSCON4.CSWEN4    15  Write Chip Select Enable
BUSCON4.CSREN4    14  Read Chip Select Enable
BUSCON4.RDYEN4    12  READY Input Enable
BUSCON4.BSWC4     11  BUSCON Switch Control
BUSCON4.BUSACT4   10  Bus Active Control
BUSCON4.ALECTL4   9   ALE Lengthening Control
BUSCON4.EWEN4     8   Early Write Enable
BUSCON4.BTYP_7    7   External Bus Configuration - bit 7
BUSCON4.BTYP_6    6   External Bus Configuration - bit 6
BUSCON4.MTTC4     5   Memory Tristate Time Control
BUSCON4.RWDC4     4   Read/Write Delay Control for BUSCON
BUSCON4.MCTC_3    3   Memory Cycle Time Control - bit 3
BUSCON4.MCTC_2    2   Memory Cycle Time Control - bit 2
BUSCON4.MCTC_1    1   Memory Cycle Time Control - bit 1
BUSCON4.MCTC_0    0   Memory Cycle Time Control - bit 0
ZEROS            0xFF1C   Constant Value 0's Register (read only)
ONES             0xFF1E   Constant Value 1's Register (read only)
T78CON           0xFF20   CAPCOM Timer 7 and 8 Control Register      
T78CON.T8R        14  Timer/Counter 8 Run Control
T78CON.T8M        11  Timer/Counter 8 Mode Selection
T78CON.T8I_10     10  Timer/Counter 8 Input Selection - bit 10
T78CON.T8I_9      9   Timer/Counter 8 Input Selection - bit 9 
T78CON.T8I_8      8   Timer/Counter 8 Input Selection - bit 8 
T78CON.T7R        6   Timer/Counter 7 Run Control
T78CON.T7M        3   Timer/Counter 7 Mode Selection
T78CON.T7I_2      2   Timer/Counter 7 Input Selection - bit 2
T78CON.T7I_1      1   Timer/Counter 7 Input Selection - bit 1
T78CON.T7I_0      0   Timer/Counter 7 Input Selection - bit 0
CCM4             0xFF22   CAPCOM Mode Control Register 4
CCM4.ACC19        15  Allocation Bit for Capture/Compare Register CC4
CCM4.CCMOD19_14   14  Mode Selection for Capture/Compare Register CC4 bit 14
CCM4.CCMOD19_13   13  Mode Selection for Capture/Compare Register CC4 bit 13
CCM4.CCMOD19_12   12  Mode Selection for Capture/Compare Register CC4 bit 12
CCM4.ACC18        11  Allocation Bit for Capture/Compare Register CC4       
CCM4.CCMOD18_10   10  Mode Selection for Capture/Compare Register CC4 bit 10
CCM4.CCMOD18_9    9   Mode Selection for Capture/Compare Register CC4 bit 9 
CCM4.CCMOD18_8    8   Mode Selection for Capture/Compare Register CC4 bit 8 
CCM4.ACC17        7   Allocation Bit for Capture/Compare Register CC4       
CCM4.CCMOD17_6    6   Mode Selection for Capture/Compare Register CC4 bit 6 
CCM4.CCMOD17_5    5   Mode Selection for Capture/Compare Register CC4 bit 5 
CCM4.CCMOD17_4    4   Mode Selection for Capture/Compare Register CC4 bit 4 
CCM4.ACC16        3   Allocation Bit for Capture/Compare Register CC4       
CCM4.CCMOD16_2    2   Mode Selection for Capture/Compare Register CC4 bit 2 
CCM4.CCMOD16_1    1   Mode Selection for Capture/Compare Register CC4 bit 1 
CCM4.CCMOD16_0    0   Mode Selection for Capture/Compare Register CC4 bit 0 
CCM5             0xFF24 CAPCOM Mode Control Register 5
CCM5.ACC23        15  Allocation Bit for Capture/Compare Register CC4       
CCM5.CCMOD23_14   14  Mode Selection for Capture/Compare Register CC4 bit 14
CCM5.CCMOD23_13   13  Mode Selection for Capture/Compare Register CC4 bit 13
CCM5.CCMOD23_12   12  Mode Selection for Capture/Compare Register CC4 bit 12
CCM5.ACC22        11  Allocation Bit for Capture/Compare Register CC4       
CCM5.CCMOD22_10   10  Mode Selection for Capture/Compare Register CC4 bit 10
CCM5.CCMOD22_9    9   Mode Selection for Capture/Compare Register CC4 bit 9 
CCM5.CCMOD22_8    8   Mode Selection for Capture/Compare Register CC4 bit 8 
CCM5.ACC21        7   Allocation Bit for Capture/Compare Register CC4       
CCM5.CCMOD21_6    6   Mode Selection for Capture/Compare Register CC4 bit 6 
CCM5.CCMOD21_5    5   Mode Selection for Capture/Compare Register CC4 bit 5 
CCM5.CCMOD21_4    4   Mode Selection for Capture/Compare Register CC4 bit 4 
CCM5.ACC20        3   Allocation Bit for Capture/Compare Register CC4       
CCM5.CCMOD20_2    2   Mode Selection for Capture/Compare Register CC4 bit 2 
CCM5.CCMOD20_1    1   Mode Selection for Capture/Compare Register CC4 bit 1 
CCM5.CCMOD20_0    0   Mode Selection for Capture/Compare Register CC4 bit 0 
CCM6             0xFF26 CAPCOM Mode Control Register 6
CCM6.ACC27        15  Allocation Bit for Capture/Compare Register CC4       
CCM6.CCMOD27_14   14  Mode Selection for Capture/Compare Register CC4 bit 14
CCM6.CCMOD27_13   13  Mode Selection for Capture/Compare Register CC4 bit 13
CCM6.CCMOD27_12   12  Mode Selection for Capture/Compare Register CC4 bit 12
CCM6.ACC26        11  Allocation Bit for Capture/Compare Register CC4       
CCM6.CCMOD26_10   10  Mode Selection for Capture/Compare Register CC4 bit 10
CCM6.CCMOD26_9    9   Mode Selection for Capture/Compare Register CC4 bit 9 
CCM6.CCMOD26_8    8   Mode Selection for Capture/Compare Register CC4 bit 8 
CCM6.ACC25        7   Allocation Bit for Capture/Compare Register CC4       
CCM6.CCMOD25_6    6   Mode Selection for Capture/Compare Register CC4 bit 6 
CCM6.CCMOD25_5    5   Mode Selection for Capture/Compare Register CC4 bit 5 
CCM6.CCMOD25_4    4   Mode Selection for Capture/Compare Register CC4 bit 4 
CCM6.ACC24        3   Allocation Bit for Capture/Compare Register CC4       
CCM6.CCMOD24_2    2   Mode Selection for Capture/Compare Register CC4 bit 2 
CCM6.CCMOD24_1    1   Mode Selection for Capture/Compare Register CC4 bit 1 
CCM6.CCMOD24_0    0   Mode Selection for Capture/Compare Register CC4 bit 0 
CCM7             0xFF28 CAPCOM Mode Control Register 7
CCM7.ACC31        15  Allocation Bit for Capture/Compare Register CC4       
CCM7.CCMOD31_14   14  Mode Selection for Capture/Compare Register CC4 bit 14
CCM7.CCMOD31_13   13  Mode Selection for Capture/Compare Register CC4 bit 13
CCM7.CCMOD31_12   12  Mode Selection for Capture/Compare Register CC4 bit 12
CCM7.ACC30        11  Allocation Bit for Capture/Compare Register CC4       
CCM7.CCMOD30_10   10  Mode Selection for Capture/Compare Register CC4 bit 10
CCM7.CCMOD30_9    9   Mode Selection for Capture/Compare Register CC4 bit 9 
CCM7.CCMOD30_8    8   Mode Selection for Capture/Compare Register CC4 bit 8 
CCM7.ACC29        7   Allocation Bit for Capture/Compare Register CC4       
CCM7.CCMOD29_6    6   Mode Selection for Capture/Compare Register CC4 bit 6 
CCM7.CCMOD29_5    5   Mode Selection for Capture/Compare Register CC4 bit 5 
CCM7.CCMOD29_4    4   Mode Selection for Capture/Compare Register CC4 bit 4 
CCM7.ACC28        3   Allocation Bit for Capture/Compare Register CC4       
CCM7.CCMOD28_2    2   Mode Selection for Capture/Compare Register CC4 bit 2 
CCM7.CCMOD28_1    1   Mode Selection for Capture/Compare Register CC4 bit 1 
CCM7.CCMOD28_0    0   Mode Selection for Capture/Compare Register CC4 bit 0 
T2CON            0xFF40   GPT1 Timer 2 Control Register
T2CON.T2OTL       10  Timer 2 Output Toggle Latch
T2CON.T2OE        9   Alternate Output Function Enable
T2CON.T2UDE       8   Timer 2 External Up/Down Enable
T2CON.T2UD        7   Timer 2 Up / Down Control
T2CON.T2R         6   Timer 2 Run Bit
T2CON.T2M_5       5   Timer 2 Mode Control - bit 5
T2CON.T2M_4       4   Timer 2 Mode Control - bit 4
T2CON.T2M_3       3   Timer 2 Mode Control - bit 3
T2CON.T2I_2       2   Timer 2 Input Selection - bit 2
T2CON.T2I_1       1   Timer 2 Input Selection - bit 1
T2CON.T2I_0       0   Timer 2 Input Selection - bit 0
T3CON            0xFF42   GPT1 Timer 3 Control Register
T3CON.T3OTL       10  Timer 3 Output Toggle Latch
T3CON.T3OE        9   Alternate Output Function Enable
T3CON.T3UDE       8   Timer 3 External Up/Down Enable
T3CON.T3UD        7   Timer 3 Up / Down Control
T3CON.T3R         6   Timer 3 Run Bit
T3CON.T3M_5       5   Timer 3 Mode Control - bit 5
T3CON.T3M_4       4   Timer 3 Mode Control - bit 4
T3CON.T3M_3       3   Timer 3 Mode Control - bit 3
T3CON.T3I_2       2   Timer 3 Input Selection - bit 2
T3CON.T3I_1       1   Timer 3 Input Selection - bit 1
T3CON.T3I_0       0   Timer 3 Input Selection - bit 0
T4CON            0xFF44   GPT1 Timer 4 Control Register
T4CON.T4OTL       10  Timer 4 Output Toggle Latch
T4CON.T4OE        9   Alternate Output Function Enable
T4CON.T4UDE       8   Timer 4 External Up/Down Enable
T4CON.T4UD        7   Timer 4 Up / Down Control
T4CON.T4R         6   Timer 4 Run Bit
T4CON.T4M_5       5   Timer 4 Mode Control - bit 5
T4CON.T4M_4       4   Timer 4 Mode Control - bit 4
T4CON.T4M_3       3   Timer 4 Mode Control - bit 3
T4CON.T4I_2       2   Timer 4 Input Selection - bit 2
T4CON.T4I_1       1   Timer 4 Input Selection - bit 1
T4CON.T4I_0       0   Timer 4 Input Selection - bit 0
T5CON            0xFF46   GPT2 Timer 5 Control Register
T5CON.T5SR        15  Timer 5 Reload Mode Enable
T5CON.T5CLR       14  Timer 5 Clear Bit
T5CON.CI_13       13  Register CAPREL Capture Trigger Selection - bit 13
T5CON.CI_12       12  Register CAPREL Capture Trigger Selection - bit 12
T5CON.CT3         10  Timer 3 Capture Trigger Enable
T5CON.T5UD        7   Timer 5 Up / Down Control
T5CON.T5R         6   Timer 5 Run Bit
T5CON.T5M_5       5   Timer 5 Mode Control - bit 5
T5CON.T5M_4       4   Timer 5 Mode Control - bit 4
T5CON.T5M_3       3   Timer 5 Mode Control - bit 3
T5CON.T5I_2       2   Timer 5 Input Selection - bit 2
T5CON.T5I_1       1   Timer 5 Input Selection - bit 1
T5CON.T5I_0       0   Timer 5 Input Selection - bit 0
T6CON            0xFF48   GPT2 Timer 6 Control Register
T6CON.T6SR        15  Timer 6 Reload Mode Enable
T6CON.T6OTL       10  Timer 6 Output Toggle Latch
T6CON.T6OE        9   Alternate Output Function Enable
T6CON.T6UD        7   Timer 6 Up / Down Control
T6CON.T6R         6   Timer 6 Run Bit
T6CON.T6M_5       5   Timer 6 Mode Control - bit 5
T6CON.T6M_4       4   Timer 6 Mode Control - bit 4
T6CON.T6M_3       3   Timer 6 Mode Control - bit 3
T6CON.T6I_2       2   Timer 6 Input Selection - bit 2
T6CON.T6I_1       1   Timer 6 Input Selection - bit 1
T6CON.T6I_0       0   Timer 6 Input Selection - bit 0
T01CON           0xFF50   CAPCOM Timer 0 and Timer 1 Ctrl. Reg.
T01CON.T1R        14  Timer/Counter 1 Run Control
T01CON.T1M        11  Timer/Counter 1 Mode Selection
T01CON.T1I_10     10  Timer/Counter 1 Input Selection - bit 10
T01CON.T1I_9      9   Timer/Counter 1 Input Selection - bit 9 
T01CON.T1I_8      8   Timer/Counter 1 Input Selection - bit 8 
T01CON.T0R        6   Timer/Counter 0 Run Control
T01CON.T0M        3   Timer/Counter 0 Mode Selection
T01CON.T0I_2      2   Timer/Counter 0 Input Selection - bit 2
T01CON.T0I_1      1   Timer/Counter 0 Input Selection - bit 1
T01CON.T0I_0      0   Timer/Counter 0 Input Selection - bit 0
CCM0             0xFF52   CAPCOM Mode Control Register 0
CCM0.ACC3         15  Allocation Bit for Capture/Compare Register CC0       
CCM0.CCMOD3_14    14  Mode Selection for Capture/Compare Register CC0 bit 14
CCM0.CCMOD3_13    13  Mode Selection for Capture/Compare Register CC0 bit 13
CCM0.CCMOD3_12    12  Mode Selection for Capture/Compare Register CC0 bit 12
CCM0.ACC2         11  Allocation Bit for Capture/Compare Register CC0       
CCM0.CCMOD2_10    10  Mode Selection for Capture/Compare Register CC0 bit 10
CCM0.CCMOD2_9     9   Mode Selection for Capture/Compare Register CC0 bit 9 
CCM0.CCMOD2_8     8   Mode Selection for Capture/Compare Register CC0 bit 8 
CCM0.ACC1         7   Allocation Bit for Capture/Compare Register CC0       
CCM0.CCMOD1_6     6   Mode Selection for Capture/Compare Register CC0 bit 6 
CCM0.CCMOD1_5     5   Mode Selection for Capture/Compare Register CC0 bit 5 
CCM0.CCMOD1_4     4   Mode Selection for Capture/Compare Register CC0 bit 4 
CCM0.ACC0         3   Allocation Bit for Capture/Compare Register CC0       
CCM0.CCMOD0_2     2   Mode Selection for Capture/Compare Register CC0 bit 2 
CCM0.CCMOD0_1     1   Mode Selection for Capture/Compare Register CC0 bit 1 
CCM0.CCMOD0_0     0   Mode Selection for Capture/Compare Register CC0 bit 0 
CCM1             0xFF54   CAPCOM Mode Control Register 1
CCM1.ACC7         15  Allocation Bit for Capture/Compare Register CC1       
CCM1.CCMOD7_14    14  Mode Selection for Capture/Compare Register CC1 bit 14
CCM1.CCMOD7_13    13  Mode Selection for Capture/Compare Register CC1 bit 13
CCM1.CCMOD7_12    12  Mode Selection for Capture/Compare Register CC1 bit 12
CCM1.ACC6         11  Allocation Bit for Capture/Compare Register CC1       
CCM1.CCMOD6_10    10  Mode Selection for Capture/Compare Register CC1 bit 10
CCM1.CCMOD6_9     9   Mode Selection for Capture/Compare Register CC1 bit 9 
CCM1.CCMOD6_8     8   Mode Selection for Capture/Compare Register CC1 bit 8 
CCM1.ACC5         7   Allocation Bit for Capture/Compare Register CC1       
CCM1.CCMOD5_6     6   Mode Selection for Capture/Compare Register CC1 bit 6 
CCM1.CCMOD5_5     5   Mode Selection for Capture/Compare Register CC1 bit 5 
CCM1.CCMOD5_4     4   Mode Selection for Capture/Compare Register CC1 bit 4 
CCM1.ACC4         3   Allocation Bit for Capture/Compare Register CC1       
CCM1.CCMOD4_2     2   Mode Selection for Capture/Compare Register CC1 bit 2 
CCM1.CCMOD4_1     1   Mode Selection for Capture/Compare Register CC1 bit 1 
CCM1.CCMOD4_0     0   Mode Selection for Capture/Compare Register CC1 bit 0 
CCM2             0xFF56 CAPCOM Mode Control Register 2
CCM2.ACC11        15  Allocation Bit for Capture/Compare Register CC2
CCM2.CCMOD11_14   14  Mode Selection for Capture/Compare Register CC2 bit 14
CCM2.CCMOD11_13   13  Mode Selection for Capture/Compare Register CC2 bit 13
CCM2.CCMOD11_12   12  Mode Selection for Capture/Compare Register CC2 bit 12
CCM2.ACC10        11  Allocation Bit for Capture/Compare Register CC2     
CCM2.CCMOD10_10   10  Mode Selection for Capture/Compare Register CC2 bit 10
CCM2.CCMOD10_9    9   Mode Selection for Capture/Compare Register CC2 bit 9 
CCM2.CCMOD10_8    8   Mode Selection for Capture/Compare Register CC2 bit 8 
CCM2.ACC9         7   Allocation Bit for Capture/Compare Register CC2     
CCM2.CCMOD9_6     6   Mode Selection for Capture/Compare Register CC2 bit 6
CCM2.CCMOD9_5     5   Mode Selection for Capture/Compare Register CC2 bit 5
CCM2.CCMOD9_4     4   Mode Selection for Capture/Compare Register CC2 bit 4
CCM2.ACC8         3   Allocation Bit for Capture/Compare Register CC2      
CCM2.CCMOD8_2     2   Mode Selection for Capture/Compare Register CC2 bit 2
CCM2.CCMOD8_1     1   Mode Selection for Capture/Compare Register CC2 bit 1
CCM2.CCMOD8_0     0   Mode Selection for Capture/Compare Register CC2 bit 0
CCM3             0xFF58 CAPCOM Mode Control Register 3
CCM3.ACC15        15  Allocation Bit for Capture/Compare Register CC3       
CCM3.CCMOD15_14   14  Mode Selection for Capture/Compare Register CC3 bit 14
CCM3.CCMOD15_13   13  Mode Selection for Capture/Compare Register CC3 bit 13
CCM3.CCMOD15_12   12  Mode Selection for Capture/Compare Register CC3 bit 12
CCM3.ACC14        11  Allocation Bit for Capture/Compare Register CC3       
CCM3.CCMOD14_10   10  Mode Selection for Capture/Compare Register CC3 bit 10
CCM3.CCMOD14_9    9   Mode Selection for Capture/Compare Register CC3 bit 9 
CCM3.CCMOD14_8    8   Mode Selection for Capture/Compare Register CC3 bit 8 
CCM3.ACC13        7   Allocation Bit for Capture/Compare Register CC3       
CCM3.CCMOD13_6    6   Mode Selection for Capture/Compare Register CC3 bit 6 
CCM3.CCMOD13_5    5   Mode Selection for Capture/Compare Register CC3 bit 5 
CCM3.CCMOD13_4    4   Mode Selection for Capture/Compare Register CC3 bit 4 
CCM3.ACC12        3   Allocation Bit for Capture/Compare Register CC3       
CCM3.CCMOD12_2    2   Mode Selection for Capture/Compare Register CC3 bit 2 
CCM3.CCMOD12_1    1   Mode Selection for Capture/Compare Register CC3 bit 1 
CCM3.CCMOD12_0    0   Mode Selection for Capture/Compare Register CC3 bit 0 
T2IC             0xFF60   GPT1 Timer 2 Interrupt Control Register
T2IC.T2IR         7   Interrupt Request Flag
T2IC.T2IE         6   Interrupt Enable Control Bit (individually enables/disables a specific source)
T2IC.ILVL_5       5   Interrupt Priority Level - bit 5
T2IC.ILVL_4       4   Interrupt Priority Level - bit 4
T2IC.ILVL_3       3   Interrupt Priority Level - bit 3
T2IC.ILVL_2       2   Interrupt Priority Level - bit 2
T2IC.GLVL_1       1   Group Level - bit 1
T2IC.GLVL_0       0   Group Level - bit 0
T3IC             0xFF62   GPT1 Timer 3 Interrupt Control Register
T3IC.T3IR         7   Interrupt Request Flag
T3IC.T3IE         6   Interrupt Enable Control Bit (individually enables/disables a specific source)
T3IC.ILVL_5       5   Interrupt Priority Level - bit 5
T3IC.ILVL_4       4   Interrupt Priority Level - bit 4
T3IC.ILVL_3       3   Interrupt Priority Level - bit 3
T3IC.ILVL_2       2   Interrupt Priority Level - bit 2
T3IC.GLVL_1       1   Group Level - bit 1
T3IC.GLVL_0       0   Group Level - bit 0
T4IC             0xFF64   GPT1 Timer 4 Interrupt Control Register
T4IC.T4IR         7   Interrupt Request Flag
T4IC.T4IE         6   Interrupt Enable Control Bit (individually enables/disables a specific source)
T4IC.ILVL_5       5   Interrupt Priority Level - bit 5
T4IC.ILVL_4       4   Interrupt Priority Level - bit 4
T4IC.ILVL_3       3   Interrupt Priority Level - bit 3
T4IC.ILVL_2       2   Interrupt Priority Level - bit 2
T4IC.GLVL_1       1   Group Level - bit 1
T4IC.GLVL_0       0   Group Level - bit 0
T5IC             0xFF66   GPT2 Timer 5 Interrupt Control Register
T5IC.T5IR         7   Interrupt Request Flag
T5IC.T5IE         6   Interrupt Enable Control Bit (individually enables/disables a specific source)
T5IC.ILVL_5       5   Interrupt Priority Level - bit 5
T5IC.ILVL_4       4   Interrupt Priority Level - bit 4
T5IC.ILVL_3       3   Interrupt Priority Level - bit 3
T5IC.ILVL_2       2   Interrupt Priority Level - bit 2
T5IC.GLVL_1       1   Group Level - bit 1
T5IC.GLVL_0       0   Group Level - bit 0
T6IC             0xFF68   GPT2 Timer 6 Interrupt Control Register
T6IC.T2IR         7   Interrupt Request Flag
T6IC.T2IE         6   Interrupt Enable Control Bit (individually enables/disables a specific source)
T6IC.ILVL_5       5   Interrupt Priority Level - bit 5
T6IC.ILVL_4       4   Interrupt Priority Level - bit 4
T6IC.ILVL_3       3   Interrupt Priority Level - bit 3
T6IC.ILVL_2       2   Interrupt Priority Level - bit 2
T6IC.GLVL_1       1   Group Level - bit 1
T6IC.GLVL_0       0   Group Level - bit 0
CRIC             0xFF6A   GPT2 CAPREL Interrupt Control Register
CRIC.CRIR         7   Interrupt Request Flag
CRIC.CRIE         6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CRIC.ILVL_5       5   Interrupt Priority Level - bit 5
CRIC.ILVL_4       4   Interrupt Priority Level - bit 4
CRIC.ILVL_3       3   Interrupt Priority Level - bit 3
CRIC.ILVL_2       2   Interrupt Priority Level - bit 2
CRIC.GLVL_1       1   Group Level - bit 1
CRIC.GLVL_0       0   Group Level - bit 0
S0TIC            0xFF6C   Serial Channel 0 Transmit Interrupt Control Register
S0TIC.S0TIR       7   Interrupt Request Flag
S0TIC.S0TIE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
S0TIC.ILVL_5      5   Interrupt Priority Level - bit 5
S0TIC.ILVL_4      4   Interrupt Priority Level - bit 4
S0TIC.ILVL_3      3   Interrupt Priority Level - bit 3
S0TIC.ILVL_2      2   Interrupt Priority Level - bit 2
S0TIC.GLVL_1      1   Group Level - bit 1
S0TIC.GLVL_0      0   Group Level - bit 0
S0RIC            0xFF6E   Serial Channel 0 Receive Interrupt Control Register
S0RIC.S0RIR       7   Interrupt Request Flag
S0RIC.S0RIE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
S0RIC.ILVL_5      5   Interrupt Priority Level - bit 5
S0RIC.ILVL_4      4   Interrupt Priority Level - bit 4
S0RIC.ILVL_3      3   Interrupt Priority Level - bit 3
S0RIC.ILVL_2      2   Interrupt Priority Level - bit 2
S0RIC.GLVL_1      1   Group Level - bit 1
S0RIC.GLVL_0      0   Group Level - bit 0
S0EIC            0xFF70   Serial Channel 0 Error Interrupt Control Register
S0EIC.S0EIR       7   Interrupt Request Flag
S0EIC.S0EIE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
S0EIC.ILVL_5      5   Interrupt Priority Level - bit 5
S0EIC.ILVL_4      4   Interrupt Priority Level - bit 4
S0EIC.ILVL_3      3   Interrupt Priority Level - bit 3
S0EIC.ILVL_2      2   Interrupt Priority Level - bit 2
S0EIC.GLVL_1      1   Group Level - bit 1
S0EIC.GLVL_0      0   Group Level - bit 0
SSCTIC           0xFF72   SSC Transmit Interrupt Control Register
SSCTIC.SSCTIR     7   Interrupt Request Flag
SSCTIC.SSCTIE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
SSCTIC.ILVL_5     5   Interrupt Priority Level - bit 5
SSCTIC.ILVL_4     4   Interrupt Priority Level - bit 4
SSCTIC.ILVL_3     3   Interrupt Priority Level - bit 3
SSCTIC.ILVL_2     2   Interrupt Priority Level - bit 2
SSCTIC.GLVL_1     1   Group Level - bit 1
SSCTIC.GLVL_0     0   Group Level - bit 0
SSCRIC           0xFF74   SSC Receive Interrupt Control Register
SSCRIC.SSCRIR     7   Interrupt Request Flag
SSCRIC.SSCRIE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
SSCRIC.ILVL_5     5   Interrupt Priority Level - bit 5
SSCRIC.ILVL_4     4   Interrupt Priority Level - bit 4
SSCRIC.ILVL_3     3   Interrupt Priority Level - bit 3
SSCRIC.ILVL_2     2   Interrupt Priority Level - bit 2
SSCRIC.GLVL_1     1   Group Level - bit 1
SSCRIC.GLVL_0     0   Group Level - bit 0
SSCEIC           0xFF76   SSC Error Interrupt Control Register
SSCEIC.SSCEIR     7   Interrupt Request Flag
SSCEIC.SSCEIE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
SSCEIC.ILVL_5     5   Interrupt Priority Level - bit 5
SSCEIC.ILVL_4     4   Interrupt Priority Level - bit 4
SSCEIC.ILVL_3     3   Interrupt Priority Level - bit 3
SSCEIC.ILVL_2     2   Interrupt Priority Level - bit 2
SSCEIC.GLVL_1     1   Group Level - bit 1
SSCEIC.GLVL_0     0   Group Level - bit 0
CC0IC            0xFF78   CAPCOM Register 0 Interrupt Ctrl. Reg.
CC0IC.CC0IR       7   Interrupt Request Flag
CC0IC.CC0IE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC0IC.ILVL_5      5   Interrupt Priority Level - bit 5
CC0IC.ILVL_4      4   Interrupt Priority Level - bit 4
CC0IC.ILVL_3      3   Interrupt Priority Level - bit 3
CC0IC.ILVL_2      2   Interrupt Priority Level - bit 2
CC0IC.GLVL_1      1   Group Level - bit 1
CC0IC.GLVL_0      0   Group Level - bit 0
CC1IC            0xFF7A   CAPCOM Register 1 Interrupt Ctrl. Reg.
CC1IC.CC1IR       7   Interrupt Request Flag
CC1IC.CC1IE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC1IC.ILVL_5      5   Interrupt Priority Level - bit 5
CC1IC.ILVL_4      4   Interrupt Priority Level - bit 4
CC1IC.ILVL_3      3   Interrupt Priority Level - bit 3
CC1IC.ILVL_2      2   Interrupt Priority Level - bit 2
CC1IC.GLVL_1      1   Group Level - bit 1
CC1IC.GLVL_0      0   Group Level - bit 0
CC2IC            0xFF7C   CAPCOM Register 2 Interrupt Ctrl. Reg.
CC2IC.CC2IR       7   Interrupt Request Flag
CC2IC.CC2IE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC2IC.ILVL_5      5   Interrupt Priority Level - bit 5
CC2IC.ILVL_4      4   Interrupt Priority Level - bit 4
CC2IC.ILVL_3      3   Interrupt Priority Level - bit 3
CC2IC.ILVL_2      2   Interrupt Priority Level - bit 2
CC2IC.GLVL_1      1   Group Level - bit 1
CC2IC.GLVL_0      0   Group Level - bit 0
CC3IC            0xFF7E   CAPCOM Register 3 Interrupt Ctrl. Reg.
CC3IC.CC3IR       7   Interrupt Request Flag
CC3IC.CC3IE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC3IC.ILVL_5      5   Interrupt Priority Level - bit 5
CC3IC.ILVL_4      4   Interrupt Priority Level - bit 4
CC3IC.ILVL_3      3   Interrupt Priority Level - bit 3
CC3IC.ILVL_2      2   Interrupt Priority Level - bit 2
CC3IC.GLVL_1      1   Group Level - bit 1
CC3IC.GLVL_0      0   Group Level - bit 0
CC4IC            0xFF80   CAPCOM Register 4 Interrupt Ctrl. Reg.
CC4IC.CC4IR       7   Interrupt Request Flag
CC4IC.CC4IE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC4IC.ILVL_5      5   Interrupt Priority Level - bit 5
CC4IC.ILVL_4      4   Interrupt Priority Level - bit 4
CC4IC.ILVL_3      3   Interrupt Priority Level - bit 3
CC4IC.ILVL_2      2   Interrupt Priority Level - bit 2
CC4IC.GLVL_1      1   Group Level - bit 1
CC4IC.GLVL_0      0   Group Level - bit 0
CC5IC            0xFF82   CAPCOM Register 5 Interrupt Ctrl. Reg.
CC5IC.CC5IR       7   Interrupt Request Flag
CC5IC.CC5IE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC5IC.ILVL_5      5   Interrupt Priority Level - bit 5
CC5IC.ILVL_4      4   Interrupt Priority Level - bit 4
CC5IC.ILVL_3      3   Interrupt Priority Level - bit 3
CC5IC.ILVL_2      2   Interrupt Priority Level - bit 2
CC5IC.GLVL_1      1   Group Level - bit 1
CC5IC.GLVL_0      0   Group Level - bit 0
CC6IC            0xFF84   CAPCOM Register 6 Interrupt Ctrl. Reg.
CC6IC.CC6IR       7   Interrupt Request Flag
CC6IC.CC6IE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC6IC.ILVL_5      5   Interrupt Priority Level - bit 5
CC6IC.ILVL_4      4   Interrupt Priority Level - bit 4
CC6IC.ILVL_3      3   Interrupt Priority Level - bit 3
CC6IC.ILVL_2      2   Interrupt Priority Level - bit 2
CC6IC.GLVL_1      1   Group Level - bit 1
CC6IC.GLVL_0      0   Group Level - bit 0
CC7IC            0xFF86   CAPCOM Register 7 Interrupt Ctrl. Reg.
CC7IC.CC7IR       7   Interrupt Request Flag
CC7IC.CC7IE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC7IC.ILVL_5      5   Interrupt Priority Level - bit 5
CC7IC.ILVL_4      4   Interrupt Priority Level - bit 4
CC7IC.ILVL_3      3   Interrupt Priority Level - bit 3
CC7IC.ILVL_2      2   Interrupt Priority Level - bit 2
CC7IC.GLVL_1      1   Group Level - bit 1
CC7IC.GLVL_0      0   Group Level - bit 0
CC8IC            0xFF88   CAPCOM Register 8 Interrupt Ctrl. Reg.
CC8IC.CC8IR       7   Interrupt Request Flag
CC8IC.CC8IE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC8IC.ILVL_5      5   Interrupt Priority Level - bit 5
CC8IC.ILVL_4      4   Interrupt Priority Level - bit 4
CC8IC.ILVL_3      3   Interrupt Priority Level - bit 3
CC8IC.ILVL_2      2   Interrupt Priority Level - bit 2
CC8IC.GLVL_1      1   Group Level - bit 1
CC8IC.GLVL_0      0   Group Level - bit 0
CC9IC            0xFF8A   CAPCOM Register 9 Interrupt Ctrl. Reg.
CC9IC.CC9IR       7   Interrupt Request Flag
CC9IC.CC9IE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC9IC.ILVL_5      5   Interrupt Priority Level - bit 5
CC9IC.ILVL_4      4   Interrupt Priority Level - bit 4
CC9IC.ILVL_3      3   Interrupt Priority Level - bit 3
CC9IC.ILVL_2      2   Interrupt Priority Level - bit 2
CC9IC.GLVL_1      1   Group Level - bit 1
CC9IC.GLVL_0      0   Group Level - bit 0
CC10IC           0xFF8C   CAPCOM Register 10 Interrupt Ctrl. Reg.
CC10IC.CC10IR     7   Interrupt Request Flag
CC10IC.CC10IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC10IC.ILVL_5     5   Interrupt Priority Level - bit 5
CC10IC.ILVL_4     4   Interrupt Priority Level - bit 4
CC10IC.ILVL_3     3   Interrupt Priority Level - bit 3
CC10IC.ILVL_2     2   Interrupt Priority Level - bit 2
CC10IC.GLVL_1     1   Group Level - bit 1
CC10IC.GLVL_0     0   Group Level - bit 0
CC11IC           0xFF8E   CAPCOM Register 11 Interrupt Ctrl. Reg.
CC11IC.CC11IR     7   Interrupt Request Flag
CC11IC.CC11IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC11IC.ILVL_5     5   Interrupt Priority Level - bit 5
CC11IC.ILVL_4     4   Interrupt Priority Level - bit 4
CC11IC.ILVL_3     3   Interrupt Priority Level - bit 3
CC11IC.ILVL_2     2   Interrupt Priority Level - bit 2
CC11IC.GLVL_1     1   Group Level - bit 1
CC11IC.GLVL_0     0   Group Level - bit 0
CC12IC           0xFF90   CAPCOM Register 12 Interrupt Ctrl. Reg.
CC12IC.CC12IR     7   Interrupt Request Flag
CC12IC.CC12IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC12IC.ILVL_5     5   Interrupt Priority Level - bit 5
CC12IC.ILVL_4     4   Interrupt Priority Level - bit 4
CC12IC.ILVL_3     3   Interrupt Priority Level - bit 3
CC12IC.ILVL_2     2   Interrupt Priority Level - bit 2
CC12IC.GLVL_1     1   Group Level - bit 1
CC12IC.GLVL_0     0   Group Level - bit 0
CC13IC           0xFF92   CAPCOM Register 13 Interrupt Ctrl. Reg.
CC13IC.CC13IR     7   Interrupt Request Flag
CC13IC.CC13IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC13IC.ILVL_5     5   Interrupt Priority Level - bit 5
CC13IC.ILVL_4     4   Interrupt Priority Level - bit 4
CC13IC.ILVL_3     3   Interrupt Priority Level - bit 3
CC13IC.ILVL_2     2   Interrupt Priority Level - bit 2
CC13IC.GLVL_1     1   Group Level - bit 1
CC13IC.GLVL_0     0   Group Level - bit 0
CC14IC           0xFF94   CAH CAPCOM Register 14 Interrupt Ctrl. Reg.
CC14IC.CC14IR     7   Interrupt Request Flag
CC14IC.CC14IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC14IC.ILVL_5     5   Interrupt Priority Level - bit 5
CC14IC.ILVL_4     4   Interrupt Priority Level - bit 4
CC14IC.ILVL_3     3   Interrupt Priority Level - bit 3
CC14IC.ILVL_2     2   Interrupt Priority Level - bit 2
CC14IC.GLVL_1     1   Group Level - bit 1
CC14IC.GLVL_0     0   Group Level - bit 0
CC15IC           0xFF96   CBH CAPCOM Register 15 Interrupt Ctrl. Reg.
CC15IC.CC15IR     7   Interrupt Request Flag
CC15IC.CC15IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC15IC.ILVL_5     5   Interrupt Priority Level - bit 5
CC15IC.ILVL_4     4   Interrupt Priority Level - bit 4
CC15IC.ILVL_3     3   Interrupt Priority Level - bit 3
CC15IC.ILVL_2     2   Interrupt Priority Level - bit 2
CC15IC.GLVL_1     1   Group Level - bit 1
CC15IC.GLVL_0     0   Group Level - bit 0
ADCIC            0xFF98   CCH A/D Converter End of Conversion Interrupt Control Register
ADCIC.ADCIR       7   Interrupt Request Flag
ADCIC.ADCIE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
ADCIC.ILVL_5      5   Interrupt Priority Level - bit 5
ADCIC.ILVL_4      4   Interrupt Priority Level - bit 4
ADCIC.ILVL_3      3   Interrupt Priority Level - bit 3
ADCIC.ILVL_2      2   Interrupt Priority Level - bit 2
ADCIC.GLVL_1      1   Group Level - bit 1
ADCIC.GLVL_0      0   Group Level - bit 0
ADEIC            0xFF9A   CDH A/D Converter Overrun Error Interrupt Control Register
ADEIC.ADEIR       7   Interrupt Request Flag
ADEIC.ADEIE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
ADEIC.ILVL_5      5   Interrupt Priority Level - bit 5
ADEIC.ILVL_4      4   Interrupt Priority Level - bit 4
ADEIC.ILVL_3      3   Interrupt Priority Level - bit 3
ADEIC.ILVL_2      2   Interrupt Priority Level - bit 2
ADEIC.GLVL_1      1   Group Level - bit 1
ADEIC.GLVL_0      0   Group Level - bit 0
T0IC             0xFF9C   CEH CAPCOM Timer 0 Interrupt Ctrl. Reg.
T0IC.T0IR         7   Interrupt Request Flag
T0IC.T0IE         6   Interrupt Enable Control Bit (individually enables/disables a specific source)
T0IC.ILVL_5       5   Interrupt Priority Level - bit 5
T0IC.ILVL_4       4   Interrupt Priority Level - bit 4
T0IC.ILVL_3       3   Interrupt Priority Level - bit 3
T0IC.ILVL_2       2   Interrupt Priority Level - bit 2
T0IC.GLVL_1       1   Group Level - bit 1
T0IC.GLVL_0       0   Group Level - bit 0
T1IC             0xFF9E   CFH CAPCOM Timer 1 Interrupt Ctrl. Reg.
T1IC.T1IR         7   Interrupt Request Flag
T1IC.T1IE         6   Interrupt Enable Control Bit (individually enables/disables a specific source)
T1IC.ILVL_5       5   Interrupt Priority Level - bit 5
T1IC.ILVL_4       4   Interrupt Priority Level - bit 4
T1IC.ILVL_3       3   Interrupt Priority Level - bit 3
T1IC.ILVL_2       2   Interrupt Priority Level - bit 2
T1IC.GLVL_1       1   Group Level - bit 1
T1IC.GLVL_0       0   Group Level - bit 0
ADCON            0xFFA0   A/D Converter Control Register
ADCON.ADCTC_15    15  ADC Conversion Time Control - bit 15
ADCON.ADCTC_14    14  ADC Conversion Time Control - bit 14
ADCON.ADSTC_13    13  ADC Sample Time Control - bit 13
ADCON.ADSTC_12    12  ADC Sample Time Control - bit 12
ADCON.ADCRQ       11  ADC Channel Injection Request Flag
ADCON.ADCIN       10  ADC Channel Injection Enable
ADCON.ADWR        9   ADC Wait for Read Control
ADCON.ADBSY       8   ADC Busy Flag
ADCON.ADST        7   ADC Start Bit
ADCON.ADM_5       5   ADC Mode Selection - bit 5
ADCON.ADM_4       4   ADC Mode Selection - bit 4
ADCON.ADCH_3      3   ADC Analog Channel Input Selection - bit 3
ADCON.ADCH_2      2   ADC Analog Channel Input Selection - bit 2
ADCON.ADCH_1      1   ADC Analog Channel Input Selection - bit 1
ADCON.ADCH_0      0   ADC Analog Channel Input Selection - bit 0
P5               0xFFA2   Port 5 Register (read only)
P5.P5_15          15  Port data register P5 bit 15
P5.P5_14          14  Port data register P5 bit 14
P5.P5_13          13  Port data register P5 bit 13
P5.P5_12          12  Port data register P5 bit 12
P5.P5_7           7   Port data register P5 bit 7 
P5.P5_6           6   Port data register P5 bit 6 
P5.P5_5           5   Port data register P5 bit 5 
P5.P5_4           4   Port data register P5 bit 4 
P5.P5_3           3   Port data register P5 bit 3 
P5.P5_2           2   Port data register P5 bit 2 
P5.P5_1           1   Port data register P5 bit 1 
P5.P5_0           0   Port data register P5 bit 0 
P5DIDIS          0xFFA4   Port 5 Digital Input Disable Register
P5DIDIS.P5D_15    15  Port 5 Bit 15 Digital Input Control
P5DIDIS.P5D_14    14  Port 5 Bit 14 Digital Input Control
P5DIDIS.P5D_13    13  Port 5 Bit 13 Digital Input Control
P5DIDIS.P5D_12    12  Port 5 Bit 12 Digital Input Control
P5DIDIS.P5D_7     7   Port 5 Bit 7  Digital Input Control
P5DIDIS.P5D_6     6   Port 5 Bit 6  Digital Input Control
P5DIDIS.P5D_5     5   Port 5 Bit 5  Digital Input Control
P5DIDIS.P5D_4     4   Port 5 Bit 4  Digital Input Control
P5DIDIS.P5D_3     3   Port 5 Bit 3  Digital Input Control
P5DIDIS.P5D_2     2   Port 5 Bit 2  Digital Input Control
P5DIDIS.P5D_1     1   Port 5 Bit 1  Digital Input Control
P5DIDIS.P5D_0     0   Port 5 Bit 0  Digital Input Control
FOCON            0xFFAA   Frequency Output Control Register
FOCON.FOEN        15  Frequency Output Enable
FOCON.FOSS        14  Frequency Output Signal Select
FOCON.FORV_13     13  Frequency Output Reload Value - bit 13
FOCON.FORV_12     12  Frequency Output Reload Value - bit 12
FOCON.FORV_11     11  Frequency Output Reload Value - bit 11
FOCON.FORV_10     10  Frequency Output Reload Value - bit 10
FOCON.FORV_9      9   Frequency Output Reload Value - bit 9 
FOCON.FORV_8      8   Frequency Output Reload Value - bit 8 
FOCON.FOTL        6   Frequency Output Toggle Latch
FOCON.FOCNT_5     5   Frequency Output Counter - bit 5
FOCON.FOCNT_4     4   Frequency Output Counter - bit 4
FOCON.FOCNT_3     3   Frequency Output Counter - bit 3
FOCON.FOCNT_2     2   Frequency Output Counter - bit 2
FOCON.FOCNT_1     1   Frequency Output Counter - bit 1
FOCON.FOCNT_0     0   Frequency Output Counter - bit 0
TFR              0xFFAC   Trap Flag Register
TFR.NMI           15  Non Maskable Interrupt Flag
TFR.STKOF         14  Stack Overflow Flag
TFR.STKUF         13  Stack Underflow Flag
TFR.UNDOPC        7   Undefined Opcode Flag
TFR.PRTFLT        3   Protection Fault Flag
TFR.ILLOPA        2   Illegal Word Operand Access Flag
TFR.ILLINA        1   Illegal Instruction Access Flag
TFR.ILLBUS        0   Illegal External Bus Access Flag
WDTCON           0xFFAE   Watchdog Timer Control Register      
WDTCON.WDTREL_15  15  Watchdog Timer Reload Value - bit 15
WDTCON.WDTREL_14  14  Watchdog Timer Reload Value - bit 14
WDTCON.WDTREL_13  13  Watchdog Timer Reload Value - bit 13
WDTCON.WDTREL_12  12  Watchdog Timer Reload Value - bit 12
WDTCON.WDTREL_11  11  Watchdog Timer Reload Value - bit 11
WDTCON.WDTREL_10  10  Watchdog Timer Reload Value - bit 10
WDTCON.WDTREL_9   9   Watchdog Timer Reload Value - bit 9 
WDTCON.WDTREL_8   8   Watchdog Timer Reload Value - bit 8 
WDTCON.WDTPRE     7   Watchdog Timer Input Prescaler Control
WDTCON.LHWR       4   Long Hardware Reset Indication Flag
WDTCON.SHWR       3   Short Hardware Reset Indication Flag
WDTCON.SWR        2   Software Reset Indication Flag
WDTCON.WDTR       1   Watchdog Timer Reset Indication Flag
WDTCON.WDTIN      0   Watchdog Timer Input Frequency Select
S0CON            0xFFB0   Serial Channel 0 Control Register    
S0CON.S0R         15  Baudrate Generator Run Bit
S0CON.S0LB        14  LoopBack Mode Enable Bit
S0CON.S0BRS       13  Baudrate Selection Bit
S0CON.S0ODD       12  Parity Selection Bit
S0CON.S0OE        10  Overrun Error Flag
S0CON.S0FE        9   Framing Error Flag
S0CON.S0PE        8   Parity Error Flag
S0CON.S0OEN       7   Overrun Check Enable Bit
S0CON.S0FEN       6   Framing Check Enable Bit
S0CON.S0PEN       5   Parity Check Enable Bit
S0CON.S0REN       4   Receiver Enable Bit
S0CON.S0STP       3   Number of Stop Bits Selection
S0CON.S0M_2       2   ASC0 Mode Control - bit 2
S0CON.S0M_1       1   ASC0 Mode Control - bit 1
S0CON.S0M_0       0   ASC0 Mode Control - bit 0
SSCCON           0xFFB2   SSC Control Register                 
P2               0xFFC0   Port 2 Register
P2.P2_15          15  Port data register P2 bit 15
P2.P2_14          14  Port data register P2 bit 14
P2.P2_13          13  Port data register P2 bit 13
P2.P2_12          12  Port data register P2 bit 12
P2.P2_11          11  Port data register P2 bit 11
P2.P2_10          10  Port data register P2 bit 10
P2.P2_9           9   Port data register P2 bit 9 
P2.P2_8           8   Port data register P2 bit 8 
DP2              0xFFC2   Port 2 Direction Control Register
DP2.DP2_15        15  Port direction register DP2 bit 15
DP2.DP2_14        14  Port direction register DP2 bit 14
DP2.DP2_13        13  Port direction register DP2 bit 13
DP2.DP2_12        12  Port direction register DP2 bit 12
DP2.DP2_11        11  Port direction register DP2 bit 11
DP2.DP2_10        10  Port direction register DP2 bit 10
DP2.DP2_9         9   Port direction register DP2 bit 9 
DP2.DP2_8         8   Port direction register DP2 bit 8 
P3               0xFFC4   Port 3 Register
P3.P3_15          15  Port data register P3 bit 15
P3.P3_13          13  Port data register P3 bit 13
P3.P3_12          12  Port data register P3 bit 12
P3.P3_11          11  Port data register P3 bit 11
P3.P3_10          10  Port data register P3 bit 10
P3.P3_9           9   Port data register P3 bit 9 
P3.P3_8           8   Port data register P3 bit 8 
P3.P3_7           7   Port data register P3 bit 7 
P3.P3_6           6   Port data register P3 bit 6 
P3.P3_5           5   Port data register P3 bit 5 
P3.P3_4           4   Port data register P3 bit 4 
P3.P3_3           3   Port data register P3 bit 3 
P3.P3_2           2   Port data register P3 bit 2 
P3.P3_1           1   Port data register P3 bit 1 
P3.P3_0           0   Port data register P3 bit 0 
DP3              0xFFC6   Port 3 Direction Control Register
DP3.DP3_15        15  Port direction register DP3 bit 15
DP3.DP3_13        13  Port direction register DP3 bit 13
DP3.DP3_12        12  Port direction register DP3 bit 12
DP3.DP3_11        11  Port direction register DP3 bit 11
DP3.DP3_10        10  Port direction register DP3 bit 10
DP3.DP3_9         9   Port direction register DP3 bit 9 
DP3.DP3_8         8   Port direction register DP3 bit 8 
DP3.DP3_7         7   Port direction register DP3 bit 7 
DP3.DP3_6         6   Port direction register DP3 bit 6 
DP3.DP3_5         5   Port direction register DP3 bit 5 
DP3.DP3_4         4   Port direction register DP3 bit 4 
DP3.DP3_3         3   Port direction register DP3 bit 3 
DP3.DP3_2         2   Port direction register DP3 bit 2 
DP3.DP3_1         1   Port direction register DP3 bit 1 
DP3.DP3_0         0   Port direction register DP3 bit 0 
P4               0xFFC8   Port 4 Register (7 bits)
P4.P4_7           7   Port data register P4 bit 7 
P4.P4_6           6   Port data register P4 bit 6 
P4.P4_5           5   Port data register P4 bit 5 
P4.P4_4           4   Port data register P4 bit 4 
P4.P4_3           3   Port data register P4 bit 3 
P4.P4_2           2   Port data register P4 bit 2 
P4.P4_1           1   Port data register P4 bit 1 
P4.P4_0           0   Port data register P4 bit 0 
DP4              0xFFCA   Port 4 Direction Control Register
DP4.DP4_7         7   Port direction register DP4 bit 7 
DP4.DP4_6         6   Port direction register DP4 bit 6 
DP4.DP4_5         5   Port direction register DP4 bit 5 
DP4.DP4_4         4   Port direction register DP4 bit 4 
DP4.DP4_3         3   Port direction register DP4 bit 3 
DP4.DP4_2         2   Port direction register DP4 bit 2 
DP4.DP4_1         1   Port direction register DP4 bit 1 
DP4.DP4_0         0   Port direction register DP4 bit 0 
P6               0xFFCC   Port 6 Register (8 bits)
P6.P6_7           7   Port data register P6 bit 7 
P6.P6_6           6   Port data register P6 bit 6 
P6.P6_5           5   Port data register P6 bit 5 
P6.P6_4           4   Port data register P6 bit 4 
P6.P6_3           3   Port data register P6 bit 3 
P6.P6_2           2   Port data register P6 bit 2 
P6.P6_1           1   Port data register P6 bit 1 
P6.P6_0           0   Port data register P6 bit 0 
DP6              0xFFCE   Port 6 Direction Control Register
DP6.DP6_7         7   Port direction register DP6 bit 7 
DP6.DP6_6         6   Port direction register DP6 bit 6 
DP6.DP6_5         5   Port direction register DP6 bit 5 
DP6.DP6_4         4   Port direction register DP6 bit 4 
DP6.DP6_3         3   Port direction register DP6 bit 3 
DP6.DP6_2         2   Port direction register DP6 bit 2 
DP6.DP6_1         1   Port direction register DP6 bit 1 
DP6.DP6_0         0   Port direction register DP6 bit 0 
P7               0xFFD0   Port 7 Register (8 bits)
P7.P7_7           7   Port data register P7 bit 7 
P7.P7_6           6   Port data register P7 bit 6 
P7.P7_5           5   Port data register P7 bit 5 
P7.P7_4           4   Port data register P7 bit 4 
DP7              0xFFD2   Port 7 Direction Control Register
DP7.DP7_7         7   Port direction register DP7 bit 7 
DP7.DP7_6         6   Port direction register DP7 bit 6 
DP7.DP7_5         5   Port direction register DP7 bit 5 
DP7.DP7_4         4   Port direction register DP7 bit 4 
P9               0xFFD8   Port 9 Register (8 bits)
P9.P9_5           5   Port data register P9 bit 5 
P9.P9_4           4   Port data register P9 bit 4 
P9.P9_3           3   Port data register P9 bit 3 
P9.P9_2           2   Port data register P9 bit 2 
P9.P9_1           1   Port data register P9 bit 1 
P9.P9_0           0   Port data register P9 bit 0 
DP9              0xFFDA   Port 9 Direction Control Register
DP9.DP9_5         5   Port direction register DP9 bit 5 
DP9.DP9_4         4   Port direction register DP9 bit 4 
DP9.DP9_3         3   Port direction register DP9 bit 3 
DP9.DP9_2         2   Port direction register DP9 bit 2 
DP9.DP9_1         1   Port direction register DP9 bit 1 
DP9.DP9_0         0   Port direction register DP9 bit 0 


.C161O
; Register Declarations for C161V/K/O and C161SI/CI/RI Processor
; m161.pdf

; C161CS-32RF    (ROM 265 KB, RAM 10 KB)
; C161K-LM       (RAM 1 KB)
; C161O-LM       (RAM 2 KB)
; C161O-LM 3V    (RAM 2 KB)
; C161PI-LM      (RAM 3 KB)
; C161PI-LF      (RAM 3 KB)
; C161PI-LM 3V   (RAM 3 KB)
; C161PI-LF 3V   (RAM 3 KB)


; MEMORY MAP
area CODE ROM            0x0000:0x8000   Internal ROM Area
area CODE MEM_EXT        0x8000:0xF000   External Memory
area DATA E_SFR          0xF000:0xF200   ESFR Area
area BSS  RESERVED       0xF200:0xF600   
area CODE RAM            0xF600:0xFE00   External RAM
area DATA SFR            0xFE00:0x10000  SFR Area


; Interrupt and reset vector assignments
entry RESET     0x0000   RESET
entry NMITRAP   0x0008   NMITRAP Non-Maskable Interrupt (Class A Hardware Traps)
entry STOTRAP   0x0010   STOTRAP Stack Overflow (Class A Hardware Traps)
entry STUTRAP   0x0018   STUTRAP Stack Underflow (Class A Hardware Traps)
entry BTRAP     0x0028   BTRAP Class B Hardware Traps
entry CC9INT    0x0064   External Interrupt 1
entry CC10INT   0x0068   External Interrupt 2
entry CC11INT   0x006C   External Interrupt 3
entry CC12INT   0x0070   External Interrupt 4
entry CC13INT   0x0074   External Interrupt 5
entry CC14INT   0x0078   External Interrupt 6
entry CC15INT   0x007C   External Interrupt 7
entry T2INT     0x0088   GPT1 Timer 2 
entry T3INT     0x008C   GPT1 Timer 3 
entry T4INT     0x0090   GPT1 Timer 4 
entry T5INT     0x0094   GPT2 Timer 5 
entry T6INT     0x0098   GPT2 Timer 6 
entry CRINT     0x009C   GPT2 CAPREL Reg
entry S0TINT    0x00A8   ASC0 Transmit 
entry S0RINT    0x00AC   ASC0 Receive 
entry S0EINT    0x00B0   ASC0 Error 
entry SCTINT    0x00B4   SSC Transmit 
entry SCRINT    0x00B8   SSC Receive 
entry SCEINT    0x00BC   SSC Error 
entry S0TBINT   0x011C   ASC0 Transmit Buffer 


; INPUT/OUTPUT PORTS
SSCTB            0xF0B0 SSC Transmit Buffer
SSCRB            0xF0B2 SSC Receive Buffer
SSCBR            0xF0B4 SSC Baudrate Register
DP0L             0xF100 P0L Direction Control Register
DP0L.DP0L_7       7   Port direction register DP0L bit 7
DP0L.DP0L_6       6   Port direction register DP0L bit 6
DP0L.DP0L_5       5   Port direction register DP0L bit 5
DP0L.DP0L_4       4   Port direction register DP0L bit 4
DP0L.DP0L_3       3   Port direction register DP0L bit 3
DP0L.DP0L_2       2   Port direction register DP0L bit 2
DP0L.DP0L_1       1   Port direction register DP0L bit 1
DP0L.DP0L_0       0   Port direction register DP0L bit 0
DP0H             0xF102 P0H Direction Control Register
DP0H.DP0H_7       7   Port direction register DP0H bit 7
DP0H.DP0H_6       6   Port direction register DP0H bit 6
DP0H.DP0H_5       5   Port direction register DP0H bit 5
DP0H.DP0H_4       4   Port direction register DP0H bit 4
DP0H.DP0H_3       3   Port direction register DP0H bit 3
DP0H.DP0H_2       2   Port direction register DP0H bit 2
DP0H.DP0H_1       1   Port direction register DP0H bit 1
DP0H.DP0H_0       0   Port direction register DP0H bit 0
DP1L             0xF104 P1L Direction Control Register
DP1L.DP1L_7       7   Port direction register DP1L bit 7
DP1L.DP1L_6       6   Port direction register DP1L bit 6
DP1L.DP1L_5       5   Port direction register DP1L bit 5
DP1L.DP1L_4       4   Port direction register DP1L bit 4
DP1L.DP1L_3       3   Port direction register DP1L bit 3
DP1L.DP1L_2       2   Port direction register DP1L bit 2
DP1L.DP1L_1       1   Port direction register DP1L bit 1
DP1L.DP1L_0       0   Port direction register DP1L bit 0
DP1H             0xF106 P1H Direction Control Register
DP1H.DP1H_7       7   Port direction register DP1H bit 7
DP1H.DP1H_6       6   Port direction register DP1H bit 6
DP1H.DP1H_5       5   Port direction register DP1H bit 5
DP1H.DP1H_4       4   Port direction register DP1H bit 4
DP1H.DP1H_3       3   Port direction register DP1H bit 3
DP1H.DP1H_2       2   Port direction register DP1H bit 2
DP1H.DP1H_1       1   Port direction register DP1H bit 1
DP1H.DP1H_0       0   Port direction register DP1H bit 0
RP0H             0xF108 System Startup Configuration Register (read only)
RP0H.CLKCFG7      7   Clock Generation Mode Configuration bit 7
RP0H.CLKCFG6      6   Clock Generation Mode Configuration bit 6
RP0H.CLKCFG5      5   Clock Generation Mode Configuration bit 5
RP0H.SALSEL4      4   Segment Address Line Selection bit 4
RP0H.SALSEL3      3   Segment Address Line Selection bit 3
RP0H.CSSEL2       2   Chip Select Line Selection bit 2
RP0H.CSSEL1       1   Chip Select Line Selection bit 1
RP0H.WRC          0   Write Configuration
S0TBIC           0xF19C Serial Channel 0 Transmit Buffer Interrupt Control Register
S0TBIC.S0TBIR     7
S0TBIC.S0TBIE     6
S0TBIC.ILVL5      5
S0TBIC.ILVL4      4
S0TBIC.ILVL3      3
S0TBIC.ILVL2      2
S0TBIC.GLVL1      1
S0TBIC.GLVL0      0
EXICON           0xF1C0 External Interrupt Control Register
EXICON.EXI7ES15   15  External Interrupt 7 Edge Selection bit 15
EXICON.EXI7ES14   14  External Interrupt 7 Edge Selection bit 14
EXICON.EXI6ES13   13  External Interrupt 6 Edge Selection bit 13
EXICON.EXI6ES12   12  External Interrupt 6 Edge Selection bit 12
EXICON.EXI5ES11   11  External Interrupt 5 Edge Selection bit 11
EXICON.EXI5ES10   10  External Interrupt 5 Edge Selection bit 10
EXICON.EXI4ES9    9   External Interrupt 4 Edge Selection bit 9 
EXICON.EXI4ES8    8   External Interrupt 4 Edge Selection bit 8 
EXICON.EXI3ES7    7   External Interrupt 3 Edge Selection bit 7 
EXICON.EXI3ES6    6   External Interrupt 3 Edge Selection bit 6 
EXICON.EXI2ES5    5   External Interrupt 2 Edge Selection bit 5 
EXICON.EXI2ES4    4   External Interrupt 2 Edge Selection bit 4 
EXICON.EXI1ES3    3   External Interrupt 1 Edge Selection bit 3 
EXICON.EXI1ES2    2   External Interrupt 1 Edge Selection bit 2 
ODP2             0xF1C2 Port 2 Open Drain Control Register
ODP2.ODP2_15      15  Port 2 Open Drain control register bit 15
ODP2.ODP2_14      14  Port 2 Open Drain control register bit 14
ODP2.ODP2_13      13  Port 2 Open Drain control register bit 13
ODP2.ODP2_12      12  Port 2 Open Drain control register bit 12
ODP2.ODP2_11      11  Port 2 Open Drain control register bit 11
ODP2.ODP2_10      10  Port 2 Open Drain control register bit 10
ODP2.ODP2_9       9   Port 2 Open Drain control register bit 9 
ODP3             0xF1C6 Port 3 Open Drain Control Register
ODP3.ODP3_13      13  Port 3 Open Drain control register bit 13
ODP3.ODP3_11      11  Port 3 Open Drain control register bit 11
ODP3.ODP3_10      10  Port 3 Open Drain control register bit 10
ODP3.ODP3_9       9   Port 3 Open Drain control register bit 9 
ODP3.ODP3_8       8   Port 3 Open Drain control register bit 8 
ODP3.ODP3_7       7   Port 3 Open Drain control register bit 7 
ODP3.ODP3_6       6   Port 3 Open Drain control register bit 6 
ODP3.ODP3_5       5   Port 3 Open Drain control register bit 5 
ODP3.ODP3_4       4   Port 3 Open Drain control register bit 4 
ODP3.ODP3_3       3   Port 3 Open Drain control register bit 3 
ODP3.ODP3_2       2   Port 3 Open Drain control register bit 2 
ODP6             0xF1CE Port 6 Open Drain Control Register
ODP6.ODP6_3       3   Port 6 Open Drain control register bit 3
ODP6.ODP6_2       2   Port 6 Open Drain control register bit 2
ODP6.ODP6_1       1   Port 6 Open Drain control register bit 1
ODP6.ODP6_0       0   Port 6 Open Drain control register bit 0
DPP0             0xFE00 CPU Data Page Pointer 0 Register (10 bits)
DPP0.DPP0PN9      9   Data Page Number of DPP9
DPP0.DPP0PN8      8   Data Page Number of DPP8
DPP0.DPP0PN7      7   Data Page Number of DPP7
DPP0.DPP0PN6      6   Data Page Number of DPP6
DPP0.DPP0PN5      5   Data Page Number of DPP5
DPP0.DPP0PN4      4   Data Page Number of DPP4
DPP0.DPP0PN3      3   Data Page Number of DPP3
DPP0.DPP0PN2      2   Data Page Number of DPP2
DPP0.DPP0PN1      1   Data Page Number of DPP1
DPP0.DPP0PN0      0   Data Page Number of DPP0
DPP1             0xFE02 CPU Data Page Pointer 1 Register (10 bits)
DPP1.DPP1PN9      9   Data Page Number of DPP9
DPP1.DPP1PN8      8   Data Page Number of DPP8
DPP1.DPP1PN7      7   Data Page Number of DPP7
DPP1.DPP1PN6      6   Data Page Number of DPP6
DPP1.DPP1PN5      5   Data Page Number of DPP5
DPP1.DPP1PN4      4   Data Page Number of DPP4
DPP1.DPP1PN3      3   Data Page Number of DPP3
DPP1.DPP1PN2      2   Data Page Number of DPP2
DPP1.DPP1PN1      1   Data Page Number of DPP1
DPP1.DPP1PN0      0   Data Page Number of DPP0
DPP2             0xFE04 CPU Data Page Pointer 2 Register (10 bits)
DPP2.DPP2PN9      9   Data Page Number of DPP9
DPP2.DPP2PN8      8   Data Page Number of DPP8
DPP2.DPP2PN7      7   Data Page Number of DPP7
DPP2.DPP2PN6      6   Data Page Number of DPP6
DPP2.DPP2PN5      5   Data Page Number of DPP5
DPP2.DPP2PN4      4   Data Page Number of DPP4
DPP2.DPP2PN3      3   Data Page Number of DPP3
DPP2.DPP2PN2      2   Data Page Number of DPP2
DPP2.DPP2PN1      1   Data Page Number of DPP1
DPP2.DPP2PN0      0   Data Page Number of DPP0
DPP3             0xFE06 CPU Data Page Pointer 3 Register (10 bits)
DPP3.DPP3PN9      9   Data Page Number of DPP9
DPP3.DPP3PN8      8   Data Page Number of DPP8
DPP3.DPP3PN7      7   Data Page Number of DPP7
DPP3.DPP3PN6      6   Data Page Number of DPP6
DPP3.DPP3PN5      5   Data Page Number of DPP5
DPP3.DPP3PN4      4   Data Page Number of DPP4
DPP3.DPP3PN3      3   Data Page Number of DPP3
DPP3.DPP3PN2      2   Data Page Number of DPP2
DPP3.DPP3PN1      1   Data Page Number of DPP1
DPP3.DPP3PN0      0   Data Page Number of DPP0
CSP              0xFE08 CPU Code Segment Pointer Register (8 bits, not directly writeable)
CSP.SEGNR7        7   Segment Number 7
CSP.SEGNR6        6   Segment Number 6
CSP.SEGNR5        5   Segment Number 5
CSP.SEGNR4        4   Segment Number 4
CSP.SEGNR3        3   Segment Number 3
CSP.SEGNR2        2   Segment Number 2
CSP.SEGNR1        1   Segment Number 1
CSP.SEGNR0        0   Segment Number 0
MDH              0xFE0C CPU Multiply Divide Register - High Word
MDH.MDH15         15
MDH.MDH14         14
MDH.MDH13         13
MDH.MDH12         12
MDH.MDH11         11
MDH.MDH10         10
MDH.MDH9          9
MDH.MDH8          8
MDH.MDH7          7
MDH.MDH6          6
MDH.MDH5          5
MDH.MDH4          4
MDH.MDH3          3
MDH.MDH2          2
MDH.MDH1          1
MDH.MDH0          0
MDL              0xFE0E CPU Multiply Divide Register - Low Word
MDL.MDL15         15
MDL.MDL14         14
MDL.MDL13         13
MDL.MDL12         12
MDL.MDL11         11
MDL.MDL10         10
MDL.MDL9          9
MDL.MDL8          8
MDL.MDL7          7
MDL.MDL6          6
MDL.MDL5          5
MDL.MDL4          4
MDL.MDL3          3
MDL.MDL2          2
MDL.MDL1          1
MDL.MDL0          0
CP               0xFE10 CPU Context Pointer Register
CP.CP11           11  Modifiable portion of register CP bit 11
CP.CP10           10  Modifiable portion of register CP bit 10
CP.CP9            9   Modifiable portion of register CP bit 9 
CP.CP8            8   Modifiable portion of register CP bit 8 
CP.CP7            7   Modifiable portion of register CP bit 7 
CP.CP6            6   Modifiable portion of register CP bit 6 
CP.CP5            5   Modifiable portion of register CP bit 5 
CP.CP4            4   Modifiable portion of register CP bit 4 
CP.CP3            3   Modifiable portion of register CP bit 3 
CP.CP2            2   Modifiable portion of register CP bit 2 
CP.CP1            1   Modifiable portion of register CP bit 1 
SP               0xFE12 CPU System Stack Pointer Register
SP.SP11           11  Modifiable portion of register SP 11
SP.SP10           10  Modifiable portion of register SP 10
SP.SP9            9   Modifiable portion of register SP 9 
SP.SP8            8   Modifiable portion of register SP 8 
SP.SP7            7   Modifiable portion of register SP 7 
SP.SP6            6   Modifiable portion of register SP 6 
SP.SP5            5   Modifiable portion of register SP 5 
SP.SP4            4   Modifiable portion of register SP 4 
SP.SP3            3   Modifiable portion of register SP 3 
SP.SP2            2   Modifiable portion of register SP 2 
SP.SP1            1   Modifiable portion of register SP 1 
STKOV            0xFE14 CPU Stack Overflow Pointer Register
STKOV.STKOV11     11  Modifiable portion of register STKOV bit 11
STKOV.STKOV10     10  Modifiable portion of register STKOV bit 10
STKOV.STKOV9      9   Modifiable portion of register STKOV bit 9 
STKOV.STKOV8      8   Modifiable portion of register STKOV bit 8 
STKOV.STKOV7      7   Modifiable portion of register STKOV bit 7 
STKOV.STKOV6      6   Modifiable portion of register STKOV bit 6 
STKOV.STKOV5      5   Modifiable portion of register STKOV bit 5 
STKOV.STKOV4      4   Modifiable portion of register STKOV bit 4 
STKOV.STKOV3      3   Modifiable portion of register STKOV bit 3 
STKOV.STKOV2      2   Modifiable portion of register STKOV bit 2 
STKOV.STKOV1      1   Modifiable portion of register STKOV bit 1 
STKUN            0xFE16 CPU Stack Underflow Pointer Register
STKUN.STKUN11     11  Modifiable portion of register STKUN bit 11
STKUN.STKUN10     10  Modifiable portion of register STKUN bit 10
STKUN.STKUN9      9   Modifiable portion of register STKUN bit 9 
STKUN.STKUN8      8   Modifiable portion of register STKUN bit 8 
STKUN.STKUN7      7   Modifiable portion of register STKUN bit 7 
STKUN.STKUN6      6   Modifiable portion of register STKUN bit 6 
STKUN.STKUN5      5   Modifiable portion of register STKUN bit 5 
STKUN.STKUN4      4   Modifiable portion of register STKUN bit 4 
STKUN.STKUN3      3   Modifiable portion of register STKUN bit 3 
STKUN.STKUN2      2   Modifiable portion of register STKUN bit 2 
STKUN.STKUN1      1   Modifiable portion of register STKUN bit 1 
ADDRSEL1         0xFE18 Address Select Register 1
ADDRSEL1.RGSAD15  15  Range Start Address bit 15
ADDRSEL1.RGSAD14  14  Range Start Address bit 14
ADDRSEL1.RGSAD13  13  Range Start Address bit 13
ADDRSEL1.RGSAD12  12  Range Start Address bit 12
ADDRSEL1.RGSAD11  11  Range Start Address bit 11
ADDRSEL1.RGSAD10  10  Range Start Address bit 10
ADDRSEL1.RGSAD9   9   Range Start Address bit 9 
ADDRSEL1.RGSAD8   8   Range Start Address bit 8 
ADDRSEL1.RGSAD7   7   Range Start Address bit 7 
ADDRSEL1.RGSAD6   6   Range Start Address bit 6 
ADDRSEL1.RGSAD5   5   Range Start Address bit 5 
ADDRSEL1.RGSAD4   4   Range Start Address bit 4 
ADDRSEL1.RGSZ3    3   Range Size Selection bit 3
ADDRSEL1.RGSZ2    2   Range Size Selection bit 2
ADDRSEL1.RGSZ1    1   Range Size Selection bit 1
ADDRSEL1.RGSZ0    0   Range Size Selection bit 0
ADDRSEL2         0xFE1A Address Select Register 2
ADDRSEL2.RGSAD15  15  Range Start Address bit 15
ADDRSEL2.RGSAD14  14  Range Start Address bit 14
ADDRSEL2.RGSAD13  13  Range Start Address bit 13
ADDRSEL2.RGSAD12  12  Range Start Address bit 12
ADDRSEL2.RGSAD11  11  Range Start Address bit 11
ADDRSEL2.RGSAD10  10  Range Start Address bit 10
ADDRSEL2.RGSAD9   9   Range Start Address bit 9 
ADDRSEL2.RGSAD8   8   Range Start Address bit 8 
ADDRSEL2.RGSAD7   7   Range Start Address bit 7 
ADDRSEL2.RGSAD6   6   Range Start Address bit 6 
ADDRSEL2.RGSAD5   5   Range Start Address bit 5 
ADDRSEL2.RGSAD4   4   Range Start Address bit 4 
ADDRSEL2.RGSZ3    3   Range Size Selection bit 3
ADDRSEL2.RGSZ2    2   Range Size Selection bit 2
ADDRSEL2.RGSZ1    1   Range Size Selection bit 1
ADDRSEL2.RGSZ0    0   Range Size Selection bit 0
ADDRSEL3         0xFE1C Address Select Register 3
ADDRSEL3.RGSAD15  15  Range Start Address bit 15
ADDRSEL3.RGSAD14  14  Range Start Address bit 14
ADDRSEL3.RGSAD13  13  Range Start Address bit 13
ADDRSEL3.RGSAD12  12  Range Start Address bit 12
ADDRSEL3.RGSAD11  11  Range Start Address bit 11
ADDRSEL3.RGSAD10  10  Range Start Address bit 10
ADDRSEL3.RGSAD9   9   Range Start Address bit 9 
ADDRSEL3.RGSAD8   8   Range Start Address bit 8 
ADDRSEL3.RGSAD7   7   Range Start Address bit 7 
ADDRSEL3.RGSAD6   6   Range Start Address bit 6 
ADDRSEL3.RGSAD5   5   Range Start Address bit 5 
ADDRSEL3.RGSAD4   4   Range Start Address bit 4 
ADDRSEL3.RGSZ3    3   Range Size Selection bit 3
ADDRSEL3.RGSZ2    2   Range Size Selection bit 2
ADDRSEL3.RGSZ1    1   Range Size Selection bit 1
ADDRSEL3.RGSZ0    0   Range Size Selection bit 0
ADDRSEL4         0xFE1E Address Select Register 4
ADDRSEL4.RGSAD15  15  Range Start Address bit 15
ADDRSEL4.RGSAD14  14  Range Start Address bit 14
ADDRSEL4.RGSAD13  13  Range Start Address bit 13
ADDRSEL4.RGSAD12  12  Range Start Address bit 12
ADDRSEL4.RGSAD11  11  Range Start Address bit 11
ADDRSEL4.RGSAD10  10  Range Start Address bit 10
ADDRSEL4.RGSAD9   9   Range Start Address bit 9 
ADDRSEL4.RGSAD8   8   Range Start Address bit 8 
ADDRSEL4.RGSAD7   7   Range Start Address bit 7 
ADDRSEL4.RGSAD6   6   Range Start Address bit 6 
ADDRSEL4.RGSAD5   5   Range Start Address bit 5 
ADDRSEL4.RGSAD4   4   Range Start Address bit 4 
ADDRSEL4.RGSZ3    3   Range Size Selection bit 3
ADDRSEL4.RGSZ2    2   Range Size Selection bit 2
ADDRSEL4.RGSZ1    1   Range Size Selection bit 1
ADDRSEL4.RGSZ0    0   Range Size Selection bit 0
T2               0xFE40 GPT1 Timer 2 Register
T3               0xFE42 GPT1 Timer 3 Register
T4               0xFE44 GPT1 Timer 4 Register
T5               0xFE46 GPT2 Timer 5 Register
T6               0xFE48 GPT2 Timer 6 Register
CAPREL           0xFE4A GPT2 Capture/Reload Register
WDT              0xFEAE Watchdog Timer Register (read only)
S0TBUF           0xFEB0 Serial Channel 0 Transmit Buffer Register
S0RBUF           0xFEB2 Serial Channel 0 Receive Buffer Register (read only)
S0BG             0xFEB4 Serial Channel 0 Baud Rate Generator Reload Register
PECC0            0xFEC0 PEC Channel 0 Control Register
PECC0.INC10       10  Increment Control bit 10
PECC0.INC9        9   Increment Control bit 9  
PECC0.BWT         8   Byte / Word Transfer Selection
PECC0.COUNT7      7   PEC Transfer Count bit 7
PECC0.COUNT6      6   PEC Transfer Count bit 6
PECC0.COUNT5      5   PEC Transfer Count bit 5
PECC0.COUNT4      4   PEC Transfer Count bit 4
PECC0.COUNT3      3   PEC Transfer Count bit 3
PECC0.COUNT2      2   PEC Transfer Count bit 2
PECC0.COUNT1      1   PEC Transfer Count bit 1
PECC0.COUNT0      0   PEC Transfer Count bit 0
PECC1            0xFEC2 PEC Channel 1 Control Register
PECC1.INC10       10  Increment Control bit 10
PECC1.INC9        9   Increment Control bit 9   
PECC1.BWT         8   Byte / Word Transfer Selection
PECC1.COUNT7      7   PEC Transfer Count bit 7
PECC1.COUNT6      6   PEC Transfer Count bit 6
PECC1.COUNT5      5   PEC Transfer Count bit 5
PECC1.COUNT4      4   PEC Transfer Count bit 4
PECC1.COUNT3      3   PEC Transfer Count bit 3
PECC1.COUNT2      2   PEC Transfer Count bit 2
PECC1.COUNT1      1   PEC Transfer Count bit 1
PECC1.COUNT0      0   PEC Transfer Count bit 0
PECC2            0xFEC4 PEC Channel 2 Control Register
PECC2.INC10       10  Increment Control bit 10
PECC2.INC9        9   Increment Control bit 9  
PECC2.BWT         8   Byte / Word Transfer Selection
PECC2.COUNT7      7   PEC Transfer Count bit 7
PECC2.COUNT6      6   PEC Transfer Count bit 6
PECC2.COUNT5      5   PEC Transfer Count bit 5
PECC2.COUNT4      4   PEC Transfer Count bit 4
PECC2.COUNT3      3   PEC Transfer Count bit 3
PECC2.COUNT2      2   PEC Transfer Count bit 2
PECC2.COUNT1      1   PEC Transfer Count bit 1
PECC2.COUNT0      0   PEC Transfer Count bit 0
PECC3            0xFEC6 PEC Channel 3 Control Register
PECC3.INC10       10  Increment Control bit 10
PECC3.INC9        9   Increment Control bit 9  
PECC3.BWT         8   Byte / Word Transfer Selection
PECC3.COUNT7      7   PEC Transfer Count bit 7
PECC3.COUNT6      6   PEC Transfer Count bit 6
PECC3.COUNT5      5   PEC Transfer Count bit 5
PECC3.COUNT4      4   PEC Transfer Count bit 4
PECC3.COUNT3      3   PEC Transfer Count bit 3
PECC3.COUNT2      2   PEC Transfer Count bit 2
PECC3.COUNT1      1   PEC Transfer Count bit 1
PECC3.COUNT0      0   PEC Transfer Count bit 0
PECC4            0xFEC8 PEC Channel 4 Control Register
PECC4.INC10       10  Increment Control bit 10
PECC4.INC9        9   Increment Control bit 9  
PECC4.BWT         8   Byte / Word Transfer Selection
PECC4.COUNT7      7   PEC Transfer Count bit 7
PECC4.COUNT6      6   PEC Transfer Count bit 6
PECC4.COUNT5      5   PEC Transfer Count bit 5
PECC4.COUNT4      4   PEC Transfer Count bit 4
PECC4.COUNT3      3   PEC Transfer Count bit 3
PECC4.COUNT2      2   PEC Transfer Count bit 2
PECC4.COUNT1      1   PEC Transfer Count bit 1
PECC4.COUNT0      0   PEC Transfer Count bit 0
PECC5            0xFECA PEC Channel 5 Control Register
PECC5.INC10       10  Increment Control bit 10
PECC5.INC9        9   Increment Control bit 9  
PECC5.BWT         8   Byte / Word Transfer Selection
PECC5.COUNT7      7   PEC Transfer Count bit 7
PECC5.COUNT6      6   PEC Transfer Count bit 6
PECC5.COUNT5      5   PEC Transfer Count bit 5
PECC5.COUNT4      4   PEC Transfer Count bit 4
PECC5.COUNT3      3   PEC Transfer Count bit 3
PECC5.COUNT2      2   PEC Transfer Count bit 2
PECC5.COUNT1      1   PEC Transfer Count bit 1
PECC5.COUNT0      0   PEC Transfer Count bit 0
PECC6            0xFECC PEC Channel 6 Control Register
PECC6.INC10       10  Increment Control bit 10
PECC6.INC9        9   Increment Control bit 9  
PECC6.BWT         8   Byte / Word Transfer Selection
PECC6.COUNT7      7   PEC Transfer Count bit 7
PECC6.COUNT6      6   PEC Transfer Count bit 6
PECC6.COUNT5      5   PEC Transfer Count bit 5
PECC6.COUNT4      4   PEC Transfer Count bit 4
PECC6.COUNT3      3   PEC Transfer Count bit 3
PECC6.COUNT2      2   PEC Transfer Count bit 2
PECC6.COUNT1      1   PEC Transfer Count bit 1
PECC6.COUNT0      0   PEC Transfer Count bit 0
PECC7            0xFECE PEC Channel 7 Control Register
PECC7.INC10       10  Increment Control bit 10
PECC7.INC9        9   Increment Control bit 9  
PECC7.BWT         8   Byte / Word Transfer Selection
PECC7.COUNT7      7   PEC Transfer Count bit 7
PECC7.COUNT6      6   PEC Transfer Count bit 6
PECC7.COUNT5      5   PEC Transfer Count bit 5
PECC7.COUNT4      4   PEC Transfer Count bit 4
PECC7.COUNT3      3   PEC Transfer Count bit 3
PECC7.COUNT2      2   PEC Transfer Count bit 2
PECC7.COUNT1      1   PEC Transfer Count bit 1
PECC7.COUNT0      0   PEC Transfer Count bit 0
P0L              0xFF00 Port 0 Low Register (Lower half of PORT0)
P0L.P0L_7         7   Port data register P0L bit 7
P0L.P0L_6         6   Port data register P0L bit 6
P0L.P0L_5         5   Port data register P0L bit 5
P0L.P0L_4         4   Port data register P0L bit 4
P0L.P0L_3         3   Port data register P0L bit 3
P0L.P0L_2         2   Port data register P0L bit 2
P0L.P0L_1         1   Port data register P0L bit 1
P0L.P0L_0         0   Port data register P0L bit 0
P0H              0xFF02 Port 0 High Register (Upper half of PORT0)
P0H.P0H_7         7   Port data register P0H bit 7
P0H.P0H_6         6   Port data register P0H bit 6
P0H.P0H_5         5   Port data register P0H bit 5
P0H.P0H_4         4   Port data register P0H bit 4
P0H.P0H_3         3   Port data register P0H bit 3
P0H.P0H_2         2   Port data register P0H bit 2
P0H.P0H_1         1   Port data register P0H bit 1
P0H.P0H_0         0   Port data register P0H bit 0
P1L              0xFF04 Port 1 Low Register (Lower half of PORT1)
P1L.P1L_7         7   Port data register P1L bit 7
P1L.P1L_6         6   Port data register P1L bit 6
P1L.P1L_5         5   Port data register P1L bit 5
P1L.P1L_4         4   Port data register P1L bit 4
P1L.P1L_3         3   Port data register P1L bit 3
P1L.P1L_2         2   Port data register P1L bit 2
P1L.P1L_1         1   Port data register P1L bit 1
P1L.P1L_0         0   Port data register P1L bit 0
P1H              0xFF06 Port 1 High Register (Upper half of PORT1)
P1H.P1H_7         7   Port data register P1H bit 7
P1H.P1H_6         6   Port data register P1H bit 6
P1H.P1H_5         5   Port data register P1H bit 5
P1H.P1H_4         4   Port data register P1H bit 4
P1H.P1H_3         3   Port data register P1H bit 3
P1H.P1H_2         2   Port data register P1H bit 2
P1H.P1H_1         1   Port data register P1H bit 1
P1H.P1H_0         0   Port data register P1H bit 0
BUSCON0          0xFF0C Bus Configuration Register 0
BUSCON0.CSWEN0    15  Write Chip Select Enable
BUSCON0.CSREN0    14  Read Chip Select Enable
BUSCON0.BUSACT0   10  Bus Active Control
BUSCON0.ALECTL0   9   ALE Lengthening Control
BUSCON0.BTYP7     7   External Bus Configuration bit 7
BUSCON0.BTYP6     6   External Bus Configuration bit 6
BUSCON0.MTTC0     5   Memory Tristate Time Control
BUSCON0.RWDC0     4   Read/Write Delay Control for BUSCON
BUSCON0.MCTC3     3   Memory Cycle Time Control bit 3
BUSCON0.MCTC2     2   Memory Cycle Time Control bit 2
BUSCON0.MCTC1     1   Memory Cycle Time Control bit 1
BUSCON0.MCTC0     0   Memory Cycle Time Control bit 0
MDC              0xFF0E CPU Multiply Divide Control Register
MDC.MDRIU         4   Multiply/Divide Register In Use
PSW              0xFF10 CPU Program Status Word
PSW.ILVL15        15  Interrupt Control Field 15
PSW.ILVL14        14  Interrupt Control Field 14
PSW.ILVL13        13  Interrupt Control Field 13
PSW.ILVL12        12  Interrupt Control Field 12
PSW.IEN           11  Interrupt Control Field
PSW.USR0          6   User General Purpose Flag
PSW.MULIP         5   Multiplication/Division In Progress
PSW.E             4   End of Table Flag
PSW.Z             3   Zero Flag
PSW.V             2   Overflow Result
PSW.C             1   Carry Flag
PSW.N             0   Negative Result
SYSCON           0xFF12 CPU System Configuration Register
SYSCON.STKSZ15    15  System Stack Size bit 15
SYSCON.STKSZ14    14  System Stack Size bit 14
SYSCON.STKSZ13    13  System Stack Size bit 13
SYSCON.ROMS1      12  Internal ROM Mapping
SYSCON.SGTDIS     11  Segmentation Disable/Enable Control
SYSCON.ROMEN      10  Internal ROM Enable
SYSCON.BYTDIS     9   Disable/Enable Control for Pin BHE
SYSCON.WRCFG      7   Write Configuration Control
SYSCON.XPEN       2   XBUS Peripheral Enable Bit
SYSCON.VISIBLE    1   Visible Mode Control
SYSCON.XPER_SHARE 0   XBUS Peripheral Share Mode Control
BUSCON1          0xFF14 Bus Configuration Register 1
BUSCON1.CSWEN1    15  Write Chip Select Enable
BUSCON1.CSREN1    14  Read Chip Select Enable
BUSCON1.BUSACT1   10  Bus Active Control
BUSCON1.ALECTL1   9   ALE Lengthening Control
BUSCON1.BTYP7     7   External Bus Configuration bit 7
BUSCON1.BTYP6     6   External Bus Configuration bit 6
BUSCON1.MTTC1     5   Memory Tristate Time Control
BUSCON1.RWDC1     4   Read/Write Delay Control for BUSCON
BUSCON1.MCTC3     3   Memory Cycle Time Control bit 3
BUSCON1.MCTC2     2   Memory Cycle Time Control bit 2
BUSCON1.MCTC1     1   Memory Cycle Time Control bit 1
BUSCON1.MCTC0     0   Memory Cycle Time Control bit 0
BUSCON2          0xFF16 Bus Configuration Register 2
BUSCON2.CSWEN2    15  Write Chip Select Enable
BUSCON2.CSREN2    14  Read Chip Select Enable
BUSCON2.BUSACT2   10  Bus Active Control
BUSCON2.ALECTL2   9   ALE Lengthening Control
BUSCON2.BTYP7     7   External Bus Configuration bit 7
BUSCON2.BTYP6     6   External Bus Configuration bit 6
BUSCON2.MTTC2     5   Memory Tristate Time Control
BUSCON2.RWDC2     4   Read/Write Delay Control for BUSCON
BUSCON2.MCTC3     3   Memory Cycle Time Control bit 3
BUSCON2.MCTC2     2   Memory Cycle Time Control bit 2
BUSCON2.MCTC1     1   Memory Cycle Time Control bit 1
BUSCON2.MCTC0     0   Memory Cycle Time Control bit 0
BUSCON3          0xFF18 Bus Configuration Register 3
BUSCON3.CSWEN3    15  Write Chip Select Enable
BUSCON3.CSREN3    14  Read Chip Select Enable
BUSCON3.BUSACT3   10  Bus Active Control
BUSCON3.ALECTL3   9   ALE Lengthening Control
BUSCON3.BTYP7     7   External Bus Configuration bit 7
BUSCON3.BTYP6     6   External Bus Configuration bit 6
BUSCON3.MTTC3     5   Memory Tristate Time Control
BUSCON3.RWDC3     4   Read/Write Delay Control for BUSCON
BUSCON3.MCTC3     3   Memory Cycle Time Control bit 3
BUSCON3.MCTC2     2   Memory Cycle Time Control bit 2
BUSCON3.MCTC1     1   Memory Cycle Time Control bit 1
BUSCON3.MCTC0     0   Memory Cycle Time Control bit 0
BUSCON4          0xFF1A Bus Configuration Register 4
BUSCON4.CSWEN4    15  Write Chip Select Enable
BUSCON4.CSREN4    14  Read Chip Select Enable
BUSCON4.BUSACT4   10  Bus Active Control
BUSCON4.ALECTL4   9   ALE Lengthening Control
BUSCON4.BTYP7     7   External Bus Configuration bit 7
BUSCON4.BTYP6     6   External Bus Configuration bit 6
BUSCON4.MTTC4     5   Memory Tristate Time Control
BUSCON4.RWDC4     4   Read/Write Delay Control for BUSCON
BUSCON4.MCTC3     3   Memory Cycle Time Control bit 3
BUSCON4.MCTC2     2   Memory Cycle Time Control bit 2
BUSCON4.MCTC1     1   Memory Cycle Time Control bit 1
BUSCON4.MCTC0     0   Memory Cycle Time Control bit 0
ZEROS            0xFF1C Constant Value 0's Register (read only)
ONES             0xFF1E Constant Value 1's Register (read only)
T2CON            0xFF40 GPT1 Timer 2 Control Register
T2CON.T2UDE       8   Timer 2 External Up/Down Enable
T2CON.T2UD        7   Timer 2 Up / Down Control
T2CON.T2R         6   Timer 2 Run Bit
T2CON.T2M5        5   Timer 2 Mode Control bit 5
T2CON.T2M4        4   Timer 2 Mode Control bit 4
T2CON.T2M3        3   Timer 2 Mode Control bit 3
T2CON.T2I2        2   Timer 2 Input Selection bit 2
T2CON.T2I1        1   Timer 2 Input Selection bit 1
T2CON.T2I0        0   Timer 2 Input Selection bit 0
T3CON            0xFF42 GPT1 Timer 3 Control Register
T3CON.T3OTL       10  Timer 3 Output Toggle Latch
T3CON.T3OE        9   Alternate Output Function Enable
T3CON.T3UDE       8   Timer 3 External Up/Down Enable
T3CON.T3UD        7   Timer 3 Up / Down Control
T3CON.T3R         6   Timer 3 Run Bit
T3CON.T3M5        5   Timer 3 Mode Control bit 5
T3CON.T3M4        4   Timer 3 Mode Control bit 4
T3CON.T3M3        3   Timer 3 Mode Control bit 3
T3CON.T3I2        2   Timer 3 Input Selection bit 2
T3CON.T3I1        1   Timer 3 Input Selection bit 1
T3CON.T3I0        0   Timer 3 Input Selection bit 0
T4CON            0xFF44 GPT1 Timer 4 Control Register
T4CON.T4UDE       8   Timer 4 External Up/Down Enable
T4CON.T4UD        7   Timer 4 Up / Down Control
T4CON.T4R         6   Timer 4 Run Bit
T4CON.T4M5        5   Timer 4 Mode Control bit 5
T4CON.T4M4        4   Timer 4 Mode Control bit 4
T4CON.T4M3        3   Timer 4 Mode Control bit 3
T4CON.T4I2        2   Timer 4 Input Selection bit 2
T4CON.T4I1        1   Timer 4 Input Selection bit 1
T4CON.T4I0        0   Timer 4 Input Selection bit 0
T5CON            0xFF46 GPT2 Timer 5 Control Register
T5CON.T5SC        15  Timer 5 Capture Mode Enable
T5CON.T5CLR       14  Timer 5 Clear Bit
T5CON.CI13        13  Register CAPREL Input Selection
T5CON.CI12        12  Register CAPREL Input Selection
T5CON.T5UD        7   Timer 5 Up / Down Control
T5CON.T5R         6   Timer 5 Run Bit
T5CON.T5M4        4   Timer 5 Mode Control bit 4
T5CON.T5M3        3   Timer 5 Mode Control bit 3
T5CON.T5I2        2   Timer 5 Input Selection bit 2
T5CON.T5I1        1   Timer 5 Input Selection bit 1
T5CON.T5I0        0   Timer 5 Input Selection bit 0
T6CON            0xFF48 GPT2 Timer 6 Control Register
T6CON.T6SR        15  Timer 6 Reload Mode Enable
T6CON.T6OTL       10  Timer 6 Output Toggle Latch
T6CON.T6UD        7   Timer 6 Up / Down Control
T6CON.T6R         6   Timer 6 Run Bit
T6CON.T6M5        5   Timer 6 Mode Control bit 5
T6CON.T6M4        4   Timer 6 Mode Control bit 4
T6CON.T6M3        3   Timer 6 Mode Control bit 3
T6CON.T6I2        2   Timer 6 Input Selection bit 2
T6CON.T6I1        1   Timer 6 Input Selection bit 1
T6CON.T6I0        0   Timer 6 Input Selection bit 0
T2IC             0xFF60 GPT1 Timer 2 Interrupt Control Register
T2IC.T2IR         7
T2IC.T2IE         6
T2IC.ILVL5        5
T2IC.ILVL4        4
T2IC.ILVL3        3
T2IC.ILVL2        2
T2IC.GLVL1        1
T2IC.GLVL0        0
T3IC             0xFF62 GPT1 Timer 3 Interrupt Control Register
T3IC.T3IR         7
T3IC.T3IE         6
T3IC.ILVL5        5
T3IC.ILVL4        4
T3IC.ILVL3        3
T3IC.ILVL2        2
T3IC.GLVL1        1
T3IC.GLVL0        0
T4IC             0xFF64 GPT1 Timer 4 Interrupt Control Register
T4IC.T4IR         7
T4IC.T4IE         6
T4IC.ILVL5        5
T4IC.ILVL4        4
T4IC.ILVL3        3
T4IC.ILVL2        2
T4IC.GLVL1        1
T4IC.GLVL0        0
T5IC             0xFF66 GPT2 Timer 5 Interrupt Control Register
T5IC.T5IR         7
T5IC.T5IE         6
T5IC.ILVL5        5
T5IC.ILVL4        4
T5IC.ILVL3        3
T5IC.ILVL2        2
T5IC.GLVL1        1
T5IC.GLVL0        0
T6IC             0xFF68 GPT2 Timer 6 Interrupt Control Register
T6IC.T6IR         7
T6IC.T6IE         6
T6IC.ILVL5        5
T6IC.ILVL4        4
T6IC.ILVL3        3
T6IC.ILVL2        2
T6IC.GLVL1        1
T6IC.GLVL0        0
CRIC             0xFF6A GPT2 CAPREL Interrupt Control Register
CRIC.CRIR         7
CRIC.CRIE         6
CRIC.ILVL5        5
CRIC.ILVL4        4
CRIC.ILVL3        3
CRIC.ILVL2        2
CRIC.GLVL1        1
CRIC.GLVL0        0
S0TIC            0xFF6C Serial Channel 0 Transmit Interrupt Control Register
S0TIC.S0TIR       7
S0TIC.S0TIE       6
S0TIC.ILVL5       5
S0TIC.ILVL4       4
S0TIC.ILVL3       3
S0TIC.ILVL2       2
S0TIC.GLVL1       1
S0TIC.GLVL0       0
S0RIC            0xFF6E Serial Channel 0 Receive Interrupt Control Register
S0RIC.S0RIR       7
S0RIC.S0RIE       6
S0RIC.ILVL5       5
S0RIC.ILVL4       4
S0RIC.ILVL3       3
S0RIC.ILVL2       2
S0RIC.GLVL1       1
S0RIC.GLVL0       0
S0EIC            0xFF70 Serial Channel 0 Error Interrupt Ctrl. Reg.
S0EIC.S0EIR       7
S0EIC.S0EIE       6
S0EIC.ILVL5       5
S0EIC.ILVL4       4
S0EIC.ILVL3       3
S0EIC.ILVL2       2
S0EIC.GLVL1       1
S0EIC.GLVL0       0
SSCTIC           0xFF72 SSC Transmit Interrupt Control Register
SSCTIC.SSCTIR     7
SSCTIC.SSCTIE     6
SSCTIC.ILVL5      5
SSCTIC.ILVL4      4
SSCTIC.ILVL3      3
SSCTIC.ILVL2      2
SSCTIC.GLVL1      1
SSCTIC.GLVL0      0
SSCRIC           0xFF74 SSC Receive Interrupt Control Register
SSCRIC.SSCRIR     7
SSCRIC.SSCRIE     6
SSCRIC.ILVL5      5
SSCRIC.ILVL4      4
SSCRIC.ILVL3      3
SSCRIC.ILVL2      2
SSCRIC.GLVL1      1
SSCRIC.GLVL0      0
SSCEIC           0xFF76 SSC Error Interrupt Control Register
SSCEIC.SSCEIR     7
SSCEIC.SSCEIE     6
SSCEIC.ILVL5      5
SSCEIC.ILVL4      4
SSCEIC.ILVL3      3
SSCEIC.ILVL2      2
SSCEIC.GLVL1      1
SSCEIC.GLVL0      0
CC9IC            0xFF8A External Interrupt 1 Control Register  
CC9IC.CC9IR       7
CC9IC.CC9IE       6
CC9IC.ILVL5       5
CC9IC.ILVL4       4
CC9IC.ILVL3       3
CC9IC.ILVL2       2
CC9IC.GLVL1       1
CC9IC.GLVL0       0
CC10IC           0xFF8C External Interrupt 2 Control Register  
CC10IC.CC10IR     7
CC10IC.CC10IE     6
CC10IC.ILVL5      5
CC10IC.ILVL4      4
CC10IC.ILVL3      3
CC10IC.ILVL2      2
CC10IC.GLVL1      1
CC10IC.GLVL0      0
CC11IC           0xFF8E External Interrupt 3 Control Register
CC11IC.CC11IR     7
CC11IC.CC11IE     6
CC11IC.ILVL5      5
CC11IC.ILVL4      4
CC11IC.ILVL3      3
CC11IC.ILVL2      2
CC11IC.GLVL1      1
CC11IC.GLVL0      0
CC12IC           0xFF90 External Interrupt 4 Control Register
CC12IC.CC12IR     7
CC12IC.CC12IE     6
CC12IC.ILVL5      5
CC12IC.ILVL4      4
CC12IC.ILVL3      3
CC12IC.ILVL2      2
CC12IC.GLVL1      1
CC12IC.GLVL0      0
CC13IC           0xFF92 External Interrupt 5 Control Register
CC13IC.CC13IR     7
CC13IC.CC13IE     6
CC13IC.ILVL5      5
CC13IC.ILVL4      4
CC13IC.ILVL3      3
CC13IC.ILVL2      2
CC13IC.GLVL1      1
CC13IC.GLVL0      0
CC14IC           0xFF94 External Interrupt 6 Control Register
CC14IC.CC14IR     7
CC14IC.CC14IE     6
CC14IC.ILVL5      5
CC14IC.ILVL4      4
CC14IC.ILVL3      3
CC14IC.ILVL2      2
CC14IC.GLVL1      1
CC14IC.GLVL0      0
CC15IC           0xFF96 External Interrupt 7 Control Register
CC15IC.CC15IR     7
CC15IC.CC15IE     6
CC15IC.ILVL5      5
CC15IC.ILVL4      4
CC15IC.ILVL3      3
CC15IC.ILVL2      2
CC15IC.GLVL1      1
CC15IC.GLVL0      0
P5               0xFFA2 Port 5 Register (read only)
P5.P5_15          15  Port data register P5 bit 15
P5.P5_14          14  Port data register P5 bit 14
TFR              0xFFAC Trap Flag Register
TFR.NMI           15  Non Maskable Interrupt Flag
TFR.STKOF         14  Stack Overflow Flag
TFR.STKUF         13  Stack Underflow Flag
TFR.UNDOPC        7   Undefined Opcode Flag
TFR.PRTFLT        3   Protection Fault Flag
TFR.ILLOPA        2   Illegal Word Operand Access Flag
TFR.ILLINA        1   Illegal Instruction Access Flag
TFR.ILLBUS        0   Illegal External Bus Access Flag
WDTCON           0xFFAE Watchdog Timer Control Register
WDTCON.WDTREL15   15  Watchdog Timer Reload Value bit 15
WDTCON.WDTREL14   14  Watchdog Timer Reload Value bit 14
WDTCON.WDTREL13   13  Watchdog Timer Reload Value bit 13
WDTCON.WDTREL12   12  Watchdog Timer Reload Value bit 12
WDTCON.WDTREL11   11  Watchdog Timer Reload Value bit 11
WDTCON.WDTREL10   10  Watchdog Timer Reload Value bit 10
WDTCON.WDTREL9    9   Watchdog Timer Reload Value bit 9 
WDTCON.WDTREL8    8   Watchdog Timer Reload Value bit 8 
WDTCON.WDTR       1   Watchdog Timer Reset Indication Flag
WDTCON.WDTIN      0   Watchdog Timer Input Frequency Selection
S0CON            0xFFB0 Serial Channel 0 Control Register
S0CON.S0R         15  Baudrate Generator Run Bit
S0CON.S0LB        14  LoopBack Mode Enable Bit
S0CON.S0BRS       13  Baudrate Selection Bit
S0CON.S0ODD       12  Parity Selection Bit
S0CON.S0OE        10  Overrun Error Flag
S0CON.S0FE        9   Framing Error Flag
S0CON.S0PE        8   Parity Error Flag
S0CON.S0OEN       7   Overrun Check Enable Bit
S0CON.S0FEN       6   Framing Check Enable Bit
S0CON.S0PEN       5   Parity Check Enable Bit
S0CON.S0REN       4   Receiver Enable Bit
S0CON.S0STP       3   Number of Stop Bits Selection
S0CON.S0M2        2   ASC0 Mode Control
S0CON.S0M1        1   ASC0 Mode Control
S0CON.S0M0        0   ASC0 Mode Control
SSCCON           0xFFB2 SSC Control Register
P2               0xFFC0 Port 2 Register
P2.P2_15          15  Port data register P2 bit 15
P2.P2_14          14  Port data register P2 bit 14
P2.P2_13          13  Port data register P2 bit 13
P2.P2_12          12  Port data register P2 bit 12
P2.P2_11          11  Port data register P2 bit 11
P2.P2_10          10  Port data register P2 bit 10
P2.P2_9           9   Port data register P2 bit 9 
DP2              0xFFC2 Port 2 Direction Control Register
DP2.DP2_15        15  Port direction register DP2 bit 15
DP2.DP2_14        14  Port direction register DP2 bit 14
DP2.DP2_13        13  Port direction register DP2 bit 13
DP2.DP2_12        12  Port direction register DP2 bit 12
DP2.DP2_11        11  Port direction register DP2 bit 11
DP2.DP2_10        10  Port direction register DP2 bit 10
DP2.DP2_9         9   Port direction register DP2 bit 9 
P3               0xFFC4 Port 3 Register
P3.P3_13          13  Port data register P3 bit 13
P3.P3_12          12  Port data register P3 bit 12
P3.P3_11          11  Port data register P3 bit 11
P3.P3_10          10  Port data register P3 bit 10
P3.P3_9           9   Port data register P3 bit 9 
P3.P3_8           8   Port data register P3 bit 8 
P3.P3_7           7   Port data register P3 bit 7 
P3.P3_6           6   Port data register P3 bit 6 
P3.P3_5           5   Port data register P3 bit 5 
P3.P3_4           4   Port data register P3 bit 4 
P3.P3_3           3   Port data register P3 bit 3 
P3.P3_2           2   Port data register P3 bit 2 
DP3              0xFFC6 Port 3 Direction Control Register
DP3.DP3_13        13  Port direction register DP3 bit 13
DP3.DP3_12        12  Port direction register DP3 bit 12
DP3.DP3_11        11  Port direction register DP3 bit 11
DP3.DP3_10        10  Port direction register DP3 bit 10
DP3.DP3_9         9   Port direction register DP3 bit 9 
DP3.DP3_8         8   Port direction register DP3 bit 8 
DP3.DP3_7         7   Port direction register DP3 bit 7 
DP3.DP3_6         6   Port direction register DP3 bit 6 
DP3.DP3_5         5   Port direction register DP3 bit 5 
DP3.DP3_4         4   Port direction register DP3 bit 4 
DP3.DP3_3         3   Port direction register DP3 bit 3 
DP3.DP3_2         2   Port direction register DP3 bit 2 
P4               0xFFC8 Port 4 Register
P4.P4_5           5   Port data register P4 bit 5
P4.P4_4           4   Port data register P4 bit 4
P4.P4_3           3   Port data register P4 bit 3
P4.P4_2           2   Port data register P4 bit 2
P4.P4_1           1   Port data register P4 bit 1
P4.P4_0           0   Port data register P4 bit 0
DP4              0xFFCA Port 4 Direction Control Register
DP4.DP4_5         5   Port direction register DP4 bit 5
DP4.DP4_4         4   Port direction register DP4 bit 4
DP4.DP4_3         3   Port direction register DP4 bit 3
DP4.DP4_2         2   Port direction register DP4 bit 2
DP4.DP4_1         1   Port direction register DP4 bit 1
DP4.DP4_0         0   Port direction register DP4 bit 0
P6               0xFFCC Port 6 Register (8 bits)
P6.P6_3           3   Port data register P6 bit 3
P6.P6_2           2   Port data register P6 bit 2
P6.P6_1           1   Port data register P6 bit 1
P6.P6_0           0   Port data register P6 bit 0
DP6              0xFFCE Port 6 Direction Control Register
DP6.DP6_3         3   Port direction register DP6 bit 3
DP6.DP6_2         2   Port direction register DP6 bit 2
DP6.DP6_1         1   Port direction register DP6 bit 1
DP6.DP6_0         0   Port direction register DP6 bit 0


.C161RI
; http://www.infineon.com/cgi/ecrm.dll/ecrm/scripts/public_download.jsp?oid=8095&parent_oid=13749


; MEMORY MAP
area DATA ROM            0x0000:0x8000   Internal ROM Area
area DATA MEM_EXT        0x8000:0xE000   External Memory
area DATA XRAM           0xE000:0xE800   XRAM
area BSS  RESERVED       0xE800:0xED00
area DATA I2C            0xED00:0xED0A   I2C
area BSS  RESERVED       0xED0A:0xF000
area DATA E_SFR          0xF000:0xF1E0   ESFR Area
area BSS  RESERVED       0xF1E0:0xFA00   
area DATA IRAM           0xFA00:0xFE00   IRAM
area DATA SFR            0xFE00:0x10000  SFR Area


; Interrupt and reset vector assignments
entry RESET     0x0000   RESET
entry NMITRAP   0x0008   NMITRAP Non-Maskable Interrupt (Class A Hardware Traps)
entry STOTRAP   0x0010   STOTRAP Stack Overflow (Class A Hardware Traps)
entry STUTRAP   0x0018   STUTRAP Stack Underflow (Class A Hardware Traps)
entry BTRAP     0x0028   BTRAP Class B Hardware Traps
entry CC8INT    0x0060   Fast External Interrupt 0
entry CC9INT    0x0064   Fast External Interrupt 1
entry CC10INT   0x0068   Fast External Interrupt 2
entry CC11INT   0x006C   Fast External Interrupt 3
entry CC12INT   0x0070   Fast External Interrupt 4
entry CC13INT   0x0074   Fast External Interrupt 5
entry CC14INT   0x0078   Fast External Interrupt 6
entry CC15INT   0x007C   Fast External Interrupt 7
entry T2INT     0x0088   GPT1 Timer 2
entry T3INT     0x008C   GPT1 Timer 3
entry T4INT     0x0090   GPT1 Timer 4
entry T5INT     0x0094   GPT2 Timer 5
entry T6INT     0x0098   GPT2 Timer 6
entry CRINT     0x009C   GPT2 CAPREL Register
entry ADCINT    0x00A0   A/D Conversion Complete
entry ADEINT    0x00A4   A/D Overrun Error
entry S0TINT    0x00A8   ASC0 Transmit
entry S0TBINT   0x011C   ASC0 Transmit Buffer
entry S0RINT    0x00AC   ASC0 Receive
entry S0EINT    0x00B0   ASC0 Error
entry SCTINT    0x00B4   SSC Transmit
entry SCRINT    0x00B8   SSC Receive
entry SCEINT    0x00BC   SSC Error
entry XP0INT    0x0100   I2C Data Transfer Event
entry XP1INT    0x0104   I2C Protocol Event
entry XP2INT    0x0108   X-Peripheral Node 2
entry XP3INT    0x010C   RTC (via ISNC)


; INPUT/OUTPUT PORTS
ICCFG            0xED00   I2C Configuration Register
ICCFG.BRP_15      15  Baudrate Prescaler  - bit 15
ICCFG.BRP_14      14  Baudrate Prescaler  - bit 14
ICCFG.BRP_13      13  Baudrate Prescaler  - bit 13
ICCFG.BRP_12      12  Baudrate Prescaler  - bit 12
ICCFG.BRP_11      11  Baudrate Prescaler  - bit 11
ICCFG.BRP_10      10  Baudrate Prescaler  - bit 10
ICCFG.BRP_9       9   Baudrate Prescaler  - bit 9 
ICCFG.BRP_8       8   Baudrate Prescaler  - bit 8 
ICCFG.SCLSEL1     5   SCL Pin Selection 1
ICCFG.SCLSEL0     4   SCL Pin Selection 0
ICCFG.SDASEL2     2   SDA Pin Selection 2
ICCFG.SDASEL1     1   SDA Pin Selection 1
ICCFG.SDASEL0     0   SDA Pin Selection 0
ICCON            0xED02   I2C Control Register
ICCON.TRX         7   Transmit Select
ICCON.AIRDIS      6   Auto Interrupt Reset Disable
ICCON.ACKDIS      5   Acknowledge Pulse Disable
ICCON.BUM         4   Busy Master
ICCON.MOD_3       3   Basic Operating Mode - bit 3 
ICCON.MOD_2       2   Basic Operating Mode - bit 2 
ICCON.RSC         1   Repeated Start Condition
ICCON.M10         0   Address Mode
ICST             0xED04   I2C Status Register
ICST.IRQP         6  IIC Interrupt Request Bit for Protocol Events
ICST.IRQD         5  IIC Interrupt Request Bit for Data Transfer Events
ICST.BB           4  Bus Busy
ICST.LRB          3  Last Received Bit
ICST.SLA          2  Slave
ICST.AL           1  Arbitration Lost
ICST.ADR          0  Address
ICADR            0xED06   I2C Address Register
ICADR.ICA9        9
ICADR.ICA8        8
ICADR.ICA7        7
ICADR.ICA6        6
ICADR.ICA5        5
ICADR.ICA4        4
ICADR.ICA3        3
ICADR.ICA2        2
ICADR.ICA1        1
ICADR.ICA0        0
ICRTB            0xED08   I2C Receive/Transmit Buffer
IDPROG           0xF078   Identifier
IDMEM            0xF07A   Identifier
IDCHIP           0xF07C   Identifier
IDMANUF          0xF07E   Identifier
SSCTB            0xF0B0   SSC Transmit Buffer (write only)
SSCRB            0xF0B2   SSC Receive Buffer (read only)
SSCBR            0xF0B4   SSC Baudrate Register
T14REL           0xF0D0   RTC Timer 14 Reload Register
T14              0xF0D2   RTC Timer 14 Register
RTCL             0xF0D4   RTC Low Register
RTCH             0xF0D6   RTC High Register
DP0L             0xF100   P0L Direction Control Register
DP0L.DP0L7        7   Port direction register DP0L bit 7
DP0L.DP0L6        6   Port direction register DP0L bit 6
DP0L.DP0L5        5   Port direction register DP0L bit 5
DP0L.DP0L4        4   Port direction register DP0L bit 4
DP0L.DP0L3        3   Port direction register DP0L bit 3
DP0L.DP0L2        2   Port direction register DP0L bit 2
DP0L.DP0L1        1   Port direction register DP0L bit 1
DP0L.DP0L0        0   Port direction register DP0L bit 0
DP0H             0xF102   P0H Direction Control Register
DP0H.DP0H7        7   Port direction register DP0H bit 7
DP0H.DP0H6        6   Port direction register DP0H bit 6
DP0H.DP0H5        5   Port direction register DP0H bit 5
DP0H.DP0H4        4   Port direction register DP0H bit 4
DP0H.DP0H3        3   Port direction register DP0H bit 3
DP0H.DP0H2        2   Port direction register DP0H bit 2
DP0H.DP0H1        1   Port direction register DP0H bit 1
DP0H.DP0H0        0   Port direction register DP0H bit 0
DP1L             0xF104   P1L Direction Control Register
DP1L.DP1L7        7   Port direction register DP1L bit 7
DP1L.DP1L6        6   Port direction register DP1L bit 6
DP1L.DP1L5        5   Port direction register DP1L bit 5
DP1L.DP1L4        4   Port direction register DP1L bit 4
DP1L.DP1L3        3   Port direction register DP1L bit 3
DP1L.DP1L2        2   Port direction register DP1L bit 2
DP1L.DP1L1        1   Port direction register DP1L bit 1
DP1L.DP1L0        0   Port direction register DP1L bit 0
DP1H             0xF106   P1H Direction Control Register
DP1H.DP1H7        7   Port direction register DP1H bit 7
DP1H.DP1H6        6   Port direction register DP1H bit 6
DP1H.DP1H5        5   Port direction register DP1H bit 5
DP1H.DP1H4        4   Port direction register DP1H bit 4
DP1H.DP1H3        3   Port direction register DP1H bit 3
DP1H.DP1H2        2   Port direction register DP1H bit 2
DP1H.DP1H1        1   Port direction register DP1H bit 1
DP1H.DP1H0        0   Port direction register DP1L bit 0
RP0H             0xF108   System Startup Configuration Register (Rd. only)
RP0H.CLKCFG_7     7   Clock Generation Mode Configuration - bit 7
RP0H.CLKCFG_6     6   Clock Generation Mode Configuration - bit 6
RP0H.CLKCFG_5     5   Clock Generation Mode Configuration - bit 5
RP0H.SALSEL_4     4   Segment Address Line Selection - bit 4
RP0H.SALSEL_3     3   Segment Address Line Selection - bit 3
RP0H.CSSEL_2      2   Chip Select Line Selection - bit 2
RP0H.CSSEL_1      1   Chip Select Line Selection - bit 1
RP0H.WRC          0   Write Configuration
XP0IC            0xF186   X-Peripheral 0 Interrupt Control Register
XP0IC.XP0IR       7   Interrupt Request Flag
XP0IC.XP0IE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
XP0IC.ILVL_5      5   Interrupt Priority Level - bit 5
XP0IC.ILVL_4      4   Interrupt Priority Level - bit 4
XP0IC.ILVL_3      3   Interrupt Priority Level - bit 3
XP0IC.ILVL_2      2   Interrupt Priority Level - bit 2
XP0IC.GLVL_1      1   Group Level - bit 1
XP0IC.GLVL_0      0   Group Level - bit 0
XP1IC            0xF18E   I2C Protocol Interrupt Control Register
XP1IC.XP1IR       7   Interrupt Request Flag
XP1IC.XP1IE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
XP1IC.ILVL_5      5   Interrupt Priority Level - bit 5
XP1IC.ILVL_4      4   Interrupt Priority Level - bit 4
XP1IC.ILVL_3      3   Interrupt Priority Level - bit 3
XP1IC.ILVL_2      2   Interrupt Priority Level - bit 2
XP1IC.GLVL_1      1   Group Level - bit 1
XP1IC.GLVL_0      0   Group Level - bit 0
XP2IC            0xF196   X-Peripheral 2 Interrupt Control Register
XP2IC.XP2IR       7   Interrupt Request Flag
XP2IC.XP2IE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
XP2IC.ILVL_5      5   Interrupt Priority Level - bit 5
XP2IC.ILVL_4      4   Interrupt Priority Level - bit 4
XP2IC.ILVL_3      3   Interrupt Priority Level - bit 3
XP2IC.ILVL_2      2   Interrupt Priority Level - bit 2
XP2IC.GLVL_1      1   Group Level - bit 1
XP2IC.GLVL_0      0   Group Level - bit 0
S0TBIC           0xF19C   Serial Channel 0 Transmit Buffer Interrupt Control Register
S0TBIC.S0TBIR     7   Interrupt Request Flag
S0TBIC.S0TBIE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
S0TBIC.ILVL_5     5   Interrupt Priority Level - bit 5
S0TBIC.ILVL_4     4   Interrupt Priority Level - bit 4
S0TBIC.ILVL_3     3   Interrupt Priority Level - bit 3
S0TBIC.ILVL_2     2   Interrupt Priority Level - bit 2
S0TBIC.GLVL_1     1   Group Level - bit 1
S0TBIC.GLVL_0     0   Group Level - bit 0
XP3IC            0xF19E   X-Peripheral 3 Interrupt Control Register
XP3IC.XP7IR       7   Interrupt Request Flag
XP3IC.XP7IE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
XP3IC.ILVL_5      5   Interrupt Priority Level - bit 5
XP3IC.ILVL_4      4   Interrupt Priority Level - bit 4
XP3IC.ILVL_3      3   Interrupt Priority Level - bit 3
XP3IC.ILVL_2      2   Interrupt Priority Level - bit 2
XP3IC.GLVL_1      1   Group Level - bit 1
XP3IC.GLVL_0      0   Group Level - bit 0
EXICON           0xF1C0   External Interrupt Control Register
EXICON.EXI7ES_15  15  External Interrupt 15 Edge Selection Field - bit 15
EXICON.EXI7ES_14  14  External Interrupt 14 Edge Selection Field - bit 14
EXICON.EXI6ES_13  13  External Interrupt 13 Edge Selection Field - bit 13
EXICON.EXI6ES_12  12  External Interrupt 12 Edge Selection Field - bit 12
EXICON.EXI5ES_11  11  External Interrupt 11 Edge Selection Field - bit 11
EXICON.EXI5ES_10  10  External Interrupt 10 Edge Selection Field - bit 10
EXICON.EXI4ES_9   9   External Interrupt 9 Edge Selection Field - bit 9 
EXICON.EXI4ES_8   8   External Interrupt 8 Edge Selection Field - bit 8 
EXICON.EXI3ES_7   7   External Interrupt 7 Edge Selection Field - bit 7 
EXICON.EXI3ES_6   6   External Interrupt 6 Edge Selection Field - bit 6 
EXICON.EXI2ES_5   5   External Interrupt 5 Edge Selection Field - bit 5 
EXICON.EXI2ES_4   4   External Interrupt 4 Edge Selection Field - bit 4 
EXICON.EXI1ES_3   3   External Interrupt 3 Edge Selection Field - bit 3 
EXICON.EXI1ES_2   2   External Interrupt 2 Edge Selection Field - bit 2 
EXICON.EXI0ES_1   1   External Interrupt 1 Edge Selection Field - bit 1 
EXICON.EXI0ES_0   0   External Interrupt 0 Edge Selection Field - bit 0 
ODP2             0xF1C2   Port 2 Open Drain Control Register
ODP2.ODP2_15      15  Port 2 Open Drain control register bit 15
ODP2.ODP2_14      14  Port 2 Open Drain control register bit 14
ODP2.ODP2_13      13  Port 2 Open Drain control register bit 13
ODP2.ODP2_12      12  Port 2 Open Drain control register bit 12
ODP2.ODP2_11      11  Port 2 Open Drain control register bit 11
ODP2.ODP2_10      10  Port 2 Open Drain control register bit 10
ODP2.ODP2_9       9   Port 2 Open Drain control register bit 9 
ODP2.ODP2_8       8   Port 2 Open Drain control register bit 8 
PICON            0xF1C4   Port Input Threshold Control Register
PICON.P3HIN       3   Port 3 High Byte Input Level Selection
PICON.P3LIN       2   Port 3 Low Byte Input Level Selection
PICON.P2HIN       1   Port 2 High Byte Input Level Selection
ODP3             0xF1C6   Port 3 Open Drain Control Register
ODP3.ODP3_13      13  Port 3 Open Drain control register bit 13
ODP3.ODP3_11      11  Port 3 Open Drain control register bit 11
ODP3.ODP3_10      10  Port 3 Open Drain control register bit 10
ODP3.ODP3_9       9   Port 3 Open Drain control register bit 9 
ODP3.ODP3_8       8   Port 3 Open Drain control register bit 8 
ODP3.ODP3_7       7   Port 3 Open Drain control register bit 7 
ODP3.ODP3_6       6   Port 3 Open Drain control register bit 6 
ODP3.ODP3_5       5   Port 3 Open Drain control register bit 5 
ODP3.ODP3_4       4   Port 3 Open Drain control register bit 4 
ODP3.ODP3_3       3   Port 3 Open Drain control register bit 3 
ODP3.ODP3_2       2   Port 3 Open Drain control register bit 2 
ODP3.ODP3_1       1   Port 3 Open Drain control register bit 1 
ODP3.ODP3_0       0   Port 3 Open Drain control register bit 0 
ODP6             0xF1CE   Port 6 Open Drain Control Register
ODP6.ODP6_4       4   Port 6 Open Drain control register bit 4
ODP6.ODP6_3       3   Port 6 Open Drain control register bit 3
ODP6.ODP6_2       2   Port 6 Open Drain control register bit 2
ODP6.ODP6_1       1   Port 6 Open Drain control register bit 1
ODP6.ODP6_0       0   Port 6 Open Drain control register bit 0
SYSCON2          0xF1D0   CPU System Configuration Register 2
SYSCON2.CLKLOCK   15  Clock Signal Status Bit
SYSCON2.CLKREL_14 14  Reload Counter Value for Slowdown Divider - 14
SYSCON2.CLKREL_13 13  Reload Counter Value for Slowdown Divider - 13
SYSCON2.CLKREL_12 12  Reload Counter Value for Slowdown Divider - 12
SYSCON2.CLKREL_11 11  Reload Counter Value for Slowdown Divider - 11
SYSCON2.CLKREL_10 10  Reload Counter Value for Slowdown Divider - 10
SYSCON2.CLKCON_9  9   Clock State Control - bit 9
SYSCON2.CLKCON_8  8   Clock State Control - bit 8
SYSCON2.SCS       7   SDD Clock Source
SYSCON2.RCS       6   RTC Clock Source
SYSCON2.PDCON_5   5   Power Down Control - bit 5
SYSCON2.PDCON_4   4   Power Down Control - bit 4
SYSCON2.SYSRLS_3  3   Register Release Function - bit 3
SYSCON2.SYSRLS_2  2   Register Release Function - bit 2
SYSCON2.SYSRLS_1  1   Register Release Function - bit 1
SYSCON2.SYSRLS_0  0   Register Release Function - bit 0
SYSCON3          0xF1D4   CPU System Configuration Register 3
SYSCON3.PCDDIS    15  Peripheral Clock Driver
SYSCON3.I2CDIS    11  On-chip I 2 C-Bus Module
SYSCON3.GPTDIS    3   General Purpose Timer Blocks
SYSCON3.SSCDIS    2   Synchronous Serial Channel SSC
SYSCON3.ASC0DIS   1   USART ASC0
SYSCON3.ADCDIS    0   Analog/Digital Converter
ISNC             0xF1DE   Interrupt Subnode Control Register
ISNC.PLLIE        3   Interrupt Enable Control Bit for Source PLL
ISNC.PLLIR        2   Interrupt Request Flag for Source PLL
ISNC.RTCIE        1   Interrupt Enable Control Bit for Source RTC
ISNC.RTCIR        0   Interrupt Request Flag for Source RTC
DPP0             0xFE00   CPU Data Page Pointer 0 Register (10 bits)
DPP0.DPP0PN_9     9   Data Page Number of DPP0 - bit 9
DPP0.DPP0PN_8     8   Data Page Number of DPP0 - bit 8
DPP0.DPP0PN_7     7   Data Page Number of DPP0 - bit 7
DPP0.DPP0PN_6     6   Data Page Number of DPP0 - bit 6
DPP0.DPP0PN_5     5   Data Page Number of DPP0 - bit 5
DPP0.DPP0PN_4     4   Data Page Number of DPP0 - bit 4
DPP0.DPP0PN_3     3   Data Page Number of DPP0 - bit 3
DPP0.DPP0PN_2     2   Data Page Number of DPP0 - bit 2
DPP0.DPP0PN_1     1   Data Page Number of DPP0 - bit 1
DPP0.DPP0PN_0     0   Data Page Number of DPP0 - bit 0
DPP1             0xFE02   CPU Data Page Pointer 1 Register (10 bits)
DPP1.DPP1PN_9     9   Data Page Number of DPP1 - bit 9
DPP1.DPP1PN_8     8   Data Page Number of DPP1 - bit 8
DPP1.DPP1PN_7     7   Data Page Number of DPP1 - bit 7
DPP1.DPP1PN_6     6   Data Page Number of DPP1 - bit 6
DPP1.DPP1PN_5     5   Data Page Number of DPP1 - bit 5
DPP1.DPP1PN_4     4   Data Page Number of DPP1 - bit 4
DPP1.DPP1PN_3     3   Data Page Number of DPP1 - bit 3
DPP1.DPP1PN_2     2   Data Page Number of DPP1 - bit 2
DPP1.DPP1PN_1     1   Data Page Number of DPP1 - bit 1
DPP1.DPP1PN_0     0   Data Page Number of DPP1 - bit 0
DPP2             0xFE04   CPU Data Page Pointer 2 Register (10 bits)
DPP2.DPP2PN_9     9   Data Page Number of DPP2 - bit 9
DPP2.DPP2PN_8     8   Data Page Number of DPP2 - bit 8
DPP2.DPP2PN_7     7   Data Page Number of DPP2 - bit 7
DPP2.DPP2PN_6     6   Data Page Number of DPP2 - bit 6
DPP2.DPP2PN_5     5   Data Page Number of DPP2 - bit 5
DPP2.DPP2PN_4     4   Data Page Number of DPP2 - bit 4
DPP2.DPP2PN_3     3   Data Page Number of DPP2 - bit 3
DPP2.DPP2PN_2     2   Data Page Number of DPP2 - bit 2
DPP2.DPP2PN_1     1   Data Page Number of DPP2 - bit 1
DPP2.DPP2PN_0     0   Data Page Number of DPP2 - bit 0
DPP3             0xFE06   CPU Data Page Pointer 3 Register (10 bits)
DPP3.DPP3PN_9     9   Data Page Number of DPP3 - bit 9
DPP3.DPP3PN_8     8   Data Page Number of DPP3 - bit 8
DPP3.DPP3PN_7     7   Data Page Number of DPP3 - bit 7
DPP3.DPP3PN_6     6   Data Page Number of DPP3 - bit 6
DPP3.DPP3PN_5     5   Data Page Number of DPP3 - bit 5
DPP3.DPP3PN_4     4   Data Page Number of DPP3 - bit 4
DPP3.DPP3PN_3     3   Data Page Number of DPP3 - bit 3
DPP3.DPP3PN_2     2   Data Page Number of DPP3 - bit 2
DPP3.DPP3PN_1     1   Data Page Number of DPP3 - bit 1
DPP3.DPP3PN_0     0   Data Page Number of DPP3 - bit 0
CSP              0xFE08   CPU Code Segment Pointer Register (8 bits, not directly writeable)
CSP.SEGNR_7       7   Segment Number - bit 7
CSP.SEGNR_6       6   Segment Number - bit 6
CSP.SEGNR_5       5   Segment Number - bit 5
CSP.SEGNR_4       4   Segment Number - bit 4
CSP.SEGNR_3       3   Segment Number - bit 3
CSP.SEGNR_2       2   Segment Number - bit 2
CSP.SEGNR_1       1   Segment Number - bit 1
CSP.SEGNR_0       0   Segment Number - bit 0
MDH              0xFE0C   CPU Multiply Divide Register ­ High Word
MDH.mdh_15        15
MDH.mdh_14        14
MDH.mdh_13        13
MDH.mdh_12        12
MDH.mdh_11        11
MDH.mdh_10        10
MDH.mdh_9         9 
MDH.mdh_8         8 
MDH.mdh_7         7 
MDH.mdh_6         6 
MDH.mdh_5         5 
MDH.mdh_4         4 
MDH.mdh_3         3 
MDH.mdh_2         2 
MDH.mdh_1         1 
MDH.mdh_0         0 
MDL              0xFE0E   CPU Multiply Divide Register ­ Low Word
MDL.MDL_15        15
MDL.MDL_14        14
MDL.MDL_13        13
MDL.MDL_12        12
MDL.MDL_11        11
MDL.MDL_10        10
MDL.MDL_9         9 
MDL.MDL_8         8 
MDL.MDL_7         7 
MDL.MDL_6         6 
MDL.MDL_5         5 
MDL.MDL_4         4 
MDL.MDL_3         3 
MDL.MDL_2         2 
MDL.MDL_1         1 
MDL.MDL_0         0 
CP               0xFE10   CPU Context Pointer Register
CP.cp_11          11  Modifiable portion of register CP - bit 11
CP.cp_10          10  Modifiable portion of register CP - bit 10
CP.cp_9           9   Modifiable portion of register CP - bit 9
CP.cp_8           8   Modifiable portion of register CP - bit 8
CP.cp_7           7   Modifiable portion of register CP - bit 7
CP.cp_6           6   Modifiable portion of register CP - bit 6
CP.cp_5           5   Modifiable portion of register CP - bit 5
CP.cp_4           4   Modifiable portion of register CP - bit 4
CP.cp_3           3   Modifiable portion of register CP - bit 3
CP.cp_2           2   Modifiable portion of register CP - bit 2
CP.cp_1           1   Modifiable portion of register CP - bit 1
SP               0xFE12   CPU System Stack Pointer Register
SP.sp_11          11  Modifiable portion of register SP - bit 11
SP.sp_10          10  Modifiable portion of register SP - bit 10
SP.sp_9           9   Modifiable portion of register SP - bit 9
SP.sp_8           8   Modifiable portion of register SP - bit 8
SP.sp_7           7   Modifiable portion of register SP - bit 7
SP.sp_6           6   Modifiable portion of register SP - bit 6
SP.sp_5           5   Modifiable portion of register SP - bit 5
SP.sp_4           4   Modifiable portion of register SP - bit 4
SP.sp_3           3   Modifiable portion of register SP - bit 3
SP.sp_2           2   Modifiable portion of register SP - bit 2
SP.sp_1           1   Modifiable portion of register SP - bit 1
STKOV            0xFE14   CPU Stack Overflow Pointer Register
STKOV.stkov_11    11  Modifiable portion of register STKOV - bit 11
STKOV.stkov_10    10  Modifiable portion of register STKOV - bit 10
STKOV.stkov_9     9   Modifiable portion of register STKOV - bit 9
STKOV.stkov_8     8   Modifiable portion of register STKOV - bit 8
STKOV.stkov_7     7   Modifiable portion of register STKOV - bit 7
STKOV.stkov_6     6   Modifiable portion of register STKOV - bit 6
STKOV.stkov_5     5   Modifiable portion of register STKOV - bit 5
STKOV.stkov_4     4   Modifiable portion of register STKOV - bit 4
STKOV.stkov_3     3   Modifiable portion of register STKOV - bit 3
STKOV.stkov_2     2   Modifiable portion of register STKOV - bit 2
STKOV.stkov_1     1   Modifiable portion of register STKOV - bit 1
STKUN            0xFE16   CPU Stack Underflow Pointer Register
STKUN.STKUN_11    11  Modifiable portion of register STKUN - bit 11
STKUN.STKUN_10    10  Modifiable portion of register STKUN - bit 10
STKUN.STKUN_9     9   Modifiable portion of register STKUN - bit 9
STKUN.STKUN_8     8   Modifiable portion of register STKUN - bit 8
STKUN.STKUN_7     7   Modifiable portion of register STKUN - bit 7
STKUN.STKUN_6     6   Modifiable portion of register STKUN - bit 6
STKUN.STKUN_5     5   Modifiable portion of register STKUN - bit 5
STKUN.STKUN_4     4   Modifiable portion of register STKUN - bit 4
STKUN.STKUN_3     3   Modifiable portion of register STKUN - bit 3
STKUN.STKUN_2     2   Modifiable portion of register STKUN - bit 2
STKUN.STKUN_1     1   Modifiable portion of register STKUN - bit 1
ADDRSEL1         0xFE18   Address Select Register 1
ADDRSEL1.RGSAD15  15  Range Start Address bit 15
ADDRSEL1.RGSAD14  14  Range Start Address bit 14
ADDRSEL1.RGSAD13  13  Range Start Address bit 13
ADDRSEL1.RGSAD12  12  Range Start Address bit 12
ADDRSEL1.RGSAD11  11  Range Start Address bit 11
ADDRSEL1.RGSAD10  10  Range Start Address bit 10
ADDRSEL1.RGSAD9   9   Range Start Address bit 9 
ADDRSEL1.RGSAD8   8   Range Start Address bit 8 
ADDRSEL1.RGSAD7   7   Range Start Address bit 7 
ADDRSEL1.RGSAD6   6   Range Start Address bit 6 
ADDRSEL1.RGSAD5   5   Range Start Address bit 5 
ADDRSEL1.RGSAD4   4   Range Start Address bit 4 
ADDRSEL1.RGSZ3    3   Range Size Selection bit 3
ADDRSEL1.RGSZ2    2   Range Size Selection bit 2
ADDRSEL1.RGSZ1    1   Range Size Selection bit 1
ADDRSEL1.RGSZ0    0   Range Size Selection bit 0
ADDRSEL2         0xFE1A   Address Select Register 2
ADDRSEL2.RGSAD15  15  Range Start Address bit 15
ADDRSEL2.RGSAD14  14  Range Start Address bit 14
ADDRSEL2.RGSAD13  13  Range Start Address bit 13
ADDRSEL2.RGSAD12  12  Range Start Address bit 12
ADDRSEL2.RGSAD11  11  Range Start Address bit 11
ADDRSEL2.RGSAD10  10  Range Start Address bit 10
ADDRSEL2.RGSAD9   9   Range Start Address bit 9 
ADDRSEL2.RGSAD8   8   Range Start Address bit 8 
ADDRSEL2.RGSAD7   7   Range Start Address bit 7 
ADDRSEL2.RGSAD6   6   Range Start Address bit 6 
ADDRSEL2.RGSAD5   5   Range Start Address bit 5 
ADDRSEL2.RGSAD4   4   Range Start Address bit 4 
ADDRSEL2.RGSZ3    3   Range Size Selection bit 3
ADDRSEL2.RGSZ2    2   Range Size Selection bit 2
ADDRSEL2.RGSZ1    1   Range Size Selection bit 1
ADDRSEL2.RGSZ0    0   Range Size Selection bit 0
ADDRSEL3         0xFE1C   Address Select Register 3
ADDRSEL3.RGSAD15  15  Range Start Address bit 15
ADDRSEL3.RGSAD14  14  Range Start Address bit 14
ADDRSEL3.RGSAD13  13  Range Start Address bit 13
ADDRSEL3.RGSAD12  12  Range Start Address bit 12
ADDRSEL3.RGSAD11  11  Range Start Address bit 11
ADDRSEL3.RGSAD10  10  Range Start Address bit 10
ADDRSEL3.RGSAD9   9   Range Start Address bit 9 
ADDRSEL3.RGSAD8   8   Range Start Address bit 8 
ADDRSEL3.RGSAD7   7   Range Start Address bit 7 
ADDRSEL3.RGSAD6   6   Range Start Address bit 6 
ADDRSEL3.RGSAD5   5   Range Start Address bit 5 
ADDRSEL3.RGSAD4   4   Range Start Address bit 4 
ADDRSEL3.RGSZ3    3   Range Size Selection bit 3
ADDRSEL3.RGSZ2    2   Range Size Selection bit 2
ADDRSEL3.RGSZ1    1   Range Size Selection bit 1
ADDRSEL3.RGSZ0    0   Range Size Selection bit 0
ADDRSEL4         0xFE1E   Address Select Register 4
ADDRSEL4.RGSAD15  15  Range Start Address bit 15
ADDRSEL4.RGSAD14  14  Range Start Address bit 14
ADDRSEL4.RGSAD13  13  Range Start Address bit 13
ADDRSEL4.RGSAD12  12  Range Start Address bit 12
ADDRSEL4.RGSAD11  11  Range Start Address bit 11
ADDRSEL4.RGSAD10  10  Range Start Address bit 10
ADDRSEL4.RGSAD9   9   Range Start Address bit 9 
ADDRSEL4.RGSAD8   8   Range Start Address bit 8 
ADDRSEL4.RGSAD7   7   Range Start Address bit 7 
ADDRSEL4.RGSAD6   6   Range Start Address bit 6 
ADDRSEL4.RGSAD5   5   Range Start Address bit 5 
ADDRSEL4.RGSAD4   4   Range Start Address bit 4 
ADDRSEL4.RGSZ3    3   Range Size Selection bit 3
ADDRSEL4.RGSZ2    2   Range Size Selection bit 2
ADDRSEL4.RGSZ1    1   Range Size Selection bit 1
ADDRSEL4.RGSZ0    0   Range Size Selection bit 0
T2               0xFE40   GPT1 Timer 2 Register
T3               0xFE42   GPT1 Timer 3 Register
T4               0xFE44   GPT1 Timer 4 Register
T5               0xFE46   GPT2 Timer 5 Register
T6               0xFE48   GPT2 Timer 6 Register
CAPREL           0xFE4A   GPT2 Capture/Reload Register
ADDAT            0xFEA0   A/D Converter Result Register
ADDAT2.ADRES_9    9   A/D Conversion Result - bit 9
ADDAT2.ADRES_8    8   A/D Conversion Result - bit 8
ADDAT2.ADRES_7    7   A/D Conversion Result - bit 7
ADDAT2.ADRES_6    6   A/D Conversion Result - bit 6
ADDAT2.ADRES_5    5   A/D Conversion Result - bit 5
ADDAT2.ADRES_4    4   A/D Conversion Result - bit 4
ADDAT2.ADRES_3    3   A/D Conversion Result - bit 3
ADDAT2.ADRES_2    2   A/D Conversion Result - bit 2
ADDAT2.ADRES_1    1   A/D Conversion Result - bit 1
ADDAT2.ADRES_0    0   A/D Conversion Result - bit 0
WDT              0xFEAE   Watchdog Timer Register (read only)
S0TBUF           0xFEB0   Serial Channel 0 Transmit Buffer Register
S0RBUF           0xFEB2   Serial Channel 0 Receive Buffer Register (read only)
S0BG             0xFEB4   Serial Channel 0 Baud Rate Generator Reload Register
PECC0            0xFEC0   PEC Channel 0 Control Register
PECC0.INC_10      10  Increment Control - bit 10
PECC0.INC_9       9   Increment Control - bit 9
PECC0.BWT         8   Byte/Word Transfer Selection
PECC0.COUNT_7     7   PEC Transfer Count - bit 7
PECC0.COUNT_6     6   PEC Transfer Count - bit 6
PECC0.COUNT_5     5   PEC Transfer Count - bit 5
PECC0.COUNT_4     4   PEC Transfer Count - bit 4
PECC0.COUNT_3     3   PEC Transfer Count - bit 3
PECC0.COUNT_2     2   PEC Transfer Count - bit 2
PECC0.COUNT_1     1   PEC Transfer Count - bit 1
PECC0.COUNT_0     0   PEC Transfer Count - bit 0
PECC1            0xFEC2   PEC Channel 1 Control Register
PECC1.INC_10      10  Increment Control - bit 10
PECC1.INC_9       9   Increment Control - bit 9
PECC1.BWT         8   Byte/Word Transfer Selection
PECC1.COUNT_7     7   PEC Transfer Count - bit 7
PECC1.COUNT_6     6   PEC Transfer Count - bit 6
PECC1.COUNT_5     5   PEC Transfer Count - bit 5
PECC1.COUNT_4     4   PEC Transfer Count - bit 4
PECC1.COUNT_3     3   PEC Transfer Count - bit 3
PECC1.COUNT_2     2   PEC Transfer Count - bit 2
PECC1.COUNT_1     1   PEC Transfer Count - bit 1
PECC1.COUNT_0     0   PEC Transfer Count - bit 0
PECC2            0xFEC4   PEC Channel 2 Control Register
PECC2.INC_10      10  Increment Control - bit 10
PECC2.INC_9       9   Increment Control - bit 9 
PECC2.BWT         8   Byte/Word Transfer Selection
PECC2.COUNT_7     7   PEC Transfer Count - bit 7
PECC2.COUNT_6     6   PEC Transfer Count - bit 6
PECC2.COUNT_5     5   PEC Transfer Count - bit 5
PECC2.COUNT_4     4   PEC Transfer Count - bit 4
PECC2.COUNT_3     3   PEC Transfer Count - bit 3
PECC2.COUNT_2     2   PEC Transfer Count - bit 2
PECC2.COUNT_1     1   PEC Transfer Count - bit 1
PECC2.COUNT_0     0   PEC Transfer Count - bit 0
PECC3            0xFEC6   PEC Channel 3 Control Register
PECC3.INC_10      10  Increment Control - bit 10
PECC3.INC_9       9   Increment Control - bit 9 
PECC3.BWT         8   Byte/Word Transfer Selection
PECC3.COUNT_7     7   PEC Transfer Count - bit 7
PECC3.COUNT_6     6   PEC Transfer Count - bit 6
PECC3.COUNT_5     5   PEC Transfer Count - bit 5
PECC3.COUNT_4     4   PEC Transfer Count - bit 4
PECC3.COUNT_3     3   PEC Transfer Count - bit 3
PECC3.COUNT_2     2   PEC Transfer Count - bit 2
PECC3.COUNT_1     1   PEC Transfer Count - bit 1
PECC3.COUNT_0     0   PEC Transfer Count - bit 0
PECC4            0xFEC8   PEC Channel 4 Control Register
PECC4.INC_10      10  Increment Control - bit 10
PECC4.INC_9       9   Increment Control - bit 9 
PECC4.BWT         8   Byte/Word Transfer Selection
PECC4.COUNT_7     7   PEC Transfer Count - bit 7
PECC4.COUNT_6     6   PEC Transfer Count - bit 6
PECC4.COUNT_5     5   PEC Transfer Count - bit 5
PECC4.COUNT_4     4   PEC Transfer Count - bit 4
PECC4.COUNT_3     3   PEC Transfer Count - bit 3
PECC4.COUNT_2     2   PEC Transfer Count - bit 2
PECC4.COUNT_1     1   PEC Transfer Count - bit 1
PECC4.COUNT_0     0   PEC Transfer Count - bit 0
PECC5            0xFECA   PEC Channel 5 Control Register
PECC5.INC_10      10  Increment Control - bit 10
PECC5.INC_9       9   Increment Control - bit 9 
PECC5.BWT         8   Byte/Word Transfer Selection
PECC5.COUNT_7     7   PEC Transfer Count - bit 7
PECC5.COUNT_6     6   PEC Transfer Count - bit 6
PECC5.COUNT_5     5   PEC Transfer Count - bit 5
PECC5.COUNT_4     4   PEC Transfer Count - bit 4
PECC5.COUNT_3     3   PEC Transfer Count - bit 3
PECC5.COUNT_2     2   PEC Transfer Count - bit 2
PECC5.COUNT_1     1   PEC Transfer Count - bit 1
PECC5.COUNT_0     0   PEC Transfer Count - bit 0
PECC6            0xFECC   PEC Channel 6 Control Register
PECC6.INC_10      10  Increment Control - bit 10
PECC6.INC_9       9   Increment Control - bit 9 
PECC6.BWT         8   Byte/Word Transfer Selection
PECC6.COUNT_7     7   PEC Transfer Count - bit 7
PECC6.COUNT_6     6   PEC Transfer Count - bit 6
PECC6.COUNT_5     5   PEC Transfer Count - bit 5
PECC6.COUNT_4     4   PEC Transfer Count - bit 4
PECC6.COUNT_3     3   PEC Transfer Count - bit 3
PECC6.COUNT_2     2   PEC Transfer Count - bit 2
PECC6.COUNT_1     1   PEC Transfer Count - bit 1
PECC6.COUNT_0     0   PEC Transfer Count - bit 0
PECC7            0xFECE   PEC Channel 7 Control Register
PECC7.INC_10      10  Increment Control - bit 10
PECC7.INC_9       9   Increment Control - bit 9 
PECC7.BWT         8   Byte/Word Transfer Selection
PECC7.COUNT_7     7   PEC Transfer Count - bit 7
PECC7.COUNT_6     6   PEC Transfer Count - bit 6
PECC7.COUNT_5     5   PEC Transfer Count - bit 5
PECC7.COUNT_4     4   PEC Transfer Count - bit 4
PECC7.COUNT_3     3   PEC Transfer Count - bit 3
PECC7.COUNT_2     2   PEC Transfer Count - bit 2
PECC7.COUNT_1     1   PEC Transfer Count - bit 1
PECC7.COUNT_0     0   PEC Transfer Count - bit 0
P0L              0xFF00   Port 0 Low Register (Lower half of PORT0)
P0L.P0L7          7   Port data register P0L bit 7
P0L.P0L6          6   Port data register P0L bit 6
P0L.P0L5          5   Port data register P0L bit 5
P0L.P0L4          4   Port data register P0L bit 4
P0L.P0L3          3   Port data register P0L bit 3
P0L.P0L2          2   Port data register P0L bit 2
P0L.P0L1          1   Port data register P0L bit 1
P0L.P0L0          0   Port data register P0L bit 0
P0H              0xFF02   Port 0 High Register (Upper half of PORT0)
P0H.P0H7          7   Port data register P0H bit 7
P0H.P0H6          6   Port data register P0H bit 6
P0H.P0H5          5   Port data register P0H bit 5
P0H.P0H4          4   Port data register P0H bit 4
P0H.P0H3          3   Port data register P0H bit 3
P0H.P0H2          2   Port data register P0H bit 2
P0H.P0H1          1   Port data register P0H bit 1
P0H.P0H0          0   Port data register P0H bit 0
P1L              0xFF04   Port 1 Low Register (Lower half of PORT1)
P1L.P1L7          7   Port data register P1L bit 7
P1L.P1L6          6   Port data register P1L bit 6
P1L.P1L5          5   Port data register P1L bit 5
P1L.P1L4          4   Port data register P1L bit 4
P1L.P1L3          3   Port data register P1L bit 3
P1L.P1L2          2   Port data register P1L bit 2
P1L.P1L1          1   Port data register P1L bit 1
P1L.P1L0          0   Port data register P1L bit 0
P1H              0xFF06   Port 1 High Register (Upper half of PORT1)
P1H.P1H7          7   Port data register P1H bit 7
P1H.P1H6          6   Port data register P1H bit 6
P1H.P1H5          5   Port data register P1H bit 5
P1H.P1H4          4   Port data register P1H bit 4
P1H.P1H3          3   Port data register P1H bit 3
P1H.P1H2          2   Port data register P1H bit 2
P1H.P1H1          1   Port data register P1H bit 1
P1H.P1H0          0   Port data register P1H bit 0
BUSCON0          0xFF0C   Bus Configuration Register 0
BUSCON0.CSWEN0    15  Write Chip Select Enable
BUSCON0.CSREN0    14  Read Chip Select Enable
BUSCON0.RDYEN0    12  READY Input Enable
BUSCON0.BUSACT0   10  Bus Active Control
BUSCON0.ALECTL0   9   ALE Lengthening Control
BUSCON0.BTYP_7    7   External Bus Configuration - bit 7
BUSCON0.BTYP_6    6   External Bus Configuration - bit 6
BUSCON0.MTTC0     5   Memory Tristate Time Control
BUSCON0.RWDC0     4   Read/Write Delay Control for BUSCON
BUSCON0.MCTC_3    3   Memory Cycle Time Control - bit 3
BUSCON0.MCTC_2    2   Memory Cycle Time Control - bit 2
BUSCON0.MCTC_1    1   Memory Cycle Time Control - bit 1
BUSCON0.MCTC_0    0   Memory Cycle Time Control - bit 0
MDC              0xFF0E   CPU Multiply Divide Control Register
MDC.MDRIU         4   Multiply/Divide Register In Use
PSW              0xFF10   CPU Program Status Word
PSW.ILVL_15       15  Interrupt and EBC Control Field - bit 15
PSW.ILVL_14       14  Interrupt and EBC Control Field - bit 14
PSW.ILVL_13       13  Interrupt and EBC Control Field - bit 13
PSW.ILVL_12       12  Interrupt and EBC Control Field - bit 12
PSW.IEN           11  Interrupt and EBC Control Field
PSW.HLDEN         10  Interrupt and EBC Control Field
PSW.USR0          6   User General Purpose Flag
PSW.MULIP         5   Multiplication/Division In Progress
PSW.E             4   End of Table Flag
PSW.Z             3   Zero F lag
PSW.V             2   Overflow Result
PSW.C             1   Carry Flag
PSW.N             0   Negative Result
SYSCON           0xFF12   CPU System Configuration Register
SYSCON.STKSZ_15   15  System Stack Size - bit 15
SYSCON.STKSZ_14   14  System Stack Size - bit 14
SYSCON.STKSZ_13   13  System Stack Size - bit 13
SYSCON.ROMS1      12  Internal ROM Mapping
SYSCON.SGTDIS     11  Segmentation Disable/Enable Control (Cleared after reset)
SYSCON.ROMEN      10  Internal ROM Enable (Set according to pin EA during reset)
SYSCON.BYTDIS     9   Disable/Enable Control for Pin BHE (Set according to data bus width)
SYSCON.CLKEN      8   System Clock Output Enable (CLKOUT, cleared after reset)
SYSCON.WRCFG      7   Write Configuration Control (Set according to pin P0H.0 during reset)
SYSCON.CSCFG      6   Chip Select Configuration Control (Cleared after reset)
SYSCON.OWDDIS     4   Oscillator Watchdog Disable Bit (Depending on reset configuration)
SYSCON.BDRSTEN    3   Bidirectional Reset Enable Bit
SYSCON.XPEN       2   Peripheral Enable Bit
SYSCON.VISIBLE    1   Visible Mode Control
SYSCON.XPER_SHARE 0   XBUS Peripheral Share Mode Control
BUSCON1          0xFF14   Bus Configuration Register 1
BUSCON1.CSWEN1    15  Write Chip Select Enable
BUSCON1.CSREN1    14  Read Chip Select Enable
BUSCON1.RDYEN1    12  READY Input Enable
BUSCON1.BUSACT1   10  Bus Active Control
BUSCON1.ALECTL1   9   ALE Lengthening Control
BUSCON1.BTYP_7    7   External Bus Configuration - bit 7
BUSCON1.BTYP_6    6   External Bus Configuration - bit 6
BUSCON1.MTTC1     5   Memory Tristate Time Control
BUSCON1.RWDC1     4   Read/Write Delay Control for BUSCON
BUSCON1.MCTC_3    3   Memory Cycle Time Control - bit 3
BUSCON1.MCTC_2    2   Memory Cycle Time Control - bit 2
BUSCON1.MCTC_1    1   Memory Cycle Time Control - bit 1
BUSCON1.MCTC_0    0   Memory Cycle Time Control - bit 0
BUSCON2          0xFF16   Bus Configuration Register 2
BUSCON2.CSWEN2    15  Write Chip Select Enable
BUSCON2.CSREN2    14  Read Chip Select Enable
BUSCON2.RDYEN2    12  READY Input Enable
BUSCON2.BUSACT2   10  Bus Active Control
BUSCON2.ALECTL2   9   ALE Lengthening Control
BUSCON2.BTYP_7    7   External Bus Configuration - bit 7
BUSCON2.BTYP_6    6   External Bus Configuration - bit 6
BUSCON2.MTTC2     5   Memory Tristate Time Control
BUSCON2.RWDC2     4   Read/Write Delay Control for BUSCON
BUSCON2.MCTC_3    3   Memory Cycle Time Control - bit 3
BUSCON2.MCTC_2    2   Memory Cycle Time Control - bit 2
BUSCON2.MCTC_1    1   Memory Cycle Time Control - bit 1
BUSCON2.MCTC_0    0   Memory Cycle Time Control - bit 0
BUSCON3          0xFF18   Bus Configuration Register 3
BUSCON3.CSWEN3    15  Write Chip Select Enable
BUSCON3.CSREN3    14  Read Chip Select Enable
BUSCON3.RDYEN3    12  READY Input Enable
BUSCON3.BUSACT3   10  Bus Active Control
BUSCON3.ALECTL3   9   ALE Lengthening Control
BUSCON3.BTYP_7    7   External Bus Configuration - bit 7
BUSCON3.BTYP_6    6   External Bus Configuration - bit 6
BUSCON3.MTTC3     5   Memory Tristate Time Control
BUSCON3.RWDC3     4   Read/Write Delay Control for BUSCON
BUSCON3.MCTC_3    3   Memory Cycle Time Control - bit 3
BUSCON3.MCTC_2    2   Memory Cycle Time Control - bit 2
BUSCON3.MCTC_1    1   Memory Cycle Time Control - bit 1
BUSCON3.MCTC_0    0   Memory Cycle Time Control - bit 0
BUSCON4          0xFF1A   Bus Configuration Register 4
BUSCON4.CSWEN4    15  Write Chip Select Enable
BUSCON4.CSREN4    14  Read Chip Select Enable
BUSCON4.RDYEN4    12  READY Input Enable
BUSCON4.BUSACT4   10  Bus Active Control
BUSCON4.ALECTL4   9   ALE Lengthening Control
BUSCON4.BTYP_7    7   External Bus Configuration - bit 7
BUSCON4.BTYP_6    6   External Bus Configuration - bit 6
BUSCON4.MTTC4     5   Memory Tristate Time Control
BUSCON4.RWDC4     4   Read/Write Delay Control for BUSCON
BUSCON4.MCTC_3    3   Memory Cycle Time Control - bit 3
BUSCON4.MCTC_2    2   Memory Cycle Time Control - bit 2
BUSCON4.MCTC_1    1   Memory Cycle Time Control - bit 1
BUSCON4.MCTC_0    0   Memory Cycle Time Control - bit 0
ZEROS            0xFF1C   Constant Value 0's Register (read only)
ONES             0xFF1E   Constant Value 1's Register (read only)
T2CON            0xFF40   GPT1 Timer 2 Control Register
T2CON.T2UDE       8   Timer 2 External Up/Down Enable
T2CON.T2UD        7   Timer 2 Up / Down Control
T2CON.T2R         6   Timer 2 Run Bit
T2CON.T2M_5       5   Timer 2 Mode Control - bit 5
T2CON.T2M_4       4   Timer 2 Mode Control - bit 4
T2CON.T2M_3       3   Timer 2 Mode Control - bit 3
T2CON.T2I_2       2   Timer 2 Input Selection - bit 2
T2CON.T2I_1       1   Timer 2 Input Selection - bit 1
T2CON.T2I_0       0   Timer 2 Input Selection - bit 0
T3CON            0xFF42   GPT1 Timer 3 Control Register
T3CON.T3OTL       10  Timer 3 Output Toggle Latch
T3CON.T3OE        9   Alternate Output Function Enable
T3CON.T3UDE       8   Timer 3 External Up/Down Enable
T3CON.T3UD        7   Timer 3 Up / Down Control
T3CON.T3R         6   Timer 3 Run Bit
T3CON.T3M_5       5   Timer 3 Mode Control - bit 5
T3CON.T3M_4       4   Timer 3 Mode Control - bit 4
T3CON.T3M_3       3   Timer 3 Mode Control - bit 3
T3CON.T3I_2       2   Timer 3 Input Selection - bit 2
T3CON.T3I_1       1   Timer 3 Input Selection - bit 1
T3CON.T3I_0       0   Timer 3 Input Selection - bit 0
T4CON            0xFF44   GPT1 Timer 4 Control Register
T4CON.T4UDE       8   Timer 4 External Up/Down Enable
T4CON.T4UD        7   Timer 4 Up / Down Control
T4CON.T4R         6   Timer 4 Run Bit
T4CON.T4M_5       5   Timer 4 Mode Control - bit 5
T4CON.T4M_4       4   Timer 4 Mode Control - bit 4
T4CON.T4M_3       3   Timer 4 Mode Control - bit 3
T4CON.T4I_2       2   Timer 4 Input Selection - bit 2
T4CON.T4I_1       1   Timer 4 Input Selection - bit 1
T4CON.T4I_0       0   Timer 4 Input Selection - bit 0
T5CON            0xFF46   GPT2 Timer 5 Control Register
T5CON.T5SR        15  Timer 5 Reload Mode Enable
T5CON.T5CLR       14  Timer 5 Clear Bit
T5CON.CI_13       13  Register CAPREL Capture Trigger Selection - bit 13
T5CON.CI_12       12  Register CAPREL Capture Trigger Selection - bit 12
T5CON.CT3         10  Timer 3 Capture Trigger Enable
T5CON.T5UD        7   Timer 5 Up / Down Control
T5CON.T5R         6   Timer 5 Run Bit
T5CON.T5M_4       4   Timer 5 Mode Control - bit 4
T5CON.T5M_3       3   Timer 5 Mode Control - bit 3
T5CON.T5I_2       2   Timer 5 Input Selection - bit 2
T5CON.T5I_1       1   Timer 5 Input Selection - bit 1
T5CON.T5I_0       0   Timer 5 Input Selection - bit 0
T6CON            0xFF48   GPT2 Timer 6 Control Register
T6CON.T6SR        15  Timer 6 Reload Mode Enable
T6CON.T6OTL       10  Timer 6 Output Toggle Latch
T6CON.T6UD        7   Timer 6 Up / Down Control
T6CON.T6R         6   Timer 6 Run Bit
T6CON.T6M_5       5   Timer 6 Mode Control - bit 5
T6CON.T6M_4       4   Timer 6 Mode Control - bit 4
T6CON.T6M_3       3   Timer 6 Mode Control - bit 3
T6CON.T6I_2       2   Timer 6 Input Selection - bit 2
T6CON.T6I_1       1   Timer 6 Input Selection - bit 1
T6CON.T6I_0       0   Timer 6 Input Selection - bit 0
T2IC             0xFF60   GPT1 Timer 2  Interrupt Control Register
T2IC.T2IR         7   Interrupt Request Flag
T2IC.T2IE         6   Interrupt Enable Control Bit (individually enables/disables a specific source)
T2IC.ILVL_5       5   Interrupt Priority Level - bit 5
T2IC.ILVL_4       4   Interrupt Priority Level - bit 4
T2IC.ILVL_3       3   Interrupt Priority Level - bit 3
T2IC.ILVL_2       2   Interrupt Priority Level - bit 2
T2IC.GLVL_1       1   Group Level - bit 1
T2IC.GLVL_0       0   Group Level - bit 0
T3IC             0xFF62   GPT1 Timer 3 Interrupt Control Register
T3IC.T3IR         7   Interrupt Request Flag
T3IC.T3IE         6   Interrupt Enable Control Bit (individually enables/disables a specific source)
T3IC.ILVL_5       5   Interrupt Priority Level - bit 5
T3IC.ILVL_4       4   Interrupt Priority Level - bit 4
T3IC.ILVL_3       3   Interrupt Priority Level - bit 3
T3IC.ILVL_2       2   Interrupt Priority Level - bit 2
T3IC.GLVL_1       1   Group Level - bit 1
T3IC.GLVL_0       0   Group Level - bit 0
T4IC             0xFF64   GPT1 Timer 4 Interrupt Control Register
T4IC.T4IR         7   Interrupt Request Flag
T4IC.T4IE         6   Interrupt Enable Control Bit (individually enables/disables a specific source)
T4IC.ILVL_5       5   Interrupt Priority Level - bit 5
T4IC.ILVL_4       4   Interrupt Priority Level - bit 4
T4IC.ILVL_3       3   Interrupt Priority Level - bit 3
T4IC.ILVL_2       2   Interrupt Priority Level - bit 2
T4IC.GLVL_1       1   Group Level - bit 1
T4IC.GLVL_0       0   Group Level - bit 0
T5IC             0xFF66   GPT2 Timer 5 Interrupt Control Register
T5IC.T5IR         7   Interrupt Request Flag
T5IC.T5IE         6   Interrupt Enable Control Bit (individually enables/disables a specific source)
T5IC.ILVL_5       5   Interrupt Priority Level - bit 5
T5IC.ILVL_4       4   Interrupt Priority Level - bit 4
T5IC.ILVL_3       3   Interrupt Priority Level - bit 3
T5IC.ILVL_2       2   Interrupt Priority Level - bit 2
T5IC.GLVL_1       1   Group Level - bit 1
T5IC.GLVL_0       0   Group Level - bit 0
T6IC             0xFF68   GPT2 Timer 6 Interrupt Control Register
T6IC.T2IR         7   Interrupt Request Flag
T6IC.T2IE         6   Interrupt Enable Control Bit (individually enables/disables a specific source)
T6IC.ILVL_5       5   Interrupt Priority Level - bit 5
T6IC.ILVL_4       4   Interrupt Priority Level - bit 4
T6IC.ILVL_3       3   Interrupt Priority Level - bit 3
T6IC.ILVL_2       2   Interrupt Priority Level - bit 2
T6IC.GLVL_1       1   Group Level - bit 1
T6IC.GLVL_0       0   Group Level - bit 0
CRIC             0xFF6A   GPT2 CAPREL Interrupt Control Register
CRIC.CRIR         7   Interrupt Request Flag
CRIC.CRIE         6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CRIC.ILVL_5       5   Interrupt Priority Level - bit 5
CRIC.ILVL_4       4   Interrupt Priority Level - bit 4
CRIC.ILVL_3       3   Interrupt Priority Level - bit 3
CRIC.ILVL_2       2   Interrupt Priority Level - bit 2
CRIC.GLVL_1       1   Group Level - bit 1
CRIC.GLVL_0       0   Group Level - bit 0
S0TIC            0xFF6C   Serial Channel 0 Transmit Interrupt Control Register
S0TIC.S0TIR       7   Interrupt Request Flag
S0TIC.S0TIE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
S0TIC.ILVL_5      5   Interrupt Priority Level - bit 5
S0TIC.ILVL_4      4   Interrupt Priority Level - bit 4
S0TIC.ILVL_3      3   Interrupt Priority Level - bit 3
S0TIC.ILVL_2      2   Interrupt Priority Level - bit 2
S0TIC.GLVL_1      1   Group Level - bit 1
S0TIC.GLVL_0      0   Group Level - bit 0
S0RIC            0xFF6E   Serial Channel 0 Receive Interrupt Control Register
S0RIC.S0RIR       7   Interrupt Request Flag
S0RIC.S0RIE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
S0RIC.ILVL_5      5   Interrupt Priority Level - bit 5
S0RIC.ILVL_4      4   Interrupt Priority Level - bit 4
S0RIC.ILVL_3      3   Interrupt Priority Level - bit 3
S0RIC.ILVL_2      2   Interrupt Priority Level - bit 2
S0RIC.GLVL_1      1   Group Level - bit 1
S0RIC.GLVL_0      0   Group Level - bit 0
S0EIC            0xFF70   Serial Channel 0 Error Interrupt Control Register
S0EIC.S0EIR       7   Interrupt Request Flag
S0EIC.S0EIE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
S0EIC.ILVL_5      5   Interrupt Priority Level - bit 5
S0EIC.ILVL_4      4   Interrupt Priority Level - bit 4
S0EIC.ILVL_3      3   Interrupt Priority Level - bit 3
S0EIC.ILVL_2      2   Interrupt Priority Level - bit 2
S0EIC.GLVL_1      1   Group Level - bit 1
S0EIC.GLVL_0      0   Group Level - bit 0
SSCTIC           0xFF72   SSC Transmit Interrupt Control Register
SSCTIC.SSCTIR     7   Interrupt Request Flag
SSCTIC.SSCTIE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
SSCTIC.ILVL_5     5   Interrupt Priority Level - bit 5
SSCTIC.ILVL_4     4   Interrupt Priority Level - bit 4
SSCTIC.ILVL_3     3   Interrupt Priority Level - bit 3
SSCTIC.ILVL_2     2   Interrupt Priority Level - bit 2
SSCTIC.GLVL_1     1   Group Level - bit 1
SSCTIC.GLVL_0     0   Group Level - bit 0
SSCRIC           0xFF74   SSC Receive Interrupt Control Register
SSCRIC.SSCRIR     7   Interrupt Request Flag
SSCRIC.SSCRIE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
SSCRIC.ILVL_5     5   Interrupt Priority Level - bit 5
SSCRIC.ILVL_4     4   Interrupt Priority Level - bit 4
SSCRIC.ILVL_3     3   Interrupt Priority Level - bit 3
SSCRIC.ILVL_2     2   Interrupt Priority Level - bit 2
SSCRIC.GLVL_1     1   Group Level - bit 1
SSCRIC.GLVL_0     0   Group Level - bit 0
SSCEIC           0xFF76   SSC Error Interrupt Control Register
SSCEIC.SSCEIR     7   Interrupt Request Flag
SSCEIC.SSCEIE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
SSCEIC.ILVL_5     5   Interrupt Priority Level - bit 5
SSCEIC.ILVL_4     4   Interrupt Priority Level - bit 4
SSCEIC.ILVL_3     3   Interrupt Priority Level - bit 3
SSCEIC.ILVL_2     2   Interrupt Priority Level - bit 2
SSCEIC.GLVL_1     1   Group Level - bit 1
SSCEIC.GLVL_0     0   Group Level - bit 0
CC8IC            0xFF88   CAPCOM Register 8 Interrupt Control Register
CC8IC.CC8IR       7   Interrupt Request Flag
CC8IC.CC8IE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC8IC.ILVL_5      5   Interrupt Priority Level - bit 5
CC8IC.ILVL_4      4   Interrupt Priority Level - bit 4
CC8IC.ILVL_3      3   Interrupt Priority Level - bit 3
CC8IC.ILVL_2      2   Interrupt Priority Level - bit 2
CC8IC.GLVL_1      1   Group Level - bit 1
CC8IC.GLVL_0      0   Group Level - bit 0
CC9IC            0xFF8A   CAPCOM Register 9 Interrupt Control Register
CC9IC.CC9IR       7   Interrupt Request Flag
CC9IC.CC9IE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC9IC.ILVL_5      5   Interrupt Priority Level - bit 5
CC9IC.ILVL_4      4   Interrupt Priority Level - bit 4
CC9IC.ILVL_3      3   Interrupt Priority Level - bit 3
CC9IC.ILVL_2      2   Interrupt Priority Level - bit 2
CC9IC.GLVL_1      1   Group Level - bit 1
CC9IC.GLVL_0      0   Group Level - bit 0
CC10IC           0xFF8C   CAPCOM Register 10 Interrupt Control Register
CC10IC.CC10IR     7   Interrupt Request Flag
CC10IC.CC10IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC10IC.ILVL_5     5   Interrupt Priority Level - bit 5
CC10IC.ILVL_4     4   Interrupt Priority Level - bit 4
CC10IC.ILVL_3     3   Interrupt Priority Level - bit 3
CC10IC.ILVL_2     2   Interrupt Priority Level - bit 2
CC10IC.GLVL_1     1   Group Level - bit 1
CC10IC.GLVL_0     0   Group Level - bit 0
CC11IC           0xFF8E   CAPCOM Register 11 Interrupt Control Register
CC11IC.CC11IR     7   Interrupt Request Flag
CC11IC.CC11IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC11IC.ILVL_5     5   Interrupt Priority Level - bit 5
CC11IC.ILVL_4     4   Interrupt Priority Level - bit 4
CC11IC.ILVL_3     3   Interrupt Priority Level - bit 3
CC11IC.ILVL_2     2   Interrupt Priority Level - bit 2
CC11IC.GLVL_1     1   Group Level - bit 1
CC11IC.GLVL_0     0   Group Level - bit 0
CC12IC           0xFF90   External Interrupt 4 Control Register
CC12IC.CC12IR     7   Interrupt Request Flag
CC12IC.CC12IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC12IC.ILVL_5     5   Interrupt Priority Level - bit 5
CC12IC.ILVL_4     4   Interrupt Priority Level - bit 4
CC12IC.ILVL_3     3   Interrupt Priority Level - bit 3
CC12IC.ILVL_2     2   Interrupt Priority Level - bit 2
CC12IC.GLVL_1     1   Group Level - bit 1
CC12IC.GLVL_0     0   Group Level - bit 0
CC13IC           0xFF92   External Interrupt 5 Control Register
CC13IC.CC13IR     7   Interrupt Request Flag
CC13IC.CC13IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC13IC.ILVL_5     5   Interrupt Priority Level - bit 5
CC13IC.ILVL_4     4   Interrupt Priority Level - bit 4
CC13IC.ILVL_3     3   Interrupt Priority Level - bit 3
CC13IC.ILVL_2     2   Interrupt Priority Level - bit 2
CC13IC.GLVL_1     1   Group Level - bit 1
CC13IC.GLVL_0     0   Group Level - bit 0
CC14IC           0xFF94   External Interrupt 6 Control Register
CC14IC.CC14IR     7   Interrupt Request Flag
CC14IC.CC14IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC14IC.ILVL_5     5   Interrupt Priority Level - bit 5
CC14IC.ILVL_4     4   Interrupt Priority Level - bit 4
CC14IC.ILVL_3     3   Interrupt Priority Level - bit 3
CC14IC.ILVL_2     2   Interrupt Priority Level - bit 2
CC14IC.GLVL_1     1   Group Level - bit 1
CC14IC.GLVL_0     0   Group Level - bit 0
CC15IC           0xFF96   External Interrupt 7 Control Register
CC15IC.CC15IR     7   Interrupt Request Flag
CC15IC.CC15IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CC15IC.ILVL_5     5   Interrupt Priority Level - bit 5
CC15IC.ILVL_4     4   Interrupt Priority Level - bit 4
CC15IC.ILVL_3     3   Interrupt Priority Level - bit 3
CC15IC.ILVL_2     2   Interrupt Priority Level - bit 2
CC15IC.GLVL_1     1   Group Level - bit 1
CC15IC.GLVL_0     0   Group Level - bit 0
ADCIC            0xFF98   A/D Converter End of Conversion Interrupt Control Register
ADCIC.ADCIR       7   Interrupt Request Flag
ADCIC.ADCIE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
ADCIC.ILVL_5      5   Interrupt Priority Level - bit 5
ADCIC.ILVL_4      4   Interrupt Priority Level - bit 4
ADCIC.ILVL_3      3   Interrupt Priority Level - bit 3
ADCIC.ILVL_2      2   Interrupt Priority Level - bit 2
ADCIC.GLVL_1      1   Group Level - bit 1
ADCIC.GLVL_0      0   Group Level - bit 0
ADEIC            0xFF9A   A/D Converter Overrun Error Interrupt Control Register
ADEIC.ADEIR       7   Interrupt Request Flag
ADEIC.ADEIE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
ADEIC.ILVL_5      5   Interrupt Priority Level - bit 5
ADEIC.ILVL_4      4   Interrupt Priority Level - bit 4
ADEIC.ILVL_3      3   Interrupt Priority Level - bit 3
ADEIC.ILVL_2      2   Interrupt Priority Level - bit 2
ADEIC.GLVL_1      1   Group Level - bit 1
ADEIC.GLVL_0      0   Group Level - bit 0
ADCON            0xFFA0   A/D Converter Control Register
ADCON.ADCTC_15    15  ADC Conversion Time Control - bit 15
ADCON.ADCTC_14    14  ADC Conversion Time Control - bit 14
ADCON.ADBSY       8   ADC Busy Flag
ADCON.ADST        7   ADC Start Bit
ADCON.ADRP        6   ADC Result Position
ADCON.ADM         4   ADC Mode Selection
ADCON.ADCH_1      1   ADC Analog Channel Input Selection - bit 1
ADCON.ADCH_0      0   ADC Analog Channel Input Selection - bit 0
P5               0xFFA2   Port 5 Register (read only)
P5.P5_15          15  Port data register P5 bit 15
P5.P5_14          14  Port data register P5 bit 14
P5.P5_3           3   Port data register P5 bit 3 
P5.P5_2           2   Port data register P5 bit 2 
P5.P5_1           1   Port data register P5 bit 1 
P5.P5_0           0   Port data register P5 bit 0 
P5DIDIS          0xFFA4   Port 5 Digital Input Disable Register
P5DIDIS.P5D_3     3   Port 5 Bit 3  Digital Input Control
P5DIDIS.P5D_2     2   Port 5 Bit 2  Digital Input Control
P5DIDIS.P5D_1     1   Port 5 Bit 1  Digital Input Control
P5DIDIS.P5D_0     0   Port 5 Bit 0  Digital Input Control
TFR              0xFFAC   Trap Flag Register
TFR.NMI           15  Non Maskable Interrupt Flag
TFR.STKOF         14  Stack Overflow Flag
TFR.STKUF         13  Stack Underflow Flag
TFR.UNDOPC        7   Undefined Opcode Flag
TFR.PRTFLT        3   Protection Fault Flag
TFR.ILLOPA        2   Illegal Word Operand Access Flag
TFR.ILLINA        1   Illegal Instruction Access Flag
TFR.ILLBUS        0   Illegal External Bus Access Flag
WDTCON           0xFFAE   Watchdog Timer Control Register
WDTCON.WDTREL_15  15  Watchdog Timer Reload Value - bit 15
WDTCON.WDTREL_14  14  Watchdog Timer Reload Value - bit 14
WDTCON.WDTREL_13  13  Watchdog Timer Reload Value - bit 13
WDTCON.WDTREL_12  12  Watchdog Timer Reload Value - bit 12
WDTCON.WDTREL_11  11  Watchdog Timer Reload Value - bit 11
WDTCON.WDTREL_10  10  Watchdog Timer Reload Value - bit 10
WDTCON.WDTREL_9   9   Watchdog Timer Reload Value - bit 9 
WDTCON.WDTREL_8   8   Watchdog Timer Reload Value - bit 8 
WDTCON.LHWR       4   Long Hardware Reset Indication Flag
WDTCON.SHWR       3   Short Hardware Reset Indication Flag
WDTCON.SWR        2   Software Reset Indication Flag
WDTCON.WDTR       1   Watchdog Timer Reset Indication Flag
WDTCON.WDTIN      0   Watchdog Timer Input Frequency Select
S0CON            0xFFB0   Serial Channel 0 Control Register
S0CON.S0R         15  Baudrate Generator Run Bit
S0CON.S0LB        14  LoopBack Mode Enable Bit
S0CON.S0BRS       13  Baudrate Selection Bit
S0CON.S0ODD       12  Parity Selection Bit
S0CON.S0OE        10  Overrun Error Flag
S0CON.S0FE        9   Framing Error Flag
S0CON.S0PE        8   Parity Error Flag
S0CON.S0OEN       7   Overrun Check Enable Bit
S0CON.S0FEN       6   Framing Check Enable Bit
S0CON.S0PEN       5   Parity Check Enable Bit
S0CON.S0REN       4   Receiver Enable Bit
S0CON.S0STP       3   Number of Stop Bits Selection
S0CON.S0M_2       2   ASC0 Mode Control - bit 2
S0CON.S0M_1       1   ASC0 Mode Control - bit 1
S0CON.S0M_0       0   ASC0 Mode Control - bit 0
SSCCON           0xFFB2   SSC Control Register
P2               0xFFC0   Port 2 Register
P2.P2_15          15  Port data register P2 bit 15
P2.P2_14          14  Port data register P2 bit 14
P2.P2_13          13  Port data register P2 bit 13
P2.P2_12          12  Port data register P2 bit 12
P2.P2_11          11  Port data register P2 bit 11
P2.P2_10          10  Port data register P2 bit 10
P2.P2_9           9   Port data register P2 bit 9 
P2.P2_8           8   Port data register P2 bit 8 
DP2              0xFFC2   Port 2 Direction Control Register
DP2.DP2_15        15  Port direction register DP2 bit 15
DP2.DP2_14        14  Port direction register DP2 bit 14
DP2.DP2_13        13  Port direction register DP2 bit 13
DP2.DP2_12        12  Port direction register DP2 bit 12
DP2.DP2_11        11  Port direction register DP2 bit 11
DP2.DP2_10        10  Port direction register DP2 bit 10
DP2.DP2_9         9   Port direction register DP2 bit 9 
DP2.DP2_8         8   Port direction register DP2 bit 8 
P3               0xFFC4   Port 3 Register
P3.P3_15          15  Port data register P3 bit 15
P3.P3_13          13  Port data register P3 bit 13
P3.P3_12          12  Port data register P3 bit 12
P3.P3_11          11  Port data register P3 bit 11
P3.P3_10          10  Port data register P3 bit 10
P3.P3_9           9   Port data register P3 bit 9 
P3.P3_8           8   Port data register P3 bit 8 
P3.P3_7           7   Port data register P3 bit 7 
P3.P3_6           6   Port data register P3 bit 6 
P3.P3_5           5   Port data register P3 bit 5 
P3.P3_4           4   Port data register P3 bit 4 
P3.P3_3           3   Port data register P3 bit 3 
P3.P3_2           2   Port data register P3 bit 2 
P3.P3_1           1   Port data register P3 bit 1 
P3.P3_0           0   Port data register P3 bit 0 
DP3              0xFFC6   Port 3 Direction Control Register
DP3.DP3_15        15  Port direction register DP3 bit 15
DP3.DP3_13        13  Port direction register DP3 bit 13
DP3.DP3_12        12  Port direction register DP3 bit 12
DP3.DP3_11        11  Port direction register DP3 bit 11
DP3.DP3_10        10  Port direction register DP3 bit 10
DP3.DP3_9         9   Port direction register DP3 bit 9 
DP3.DP3_8         8   Port direction register DP3 bit 8 
DP3.DP3_7         7   Port direction register DP3 bit 7 
DP3.DP3_6         6   Port direction register DP3 bit 6 
DP3.DP3_5         5   Port direction register DP3 bit 5 
DP3.DP3_4         4   Port direction register DP3 bit 4 
DP3.DP3_3         3   Port direction register DP3 bit 3 
DP3.DP3_2         2   Port direction register DP3 bit 2 
DP3.DP3_1         1   Port direction register DP3 bit 1 
DP3.DP3_0         0   Port direction register DP3 bit 0 
P4               0xFFC8   Port 4 Register (8 bits)
P4.P4_6           6   Port data register P4 bit 6 
P4.P4_5           5   Port data register P4 bit 5 
P4.P4_4           4   Port data register P4 bit 4 
P4.P4_3           3   Port data register P4 bit 3 
P4.P4_2           2   Port data register P4 bit 2 
P4.P4_1           1   Port data register P4 bit 1 
P4.P4_0           0   Port data register P4 bit 0 
DP4              0xFFCA   Port 4 Direction Control Register
DP4.DP4_6         6   Port direction register DP4 bit 6 
DP4.DP4_5         5   Port direction register DP4 bit 5 
DP4.DP4_4         4   Port direction register DP4 bit 4 
DP4.DP4_3         3   Port direction register DP4 bit 3 
DP4.DP4_2         2   Port direction register DP4 bit 2 
DP4.DP4_1         1   Port direction register DP4 bit 1 
DP4.DP4_0         0   Port direction register DP4 bit 0 
P6               0xFFCC   Port 6 Register (8 bits)
P6.P6_7           7   Port data register P6 bit 7 
P6.P6_6           6   Port data register P6 bit 6 
P6.P6_5           5   Port data register P6 bit 5 
P6.P6_4           4   Port data register P6 bit 4 
P6.P6_3           3   Port data register P6 bit 3 
P6.P6_2           2   Port data register P6 bit 2 
P6.P6_1           1   Port data register P6 bit 1 
P6.P6_0           0   Port data register P6 bit 0 
DP6              0xFFCE   Port 6 Direction Control Register
DP6.DP6_7         7   Port direction register DP6 bit 7 
DP6.DP6_6         6   Port direction register DP6 bit 6 
DP6.DP6_5         5   Port direction register DP6 bit 5 
DP6.DP6_4         4   Port direction register DP6 bit 4 
DP6.DP6_3         3   Port direction register DP6 bit 3 
DP6.DP6_2         2   Port direction register DP6 bit 2 
DP6.DP6_1         1   Port direction register DP6 bit 1 
DP6.DP6_0         0   Port direction register DP6 bit 0 


.C161U
; http://www.infineon.com/cgi/ecrm.dll/ecrm/scripts/public_download.jsp?oid=22600&parent_oid=13618


; MEMORY MAP
area DATA INT_PROG_MEM   0x0000:0x8000   Internal Program Memory Area
area BSS  RESERVED       0x8000:0xA000   Reserved for XFLASH
area BSS  RESERVED       0xA000:0xE000   Reserved for XRAM
area BSS  RESERVED       0xE000:0xE800   Reserved for Compatible XRAM
area BSS  RESERVED       0xE800:0xED00   Reserved for XPERs
area DATA EPEC           0xED00:0xED70   EPEC Register
area BSS  RESERVED       0xED70:0xEE00
area DATA USBD           0xEE00:0xEE72
area BSS  RESERVED       0xEE72:0xF000
area DATA E_SFR          0xF000:0xF200   ESFR Area
area DATA IRAM           0xF200:0xFE00   IRAM Area
area DATA SFR            0xFE00:0x10000  SFR Area 


; Interrupt and reset vector assignments
entry RESET     0x0000   RESET
entry NMITRAP   0x0008   NMITRAP Non-Maskable Interrupt (Class A Hardware Traps)
entry STOTRAP   0x0010   STOTRAP Stack Overflow (Class A Hardware Traps)
entry STUTRAP   0x0018   STUTRAP Stack Underflow (Class A Hardware Traps)
entry DEBTRAP   0x0020   Debug Trap
entry BTRAP     0x0028   BTRAP Class B Hardware Traps
entry URD3INT   0x0040   UDC RX Done3
entry URD4INT   0x0044   UDC RX Done4
entry URD5INT   0x0048   UDC RX Done5
entry URD6INT   0x004C   UDC RX Done6
entry URD7INT   0x0050   UDC RX Done7
entry UTD0INT   0x0054   UDC TX Done0
entry UTD1INT   0x0058   UDC TX Done1
entry UTD2INT   0x005C   UDC TX Done2
entry EX0INT    0x0060   Fast ext. Interrupt
entry EX1INT    0x0064   Fast ext. Interrupt
entry EX2INT    0x0068   Fast ext. Interrupt
entry EX3INT    0x006C   Fast ext. Interrupt
entry EX4INT    0x0070   Fast ext. Interrupt
entry EX5INT    0x0074   Fast ext. Interrupt
entry EX6INT    0x0078   Fast ext. Interrupt
entry EX7INT    0x007C   Fast ext. Interrupt
entry URD2INT   0x0080   UDC RX Done2
entry URD1INT   0x0084   UDC RX Done1
entry T2INT     0x0088   GPT Timer 2
entry T3INT     0x008C   GPT Timer 3
entry T4INT     0x0090   GPT Timer 4
entry T5INT     0x0094   GPT Timer 5
entry T6INT     0x0098   GPT Timer 6
entry CRINT     0x009C   GPT CAPREL Register
entry S0TINT    0x00A8   ASC Transmit
entry S0RINT    0x00AC   ASC Receive
entry S0EINT    0x00B0   ASC Error
entry SSCTINT   0x00B4   SSC Transmit
entry SSCRINT   0x00B8   SSC Receive
entry SSCEINT   0x00BC   SSC Error
entry UTD3INT   0x00C0   UDC TX Done3
entry UTD4INT   0x00C4   UDC TX Done4
entry UTD5INT   0x00C8   UDC TX Done5
entry UTD6INT   0x00CC   UDC TX Done6
entry UTD7INT   0x00D0   UDC TX Done7
entry URXRINT   0x00D4   UDC RXRR
entry UTXRINT   0x00D8   UDC TXWR
entry UCFGVINT  0x00DC   UDC Config Val
entry USOFINT   0x00E0   UDC Start of Frame
entry USSOINT   0x00E4   UDC Suspend off
entry USSINT    0x00E8   UDC Suspend
entry ULCDINT   0x00EC   UDC Load Config Done
entry USETINT   0x00F0   UDC SETUP
entry URD0INT   0x00F4   UDC RX Done0
entry EPECINT   0x00F8   EPEC
entry UTXRINT   0x0100   UDC TXWR
entry EPECINT   0x0104   EPEC
entry XP3INT    0x010C   internal PLL Lock / RTC
entry RTC_INT   0x0110   rRTC Interrupt
entry ABENDINT  0x0114   ASC Autobaud End
entry ABSTINT   0x0118   ASC Autobaud Start
entry S0TBINT   0x011C   ASC Transmit Buffer
entry CLISNINT  0x0130   CLISN Interrupt


; INPUT/OUTPUT PORTS
; R0   F0H General Purpose Register 0
; R0   F0H General Purpose Register 0
; R1   F1H General Purpose Register 1
; R1   F1H General Purpose Register 1
; R10  FAH General Purpose Register 10
; R10  FAH General Purpose Register 10
; R11  FBH General Purpose Register 11
; R11  FBH General Purpose Register 11
; R12  FCH General Purpose Register 12
; R12  FCH General Purpose Register 12
; R13  FDH General Purpose Register 13
; R13  FDH General Purpose Register 13
; R14  FEH General Purpose Register 14
; R14  FEH General Purpose Register 14
; R15  FFH General Purpose Register 15
; R15  FFH General Purpose Register 15
; R2   F2H General Purpose Register 2
; R2   F2H General Purpose Register 2
; R3   F3H General Purpose Register 3
; R3   F3H General Purpose Register 3
; R4   F4H General Purpose Register 4
; R4   F4H General Purpose Register 4
; R5   F5H General Purpose Register 5
; R5   F5H General Purpose Register 5
; R6   F6H General Purpose Register 6
; R6   F6H General Purpose Register 6
; R7   F7H General Purpose Register 7
; R7   F7H General Purpose Register 7
; R8   F8H General Purpose Register 8
; R8   F8H General Purpose Register 8
; R9   F9H General Purpose Register 9
; R9   F9H General Purpose Register 9

; EPEC Registers
EPECCLC                    0xED00   EPEC Clock Control Register
EPECCLC.EPECEX_DIS          3   EPEC Controller Clock Disable
EPECCLC.EPECGPSEN           2   EPEC Controller Clock OCDS Disable
EPECCLC.EPECDIS             1   EPEC Controller Clock Status
EPECCLC.EPECDISR            0   EPEC Controller Clock Disable
EPECID                     0xED08   EPEC Identification Register
EPECID.ID_15                15  EPEC Identification Register - bit 15
EPECID.ID_14                14  EPEC Identification Register - bit 14
EPECID.ID_13                13  EPEC Identification Register - bit 13
EPECID.ID_12                12  EPEC Identification Register - bit 12
EPECID.ID_11                11  EPEC Identification Register - bit 11
EPECID.ID_10                10  EPEC Identification Register - bit 10
EPECID.ID_9                 9   EPEC Identification Register - bit 9 
EPECID.ID_8                 8   EPEC Identification Register - bit 8 
EPECID.ID_7                 7   EPEC Identification Register - bit 7 
EPECID.ID_6                 6   EPEC Identification Register - bit 6 
EPECID.ID_5                 5   EPEC Identification Register - bit 5 
EPECID.ID_4                 4   EPEC Identification Register - bit 4 
EPECID.ID_3                 3   EPEC Identification Register - bit 3 
EPECID.ID_2                 2   EPEC Identification Register - bit 2 
EPECID.ID_1                 1   EPEC Identification Register - bit 1 
EPECID.ID_0                 0   EPEC Identification Register - bit 0 
EPEC_SPTR_IN_R00           0xED10   16 LSBs of USB endpoint#0 source pointer IN
EPEC_SPTR_IN_R01           0xED12   8 MSBs of USB endpoint#0 source pointer IN
EPEC_SPTR_OUT_R00          0xED14   16 LSBs of USB endpoint#0 source pointer OUT
EPEC_SPTR_OUT_R01          0xED16   8 MSBs of USB endpoint#0 source pointer OUT
EPEC_SPTR_REG10            0xED18   16 LSBs of USB endpoint#1 source pointer
EPEC_SPTR_REG11            0xED1A   8 MSBs of USB endpoint#1 source pointer
EPEC_SPTR_REG20            0xED1C   16 LSBs of USB endpoint#2 source pointer
EPEC_SPTR_REG21            0xED1E   8 MSBs of USB endpoint#2 source pointer
EPEC_SPTR_REG30            0xED20   16 LSBs of USB endpoint#3 source pointer
EPEC_SPTR_REG31            0xED22   8 MSBs of USB endpoint#3 source pointer
EPEC_SPTR_REG40            0xED24   16 LSBs of USB endpoint#4 source pointer
EPEC_SPTR_REG41            0xED26   8 MSBs of USB endpoint#4 source pointer
EPEC_SPTR_REG50            0xED28   16 LSBs of USB endpoint#5 source pointer
EPEC_SPTR_REG51            0xED2A   8 MSBs of USB endpoint#5 source pointer
EPEC_SPTR_REG60            0xED2C   16 LSBs of USB endpoint#6 source pointer
EPEC_SPTR_REG61            0xED2E   8 MSBs of USB endpoint#6 source pointer
EPEC_SPTR_REG70            0xED30   16 LSBs of USB endpoint#7 source pointer
EPEC_SPTR_REG71            0xED32   8 MSBs of USB endpoint#7 source pointer
EPEC_DPTR_IN_R00           0xED34   16 LSBs of USB endpoint#0 destination pointer IN
EPEC_DPTR_IN_R01           0xED36   8 MSBs of USB endpoint#0 destination pointer IN
EPEC_DPTR_OUT_R00          0xED38   16 LSBs of USB endpoint#0 destination pointer OUT
EPEC_DPTR_OUT_R01          0xED3A   8 MSBs of USB endpoint#0 destination pointer OUT
EPEC_DPTR_REG10            0xED3C   16 LSBs of USB endpoint#1 destination pointer
EPEC_DPTR_REG10.DPTR15      15
EPEC_DPTR_REG10.DPTR14      14
EPEC_DPTR_REG10.DPTR13      13
EPEC_DPTR_REG10.DPTR12      12
EPEC_DPTR_REG10.DPTR11      11
EPEC_DPTR_REG10.DPTR10      10
EPEC_DPTR_REG10.DPTR9       9 
EPEC_DPTR_REG10.DPTR8       8 
EPEC_DPTR_REG10.DPTR7       7 
EPEC_DPTR_REG10.DPTR6       6 
EPEC_DPTR_REG10.DPTR5       5 
EPEC_DPTR_REG10.DPTR4       4 
EPEC_DPTR_REG10.DPTR3       3 
EPEC_DPTR_REG10.DPTR2       2 
EPEC_DPTR_REG10.DPTR1       1 
EPEC_DPTR_REG10.DPTR0       0 
EPEC_DPTR_REG11            0xED3E   8 MSBs of USB endpoint#1 destination pointer
EPEC_DPTR_REG11.DPTR7       7
EPEC_DPTR_REG11.DPTR6       6
EPEC_DPTR_REG11.DPTR5       5
EPEC_DPTR_REG11.DPTR4       4
EPEC_DPTR_REG11.DPTR3       3
EPEC_DPTR_REG11.DPTR2       2
EPEC_DPTR_REG11.DPTR1       1
EPEC_DPTR_REG11.DPTR0       0
EPEC_DPTR_REG20            0xED40   16 LSBs of USB endpoint#2 destination pointer
EPEC_DPTR_REG20.DPTR15      15
EPEC_DPTR_REG20.DPTR14      14
EPEC_DPTR_REG20.DPTR13      13
EPEC_DPTR_REG20.DPTR12      12
EPEC_DPTR_REG20.DPTR11      11
EPEC_DPTR_REG20.DPTR10      10
EPEC_DPTR_REG20.DPTR9       9 
EPEC_DPTR_REG20.DPTR8       8 
EPEC_DPTR_REG20.DPTR7       7 
EPEC_DPTR_REG20.DPTR6       6 
EPEC_DPTR_REG20.DPTR5       5 
EPEC_DPTR_REG20.DPTR4       4 
EPEC_DPTR_REG20.DPTR3       3 
EPEC_DPTR_REG20.DPTR2       2 
EPEC_DPTR_REG20.DPTR1       1 
EPEC_DPTR_REG20.DPTR0       0 
EPEC_DPTR_REG21            0xED42   8 MSBs of USB endpoint#2 destination pointer
EPEC_DPTR_REG21.DPTR7       7
EPEC_DPTR_REG21.DPTR6       6
EPEC_DPTR_REG21.DPTR5       5
EPEC_DPTR_REG21.DPTR4       4
EPEC_DPTR_REG21.DPTR3       3
EPEC_DPTR_REG21.DPTR2       2
EPEC_DPTR_REG21.DPTR1       1
EPEC_DPTR_REG21.DPTR0       0
EPEC_DPTR_REG30            0xED44   16 LSBs of USB endpoint#3 destination pointer
EPEC_DPTR_REG30.DPTR15      15
EPEC_DPTR_REG30.DPTR14      14
EPEC_DPTR_REG30.DPTR13      13
EPEC_DPTR_REG30.DPTR12      12
EPEC_DPTR_REG30.DPTR11      11
EPEC_DPTR_REG30.DPTR10      10
EPEC_DPTR_REG30.DPTR9       9 
EPEC_DPTR_REG30.DPTR8       8 
EPEC_DPTR_REG30.DPTR7       7 
EPEC_DPTR_REG30.DPTR6       6 
EPEC_DPTR_REG30.DPTR5       5 
EPEC_DPTR_REG30.DPTR4       4 
EPEC_DPTR_REG30.DPTR3       3 
EPEC_DPTR_REG30.DPTR2       2 
EPEC_DPTR_REG30.DPTR1       1 
EPEC_DPTR_REG30.DPTR0       0 
EPEC_DPTR_REG31            0xED46   8 MSBs of USB endpoint#3 destination pointer
EPEC_DPTR_REG31.DPTR7       7
EPEC_DPTR_REG31.DPTR6       6
EPEC_DPTR_REG31.DPTR5       5
EPEC_DPTR_REG31.DPTR4       4
EPEC_DPTR_REG31.DPTR3       3
EPEC_DPTR_REG31.DPTR2       2
EPEC_DPTR_REG31.DPTR1       1
EPEC_DPTR_REG31.DPTR0       0
EPEC_DPTR_REG40            0xED48   16 LSBs of USB endpoint#4 destination pointer
EPEC_DPTR_REG40.DPTR15      15
EPEC_DPTR_REG40.DPTR14      14
EPEC_DPTR_REG40.DPTR13      13
EPEC_DPTR_REG40.DPTR12      12
EPEC_DPTR_REG40.DPTR11      11
EPEC_DPTR_REG40.DPTR10      10
EPEC_DPTR_REG40.DPTR9       9 
EPEC_DPTR_REG40.DPTR8       8 
EPEC_DPTR_REG40.DPTR7       7 
EPEC_DPTR_REG40.DPTR6       6 
EPEC_DPTR_REG40.DPTR5       5 
EPEC_DPTR_REG40.DPTR4       4 
EPEC_DPTR_REG40.DPTR3       3 
EPEC_DPTR_REG40.DPTR2       2 
EPEC_DPTR_REG40.DPTR1       1 
EPEC_DPTR_REG40.DPTR0       0 
EPEC_DPTR_REG41            0xED4A   8 MSBs of USB endpoint#4 destination pointer
EPEC_DPTR_REG41.DPTR7       7
EPEC_DPTR_REG41.DPTR6       6
EPEC_DPTR_REG41.DPTR5       5
EPEC_DPTR_REG41.DPTR4       4
EPEC_DPTR_REG41.DPTR3       3
EPEC_DPTR_REG41.DPTR2       2
EPEC_DPTR_REG41.DPTR1       1
EPEC_DPTR_REG41.DPTR0       0
EPEC_DPTR_REG50            0xED4C   16 LSBs of USB endpoint#5 destination pointer
EPEC_DPTR_REG50.DPTR15      15
EPEC_DPTR_REG50.DPTR14      14
EPEC_DPTR_REG50.DPTR13      13
EPEC_DPTR_REG50.DPTR12      12
EPEC_DPTR_REG50.DPTR11      11
EPEC_DPTR_REG50.DPTR10      10
EPEC_DPTR_REG50.DPTR9       9 
EPEC_DPTR_REG50.DPTR8       8 
EPEC_DPTR_REG50.DPTR7       7 
EPEC_DPTR_REG50.DPTR6       6 
EPEC_DPTR_REG50.DPTR5       5 
EPEC_DPTR_REG50.DPTR4       4 
EPEC_DPTR_REG50.DPTR3       3 
EPEC_DPTR_REG50.DPTR2       2 
EPEC_DPTR_REG50.DPTR1       1 
EPEC_DPTR_REG50.DPTR0       0 
EPEC_DPTR_REG51            0xED4E   8 MSBs of USB endpoint#5 destination pointer
EPEC_DPTR_REG51.DPTR7       7
EPEC_DPTR_REG51.DPTR6       6
EPEC_DPTR_REG51.DPTR5       5
EPEC_DPTR_REG51.DPTR4       4
EPEC_DPTR_REG51.DPTR3       3
EPEC_DPTR_REG51.DPTR2       2
EPEC_DPTR_REG51.DPTR1       1
EPEC_DPTR_REG51.DPTR0       0
EPEC_DPTR_REG60            0xED50   16 LSBs of USB endpoint#6 destination pointer
EPEC_DPTR_REG60.DPTR15      15
EPEC_DPTR_REG60.DPTR14      14
EPEC_DPTR_REG60.DPTR13      13
EPEC_DPTR_REG60.DPTR12      12
EPEC_DPTR_REG60.DPTR11      11
EPEC_DPTR_REG60.DPTR10      10
EPEC_DPTR_REG60.DPTR9       9 
EPEC_DPTR_REG60.DPTR8       8 
EPEC_DPTR_REG60.DPTR7       7 
EPEC_DPTR_REG60.DPTR6       6 
EPEC_DPTR_REG60.DPTR5       5 
EPEC_DPTR_REG60.DPTR4       4 
EPEC_DPTR_REG60.DPTR3       3 
EPEC_DPTR_REG60.DPTR2       2 
EPEC_DPTR_REG60.DPTR1       1 
EPEC_DPTR_REG60.DPTR0       0 
EPEC_DPTR_REG61            0xED52   8 MSBs of USB endpoint#6 destination pointer
EPEC_DPTR_REG61.DPTR7       7
EPEC_DPTR_REG61.DPTR6       6
EPEC_DPTR_REG61.DPTR5       5
EPEC_DPTR_REG61.DPTR4       4
EPEC_DPTR_REG61.DPTR3       3
EPEC_DPTR_REG61.DPTR2       2
EPEC_DPTR_REG61.DPTR1       1
EPEC_DPTR_REG61.DPTR0       0
EPEC_DPTR_REG70            0xED54   16 LSBs of USB endpoint#7 destination pointer
EPEC_DPTR_REG70.DPTR15      15
EPEC_DPTR_REG70.DPTR14      14
EPEC_DPTR_REG70.DPTR13      13
EPEC_DPTR_REG70.DPTR12      12
EPEC_DPTR_REG70.DPTR11      11
EPEC_DPTR_REG70.DPTR10      10
EPEC_DPTR_REG70.DPTR9       9 
EPEC_DPTR_REG70.DPTR8       8 
EPEC_DPTR_REG70.DPTR7       7 
EPEC_DPTR_REG70.DPTR6       6 
EPEC_DPTR_REG70.DPTR5       5 
EPEC_DPTR_REG70.DPTR4       4 
EPEC_DPTR_REG70.DPTR3       3 
EPEC_DPTR_REG70.DPTR2       2 
EPEC_DPTR_REG70.DPTR1       1 
EPEC_DPTR_REG70.DPTR0       0 
EPEC_DPTR_REG71            0xED56   8 MSBs of USB endpoint#7 destination pointer
EPEC_DPTR_REG71.DPTR7       7
EPEC_DPTR_REG71.DPTR6       6
EPEC_DPTR_REG71.DPTR5       5
EPEC_DPTR_REG71.DPTR4       4
EPEC_DPTR_REG71.DPTR3       3
EPEC_DPTR_REG71.DPTR2       2
EPEC_DPTR_REG71.DPTR1       1
EPEC_DPTR_REG71.DPTR0       0
EPEC_CTRL_IN_R0            0xED58   Control and Status register for USB endpoint#0 IN
EPEC_CTRL_OUT_R0           0xED5A   Control and Status register for USB endpoint#0 OUT
EPEC_CTRL_REG1             0xED5C   Control and Status register for USB endpoint#1
EPEC_CTRL_REG1.TXR_ENA1     15  Transfer / Receive Enable control bit
EPEC_CTRL_REG1.EXT_SRC      14   External Source
EPEC_CTRL_REG1.REQ_SRC_13   13  EPEC request sourceRX/TX Fifo - bit
EPEC_CTRL_REG1.REQ_SRC_12   12  EPEC request sourceRX/TX Fifo - bit
EPEC_CTRL_REG1.CNT_UP_DN    11  Byte Counter direction select
EPEC_CTRL_REG1.CLR          10  Clear EPEC channel
EPEC_CTRL_REG1.BYTE_CNT_9   9   Number of bytes to be transmitted - bit 9
EPEC_CTRL_REG1.BYTE_CNT_8   8   Number of bytes to be transmitted - bit 8
EPEC_CTRL_REG1.BYTE_CNT_7   7   Number of bytes to be transmitted - bit 7
EPEC_CTRL_REG1.BYTE_CNT_6   6   Number of bytes to be transmitted - bit 6
EPEC_CTRL_REG1.BYTE_CNT_5   5   Number of bytes to be transmitted - bit 5
EPEC_CTRL_REG1.BYTE_CNT_4   4   Number of bytes to be transmitted - bit 4
EPEC_CTRL_REG1.BYTE_CNT_3   3   Number of bytes to be transmitted - bit 3
EPEC_CTRL_REG1.BYTE_CNT_2   2   Number of bytes to be transmitted - bit 2
EPEC_CTRL_REG1.BYTE_CNT_1   1   Number of bytes to be transmitted - bit 1
EPEC_CTRL_REG1.BYTE_CNT_0   0   Number of bytes to be transmitted - bit 0
EPEC_CTRL_REG2             0xED5E   Control and Status register for USB endpoint#2
EPEC_CTRL_REG2.TXR_ENA1     15  Transfer / Receive Enable control bit
EPEC_CTRL_REG2.EXT_SRC      14   External Source
EPEC_CTRL_REG2.REQ_SRC_13   13  EPEC request sourceRX/TX Fifo - bit
EPEC_CTRL_REG2.REQ_SRC_12   12  EPEC request sourceRX/TX Fifo - bit
EPEC_CTRL_REG2.CNT_UP_DN    11  Byte Counter direction select
EPEC_CTRL_REG2.CLR          10  Clear EPEC channel
EPEC_CTRL_REG2.BYTE_CNT_9   9   Number of bytes to be transmitted - bit 9
EPEC_CTRL_REG2.BYTE_CNT_8   8   Number of bytes to be transmitted - bit 8
EPEC_CTRL_REG2.BYTE_CNT_7   7   Number of bytes to be transmitted - bit 7
EPEC_CTRL_REG2.BYTE_CNT_6   6   Number of bytes to be transmitted - bit 6
EPEC_CTRL_REG2.BYTE_CNT_5   5   Number of bytes to be transmitted - bit 5
EPEC_CTRL_REG2.BYTE_CNT_4   4   Number of bytes to be transmitted - bit 4
EPEC_CTRL_REG2.BYTE_CNT_3   3   Number of bytes to be transmitted - bit 3
EPEC_CTRL_REG2.BYTE_CNT_2   2   Number of bytes to be transmitted - bit 2
EPEC_CTRL_REG2.BYTE_CNT_1   1   Number of bytes to be transmitted - bit 1
EPEC_CTRL_REG2.BYTE_CNT_0   0   Number of bytes to be transmitted - bit 0
EPEC_CTRL_REG3             0xED60   Control and Status register for USB endpoint#3
EPEC_CTRL_REG3.TXR_ENA1     15  Transfer / Receive Enable control bit
EPEC_CTRL_REG3.EXT_SRC      14   External Source
EPEC_CTRL_REG3.REQ_SRC_13   13  EPEC request sourceRX/TX Fifo - bit
EPEC_CTRL_REG3.REQ_SRC_12   12  EPEC request sourceRX/TX Fifo - bit
EPEC_CTRL_REG3.CNT_UP_DN    11  Byte Counter direction select
EPEC_CTRL_REG3.CLR          10  Clear EPEC channel
EPEC_CTRL_REG3.BYTE_CNT_9   9   Number of bytes to be transmitted - bit 9
EPEC_CTRL_REG3.BYTE_CNT_8   8   Number of bytes to be transmitted - bit 8
EPEC_CTRL_REG3.BYTE_CNT_7   7   Number of bytes to be transmitted - bit 7
EPEC_CTRL_REG3.BYTE_CNT_6   6   Number of bytes to be transmitted - bit 6
EPEC_CTRL_REG3.BYTE_CNT_5   5   Number of bytes to be transmitted - bit 5
EPEC_CTRL_REG3.BYTE_CNT_4   4   Number of bytes to be transmitted - bit 4
EPEC_CTRL_REG3.BYTE_CNT_3   3   Number of bytes to be transmitted - bit 3
EPEC_CTRL_REG3.BYTE_CNT_2   2   Number of bytes to be transmitted - bit 2
EPEC_CTRL_REG3.BYTE_CNT_1   1   Number of bytes to be transmitted - bit 1
EPEC_CTRL_REG3.BYTE_CNT_0   0   Number of bytes to be transmitted - bit 0
EPEC_CTRL_REG4             0xED62   Control and Status register for USB endpoint#4
EPEC_CTRL_REG4.TXR_ENA1     15  Transfer / Receive Enable control bit
EPEC_CTRL_REG4.EXT_SRC      14   External Source
EPEC_CTRL_REG4.REQ_SRC_13   13  EPEC request sourceRX/TX Fifo - bit
EPEC_CTRL_REG4.REQ_SRC_12   12  EPEC request sourceRX/TX Fifo - bit
EPEC_CTRL_REG4.CNT_UP_DN    11  Byte Counter direction select
EPEC_CTRL_REG4.CLR          10  Clear EPEC channel
EPEC_CTRL_REG4.BYTE_CNT_9   9   Number of bytes to be transmitted - bit 9
EPEC_CTRL_REG4.BYTE_CNT_8   8   Number of bytes to be transmitted - bit 8
EPEC_CTRL_REG4.BYTE_CNT_7   7   Number of bytes to be transmitted - bit 7
EPEC_CTRL_REG4.BYTE_CNT_6   6   Number of bytes to be transmitted - bit 6
EPEC_CTRL_REG4.BYTE_CNT_5   5   Number of bytes to be transmitted - bit 5
EPEC_CTRL_REG4.BYTE_CNT_4   4   Number of bytes to be transmitted - bit 4
EPEC_CTRL_REG4.BYTE_CNT_3   3   Number of bytes to be transmitted - bit 3
EPEC_CTRL_REG4.BYTE_CNT_2   2   Number of bytes to be transmitted - bit 2
EPEC_CTRL_REG4.BYTE_CNT_1   1   Number of bytes to be transmitted - bit 1
EPEC_CTRL_REG4.BYTE_CNT_0   0   Number of bytes to be transmitted - bit 0
EPEC_CTRL_REG5             0xED64   Control and Status register for USB endpoint#5
EPEC_CTRL_REG5.TXR_ENA1     15  Transfer / Receive Enable control bit
EPEC_CTRL_REG5.EXT_SRC      14   External Source
EPEC_CTRL_REG5.REQ_SRC_13   13  EPEC request sourceRX/TX Fifo - bit
EPEC_CTRL_REG5.REQ_SRC_12   12  EPEC request sourceRX/TX Fifo - bit
EPEC_CTRL_REG5.CNT_UP_DN    11  Byte Counter direction select
EPEC_CTRL_REG5.CLR          10  Clear EPEC channel
EPEC_CTRL_REG5.BYTE_CNT_9   9   Number of bytes to be transmitted - bit 9
EPEC_CTRL_REG5.BYTE_CNT_8   8   Number of bytes to be transmitted - bit 8
EPEC_CTRL_REG5.BYTE_CNT_7   7   Number of bytes to be transmitted - bit 7
EPEC_CTRL_REG5.BYTE_CNT_6   6   Number of bytes to be transmitted - bit 6
EPEC_CTRL_REG5.BYTE_CNT_5   5   Number of bytes to be transmitted - bit 5
EPEC_CTRL_REG5.BYTE_CNT_4   4   Number of bytes to be transmitted - bit 4
EPEC_CTRL_REG5.BYTE_CNT_3   3   Number of bytes to be transmitted - bit 3
EPEC_CTRL_REG5.BYTE_CNT_2   2   Number of bytes to be transmitted - bit 2
EPEC_CTRL_REG5.BYTE_CNT_1   1   Number of bytes to be transmitted - bit 1
EPEC_CTRL_REG5.BYTE_CNT_0   0   Number of bytes to be transmitted - bit 0
EPEC_CTRL_REG6             0xED66   Control and Status register for USB endpoint#6
EPEC_CTRL_REG6.TXR_ENA1     15  Transfer / Receive Enable control bit
EPEC_CTRL_REG6.EXT_SRC      14   External Source
EPEC_CTRL_REG6.REQ_SRC_13   13  EPEC request sourceRX/TX Fifo - bit
EPEC_CTRL_REG6.REQ_SRC_12   12  EPEC request sourceRX/TX Fifo - bit
EPEC_CTRL_REG6.CNT_UP_DN    11  Byte Counter direction select
EPEC_CTRL_REG6.CLR          10  Clear EPEC channel
EPEC_CTRL_REG6.BYTE_CNT_9   9   Number of bytes to be transmitted - bit 9
EPEC_CTRL_REG6.BYTE_CNT_8   8   Number of bytes to be transmitted - bit 8
EPEC_CTRL_REG6.BYTE_CNT_7   7   Number of bytes to be transmitted - bit 7
EPEC_CTRL_REG6.BYTE_CNT_6   6   Number of bytes to be transmitted - bit 6
EPEC_CTRL_REG6.BYTE_CNT_5   5   Number of bytes to be transmitted - bit 5
EPEC_CTRL_REG6.BYTE_CNT_4   4   Number of bytes to be transmitted - bit 4
EPEC_CTRL_REG6.BYTE_CNT_3   3   Number of bytes to be transmitted - bit 3
EPEC_CTRL_REG6.BYTE_CNT_2   2   Number of bytes to be transmitted - bit 2
EPEC_CTRL_REG6.BYTE_CNT_1   1   Number of bytes to be transmitted - bit 1
EPEC_CTRL_REG6.BYTE_CNT_0   0   Number of bytes to be transmitted - bit 0
EPEC_CTRL_REG7             0xED68   Control and Status register for USB endpoint#7
EPEC_CTRL_REG7.TXR_ENA1     15  Transfer / Receive Enable control bit
EPEC_CTRL_REG7.EXT_SRC      14   External Source
EPEC_CTRL_REG7.REQ_SRC_13   13  EPEC request sourceRX/TX Fifo - bit
EPEC_CTRL_REG7.REQ_SRC_12   12  EPEC request sourceRX/TX Fifo - bit
EPEC_CTRL_REG7.CNT_UP_DN    11  Byte Counter direction select
EPEC_CTRL_REG7.CLR          10  Clear EPEC channel
EPEC_CTRL_REG7.BYTE_CNT_9   9   Number of bytes to be transmitted - bit 9
EPEC_CTRL_REG7.BYTE_CNT_8   8   Number of bytes to be transmitted - bit 8
EPEC_CTRL_REG7.BYTE_CNT_7   7   Number of bytes to be transmitted - bit 7
EPEC_CTRL_REG7.BYTE_CNT_6   6   Number of bytes to be transmitted - bit 6
EPEC_CTRL_REG7.BYTE_CNT_5   5   Number of bytes to be transmitted - bit 5
EPEC_CTRL_REG7.BYTE_CNT_4   4   Number of bytes to be transmitted - bit 4
EPEC_CTRL_REG7.BYTE_CNT_3   3   Number of bytes to be transmitted - bit 3
EPEC_CTRL_REG7.BYTE_CNT_2   2   Number of bytes to be transmitted - bit 2
EPEC_CTRL_REG7.BYTE_CNT_1   1   Number of bytes to be transmitted - bit 1
EPEC_CTRL_REG7.BYTE_CNT_0   0   Number of bytes to be transmitted - bit 0
EPEC_INT_REG               0xED6A   EPEC Interrupt
EPEC_INT_REG.RxTxSTART_15   15  Rx / Tx Start - bit 15
EPEC_INT_REG.RxTxSTART_14   14  Rx / Tx Start - bit 14
EPEC_INT_REG.RxTxSTART_13   13  Rx / Tx Start - bit 13
EPEC_INT_REG.RxTxSTART_12   12  Rx / Tx Start - bit 12
EPEC_INT_REG.RxTxSTART_11   11  Rx / Tx Start - bit 11
EPEC_INT_REG.RxTxSTART_10   10  Rx / Tx Start - bit 10
EPEC_INT_REG.RxTxSTART_9    9   Rx / Tx Start - bit 9 
EPEC_INT_REG.RxTxSTART_8    8   Rx / Tx Start - bit 8 
EPEC_INT_REG.TXDONE_INT7    7   TX packet transfer completed by EPEC - bit 7
EPEC_INT_REG.TXDONE_INT6    6   TX packet transfer completed by EPEC - bit 6
EPEC_INT_REG.TXDONE_INT5    5   TX packet transfer completed by EPEC - bit 5
EPEC_INT_REG.TXDONE_INT4    4   TX packet transfer completed by EPEC - bit 4
EPEC_INT_REG.TXDONE_INT3    3   TX packet transfer completed by EPEC - bit 3
EPEC_INT_REG.TXDONE_INT2    2   TX packet transfer completed by EPEC - bit 2
EPEC_INT_REG.TXDONE_INT1    1   TX packet transfer completed by EPEC - bit 1
EPEC_INT_REG.TXDONE_INT0    0   TX packet transfer completed by EPEC - bit 0
EPEC_INTMSK_REG            0xED6C   EPEC Interrupt Mask Register
EPEC_INTMSK_REG.RxTxSTARTMSK_15 15 Rx / Tx Start Mask - bit 15
EPEC_INTMSK_REG.RxTxSTARTMSK_14 14 Rx / Tx Start Mask - bit 14
EPEC_INTMSK_REG.RxTxSTARTMSK_13 13 Rx / Tx Start Mask - bit 13
EPEC_INTMSK_REG.RxTxSTARTMSK_12 12 Rx / Tx Start Mask - bit 12
EPEC_INTMSK_REG.RxTxSTARTMSK_11 11 Rx / Tx Start Mask - bit 11
EPEC_INTMSK_REG.RxTxSTARTMSK_10 10 Rx / Tx Start Mask - bit 10
EPEC_INTMSK_REG.RxTxSTARTMSK_9  9  Rx / Tx Start Mask - bit 9 
EPEC_INTMSK_REG.RxTxSTARTMSK_8  8  Rx / Tx Start Mask - bit 8 
EPEC_INTMSK_REG.TXDONE_INTMSK7  7  Mask interrupt TX packet transfer completed by EPEC - bit 7
EPEC_INTMSK_REG.TXDONE_INTMSK6  6  Mask interrupt TX packet transfer completed by EPEC - bit 6
EPEC_INTMSK_REG.TXDONE_INTMSK5  5  Mask interrupt TX packet transfer completed by EPEC - bit 5
EPEC_INTMSK_REG.TXDONE_INTMSK4  4  Mask interrupt TX packet transfer completed by EPEC - bit 4
EPEC_INTMSK_REG.TXDONE_INTMSK3  3  Mask interrupt TX packet transfer completed by EPEC - bit 3
EPEC_INTMSK_REG.TXDONE_INTMSK2  2  Mask interrupt TX packet transfer completed by EPEC - bit 2
EPEC_INTMSK_REG.TXDONE_INTMSK1  1  Mask interrupt TX packet transfer completed by EPEC - bit 1
EPEC_INTMSK_REG.TXDONE_INTMSK0  0  Mask interrupt TX packet transfer completed by EPEC - bit 0

; USBD Registers
USBCLC                      0xEE00   USB clock control register.
USBCLC.USBEX_DIS             3   USB Controller Clock Disable
USBCLC.USBGPSEN              2   USB Controller Clock OCDS Disable
USBCLC.USBDIS                1   USB Controller Clock Status
USBCLC.USBDISR               0   USB Controller Clock Disable
USBD_ID                     0xEE08   USB peripheral identification register, set to ZERO in the current version.
USBD_CMD_REG                0xEE10   Command register
USBD_CMD_REG.Autoflush_Enable            15
USBD_CMD_REG.Flush_TX_Channel_Select_14  14
USBD_CMD_REG.Flush_TX_Channel_Select_13  13
USBD_CMD_REG.Flush_TX_Channel_Select_12  12
USBD_CMD_REG.Flush_TX _Channel           11
USBD_CMD_REG.UDC_Suspend                 10
USBD_CMD_REG.DEV_Resume                  9 
USBD_CMD_REG.USB_TXProtect               8 
USBD_CMD_REG.STALL_EP_7                  7 
USBD_CMD_REG.STALL_EP_6                  6 
USBD_CMD_REG.STALL_EP_5                  5 
USBD_CMD_REG.STALL_EP_4                  4 
USBD_CMD_REG.STALL_EP_3                  3 
USBD_CMD_REG.STALL_EP_2                  2 
USBD_CMD_REG.STALL_EP_1                  1 
USBD_CMD_REG.STALL_EP_0                  0 
USBD_STATUS_REG0            0xEE12   USB endpoint FIFO status
USBD_STATUS_REG0.RX_EMPTY_15 15
USBD_STATUS_REG0.RX_EMPTY_14 14
USBD_STATUS_REG0.RX_EMPTY_13 13
USBD_STATUS_REG0.RX_EMPTY_12 12
USBD_STATUS_REG0.RX_EMPTY_11 11
USBD_STATUS_REG0.RX_EMPTY_10 10
USBD_STATUS_REG0.RX_EMPTY_9  9 
USBD_STATUS_REG0.RX_EMPTY_8  8 
USBD_STATUS_REG0.TX_FULL_7   7 
USBD_STATUS_REG0.TX_FULL_6   6 
USBD_STATUS_REG0.TX_FULL_5   5 
USBD_STATUS_REG0.TX_FULL_4   4 
USBD_STATUS_REG0.TX_FULL_3   3 
USBD_STATUS_REG0.TX_FULL_2   2 
USBD_STATUS_REG0.TX_FULL_1   1 
USBD_STATUS_REG0.TX_FULL_0   0 
USBD_STATUS_REG1            0xEE14   USB endpoint FIFO handshake control
USBD_STATUS_REG1.RX_XFR_ACK_15 15
USBD_STATUS_REG1.RX_XFR_ACK_14 14
USBD_STATUS_REG1.RX_XFR_ACK_13 13
USBD_STATUS_REG1.RX_XFR_ACK_12 12
USBD_STATUS_REG1.RX_XFR_ACK_11 11
USBD_STATUS_REG1.RX_XFR_ACK_10 10
USBD_STATUS_REG1.RX_XFR_ACK_9  9 
USBD_STATUS_REG1.RX_XFR_ACK_8  8 
USBD_STATUS_REG1.TX_XFR_ACK_7  7 
USBD_STATUS_REG1.TX_XFR_ACK_6  6 
USBD_STATUS_REG1.TX_XFR_ACK_5  5 
USBD_STATUS_REG1.TX_XFR_ACK_4  4 
USBD_STATUS_REG1.TX_XFR_ACK_3  3 
USBD_STATUS_REG1.TX_XFR_ACK_2  2 
USBD_STATUS_REG1.TX_XFR_ACK_1  1 
USBD_STATUS_REG1.TX_XFR_ACK_0  0 
USBD_STATUS_REG2            0xEE16   USB Device Remote Wake-Up Feature Status
USBD_STATUS_REG2.DEV_REM_WAKEUP_FEAT 0
reserv_EE18                 0xEE18   reserved
reserv_EE1A                 0xEE1A   reserved
reserv_EE1C                 0xEE1C   reserved
reserv_EE1E                 0xEE1E   reserved
reserv_EE20                 0xEE20   reserved
reserv_EE22                 0xEE22   reserved
USBD_TIME_REG               0xEE24   USB timestamp info: Frame number of the transmitted frame
USBD_TIME_REG.FRAME_NUMBER_10 10 Actual frame number - bit 10
USBD_TIME_REG.FRAME_NUMBER_9  9  Actual frame number - bit 9 
USBD_TIME_REG.FRAME_NUMBER_8  8  Actual frame number - bit 8 
USBD_TIME_REG.FRAME_NUMBER_7  7  Actual frame number - bit 7 
USBD_TIME_REG.FRAME_NUMBER_6  6  Actual frame number - bit 6 
USBD_TIME_REG.FRAME_NUMBER_5  5  Actual frame number - bit 5 
USBD_TIME_REG.FRAME_NUMBER_4  4  Actual frame number - bit 4 
USBD_TIME_REG.FRAME_NUMBER_3  3  Actual frame number - bit 3 
USBD_TIME_REG.FRAME_NUMBER_2  2  Actual frame number - bit 2 
USBD_TIME_REG.FRAME_NUMBER_1  1  Actual frame number - bit 1 
USBD_TIME_REG.FRAME_NUMBER_0  0  Actual frame number - bit 0 
USBD_SETUP_REG01            0xEE26   USB setup bytes (1:0)
USBD_Setup_REG01.Setup_Byte1_15 15 Byte 1 of SETUP command - bit 15
USBD_Setup_REG01.Setup_Byte1_14 14 Byte 1 of SETUP command - bit 14
USBD_Setup_REG01.Setup_Byte1_13 13 Byte 1 of SETUP command - bit 13
USBD_Setup_REG01.Setup_Byte1_12 12 Byte 1 of SETUP command - bit 12
USBD_Setup_REG01.Setup_Byte1_11 11 Byte 1 of SETUP command - bit 11
USBD_Setup_REG01.Setup_Byte1_10 10 Byte 1 of SETUP command - bit 10
USBD_Setup_REG01.Setup_Byte1_9  9  Byte 1 of SETUP command - bit 9 
USBD_Setup_REG01.Setup_Byte1_8  8  Byte 1 of SETUP command - bit 8 
USBD_Setup_REG01.Setup_Byte0_7  7  Byte 0 of SETUP command - bit 7 
USBD_Setup_REG01.Setup_Byte0_6  6  Byte 0 of SETUP command - bit 6 
USBD_Setup_REG01.Setup_Byte0_5  5  Byte 0 of SETUP command - bit 5 
USBD_Setup_REG01.Setup_Byte0_4  4  Byte 0 of SETUP command - bit 4 
USBD_Setup_REG01.Setup_Byte0_3  3  Byte 0 of SETUP command - bit 3 
USBD_Setup_REG01.Setup_Byte0_2  2  Byte 0 of SETUP command - bit 2 
USBD_Setup_REG01.Setup_Byte0_1  1  Byte 0 of SETUP command - bit 1 
USBD_Setup_REG01.Setup_Byte0_0  0  Byte 0 of SETUP command - bit 0 
USBD_SETUP_REG23            0xEE28   USB setup bytes (3:2)
USBD_Setup_REG23.Setup_Byte3_15 15 Byte 3 of SETUP command - bit 15
USBD_Setup_REG23.Setup_Byte3_14 14 Byte 3 of SETUP command - bit 14
USBD_Setup_REG23.Setup_Byte3_13 13 Byte 3 of SETUP command - bit 13
USBD_Setup_REG23.Setup_Byte3_12 12 Byte 3 of SETUP command - bit 12
USBD_Setup_REG23.Setup_Byte3_11 11 Byte 3 of SETUP command - bit 11
USBD_Setup_REG23.Setup_Byte3_10 10 Byte 3 of SETUP command - bit 10
USBD_Setup_REG23.Setup_Byte3_9  9  Byte 3 of SETUP command - bit 9 
USBD_Setup_REG23.Setup_Byte3_8  8  Byte 3 of SETUP command - bit 8 
USBD_Setup_REG23.Setup_Byte2_7  7  Byte 2 of SETUP command - bit 7 
USBD_Setup_REG23.Setup_Byte2_6  6  Byte 2 of SETUP command - bit 6 
USBD_Setup_REG23.Setup_Byte2_5  5  Byte 2 of SETUP command - bit 5 
USBD_Setup_REG23.Setup_Byte2_4  4  Byte 2 of SETUP command - bit 4 
USBD_Setup_REG23.Setup_Byte2_3  3  Byte 2 of SETUP command - bit 3 
USBD_Setup_REG23.Setup_Byte2_2  2  Byte 2 of SETUP command - bit 2 
USBD_Setup_REG23.Setup_Byte2_1  1  Byte 2 of SETUP command - bit 1 
USBD_Setup_REG23.Setup_Byte2_0  0  Byte 2 of SETUP command - bit 0 
USBD_SETUP_REG45            0xEE2A   USB setup bytes (5:4)
USBD_Setup_REG45.Setup_Byte5_15 15 Byte 5 of SETUP command - bit 15
USBD_Setup_REG45.Setup_Byte5_14 14 Byte 5 of SETUP command - bit 14
USBD_Setup_REG45.Setup_Byte5_13 13 Byte 5 of SETUP command - bit 13
USBD_Setup_REG45.Setup_Byte5_12 12 Byte 5 of SETUP command - bit 12
USBD_Setup_REG45.Setup_Byte5_11 11 Byte 5 of SETUP command - bit 11
USBD_Setup_REG45.Setup_Byte5_10 10 Byte 5 of SETUP command - bit 10
USBD_Setup_REG45.Setup_Byte5_9  9  Byte 5 of SETUP command - bit 9 
USBD_Setup_REG45.Setup_Byte5_8  8  Byte 5 of SETUP command - bit 8 
USBD_Setup_REG45.Setup_Byte4_7  7  Byte 4 of SETUP command - bit 7 
USBD_Setup_REG45.Setup_Byte4_6  6  Byte 4 of SETUP command - bit 6 
USBD_Setup_REG45.Setup_Byte4_5  5  Byte 4 of SETUP command - bit 5 
USBD_Setup_REG45.Setup_Byte4_4  4  Byte 4 of SETUP command - bit 4 
USBD_Setup_REG45.Setup_Byte4_3  3  Byte 4 of SETUP command - bit 3 
USBD_Setup_REG45.Setup_Byte4_2  2  Byte 4 of SETUP command - bit 2 
USBD_Setup_REG45.Setup_Byte4_1  1  Byte 4 of SETUP command - bit 1 
USBD_Setup_REG45.Setup_Byte4_0  0  Byte 4 of SETUP command - bit 0 
USBD_SETUP_REG67            0xEE2C   USB setup bytes (7:6)
USBD_Setup_REG67.Setup_Byte7_15 15 Byte 7 of SETUP command - bit 15
USBD_Setup_REG67.Setup_Byte7_14 14 Byte 7 of SETUP command - bit 14
USBD_Setup_REG67.Setup_Byte7_13 13 Byte 7 of SETUP command - bit 13
USBD_Setup_REG67.Setup_Byte7_12 12 Byte 7 of SETUP command - bit 12
USBD_Setup_REG67.Setup_Byte7_11 11 Byte 7 of SETUP command - bit 11
USBD_Setup_REG67.Setup_Byte7_10 10 Byte 7 of SETUP command - bit 10
USBD_Setup_REG67.Setup_Byte7_9  9  Byte 7 of SETUP command - bit 9 
USBD_Setup_REG67.Setup_Byte7_8  8  Byte 7 of SETUP command - bit 8 
USBD_Setup_REG67.Setup_Byte6_7  7  Byte 6 of SETUP command - bit 7 
USBD_Setup_REG67.Setup_Byte6_6  6  Byte 6 of SETUP command - bit 6 
USBD_Setup_REG67.Setup_Byte6_5  5  Byte 6 of SETUP command - bit 5 
USBD_Setup_REG67.Setup_Byte6_4  4  Byte 6 of SETUP command - bit 4 
USBD_Setup_REG67.Setup_Byte6_3  3  Byte 6 of SETUP command - bit 3 
USBD_Setup_REG67.Setup_Byte6_2  2  Byte 6 of SETUP command - bit 2 
USBD_Setup_REG67.Setup_Byte6_1  1  Byte 6 of SETUP command - bit 1 
USBD_Setup_REG67.Setup_Byte6_0  0  Byte 6 of SETUP command - bit 0 
USBD_TXWR0                  0xEE2E   USB Transmit FIFO data register
USBD_TXWR0.TXWR0_15          15  16-bit word for Transmit FIFO endpoint#0 - bit 15
USBD_TXWR0.TXWR0_14          14  16-bit word for Transmit FIFO endpoint#0 - bit 14
USBD_TXWR0.TXWR0_13          13  16-bit word for Transmit FIFO endpoint#0 - bit 13
USBD_TXWR0.TXWR0_12          12  16-bit word for Transmit FIFO endpoint#0 - bit 12
USBD_TXWR0.TXWR0_11          11  16-bit word for Transmit FIFO endpoint#0 - bit 11
USBD_TXWR0.TXWR0_10          10  16-bit word for Transmit FIFO endpoint#0 - bit 10
USBD_TXWR0.TXWR0_9           9   16-bit word for Transmit FIFO endpoint#0 - bit 9 
USBD_TXWR0.TXWR0_8           8   16-bit word for Transmit FIFO endpoint#0 - bit 8 
USBD_TXWR0.TXWR0_7           7   16-bit word for Transmit FIFO endpoint#0 - bit 7 
USBD_TXWR0.TXWR0_6           6   16-bit word for Transmit FIFO endpoint#0 - bit 6 
USBD_TXWR0.TXWR0_5           5   16-bit word for Transmit FIFO endpoint#0 - bit 5 
USBD_TXWR0.TXWR0_4           4   16-bit word for Transmit FIFO endpoint#0 - bit 4 
USBD_TXWR0.TXWR0_3           3   16-bit word for Transmit FIFO endpoint#0 - bit 3 
USBD_TXWR0.TXWR0_2           2   16-bit word for Transmit FIFO endpoint#0 - bit 2 
USBD_TXWR0.TXWR0_1           1   16-bit word for Transmit FIFO endpoint#0 - bit 1 
USBD_TXWR0.TXWR0_0           0   16-bit word for Transmit FIFO endpoint#0 - bit 0 
USBD_TXEOD0                 0xEE30   EPEC/SW End-of-packet indication for USBD.
USBD_TXEOD0.TXEOD            0
USBD_RXRR0                  0xEE32   USB Receive FIFO data register
USBD_RXRR0.RXRR0_15          15  16-bit word for Receive FIFO endpoint#0 - bit 15
USBD_RXRR0.RXRR0_14          14  16-bit word for Receive FIFO endpoint#0 - bit 14
USBD_RXRR0.RXRR0_13          13  16-bit word for Receive FIFO endpoint#0 - bit 13
USBD_RXRR0.RXRR0_12          12  16-bit word for Receive FIFO endpoint#0 - bit 12
USBD_RXRR0.RXRR0_11          11  16-bit word for Receive FIFO endpoint#0 - bit 11
USBD_RXRR0.RXRR0_10          10  16-bit word for Receive FIFO endpoint#0 - bit 10
USBD_RXRR0.RXRR0_9           9   16-bit word for Receive FIFO endpoint#0 - bit 9 
USBD_RXRR0.RXRR0_8           8   16-bit word for Receive FIFO endpoint#0 - bit 8 
USBD_RXRR0.RXRR0_7           7   16-bit word for Receive FIFO endpoint#0 - bit 7 
USBD_RXRR0.RXRR0_6           6   16-bit word for Receive FIFO endpoint#0 - bit 6 
USBD_RXRR0.RXRR0_5           5   16-bit word for Receive FIFO endpoint#0 - bit 5 
USBD_RXRR0.RXRR0_4           4   16-bit word for Receive FIFO endpoint#0 - bit 4 
USBD_RXRR0.RXRR0_3           3   16-bit word for Receive FIFO endpoint#0 - bit 3 
USBD_RXRR0.RXRR0_2           2   16-bit word for Receive FIFO endpoint#0 - bit 2 
USBD_RXRR0.RXRR0_1           1   16-bit word for Receive FIFO endpoint#0 - bit 1 
USBD_RXRR0.RXRR0_0           0   16-bit word for Receive FIFO endpoint#0 - bit 0 
USBD_RX_BYTECNT0            0xEE34   USB receive packet length in bytes
USBD_RX_BYTECNT0.RX_STATUS   15  packet status indication
USBD_RX_BYTECNT0.RX_BYTECNT_9 9  10-bit byte counter for received packet in endpoint#0 - bit 9
USBD_RX_BYTECNT0.RX_BYTECNT_8 8  10-bit byte counter for received packet in endpoint#0 - bit 8
USBD_RX_BYTECNT0.RX_BYTECNT_7 7  10-bit byte counter for received packet in endpoint#0 - bit 7
USBD_RX_BYTECNT0.RX_BYTECNT_6 6  10-bit byte counter for received packet in endpoint#0 - bit 6
USBD_RX_BYTECNT0.RX_BYTECNT_5 5  10-bit byte counter for received packet in endpoint#0 - bit 5
USBD_RX_BYTECNT0.RX_BYTECNT_4 4  10-bit byte counter for received packet in endpoint#0 - bit 4
USBD_RX_BYTECNT0.RX_BYTECNT_3 3  10-bit byte counter for received packet in endpoint#0 - bit 3
USBD_RX_BYTECNT0.RX_BYTECNT_2 2  10-bit byte counter for received packet in endpoint#0 - bit 2
USBD_RX_BYTECNT0.RX_BYTECNT_1 1  10-bit byte counter for received packet in endpoint#0 - bit 1
USBD_RX_BYTECNT0.RX_BYTECNT_0 0  10-bit byte counter for received packet in endpoint#0 - bit 0
USBD_TXWR1                  0xEE36   USB Transmit FIFO data register
USBD_TXWR1.TXWR1_15          15  16-bit word for Transmit FIFO endpoint#1 - bit 15
USBD_TXWR1.TXWR1_14          14  16-bit word for Transmit FIFO endpoint#1 - bit 14
USBD_TXWR1.TXWR1_13          13  16-bit word for Transmit FIFO endpoint#1 - bit 13
USBD_TXWR1.TXWR1_12          12  16-bit word for Transmit FIFO endpoint#1 - bit 12
USBD_TXWR1.TXWR1_11          11  16-bit word for Transmit FIFO endpoint#1 - bit 11
USBD_TXWR1.TXWR1_10          10  16-bit word for Transmit FIFO endpoint#1 - bit 10
USBD_TXWR1.TXWR1_9           9   16-bit word for Transmit FIFO endpoint#1 - bit 9 
USBD_TXWR1.TXWR1_8           8   16-bit word for Transmit FIFO endpoint#1 - bit 8 
USBD_TXWR1.TXWR1_7           7   16-bit word for Transmit FIFO endpoint#1 - bit 7 
USBD_TXWR1.TXWR1_6           6   16-bit word for Transmit FIFO endpoint#1 - bit 6 
USBD_TXWR1.TXWR1_5           5   16-bit word for Transmit FIFO endpoint#1 - bit 5 
USBD_TXWR1.TXWR1_4           4   16-bit word for Transmit FIFO endpoint#1 - bit 4 
USBD_TXWR1.TXWR1_3           3   16-bit word for Transmit FIFO endpoint#1 - bit 3 
USBD_TXWR1.TXWR1_2           2   16-bit word for Transmit FIFO endpoint#1 - bit 2 
USBD_TXWR1.TXWR1_1           1   16-bit word for Transmit FIFO endpoint#1 - bit 1 
USBD_TXWR1.TXWR1_0           0   16-bit word for Transmit FIFO endpoint#1 - bit 0 
USBD_TXEOD1                 0xEE38   EPEC/SW End-of-packet indication for USBD.
USBD_TXEOD1.TXEOD            0
USBD_RXRR1                  0xEE3A   USB Receive FIFO data register
USBD_RXRR1.RXRR1_15          15  16-bit word for Receive FIFO endpoint#1 - bit 15
USBD_RXRR1.RXRR1_14          14  16-bit word for Receive FIFO endpoint#1 - bit 14
USBD_RXRR1.RXRR1_13          13  16-bit word for Receive FIFO endpoint#1 - bit 13
USBD_RXRR1.RXRR1_12          12  16-bit word for Receive FIFO endpoint#1 - bit 12
USBD_RXRR1.RXRR1_11          11  16-bit word for Receive FIFO endpoint#1 - bit 11
USBD_RXRR1.RXRR1_10          10  16-bit word for Receive FIFO endpoint#1 - bit 10
USBD_RXRR1.RXRR1_9           9   16-bit word for Receive FIFO endpoint#1 - bit 9 
USBD_RXRR1.RXRR1_8           8   16-bit word for Receive FIFO endpoint#1 - bit 8 
USBD_RXRR1.RXRR1_7           7   16-bit word for Receive FIFO endpoint#1 - bit 7 
USBD_RXRR1.RXRR1_6           6   16-bit word for Receive FIFO endpoint#1 - bit 6 
USBD_RXRR1.RXRR1_5           5   16-bit word for Receive FIFO endpoint#1 - bit 5 
USBD_RXRR1.RXRR1_4           4   16-bit word for Receive FIFO endpoint#1 - bit 4 
USBD_RXRR1.RXRR1_3           3   16-bit word for Receive FIFO endpoint#1 - bit 3 
USBD_RXRR1.RXRR1_2           2   16-bit word for Receive FIFO endpoint#1 - bit 2 
USBD_RXRR1.RXRR1_1           1   16-bit word for Receive FIFO endpoint#1 - bit 1 
USBD_RXRR1.RXRR1_0           0   16-bit word for Receive FIFO endpoint#1 - bit 0 
USBD_RX_BYTECNT1            0xEE3C   USB receive packet length in bytes
USBD_RX_BYTECNT1.RX_STATUS   15  packet status indication
USBD_RX_BYTECNT1.RX_BYTECNT_9 9  10-bit byte counter for received packet in endpoint#1 - bit 9
USBD_RX_BYTECNT1.RX_BYTECNT_8 8  10-bit byte counter for received packet in endpoint#1 - bit 8
USBD_RX_BYTECNT1.RX_BYTECNT_7 7  10-bit byte counter for received packet in endpoint#1 - bit 7
USBD_RX_BYTECNT1.RX_BYTECNT_6 6  10-bit byte counter for received packet in endpoint#1 - bit 6
USBD_RX_BYTECNT1.RX_BYTECNT_5 5  10-bit byte counter for received packet in endpoint#1 - bit 5
USBD_RX_BYTECNT1.RX_BYTECNT_4 4  10-bit byte counter for received packet in endpoint#1 - bit 4
USBD_RX_BYTECNT1.RX_BYTECNT_3 3  10-bit byte counter for received packet in endpoint#1 - bit 3
USBD_RX_BYTECNT1.RX_BYTECNT_2 2  10-bit byte counter for received packet in endpoint#1 - bit 2
USBD_RX_BYTECNT1.RX_BYTECNT_1 1  10-bit byte counter for received packet in endpoint#1 - bit 1
USBD_RX_BYTECNT1.RX_BYTECNT_0 0  10-bit byte counter for received packet in endpoint#1 - bit 0
USBD_TXWR2                  0xEE3E   USB Transmit FIFO data register
USBD_TXWR2.TXWR2_15          15  16-bit word for Transmit FIFO endpoint#2 - bit 15
USBD_TXWR2.TXWR2_14          14  16-bit word for Transmit FIFO endpoint#2 - bit 14
USBD_TXWR2.TXWR2_13          13  16-bit word for Transmit FIFO endpoint#2 - bit 13
USBD_TXWR2.TXWR2_12          12  16-bit word for Transmit FIFO endpoint#2 - bit 12
USBD_TXWR2.TXWR2_11          11  16-bit word for Transmit FIFO endpoint#2 - bit 11
USBD_TXWR2.TXWR2_10          10  16-bit word for Transmit FIFO endpoint#2 - bit 10
USBD_TXWR2.TXWR2_9           9   16-bit word for Transmit FIFO endpoint#2 - bit 9 
USBD_TXWR2.TXWR2_8           8   16-bit word for Transmit FIFO endpoint#2 - bit 8 
USBD_TXWR2.TXWR2_7           7   16-bit word for Transmit FIFO endpoint#2 - bit 7 
USBD_TXWR2.TXWR2_6           6   16-bit word for Transmit FIFO endpoint#2 - bit 6 
USBD_TXWR2.TXWR2_5           5   16-bit word for Transmit FIFO endpoint#2 - bit 5 
USBD_TXWR2.TXWR2_4           4   16-bit word for Transmit FIFO endpoint#2 - bit 4 
USBD_TXWR2.TXWR2_3           3   16-bit word for Transmit FIFO endpoint#2 - bit 3 
USBD_TXWR2.TXWR2_2           2   16-bit word for Transmit FIFO endpoint#2 - bit 2 
USBD_TXWR2.TXWR2_1           1   16-bit word for Transmit FIFO endpoint#2 - bit 1 
USBD_TXWR2.TXWR2_0           0   16-bit word for Transmit FIFO endpoint#2 - bit 0 
USBD_TXEOD2                 0xEE40   EPEC/SW End-of-packet indication for USBD.
USBD_TXEOD2.TXEOD            0
USBD_RXRR2                  0xEE42   USB Receive FIFO data register
USBD_RXRR2.RXRR2_15          15  16-bit word for Receive FIFO endpoint#2 - bit 15
USBD_RXRR2.RXRR2_14          14  16-bit word for Receive FIFO endpoint#2 - bit 14
USBD_RXRR2.RXRR2_13          13  16-bit word for Receive FIFO endpoint#2 - bit 13
USBD_RXRR2.RXRR2_12          12  16-bit word for Receive FIFO endpoint#2 - bit 12
USBD_RXRR2.RXRR2_11          11  16-bit word for Receive FIFO endpoint#2 - bit 11
USBD_RXRR2.RXRR2_10          10  16-bit word for Receive FIFO endpoint#2 - bit 10
USBD_RXRR2.RXRR2_9           9   16-bit word for Receive FIFO endpoint#2 - bit 9 
USBD_RXRR2.RXRR2_8           8   16-bit word for Receive FIFO endpoint#2 - bit 8 
USBD_RXRR2.RXRR2_7           7   16-bit word for Receive FIFO endpoint#2 - bit 7 
USBD_RXRR2.RXRR2_6           6   16-bit word for Receive FIFO endpoint#2 - bit 6 
USBD_RXRR2.RXRR2_5           5   16-bit word for Receive FIFO endpoint#2 - bit 5 
USBD_RXRR2.RXRR2_4           4   16-bit word for Receive FIFO endpoint#2 - bit 4 
USBD_RXRR2.RXRR2_3           3   16-bit word for Receive FIFO endpoint#2 - bit 3 
USBD_RXRR2.RXRR2_2           2   16-bit word for Receive FIFO endpoint#2 - bit 2 
USBD_RXRR2.RXRR2_1           1   16-bit word for Receive FIFO endpoint#2 - bit 1 
USBD_RXRR2.RXRR2_0           0   16-bit word for Receive FIFO endpoint#2 - bit 0 
USBD_RX_BYTECNT2            0xEE44   USB receive packet length in bytes
USBD_RX_BYTECNT2.RX_STATUS   15  packet status indication
USBD_RX_BYTECNT2.RX_BYTECNT_9 9  10-bit byte counter for received packet in endpoint#2 - bit 9
USBD_RX_BYTECNT2.RX_BYTECNT_8 8  10-bit byte counter for received packet in endpoint#2 - bit 8
USBD_RX_BYTECNT2.RX_BYTECNT_7 7  10-bit byte counter for received packet in endpoint#2 - bit 7
USBD_RX_BYTECNT2.RX_BYTECNT_6 6  10-bit byte counter for received packet in endpoint#2 - bit 6
USBD_RX_BYTECNT2.RX_BYTECNT_5 5  10-bit byte counter for received packet in endpoint#2 - bit 5
USBD_RX_BYTECNT2.RX_BYTECNT_4 4  10-bit byte counter for received packet in endpoint#2 - bit 4
USBD_RX_BYTECNT2.RX_BYTECNT_3 3  10-bit byte counter for received packet in endpoint#2 - bit 3
USBD_RX_BYTECNT2.RX_BYTECNT_2 2  10-bit byte counter for received packet in endpoint#2 - bit 2
USBD_RX_BYTECNT2.RX_BYTECNT_1 1  10-bit byte counter for received packet in endpoint#2 - bit 1
USBD_RX_BYTECNT2.RX_BYTECNT_0 0  10-bit byte counter for received packet in endpoint#2 - bit 0
USBD_TXWR3                  0xEE46   USB Transmit FIFO data register
USBD_TXWR3.TXWR3_15          15  16-bit word for Transmit FIFO endpoint#3 - bit 15
USBD_TXWR3.TXWR3_14          14  16-bit word for Transmit FIFO endpoint#3 - bit 14
USBD_TXWR3.TXWR3_13          13  16-bit word for Transmit FIFO endpoint#3 - bit 13
USBD_TXWR3.TXWR3_12          12  16-bit word for Transmit FIFO endpoint#3 - bit 12
USBD_TXWR3.TXWR3_11          11  16-bit word for Transmit FIFO endpoint#3 - bit 11
USBD_TXWR3.TXWR3_10          10  16-bit word for Transmit FIFO endpoint#3 - bit 10
USBD_TXWR3.TXWR3_9           9   16-bit word for Transmit FIFO endpoint#3 - bit 9 
USBD_TXWR3.TXWR3_8           8   16-bit word for Transmit FIFO endpoint#3 - bit 8 
USBD_TXWR3.TXWR3_7           7   16-bit word for Transmit FIFO endpoint#3 - bit 7 
USBD_TXWR3.TXWR3_6           6   16-bit word for Transmit FIFO endpoint#3 - bit 6 
USBD_TXWR3.TXWR3_5           5   16-bit word for Transmit FIFO endpoint#3 - bit 5 
USBD_TXWR3.TXWR3_4           4   16-bit word for Transmit FIFO endpoint#3 - bit 4 
USBD_TXWR3.TXWR3_3           3   16-bit word for Transmit FIFO endpoint#3 - bit 3 
USBD_TXWR3.TXWR3_2           2   16-bit word for Transmit FIFO endpoint#3 - bit 2 
USBD_TXWR3.TXWR3_1           1   16-bit word for Transmit FIFO endpoint#3 - bit 1 
USBD_TXWR3.TXWR3_0           0   16-bit word for Transmit FIFO endpoint#3 - bit 0 
USBD_TXEOD3                 0xEE48   EPEC/SW End-of-packet indication for USBD.
USBD_TXEOD3.TXEOD            0
USBD_RXRR3                  0xEE4A   USB Receive FIFO data register
USBD_RXRR3.RXRR3_15          15  16-bit word for Receive FIFO endpoint#3 - bit 15
USBD_RXRR3.RXRR3_14          14  16-bit word for Receive FIFO endpoint#3 - bit 14
USBD_RXRR3.RXRR3_13          13  16-bit word for Receive FIFO endpoint#3 - bit 13
USBD_RXRR3.RXRR3_12          12  16-bit word for Receive FIFO endpoint#3 - bit 12
USBD_RXRR3.RXRR3_11          11  16-bit word for Receive FIFO endpoint#3 - bit 11
USBD_RXRR3.RXRR3_10          10  16-bit word for Receive FIFO endpoint#3 - bit 10
USBD_RXRR3.RXRR3_9           9   16-bit word for Receive FIFO endpoint#3 - bit 9 
USBD_RXRR3.RXRR3_8           8   16-bit word for Receive FIFO endpoint#3 - bit 8 
USBD_RXRR3.RXRR3_7           7   16-bit word for Receive FIFO endpoint#3 - bit 7 
USBD_RXRR3.RXRR3_6           6   16-bit word for Receive FIFO endpoint#3 - bit 6 
USBD_RXRR3.RXRR3_5           5   16-bit word for Receive FIFO endpoint#3 - bit 5 
USBD_RXRR3.RXRR3_4           4   16-bit word for Receive FIFO endpoint#3 - bit 4 
USBD_RXRR3.RXRR3_3           3   16-bit word for Receive FIFO endpoint#3 - bit 3 
USBD_RXRR3.RXRR3_2           2   16-bit word for Receive FIFO endpoint#3 - bit 2 
USBD_RXRR3.RXRR3_1           1   16-bit word for Receive FIFO endpoint#3 - bit 1 
USBD_RXRR3.RXRR3_0           0   16-bit word for Receive FIFO endpoint#3 - bit 0 
USBD_RX_BYTECNT3            0xEE4C   USB receive packet length in bytes
USBD_RX_BYTECNT3.RX_STATUS   15  packet status indication
USBD_RX_BYTECNT3.RX_BYTECNT_9 9  10-bit byte counter for received packet in endpoint#3 - bit 9
USBD_RX_BYTECNT3.RX_BYTECNT_8 8  10-bit byte counter for received packet in endpoint#3 - bit 8
USBD_RX_BYTECNT3.RX_BYTECNT_7 7  10-bit byte counter for received packet in endpoint#3 - bit 7
USBD_RX_BYTECNT3.RX_BYTECNT_6 6  10-bit byte counter for received packet in endpoint#3 - bit 6
USBD_RX_BYTECNT3.RX_BYTECNT_5 5  10-bit byte counter for received packet in endpoint#3 - bit 5
USBD_RX_BYTECNT3.RX_BYTECNT_4 4  10-bit byte counter for received packet in endpoint#3 - bit 4
USBD_RX_BYTECNT3.RX_BYTECNT_3 3  10-bit byte counter for received packet in endpoint#3 - bit 3
USBD_RX_BYTECNT3.RX_BYTECNT_2 2  10-bit byte counter for received packet in endpoint#3 - bit 2
USBD_RX_BYTECNT3.RX_BYTECNT_1 1  10-bit byte counter for received packet in endpoint#3 - bit 1
USBD_RX_BYTECNT3.RX_BYTECNT_0 0  10-bit byte counter for received packet in endpoint#3 - bit 0
USBD_TXWR4                  0xEE4E   USB Transmit FIFO data register
USBD_TXWR4.TXWR4_15          15  16-bit word for Transmit FIFO endpoint#4 - bit 15
USBD_TXWR4.TXWR4_14          14  16-bit word for Transmit FIFO endpoint#4 - bit 14
USBD_TXWR4.TXWR4_13          13  16-bit word for Transmit FIFO endpoint#4 - bit 13
USBD_TXWR4.TXWR4_12          12  16-bit word for Transmit FIFO endpoint#4 - bit 12
USBD_TXWR4.TXWR4_11          11  16-bit word for Transmit FIFO endpoint#4 - bit 11
USBD_TXWR4.TXWR4_10          10  16-bit word for Transmit FIFO endpoint#4 - bit 10
USBD_TXWR4.TXWR4_9           9   16-bit word for Transmit FIFO endpoint#4 - bit 9 
USBD_TXWR4.TXWR4_8           8   16-bit word for Transmit FIFO endpoint#4 - bit 8 
USBD_TXWR4.TXWR4_7           7   16-bit word for Transmit FIFO endpoint#4 - bit 7 
USBD_TXWR4.TXWR4_6           6   16-bit word for Transmit FIFO endpoint#4 - bit 6 
USBD_TXWR4.TXWR4_5           5   16-bit word for Transmit FIFO endpoint#4 - bit 5 
USBD_TXWR4.TXWR4_4           4   16-bit word for Transmit FIFO endpoint#4 - bit 4 
USBD_TXWR4.TXWR4_3           3   16-bit word for Transmit FIFO endpoint#4 - bit 3 
USBD_TXWR4.TXWR4_2           2   16-bit word for Transmit FIFO endpoint#4 - bit 2 
USBD_TXWR4.TXWR4_1           1   16-bit word for Transmit FIFO endpoint#4 - bit 1 
USBD_TXWR4.TXWR4_0           0   16-bit word for Transmit FIFO endpoint#4 - bit 0 
USBD_TXEOD4                 0xEE50   EPEC/SW End-of-packet indication for USBD.
USBD_TXEOD4.TXEOD            0
USBD_RXRR4                  0xEE52   USB Receive FIFO data register
USBD_RXRR4.RXRR4_15          15  16-bit word for Receive FIFO endpoint#4 - bit 15
USBD_RXRR4.RXRR4_14          14  16-bit word for Receive FIFO endpoint#4 - bit 14
USBD_RXRR4.RXRR4_13          13  16-bit word for Receive FIFO endpoint#4 - bit 13
USBD_RXRR4.RXRR4_12          12  16-bit word for Receive FIFO endpoint#4 - bit 12
USBD_RXRR4.RXRR4_11          11  16-bit word for Receive FIFO endpoint#4 - bit 11
USBD_RXRR4.RXRR4_10          10  16-bit word for Receive FIFO endpoint#4 - bit 10
USBD_RXRR4.RXRR4_9           9   16-bit word for Receive FIFO endpoint#4 - bit 9 
USBD_RXRR4.RXRR4_8           8   16-bit word for Receive FIFO endpoint#4 - bit 8 
USBD_RXRR4.RXRR4_7           7   16-bit word for Receive FIFO endpoint#4 - bit 7 
USBD_RXRR4.RXRR4_6           6   16-bit word for Receive FIFO endpoint#4 - bit 6 
USBD_RXRR4.RXRR4_5           5   16-bit word for Receive FIFO endpoint#4 - bit 5 
USBD_RXRR4.RXRR4_4           4   16-bit word for Receive FIFO endpoint#4 - bit 4 
USBD_RXRR4.RXRR4_3           3   16-bit word for Receive FIFO endpoint#4 - bit 3 
USBD_RXRR4.RXRR4_2           2   16-bit word for Receive FIFO endpoint#4 - bit 2 
USBD_RXRR4.RXRR4_1           1   16-bit word for Receive FIFO endpoint#4 - bit 1 
USBD_RXRR4.RXRR4_0           0   16-bit word for Receive FIFO endpoint#4 - bit 0 
USBD_RX_BYTECNT4            0xEE54   USB receive packet length in bytes
USBD_RX_BYTECNT4.RX_STATUS   15  packet status indication
USBD_RX_BYTECNT4.RX_BYTECNT_9 9  10-bit byte counter for received packet in endpoint#4 - bit 9
USBD_RX_BYTECNT4.RX_BYTECNT_8 8  10-bit byte counter for received packet in endpoint#4 - bit 8
USBD_RX_BYTECNT4.RX_BYTECNT_7 7  10-bit byte counter for received packet in endpoint#4 - bit 7
USBD_RX_BYTECNT4.RX_BYTECNT_6 6  10-bit byte counter for received packet in endpoint#4 - bit 6
USBD_RX_BYTECNT4.RX_BYTECNT_5 5  10-bit byte counter for received packet in endpoint#4 - bit 5
USBD_RX_BYTECNT4.RX_BYTECNT_4 4  10-bit byte counter for received packet in endpoint#4 - bit 4
USBD_RX_BYTECNT4.RX_BYTECNT_3 3  10-bit byte counter for received packet in endpoint#4 - bit 3
USBD_RX_BYTECNT4.RX_BYTECNT_2 2  10-bit byte counter for received packet in endpoint#4 - bit 2
USBD_RX_BYTECNT4.RX_BYTECNT_1 1  10-bit byte counter for received packet in endpoint#4 - bit 1
USBD_RX_BYTECNT4.RX_BYTECNT_0 0  10-bit byte counter for received packet in endpoint#4 - bit 0
USBD_TXWR5                  0xEE56   USB Transmit FIFO data register
USBD_TXWR5.TXWR5_15          15  16-bit word for Transmit FIFO endpoint#5 - bit 15
USBD_TXWR5.TXWR5_14          14  16-bit word for Transmit FIFO endpoint#5 - bit 14
USBD_TXWR5.TXWR5_13          13  16-bit word for Transmit FIFO endpoint#5 - bit 13
USBD_TXWR5.TXWR5_12          12  16-bit word for Transmit FIFO endpoint#5 - bit 12
USBD_TXWR5.TXWR5_11          11  16-bit word for Transmit FIFO endpoint#5 - bit 11
USBD_TXWR5.TXWR5_10          10  16-bit word for Transmit FIFO endpoint#5 - bit 10
USBD_TXWR5.TXWR5_9           9   16-bit word for Transmit FIFO endpoint#5 - bit 9 
USBD_TXWR5.TXWR5_8           8   16-bit word for Transmit FIFO endpoint#5 - bit 8 
USBD_TXWR5.TXWR5_7           7   16-bit word for Transmit FIFO endpoint#5 - bit 7 
USBD_TXWR5.TXWR5_6           6   16-bit word for Transmit FIFO endpoint#5 - bit 6 
USBD_TXWR5.TXWR5_5           5   16-bit word for Transmit FIFO endpoint#5 - bit 5 
USBD_TXWR5.TXWR5_4           4   16-bit word for Transmit FIFO endpoint#5 - bit 4 
USBD_TXWR5.TXWR5_3           3   16-bit word for Transmit FIFO endpoint#5 - bit 3 
USBD_TXWR5.TXWR5_2           2   16-bit word for Transmit FIFO endpoint#5 - bit 2 
USBD_TXWR5.TXWR5_1           1   16-bit word for Transmit FIFO endpoint#5 - bit 1 
USBD_TXWR5.TXWR5_0           0   16-bit word for Transmit FIFO endpoint#5 - bit 0 
USBD_TXEOD5                 0xEE58   EPEC/SW End-of-packet indication for USBD.
USBD_TXEOD5.TXEOD            0
USBD_RXRR5                  0xEE5A   USB Receive FIFO data register
USBD_RXRR5.RXRR5_15          15  16-bit word for Receive FIFO endpoint#5 - bit 15
USBD_RXRR5.RXRR5_14          14  16-bit word for Receive FIFO endpoint#5 - bit 14
USBD_RXRR5.RXRR5_13          13  16-bit word for Receive FIFO endpoint#5 - bit 13
USBD_RXRR5.RXRR5_12          12  16-bit word for Receive FIFO endpoint#5 - bit 12
USBD_RXRR5.RXRR5_11          11  16-bit word for Receive FIFO endpoint#5 - bit 11
USBD_RXRR5.RXRR5_10          10  16-bit word for Receive FIFO endpoint#5 - bit 10
USBD_RXRR5.RXRR5_9           9   16-bit word for Receive FIFO endpoint#5 - bit 9 
USBD_RXRR5.RXRR5_8           8   16-bit word for Receive FIFO endpoint#5 - bit 8 
USBD_RXRR5.RXRR5_7           7   16-bit word for Receive FIFO endpoint#5 - bit 7 
USBD_RXRR5.RXRR5_6           6   16-bit word for Receive FIFO endpoint#5 - bit 6 
USBD_RXRR5.RXRR5_5           5   16-bit word for Receive FIFO endpoint#5 - bit 5 
USBD_RXRR5.RXRR5_4           4   16-bit word for Receive FIFO endpoint#5 - bit 4 
USBD_RXRR5.RXRR5_3           3   16-bit word for Receive FIFO endpoint#5 - bit 3 
USBD_RXRR5.RXRR5_2           2   16-bit word for Receive FIFO endpoint#5 - bit 2 
USBD_RXRR5.RXRR5_1           1   16-bit word for Receive FIFO endpoint#5 - bit 1 
USBD_RXRR5.RXRR5_0           0   16-bit word for Receive FIFO endpoint#5 - bit 0 
USBD_RX_BYTECNT5            0xEE5C   USB receive packet length in bytes
USBD_RX_BYTECNT5.RX_STATUS   15  packet status indication
USBD_RX_BYTECNT5.RX_BYTECNT_9 9  10-bit byte counter for received packet in endpoint#5 - bit 9
USBD_RX_BYTECNT5.RX_BYTECNT_8 8  10-bit byte counter for received packet in endpoint#5 - bit 8
USBD_RX_BYTECNT5.RX_BYTECNT_7 7  10-bit byte counter for received packet in endpoint#5 - bit 7
USBD_RX_BYTECNT5.RX_BYTECNT_6 6  10-bit byte counter for received packet in endpoint#5 - bit 6
USBD_RX_BYTECNT5.RX_BYTECNT_5 5  10-bit byte counter for received packet in endpoint#5 - bit 5
USBD_RX_BYTECNT5.RX_BYTECNT_4 4  10-bit byte counter for received packet in endpoint#5 - bit 4
USBD_RX_BYTECNT5.RX_BYTECNT_3 3  10-bit byte counter for received packet in endpoint#5 - bit 3
USBD_RX_BYTECNT5.RX_BYTECNT_2 2  10-bit byte counter for received packet in endpoint#5 - bit 2
USBD_RX_BYTECNT5.RX_BYTECNT_1 1  10-bit byte counter for received packet in endpoint#5 - bit 1
USBD_RX_BYTECNT5.RX_BYTECNT_0 0  10-bit byte counter for received packet in endpoint#5 - bit 0
USBD_TXWR6                  0xEE5E   USB Transmit FIFO data register
USBD_TXWR6.TXWR6_15          15  16-bit word for Transmit FIFO endpoint#6 - bit 15
USBD_TXWR6.TXWR6_14          14  16-bit word for Transmit FIFO endpoint#6 - bit 14
USBD_TXWR6.TXWR6_13          13  16-bit word for Transmit FIFO endpoint#6 - bit 13
USBD_TXWR6.TXWR6_12          12  16-bit word for Transmit FIFO endpoint#6 - bit 12
USBD_TXWR6.TXWR6_11          11  16-bit word for Transmit FIFO endpoint#6 - bit 11
USBD_TXWR6.TXWR6_10          10  16-bit word for Transmit FIFO endpoint#6 - bit 10
USBD_TXWR6.TXWR6_9           9   16-bit word for Transmit FIFO endpoint#6 - bit 9 
USBD_TXWR6.TXWR6_8           8   16-bit word for Transmit FIFO endpoint#6 - bit 8 
USBD_TXWR6.TXWR6_7           7   16-bit word for Transmit FIFO endpoint#6 - bit 7 
USBD_TXWR6.TXWR6_6           6   16-bit word for Transmit FIFO endpoint#6 - bit 6 
USBD_TXWR6.TXWR6_5           5   16-bit word for Transmit FIFO endpoint#6 - bit 5 
USBD_TXWR6.TXWR6_4           4   16-bit word for Transmit FIFO endpoint#6 - bit 4 
USBD_TXWR6.TXWR6_3           3   16-bit word for Transmit FIFO endpoint#6 - bit 3 
USBD_TXWR6.TXWR6_2           2   16-bit word for Transmit FIFO endpoint#6 - bit 2 
USBD_TXWR6.TXWR6_1           1   16-bit word for Transmit FIFO endpoint#6 - bit 1 
USBD_TXWR6.TXWR6_0           0   16-bit word for Transmit FIFO endpoint#6 - bit 0 
USBD_TXEOD6                 0xEE60   EPEC/SW End-of-packet indication for USBD.
USBD_TXEOD6.TXEOD            0
USBD_RXRR6                  0xEE62   USB Receive FIFO data register
USBD_RXRR6.RXRR6_15          15  16-bit word for Receive FIFO endpoint#6 - bit 15
USBD_RXRR6.RXRR6_14          14  16-bit word for Receive FIFO endpoint#6 - bit 14
USBD_RXRR6.RXRR6_13          13  16-bit word for Receive FIFO endpoint#6 - bit 13
USBD_RXRR6.RXRR6_12          12  16-bit word for Receive FIFO endpoint#6 - bit 12
USBD_RXRR6.RXRR6_11          11  16-bit word for Receive FIFO endpoint#6 - bit 11
USBD_RXRR6.RXRR6_10          10  16-bit word for Receive FIFO endpoint#6 - bit 10
USBD_RXRR6.RXRR6_9           9   16-bit word for Receive FIFO endpoint#6 - bit 9 
USBD_RXRR6.RXRR6_8           8   16-bit word for Receive FIFO endpoint#6 - bit 8 
USBD_RXRR6.RXRR6_7           7   16-bit word for Receive FIFO endpoint#6 - bit 7 
USBD_RXRR6.RXRR6_6           6   16-bit word for Receive FIFO endpoint#6 - bit 6 
USBD_RXRR6.RXRR6_5           5   16-bit word for Receive FIFO endpoint#6 - bit 5 
USBD_RXRR6.RXRR6_4           4   16-bit word for Receive FIFO endpoint#6 - bit 4 
USBD_RXRR6.RXRR6_3           3   16-bit word for Receive FIFO endpoint#6 - bit 3 
USBD_RXRR6.RXRR6_2           2   16-bit word for Receive FIFO endpoint#6 - bit 2 
USBD_RXRR6.RXRR6_1           1   16-bit word for Receive FIFO endpoint#6 - bit 1 
USBD_RXRR6.RXRR6_0           0   16-bit word for Receive FIFO endpoint#6 - bit 0 
USBD_RX_BYTECNT6            0xEE64   USB receive packet length in bytes
USBD_RX_BYTECNT6.RX_STATUS   15  packet status indication
USBD_RX_BYTECNT6.RX_BYTECNT_9 9  10-bit byte counter for received packet in endpoint#6 - bit 9
USBD_RX_BYTECNT6.RX_BYTECNT_8 8  10-bit byte counter for received packet in endpoint#6 - bit 8
USBD_RX_BYTECNT6.RX_BYTECNT_7 7  10-bit byte counter for received packet in endpoint#6 - bit 7
USBD_RX_BYTECNT6.RX_BYTECNT_6 6  10-bit byte counter for received packet in endpoint#6 - bit 6
USBD_RX_BYTECNT6.RX_BYTECNT_5 5  10-bit byte counter for received packet in endpoint#6 - bit 5
USBD_RX_BYTECNT6.RX_BYTECNT_4 4  10-bit byte counter for received packet in endpoint#6 - bit 4
USBD_RX_BYTECNT6.RX_BYTECNT_3 3  10-bit byte counter for received packet in endpoint#6 - bit 3
USBD_RX_BYTECNT6.RX_BYTECNT_2 2  10-bit byte counter for received packet in endpoint#6 - bit 2
USBD_RX_BYTECNT6.RX_BYTECNT_1 1  10-bit byte counter for received packet in endpoint#6 - bit 1
USBD_RX_BYTECNT6.RX_BYTECNT_0 0  10-bit byte counter for received packet in endpoint#6 - bit 0
USBD_TXWR7                  0xEE66   USB Transmit FIFO data register
USBD_TXWR7.TXWR7_15          15  16-bit word for Transmit FIFO endpoint#7 - bit 15
USBD_TXWR7.TXWR7_14          14  16-bit word for Transmit FIFO endpoint#7 - bit 14
USBD_TXWR7.TXWR7_13          13  16-bit word for Transmit FIFO endpoint#7 - bit 13
USBD_TXWR7.TXWR7_12          12  16-bit word for Transmit FIFO endpoint#7 - bit 12
USBD_TXWR7.TXWR7_11          11  16-bit word for Transmit FIFO endpoint#7 - bit 11
USBD_TXWR7.TXWR7_10          10  16-bit word for Transmit FIFO endpoint#7 - bit 10
USBD_TXWR7.TXWR7_9           9   16-bit word for Transmit FIFO endpoint#7 - bit 9 
USBD_TXWR7.TXWR7_8           8   16-bit word for Transmit FIFO endpoint#7 - bit 8 
USBD_TXWR7.TXWR7_7           7   16-bit word for Transmit FIFO endpoint#7 - bit 7 
USBD_TXWR7.TXWR7_6           6   16-bit word for Transmit FIFO endpoint#7 - bit 6 
USBD_TXWR7.TXWR7_5           5   16-bit word for Transmit FIFO endpoint#7 - bit 5 
USBD_TXWR7.TXWR7_4           4   16-bit word for Transmit FIFO endpoint#7 - bit 4 
USBD_TXWR7.TXWR7_3           3   16-bit word for Transmit FIFO endpoint#7 - bit 3 
USBD_TXWR7.TXWR7_2           2   16-bit word for Transmit FIFO endpoint#7 - bit 2 
USBD_TXWR7.TXWR7_1           1   16-bit word for Transmit FIFO endpoint#7 - bit 1 
USBD_TXWR7.TXWR7_0           0   16-bit word for Transmit FIFO endpoint#7 - bit 0 
USBD_TXEOD7                 0xEE68   EPEC/SW End-of-packet indication for USBD.
USBD_TXEOD7.TXEOD            0
USBD_RXRR7                  0xEE6A   USB Receive FIFO data register
USBD_RXRR7.RXRR7_15          15  16-bit word for Receive FIFO endpoint#7 - bit 15
USBD_RXRR7.RXRR7_14          14  16-bit word for Receive FIFO endpoint#7 - bit 14
USBD_RXRR7.RXRR7_13          13  16-bit word for Receive FIFO endpoint#7 - bit 13
USBD_RXRR7.RXRR7_12          12  16-bit word for Receive FIFO endpoint#7 - bit 12
USBD_RXRR7.RXRR7_11          11  16-bit word for Receive FIFO endpoint#7 - bit 11
USBD_RXRR7.RXRR7_10          10  16-bit word for Receive FIFO endpoint#7 - bit 10
USBD_RXRR7.RXRR7_9           9   16-bit word for Receive FIFO endpoint#7 - bit 9 
USBD_RXRR7.RXRR7_8           8   16-bit word for Receive FIFO endpoint#7 - bit 8 
USBD_RXRR7.RXRR7_7           7   16-bit word for Receive FIFO endpoint#7 - bit 7 
USBD_RXRR7.RXRR7_6           6   16-bit word for Receive FIFO endpoint#7 - bit 6 
USBD_RXRR7.RXRR7_5           5   16-bit word for Receive FIFO endpoint#7 - bit 5 
USBD_RXRR7.RXRR7_4           4   16-bit word for Receive FIFO endpoint#7 - bit 4 
USBD_RXRR7.RXRR7_3           3   16-bit word for Receive FIFO endpoint#7 - bit 3 
USBD_RXRR7.RXRR7_2           2   16-bit word for Receive FIFO endpoint#7 - bit 2 
USBD_RXRR7.RXRR7_1           1   16-bit word for Receive FIFO endpoint#7 - bit 1 
USBD_RXRR7.RXRR7_0           0   16-bit word for Receive FIFO endpoint#7 - bit 0 
USBD_RX_BYTECNT7            0xEE6C   USB receive packet length in bytes
USBD_RX_BYTECNT7.RX_STATUS   15  packet status indication
USBD_RX_BYTECNT7.RX_BYTECNT_9 9  10-bit byte counter for received packet in endpoint#7 - bit 9
USBD_RX_BYTECNT7.RX_BYTECNT_8 8  10-bit byte counter for received packet in endpoint#7 - bit 8
USBD_RX_BYTECNT7.RX_BYTECNT_7 7  10-bit byte counter for received packet in endpoint#7 - bit 7
USBD_RX_BYTECNT7.RX_BYTECNT_6 6  10-bit byte counter for received packet in endpoint#7 - bit 6
USBD_RX_BYTECNT7.RX_BYTECNT_5 5  10-bit byte counter for received packet in endpoint#7 - bit 5
USBD_RX_BYTECNT7.RX_BYTECNT_4 4  10-bit byte counter for received packet in endpoint#7 - bit 4
USBD_RX_BYTECNT7.RX_BYTECNT_3 3  10-bit byte counter for received packet in endpoint#7 - bit 3
USBD_RX_BYTECNT7.RX_BYTECNT_2 2  10-bit byte counter for received packet in endpoint#7 - bit 2
USBD_RX_BYTECNT7.RX_BYTECNT_1 1  10-bit byte counter for received packet in endpoint#7 - bit 1
USBD_RX_BYTECNT7.RX_BYTECNT_0 0  10-bit byte counter for received packet in endpoint#7 - bit 0
USBD_CFGVAL                 0xEE6E   Current Configuration & Alternate Setting selected by Host
USBD_CFGVAL.AS_IF3_9         9   Alternate Setting selected for Interface 3 - bit 9
USBD_CFGVAL.AS_IF3_8         8   Alternate Setting selected for Interface 3 - bit 8
USBD_CFGVAL.AS_IF2_7         7   Alternate Setting selected for Interface 2 - bit 7
USBD_CFGVAL.AS_IF2_6         6   Alternate Setting selected for Interface 2 - bit 6
USBD_CFGVAL.AS_IF1_5         5   Alternate Setting selected for Interface 1 - bit 5
USBD_CFGVAL.AS_IF1_4         4   Alternate Setting selected for Interface 1 - bit 4
USBD_CFGVAL.AS_IF0_3         3   Alternate Setting selected for Interface 0 - bit 3
USBD_CFGVAL.AS_IF0_2         2   Alternate Setting selected for Interface 0 - bit 2
USBD_CFGVAL.CFG_1            1   Configuration selected by host 'xx' - bit 1
USBD_CFGVAL.CFG_0            0   Configuration selected by host 'xx' - bit 0
USBC_CMD_RESET              0xEE70   USB Block Reset
USBC_CMD_RESET.USBC_RST      0   Resets the USB block including the transmit and receive logic



XADRS1           0xF014   XBUS Address Select Register 1
XADRS1.RGSAD15    15  Range Start Address bit 15
XADRS1.RGSAD14    14  Range Start Address bit 14
XADRS1.RGSAD13    13  Range Start Address bit 13
XADRS1.RGSAD12    12  Range Start Address bit 12
XADRS1.RGSAD11    11  Range Start Address bit 11
XADRS1.RGSAD10    10  Range Start Address bit 10
XADRS1.RGSAD9     9   Range Start Address bit 9
XADRS1.RGSAD8     8   Range Start Address bit 8
XADRS1.RGSAD7     7   Range Start Address bit 7
XADRS1.RGSAD6     6   Range Start Address bit 6
XADRS1.RGSAD5     5   Range Start Address bit 5
XADRS1.RGSAD4     4   Range Start Address bit 4
XADRS1.RGSZ3      3   Range Size Selection bit 3
XADRS1.RGSZ2      2   Range Size Selection bit 2
XADRS1.RGSZ1      1   Range Size Selection bit 1
XADRS1.RGSZ0      0   Range Size Selection bit 0
XADRS2           0xF016   XBUS Address Select Register 2
XADRS2.RGSAD15    15  Range Start Address bit 15
XADRS2.RGSAD14    14  Range Start Address bit 14
XADRS2.RGSAD13    13  Range Start Address bit 13
XADRS2.RGSAD12    12  Range Start Address bit 12
XADRS2.RGSAD11    11  Range Start Address bit 11
XADRS2.RGSAD10    10  Range Start Address bit 10
XADRS2.RGSAD9     9   Range Start Address bit 9
XADRS2.RGSAD8     8   Range Start Address bit 8
XADRS2.RGSAD7     7   Range Start Address bit 7
XADRS2.RGSAD6     6   Range Start Address bit 6
XADRS2.RGSAD5     5   Range Start Address bit 5
XADRS2.RGSAD4     4   Range Start Address bit 4
XADRS2.RGSZ3      3   Range Size Selection bit 3
XADRS2.RGSZ2      2   Range Size Selection bit 2
XADRS2.RGSZ1      1   Range Size Selection bit 1
XADRS2.RGSZ0      0   Range Size Selection bit 0
XADRS3           0xF018   XBUS Address Select Register 3
XADRS3.RGSAD15    15  Range Start Address bit 15
XADRS3.RGSAD14    14  Range Start Address bit 14
XADRS3.RGSAD13    13  Range Start Address bit 13
XADRS3.RGSAD12    12  Range Start Address bit 12
XADRS3.RGSAD11    11  Range Start Address bit 11
XADRS3.RGSAD10    10  Range Start Address bit 10
XADRS3.RGSAD9     9   Range Start Address bit 9
XADRS3.RGSAD8     8   Range Start Address bit 8
XADRS3.RGSAD7     7   Range Start Address bit 7
XADRS3.RGSAD6     6   Range Start Address bit 6
XADRS3.RGSAD5     5   Range Start Address bit 5
XADRS3.RGSAD4     4   Range Start Address bit 4
XADRS3.RGSZ3      3   Range Size Selection bit 3
XADRS3.RGSZ2      2   Range Size Selection bit 2
XADRS3.RGSZ1      1   Range Size Selection bit 1
XADRS3.RGSZ0      0   Range Size Selection bit 0
XADRS4           0xF01A   XBUS Address Select Register 4
XADRS4.RGSAD15    15  Range Start Address bit 15
XADRS4.RGSAD14    14  Range Start Address bit 14
XADRS4.RGSAD13    13  Range Start Address bit 13
XADRS4.RGSAD12    12  Range Start Address bit 12
XADRS4.RGSAD11    11  Range Start Address bit 11
XADRS4.RGSAD10    10  Range Start Address bit 10
XADRS4.RGSAD9     9   Range Start Address bit 9
XADRS4.RGSAD8     8   Range Start Address bit 8
XADRS4.RGSAD7     7   Range Start Address bit 7
XADRS4.RGSAD6     6   Range Start Address bit 6
XADRS4.RGSAD5     5   Range Start Address bit 5
XADRS4.RGSAD4     4   Range Start Address bit 4
XADRS4.RGSZ3      3   Range Size Selection bit 3
XADRS4.RGSZ2      2   Range Size Selection bit 2
XADRS4.RGSZ1      1   Range Size Selection bit 1
XADRS4.RGSZ0      0   Range Size Selection bit 0
XADRS5           0xF01C   XBUS Address Select Register 5
XADRS5.RGSAD15    15  Range Start Address bit 15
XADRS5.RGSAD14    14  Range Start Address bit 14
XADRS5.RGSAD13    13  Range Start Address bit 13
XADRS5.RGSAD12    12  Range Start Address bit 12
XADRS5.RGSAD11    11  Range Start Address bit 11
XADRS5.RGSAD10    10  Range Start Address bit 10
XADRS5.RGSAD9     9   Range Start Address bit 9
XADRS5.RGSAD8     8   Range Start Address bit 8
XADRS5.RGSAD7     7   Range Start Address bit 7
XADRS5.RGSAD6     6   Range Start Address bit 6
XADRS5.RGSAD5     5   Range Start Address bit 5
XADRS5.RGSAD4     4   Range Start Address bit 4
XADRS5.RGSZ3      3   Range Size Selection bit 3
XADRS5.RGSZ2      2   Range Size Selection bit 2
XADRS5.RGSZ1      1   Range Size Selection bit 1
XADRS5.RGSZ0      0   Range Size Selection bit 0
XADRS6           0xF01E   XBUS Address Select Register 6
XADRS6.RGSAD15    15  Range Start Address bit 15
XADRS6.RGSAD14    14  Range Start Address bit 14
XADRS6.RGSAD13    13  Range Start Address bit 13
XADRS6.RGSAD12    12  Range Start Address bit 12
XADRS6.RGSAD11    11  Range Start Address bit 11
XADRS6.RGSAD10    10  Range Start Address bit 10
XADRS6.RGSAD9     9   Range Start Address bit 9
XADRS6.RGSAD8     8   Range Start Address bit 8
XADRS6.RGSAD7     7   Range Start Address bit 7
XADRS6.RGSAD6     6   Range Start Address bit 6
XADRS6.RGSAD5     5   Range Start Address bit 5
XADRS6.RGSAD4     4   Range Start Address bit 4
XADRS6.RGSZ3      3   Range Size Selection bit 3
XADRS6.RGSZ2      2   Range Size Selection bit 2
XADRS6.RGSZ1      1   Range Size Selection bit 1
XADRS6.RGSZ0      0   Range Size Selection bit 0
XPERCON          0xF024   XBUS Peripheral Control Register
XPERCON.XPER7     7
XPERCON.XPER6     6
XPERCON.XPER5     5
IDMEM2           0xF076   Identifier
IDPROG           0xF078   Identifier
IDPROG.PROGVPP_15 15  Programming VPP Voltage - bit 15
IDPROG.PROGVPP_14 14  Programming VPP Voltage - bit 14
IDPROG.PROGVPP_13 13  Programming VPP Voltage - bit 13
IDPROG.PROGVPP_12 12  Programming VPP Voltage - bit 12
IDPROG.PROGVPP_11 11  Programming VPP Voltage - bit 11
IDPROG.PROGVPP_10 10  Programming VPP Voltage - bit 10
IDPROG.PROGVPP_9  9   Programming VPP Voltage - bit 9 
IDPROG.PROGVPP_8  8   Programming VPP Voltage - bit 8 
IDPROG.PROGVDD_7  7   Programming VDD Voltage - bit 7 
IDPROG.PROGVDD_6  6   Programming VDD Voltage - bit 6 
IDPROG.PROGVDD_5  5   Programming VDD Voltage - bit 5 
IDPROG.PROGVDD_4  4   Programming VDD Voltage - bit 4 
IDPROG.PROGVDD_3  3   Programming VDD Voltage - bit 3 
IDPROG.PROGVDD_2  2   Programming VDD Voltage - bit 2 
IDPROG.PROGVDD_1  1   Programming VDD Voltage - bit 1 
IDPROG.PROGVDD_0  0   Programming VDD Voltage - bit 0 
IDMEM            0xF07A   Identifier
IDMEM.Type_15     15  Type of on-chip Program Memory - bit 15
IDMEM.Type_14     14  Type of on-chip Program Memory - bit 14
IDMEM.Type_13     13  Type of on-chip Program Memory - bit 13
IDMEM.Type_12     12  Type of on-chip Program Memory - bit 12
IDMEM.Size_11     11  Size of on-chip Program Memory - bit 11
IDMEM.Size_10     10  Size of on-chip Program Memory - bit 10
IDMEM.Size_9      9   Size of on-chip Program Memory - bit 9 
IDMEM.Size_8      8   Size of on-chip Program Memory - bit 8 
IDMEM.Size_7      7   Size of on-chip Program Memory - bit 7 
IDMEM.Size_6      6   Size of on-chip Program Memory - bit 6 
IDMEM.Size_5      5   Size of on-chip Program Memory - bit 5 
IDMEM.Size_4      4   Size of on-chip Program Memory - bit 4 
IDMEM.Size_3      3   Size of on-chip Program Memory - bit 3 
IDMEM.Size_2      2   Size of on-chip Program Memory - bit 2 
IDMEM.Size_1      1   Size of on-chip Program Memory - bit 1 
IDMEM.Size_0      0   Size of on-chip Program Memory - bit 0 
IDCHIP           0xF07C   Identifier
IDCHIP.CHIPID_15  15  Device Identification - bit 15
IDCHIP.CHIPID_14  14  Device Identification - bit 14
IDCHIP.CHIPID_13  13  Device Identification - bit 13
IDCHIP.CHIPID_12  12  Device Identification - bit 12
IDCHIP.CHIPID_11  11  Device Identification - bit 11
IDCHIP.CHIPID_10  10  Device Identification - bit 10
IDCHIP.CHIPID_9   9   Device Identification - bit 9
IDCHIP.CHIPID_8   8   Device Identification - bit 8
IDCHIP.Revision_7 7   Device Revision Code - bit 7
IDCHIP.Revision_6 6   Device Revision Code - bit 6
IDCHIP.Revision_5 5   Device Revision Code - bit 5
IDCHIP.Revision_4 4   Device Revision Code - bit 4
IDCHIP.Revision_3 3   Device Revision Code - bit 3
IDCHIP.Revision_2 2   Device Revision Code - bit 2
IDCHIP.Revision_1 1   Device Revision Code - bit 1
IDCHIP.Revision_0 0   Device Revision Code - bit 0
IDMANUF          0xF07E   Identifier
IDMANUF.MANUF_15  15  Manufacturer - bit 15
IDMANUF.MANUF_14  14  Manufacturer - bit 14
IDMANUF.MANUF_13  13  Manufacturer - bit 13
IDMANUF.MANUF_12  12  Manufacturer - bit 12
IDMANUF.MANUF_11  11  Manufacturer - bit 11
IDMANUF.MANUF_10  10  Manufacturer - bit 10
IDMANUF.MANUF_9   9   Manufacturer - bit 9 
IDMANUF.MANUF_8   8   Manufacturer - bit 8 
IDMANUF.MANUF_7   7   Manufacturer - bit 7 
IDMANUF.MANUF_6   6   Manufacturer - bit 6 
IDMANUF.MANUF_5   5   Manufacturer - bit 5 
IDMANUF.DEPT_4    4   Department - bit 4 
IDMANUF.DEPT_3    3   Department - bit 3 
IDMANUF.DEPT_2    2   Department - bit 2 
IDMANUF.DEPT_1    1   Department - bit 1 
IDMANUF.DEPT_0    0   Department - bit 0 
SSCTB            0xF0B0   SSC Transmit Buffer (WO)
SSCRB            0xF0B2   SSC Receive Buffer (RO)
SSCBR            0xF0B4   SSC Baudrate Register
SSCCLC           0xF0B6   SSC Clock Control Register
SSCCLC.EXDISR     3   External Disable Request
SSCCLC.SUSPEN     2   Peripheral Suspend Enable Bit for OCDS
SSCCLC.SSCDISS    1   SSC Disable Status Bit
SSCCLC.SSCDISR    0   SSC Disable Request Bit
SCUSLC           0xF0C0   Security Level Control Register
SCUSLC.COMMAND_15 15
SCUSLC.COMMAND_14 14
SCUSLC.COMMAND_13 13
SCUSLC.COMMAND_12 12
SCUSLC.COMMAND_11 11
SCUSLC.COMMAND_10 10
SCUSLC.COMMAND_9  9 
SCUSLC.COMMAND_8  8 
SCUSLC.COMMAND_7  7 
SCUSLC.COMMAND_6  6 
SCUSLC.COMMAND_5  5 
SCUSLC.COMMAND_4  4 
SCUSLC.COMMAND_3  3 
SCUSLC.COMMAND_2  2 
SCUSLC.COMMAND_1  1 
SCUSLC.COMMAND_0  0 
SCUSLS           0xF0C2   Security Level Status Register
SCUSLS.STATE_15   15  Actual State - bit 15
SCUSLS.STATE_14   14  Actual State - bit 14
SCUSLS.STATE_13   13  Actual State - bit 13
SCUSLS.SL_12      12  Security Level - bit 12
SCUSLS.SL_11      11  Security Level - bit 11
SCUSLS.PASSWORD_7 7   Current Password - bit 7
SCUSLS.PASSWORD_6 6   Current Password - bit 6
SCUSLS.PASSWORD_5 5   Current Password - bit 5
SCUSLS.PASSWORD_4 4   Current Password - bit 4
SCUSLS.PASSWORD_3 3   Current Password - bit 3
SCUSLS.PASSWORD_2 2   Current Password - bit 2
SCUSLS.PASSWORD_1 1   Current Password - bit 1
SCUSLS.PASSWORD_0 0   Current Password - bit 0
RTCCLC           0xF0C8   RTC Clock Control Register
RTCCLC.EXDISR     3   External Disable Request
RTCCLC.SUSPEN     2   Peripheral Suspend Enable Bit for OCDS
RTCCLC.RTCDISS    1   RTC Disable Status Bit
RTCCLC.RTCDISR    0   RTC Disable Request Bit
RTCRELL          0xF0CC   RTC Timer Reload Register Low
RTCRELH          0xF0CE   RTC Timer Reload Register High
T14REL           0xF0D0   Timer 14 Reload Register
T14              0xF0D2   Timer 14 Register
RTCL             0xF0D4   RTC Timer Register Low
RTCH             0xF0D6   RTC Timer Register High
DTIDR            0xF0D8   Task ID register1)
DP0L             0xF100   80H P0L Direction Control Register
DP0L.DP0L7        7   Port direction register DP0L bit 7
DP0L.DP0L6        6   Port direction register DP0L bit 6
DP0L.DP0L5        5   Port direction register DP0L bit 5
DP0L.DP0L4        4   Port direction register DP0L bit 4
DP0L.DP0L3        3   Port direction register DP0L bit 3
DP0L.DP0L2        2   Port direction register DP0L bit 2
DP0L.DP0L1        1   Port direction register DP0L bit 1
DP0L.DP0L0        0   Port direction register DP0L bit 0
DP0H             0xF102   81H P0H Direction Control Register
DP0H.DP0H7        7   Port direction register DP0H bit 7
DP0H.DP0H6        6   Port direction register DP0H bit 6
DP0H.DP0H5        5   Port direction register DP0H bit 5
DP0H.DP0H4        4   Port direction register DP0H bit 4
DP0H.DP0H3        3   Port direction register DP0H bit 3
DP0H.DP0H2        2   Port direction register DP0H bit 2
DP0H.DP0H1        1   Port direction register DP0H bit 1
DP0H.DP0H0        0   Port direction register DP0H bit 0
DP1L             0xF104   82H P1L Direction Control Register
DP1L.DP1L7        7   Port direction register DP1L bit 7
DP1L.DP1L6        6   Port direction register DP1L bit 6
DP1L.DP1L5        5   Port direction register DP1L bit 5
DP1L.DP1L4        4   Port direction register DP1L bit 4
DP1L.DP1L3        3   Port direction register DP1L bit 3
DP1L.DP1L2        2   Port direction register DP1L bit 2
DP1L.DP1L1        1   Port direction register DP1L bit 1
DP1L.DP1L0        0   Port direction register DP1L bit 0
DP1H             0xF106   83H P1H Direction Control Register
DP1H.DP1H7        7   Port direction register DP1H bit 7
DP1H.DP1H6        6   Port direction register DP1H bit 6
DP1H.DP1H5        5   Port direction register DP1H bit 5
DP1H.DP1H4        4   Port direction register DP1H bit 4
DP1H.DP1H3        3   Port direction register DP1H bit 3
DP1H.DP1H2        2   Port direction register DP1H bit 2
DP1H.DP1H1        1   Port direction register DP1H bit 1
DP1H.DP1H0        0   Port direction register DP1L bit 0
RP0H             0xF108   84H System Startup Configuration Register (RO)
RP0H.CLKCFG_7     7   Clock Generation Mode Configuration - bit 7
RP0H.CLKCFG_6     6   Clock Generation Mode Configuration - bit 6
RP0H.CLKCFG_5     5   Clock Generation Mode Configuration - bit 5
RP0H.SALSEL_4     4   Segment Address Line Selection - bit 4
RP0H.SALSEL_3     3   Segment Address Line Selection - bit 3
RP0H.CSSEL_2      2   Chip Select Line Selection - bit 2
RP0H.CSSEL_1      1   Chip Select Line Selection - bit 1
RP0H.WRC          0   Write Configuration
XBCON1           0xF114   8AH XBUS Control register 1: reserved
XBCON2           0xF116   8BH XBUS Control register 2: USB module
XBCON3           0xF118   8CH XBUS Control register 3: EPEC module
XBCON4           0xF11A   8DH XBUS Control register 4: reserved
XBCON5           0xF11C   8EH XBUS Control register 5: reserved
XBCON6           0xF11E   8FH XBUS Control register 6: reserved
UTD3IC           0xF160   B0H UDC TX Done3  Interrupt Control Register
UTD3IC.UTD3IR     7   Interrupt Request Flag
UTD3IC.UTD3IE     6   Interrupt Enable Control Bit
UTD3IC.ILVL_5     5   Interrupt Priority Level - bit 5
UTD3IC.ILVL_4     4   Interrupt Priority Level - bit 4
UTD3IC.ILVL_3     3   Interrupt Priority Level - bit 3
UTD3IC.ILVL_2     2   Interrupt Priority Level - bit 2
UTD3IC.GLVL_1     1   Group Level - bit 1
UTD3IC.GLVL_0     0   Group Level - bit 0
UTD4IC           0xF162   B1H UDC TX Done4  Interrupt Control Register
UTD4IC.UTD4IR     7   Interrupt Request Flag
UTD4IC.UTD4IE     6   Interrupt Enable Control Bit
UTD4IC.ILVL_5     5   Interrupt Priority Level - bit 5
UTD4IC.ILVL_4     4   Interrupt Priority Level - bit 4
UTD4IC.ILVL_3     3   Interrupt Priority Level - bit 3
UTD4IC.ILVL_2     2   Interrupt Priority Level - bit 2
UTD4IC.GLVL_1     1   Group Level - bit 1
UTD4IC.GLVL_0     0   Group Level - bit 0
UTD5IC           0xF164   B2H UDC TX Done5  Interrupt Control Register
UTD5IC.UTD5IR     7   Interrupt Request Flag
UTD5IC.UTD5IE     6   Interrupt Enable Control Bit
UTD5IC.ILVL_5     5   Interrupt Priority Level - bit 5
UTD5IC.ILVL_4     4   Interrupt Priority Level - bit 4
UTD5IC.ILVL_3     3   Interrupt Priority Level - bit 3
UTD5IC.ILVL_2     2   Interrupt Priority Level - bit 2
UTD5IC.GLVL_1     1   Group Level - bit 1
UTD5IC.GLVL_0     0   Group Level - bit 0
UTD6IC           0xF166   B3H UDC TX Done6  Interrupt Control Register
UTD6IC.UTD6IR     7   Interrupt Request Flag
UTD6IC.UTD6IE     6   Interrupt Enable Control Bit
UTD6IC.ILVL_5     5   Interrupt Priority Level - bit 5
UTD6IC.ILVL_4     4   Interrupt Priority Level - bit 4
UTD6IC.ILVL_3     3   Interrupt Priority Level - bit 3
UTD6IC.ILVL_2     2   Interrupt Priority Level - bit 2
UTD6IC.GLVL_1     1   Group Level - bit 1
UTD6IC.GLVL_0     0   Group Level - bit 0
UTD7IC           0xF168   B4H UDC TX Done7  Interrupt Control Register
UTD7IC.UTD7IR     7   Interrupt Request Flag
UTD7IC.UTD7IE     6   Interrupt Enable Control Bit
UTD7IC.ILVL_5     5   Interrupt Priority Level - bit 5
UTD7IC.ILVL_4     4   Interrupt Priority Level - bit 4
UTD7IC.ILVL_3     3   Interrupt Priority Level - bit 3
UTD7IC.ILVL_2     2   Interrupt Priority Level - bit 2
UTD7IC.GLVL_1     1   Group Level - bit 1
UTD7IC.GLVL_0     0   Group Level - bit 0
URXRIC           0xF16A   B5H UDC RXRR  Interrupt Control Register
URXRIC.URXRIR     7   Interrupt Request Flag          
URXRIC.URXRIE     6   Interrupt Enable Control Bit    
URXRIC.ILVL_5     5   Interrupt Priority Level - bit 5
URXRIC.ILVL_4     4   Interrupt Priority Level - bit 4
URXRIC.ILVL_3     3   Interrupt Priority Level - bit 3
URXRIC.ILVL_2     2   Interrupt Priority Level - bit 2
URXRIC.GLVL_1     1   Group Level - bit 1             
URXRIC.GLVL_0     0   Group Level - bit 0             
UTXRIC           0xF16C   B6H UDC TXWR  Interrupt Control Register
UTXRIC.UTXRIR     7   Interrupt Request Flag          
UTXRIC.UTXRIE     6   Interrupt Enable Control Bit    
UTXRIC.ILVL_5     5   Interrupt Priority Level - bit 5
UTXRIC.ILVL_4     4   Interrupt Priority Level - bit 4
UTXRIC.ILVL_3     3   Interrupt Priority Level - bit 3
UTXRIC.ILVL_2     2   Interrupt Priority Level - bit 2
UTXRIC.GLVL_1     1   Group Level - bit 1             
UTXRIC.GLVL_0     0   Group Level - bit 0
UCFGVIC          0xF16E   B7H UDC Config Val Interrupt Control Register
UCFGVIC.UCFGVIR   7   Interrupt Request Flag          
UCFGVIC.UCFGVIE   6   Interrupt Enable Control Bit    
UCFGVIC.ILVL_5    5   Interrupt Priority Level - bit 5
UCFGVIC.ILVL_4    4   Interrupt Priority Level - bit 4
UCFGVIC.ILVL_3    3   Interrupt Priority Level - bit 3
UCFGVIC.ILVL_2    2   Interrupt Priority Level - bit 2
UCFGVIC.GLVL_1    1   Group Level - bit 1             
UCFGVIC.GLVL_0    0   Group Level - bit 0
USOFIC           0xF170   B8H UDC Start of Frame Interrupt Control Register
USOFIC.USOFIR     7   Interrupt Request Flag          
USOFIC.USOFIE     6   Interrupt Enable Control Bit    
USOFIC.ILVL_5     5   Interrupt Priority Level - bit 5
USOFIC.ILVL_4     4   Interrupt Priority Level - bit 4
USOFIC.ILVL_3     3   Interrupt Priority Level - bit 3
USOFIC.ILVL_2     2   Interrupt Priority Level - bit 2
USOFIC.GLVL_1     1   Group Level - bit 1             
USOFIC.GLVL_0     0   Group Level - bit 0
USSOIC           0xF172   B9H UDC Suspend  off Interrupt Control Register
USSOIC.USSOIR     7   Interrupt Request Flag          
USSOIC.USSOIE     6   Interrupt Enable Control Bit    
USSOIC.ILVL_5     5   Interrupt Priority Level - bit 5
USSOIC.ILVL_4     4   Interrupt Priority Level - bit 4
USSOIC.ILVL_3     3   Interrupt Priority Level - bit 3
USSOIC.ILVL_2     2   Interrupt Priority Level - bit 2
USSOIC.GLVL_1     1   Group Level - bit 1             
USSOIC.GLVL_0     0   Group Level - bit 0
USSIC            0xF174   BAH UDC Suspend  Interrupt Control Register
USSIC.USSIR       7   Interrupt Request Flag
USSIC.USSIE       6   Interrupt Enable Control Bit
USSIC.ILVL_5      5   Interrupt Priority Level - bit 5
USSIC.ILVL_4      4   Interrupt Priority Level - bit 4
USSIC.ILVL_3      3   Interrupt Priority Level - bit 3
USSIC.ILVL_2      2   Interrupt Priority Level - bit 2
USSIC.GLVL_1      1   Group Level - bit 1
USSIC.GLVL_0      0   Group Level - bit 0
ULCDIC           0xF176   BBH UDC Load Config Done  Interrupt Control Register
ULCDIC.ULCDIR     7   Interrupt Request Flag          
ULCDIC.ULCDIE     6   Interrupt Enable Control Bit    
ULCDIC.ILVL_5     5   Interrupt Priority Level - bit 5
ULCDIC.ILVL_4     4   Interrupt Priority Level - bit 4
ULCDIC.ILVL_3     3   Interrupt Priority Level - bit 3
ULCDIC.ILVL_2     2   Interrupt Priority Level - bit 2
ULCDIC.GLVL_1     1   Group Level - bit 1             
ULCDIC.GLVL_0     0   Group Level - bit 0
USETIC           0xF178   BCH UDC SETUP Interrupt Control Register
USETIC.USETIR     7   Interrupt Request Flag          
USETIC.USETIE     6   Interrupt Enable Control Bit    
USETIC.ILVL_5     5   Interrupt Priority Level - bit 5
USETIC.ILVL_4     4   Interrupt Priority Level - bit 4
USETIC.ILVL_3     3   Interrupt Priority Level - bit 3
USETIC.ILVL_2     2   Interrupt Priority Level - bit 2
USETIC.GLVL_1     1   Group Level - bit 1             
USETIC.GLVL_0     0   Group Level - bit 0
URD0IC           0xF17A   BDH UDC RX Done0  Interrupt Control Register
URD0IC.URD0IR     7   Interrupt Request Flag          
URD0IC.URD0IE     6   Interrupt Enable Control Bit    
URD0IC.ILVL_5     5   Interrupt Priority Level - bit 5
URD0IC.ILVL_4     4   Interrupt Priority Level - bit 4
URD0IC.ILVL_3     3   Interrupt Priority Level - bit 3
URD0IC.ILVL_2     2   Interrupt Priority Level - bit 2
URD0IC.GLVL_1     1   Group Level - bit 1             
URD0IC.GLVL_0     0   Group Level - bit 0
EPECIC           0xF17C   BEH EPEC Interrupt
PECCLIC          0xF180   C0H PEC Channel Link Interrupt Control Register
PECCLIC.PECCLIR   7   Interrupt Request Flag          
PECCLIC.PECCLIE   6   Interrupt Enable Control Bit    
PECCLIC.ILVL_5    5   Interrupt Priority Level - bit 5
PECCLIC.ILVL_4    4   Interrupt Priority Level - bit 4
PECCLIC.ILVL_3    3   Interrupt Priority Level - bit 3
PECCLIC.ILVL_2    2   Interrupt Priority Level - bit 2
PECCLIC.GLVL_1    1   Group Level - bit 1             
PECCLIC.GLVL_0    0   Group Level - bit 0
RTC_INTIC        0xF184   RTC_INT Sub Node Interrupt Register
XP0IC            0xF186   X-Bus Peripheral 0 UDC TXWR Interrupt Control Register
XP0IC.XP0IR       7   Interrupt Request Flag
XP0IC.XP0IE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
XP0IC.ILVL_5      5   Interrupt Priority Level - bit 5
XP0IC.ILVL_4      4   Interrupt Priority Level - bit 4
XP0IC.ILVL_3      3   Interrupt Priority Level - bit 3
XP0IC.ILVL_2      2   Interrupt Priority Level - bit 2
XP0IC.GLVL_1      1   Group Level - bit 1
XP0IC.GLVL_0      0   Group Level - bit 0
ABENDIC          0xF18C   ASC Autobaud End Interrupt Control Register
ABENDIC.ABENDIR   7   Interrupt Request Flag
ABENDIC.ABENDIE   6   Interrupt Enable Control Bit (individually enables/disables a specific source)
ABENDIC.ILVL_5    5   Interrupt Priority Level - bit 5
ABENDIC.ILVL_4    4   Interrupt Priority Level - bit 4
ABENDIC.ILVL_3    3   Interrupt Priority Level - bit 3
ABENDIC.ILVL_2    2   Interrupt Priority Level - bit 2
ABENDIC.GLVL_1    1   Group Level - bit 1
ABENDIC.GLVL_0    0   Group Level - bit 0
XP1IC            0xF18E   X-Bus Peripheral 1 EPEC Interrupt Control Register
XP1IC.XP1IR       7   Interrupt Request Flag
XP1IC.XP1IE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
XP1IC.ILVL_5      5   Interrupt Priority Level - bit 5
XP1IC.ILVL_4      4   Interrupt Priority Level - bit 4
XP1IC.ILVL_3      3   Interrupt Priority Level - bit 3
XP1IC.ILVL_2      2   Interrupt Priority Level - bit 2
XP1IC.GLVL_1      1   Group Level - bit 1
XP1IC.GLVL_0      0   Group Level - bit 0
ABSTIC           0xF194   ASC Autobaud Start Interrupt Control Register
ABSTIC.ABSTIR     7   Interrupt Request Flag
ABSTIC.ABSTIE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
ABSTIC.ILVL_5     5   Interrupt Priority Level - bit 5
ABSTIC.ILVL_4     4   Interrupt Priority Level - bit 4
ABSTIC.ILVL_3     3   Interrupt Priority Level - bit 3
ABSTIC.ILVL_2     2   Interrupt Priority Level - bit 2
ABSTIC.GLVL_1     1   Group Level - bit 1
ABSTIC.GLVL_0     0   Group Level - bit 0
RES6IC           0xF19A   reserved
S0TBIC           0xF19C   Serial Channel 0 Transmit Buffer IC Register
XP3IC            0xF19E   X-Bus Peripheral 3 PLL/RTC Interrupt Control Register
XP3IC.XP7IR       7   Interrupt Request Flag
XP3IC.XP7IE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
XP3IC.ILVL_5      5   Interrupt Priority Level - bit 5
XP3IC.ILVL_4      4   Interrupt Priority Level - bit 4
XP3IC.ILVL_3      3   Interrupt Priority Level - bit 3
XP3IC.ILVL_2      2   Interrupt Priority Level - bit 2
XP3IC.GLVL_1      1   Group Level - bit 1
XP3IC.GLVL_0      0   Group Level - bit 0
EXICON           0xF1C0   External Interrupt Control Register
EXICON.EXI7ES_15  15  External Interrupt 15 Edge Selection Field - bit 15
EXICON.EXI7ES_14  14  External Interrupt 14 Edge Selection Field - bit 14
EXICON.EXI6ES_13  13  External Interrupt 13 Edge Selection Field - bit 13
EXICON.EXI6ES_12  12  External Interrupt 12 Edge Selection Field - bit 12
EXICON.EXI5ES_11  11  External Interrupt 11 Edge Selection Field - bit 11
EXICON.EXI5ES_10  10  External Interrupt 10 Edge Selection Field - bit 10
EXICON.EXI4ES_9   9   External Interrupt 9 Edge Selection Field - bit 9 
EXICON.EXI4ES_8   8   External Interrupt 8 Edge Selection Field - bit 8 
EXICON.EXI3ES_7   7   External Interrupt 7 Edge Selection Field - bit 7 
EXICON.EXI3ES_6   6   External Interrupt 6 Edge Selection Field - bit 6 
EXICON.EXI2ES_5   5   External Interrupt 5 Edge Selection Field - bit 5 
EXICON.EXI2ES_4   4   External Interrupt 4 Edge Selection Field - bit 4 
EXICON.EXI1ES_3   3   External Interrupt 3 Edge Selection Field - bit 3 
EXICON.EXI1ES_2   2   External Interrupt 2 Edge Selection Field - bit 2 
EXICON.EXI0ES_1   1   External Interrupt 1 Edge Selection Field - bit 1 
EXICON.EXI0ES_0   0   External Interrupt 0 Edge Selection Field - bit 0 
ODP2             0xF1C2   Port 2 Open Drain Control Register
ODP2.ODP2_1       1   Port 2 Open Drain control register bit 1
ODP2.ODP2_0       0   Port 2 Open Drain control register bit 0
ODP3             0xF1C6   Port 3 Open Drain Control Register
ODP3.ODP3_15      15  Port 3 Open Drain control register bit 15
ODP3.ODP3_13      13  Port 3 Open Drain control register bit 13
ODP3.ODP3_11      11  Port 3 Open Drain control register bit 11
ODP3.ODP3_10      10  Port 3 Open Drain control register bit 10
ODP3.ODP3_9       9   Port 3 Open Drain control register bit 9 
ODP3.ODP3_8       8   Port 3 Open Drain control register bit 8 
ODP3.ODP3_6       6   Port 3 Open Drain control register bit 6 
ODP3.ODP3_5       5   Port 3 Open Drain control register bit 5 
ODP3.ODP3_3       3   Port 3 Open Drain control register bit 3 
RTCISNC          0xF1C8   RTC Interrupt Sub Node Control Register
RTCISNC.RTC3IR    9   RTC3 Interrupt Request Flag (bit protected)
RTCISNC.RTC3IE    8   RTC3 Interrupt Enable Control Bit
RTCISNC.RTC2IR    7   RTC2 Interrupt Request Flag (bit protected)
RTCISNC.RTC2IE    6   RTC2 Interrupt Enable Control Bit          
RTCISNC.RTC1IR    5   RTC1 Interrupt Request Flag (bit protected)
RTCISNC.RTC1IE    4   RTC1 Interrupt Enable Control Bit          
RTCISNC.RTC0IR    3   RTC0 Interrupt Request Flag (bit protected)
RTCISNC.RTC0IE    2   RTC0 Interrupt Enable Control Bit          
RTCISNC.T14IR     1   T14 Overflow Interrupt Request Flag (bit protected)
RTCISNC.T14IE     0   T14 Overflow Interrupt Enable Control Bit
ODP4             0xF1CA   Port 4 Open Drain Control Register
ODP4.ODP4_4       4   Port 4 Open Drain control register bit 4 
ODP4.ODP4_3       3   Port 4 Open Drain control register bit 3 
ODP4.ODP4_2       2   Port 4 Open Drain control register bit 2 
ODP4.ODP4_1       1   Port 4 Open Drain control register bit 1 
ODP4.ODP4_0       0   Port 4 Open Drain control register bit 0 
RTCCON           0xF1CC   RTC Control Register
RTCCON.ACCPOS     15  RTC register access possible
RTCCON.T14INC     3   Increment T14 Timer Value
RTCCON.T14DEC     2   Decrement T14 Timer Value
RTCCON.RTCPRE     1   RTC Input Source Prescaler enable
RTCCON.RTCR       0   RTC Run Bit
ODP6             0xF1CE   Port 6 Open Drain Control Register
ODP6.ODP6_7       7   Port 6 Open Drain control register bit 7
ODP6.ODP6_6       6   Port 6 Open Drain control register bit 6
ODP6.ODP6_5       5   Port 6 Open Drain control register bit 5
ODP6.ODP6_3       3   Port 6 Open Drain control register bit 3
ODP6.ODP6_2       2   Port 6 Open Drain control register bit 2
ODP6.ODP6_1       1   Port 6 Open Drain control register bit 1
ODP6.ODP6_0       0   Port 6 Open Drain control register bit 0
SYSCON2          0xF1D0   System Configuration Register 2/ Clock Control
SYSCON2.CLKLOCK   15  Clock Signal Status Bit
SYSCON2.CLKREL_14 14  Reload Counter Value for Slowdown Divider - 14
SYSCON2.CLKREL_13 13  Reload Counter Value for Slowdown Divider - 13
SYSCON2.CLKREL_12 12  Reload Counter Value for Slowdown Divider - 12
SYSCON2.CLKREL_11 11  Reload Counter Value for Slowdown Divider - 11
SYSCON2.CLKREL_10 10  Reload Counter Value for Slowdown Divider - 10
SYSCON2.CLKCON_9  9   Clock State Control - bit 9
SYSCON2.CLKCON_8  8   Clock State Control - bit 8
SYSCON2.SCS       7   SDD Clock Source
SYSCON2.RCS       6   RTC Clock Source
SYSCON2.PDCON_5   5   Power Down Control - bit 5
SYSCON2.PDCON_4   4   Power Down Control - bit 4
SYSCON3          0xF1D4   System Configuration Register 3/ Periph. Managem.
SYSCON3.PCDDIS    15  Peripheral Clock Driver
SYSCON3.PLLDIS    13  PLL Disable Flag
SYSCON3.USBTDIS_12 12 USB Transceiver Disable Flag - bit 12
SYSCON3.USBTDIS_11 11 USB Transceiver Disable Flag - bit 11
SYSCON3.PERDIS8   8   Peripheral Disable Flag 0 - 14 - bit 8
SYSCON3.PERDIS7   7   Peripheral Disable Flag 0 - 14 - bit 7
SYSCON3.PERDIS6   6   Peripheral Disable Flag 0 - 14 - bit 6
SYSCON3.PERDIS3   3   Peripheral Disable Flag 0 - 14 - bit 3
SYSCON3.PERDIS2   2   Peripheral Disable Flag 0 - 14 - bit 2
SYSCON3.PERDIS1   1   Peripheral Disable Flag 0 - 14 - bit 1
SYSCON3.PERDIS0   0   Peripheral Disable Flag 0 - 14 - bit 0
reserv_F1D6      0xF1D6   reserved - do not use
reserv_F1D8      0xF1D8   reserved - do not use
EXISEL           0xF1DA   External Interrupt Select Register
SYSCON1          0xF1DC   System Configuration Register 1/ Sleep Mode
SYSCON1.SLEEPCON_1 1  SLEEP Mode Configuration - bit 1
SYSCON1.SLEEPCON_0 0  SLEEP Mode Configuration - bit 0
ISNC             0xF1DE   Interrupt Sub Node Control Register
ISNC.PLLIE        3   PLL Interrupt Enable Control Bit
ISNC.PLLIR        2   PLL Interrupt Request Flag
ISNC.RTCT14IE     1   T14 Overflow Interrupt Enable Control Bit
ISNC.RTCT14IR     0   T14 Overflow Interrupt Request Flag
DPP0             0xFE00   CPU Data Page Pointer 0 Register (10 bits)
DPP0.DPP0PN_9     9   Data Page Number of DPP0 - bit 9
DPP0.DPP0PN_8     8   Data Page Number of DPP0 - bit 8
DPP0.DPP0PN_7     7   Data Page Number of DPP0 - bit 7
DPP0.DPP0PN_6     6   Data Page Number of DPP0 - bit 6
DPP0.DPP0PN_5     5   Data Page Number of DPP0 - bit 5
DPP0.DPP0PN_4     4   Data Page Number of DPP0 - bit 4
DPP0.DPP0PN_3     3   Data Page Number of DPP0 - bit 3
DPP0.DPP0PN_2     2   Data Page Number of DPP0 - bit 2
DPP0.DPP0PN_1     1   Data Page Number of DPP0 - bit 1
DPP0.DPP0PN_0     0   Data Page Number of DPP0 - bit 0
DPP1             0xFE02   CPU Data Page Pointer 1 Register (10 bits)
DPP1.DPP1PN_9     9   Data Page Number of DPP1 - bit 9
DPP1.DPP1PN_8     8   Data Page Number of DPP1 - bit 8
DPP1.DPP1PN_7     7   Data Page Number of DPP1 - bit 7
DPP1.DPP1PN_6     6   Data Page Number of DPP1 - bit 6
DPP1.DPP1PN_5     5   Data Page Number of DPP1 - bit 5
DPP1.DPP1PN_4     4   Data Page Number of DPP1 - bit 4
DPP1.DPP1PN_3     3   Data Page Number of DPP1 - bit 3
DPP1.DPP1PN_2     2   Data Page Number of DPP1 - bit 2
DPP1.DPP1PN_1     1   Data Page Number of DPP1 - bit 1
DPP1.DPP1PN_0     0   Data Page Number of DPP1 - bit 0
DPP2             0xFE04   CPU Data Page Pointer 2 Register (10 bits)
DPP2.DPP2PN_9     9   Data Page Number of DPP2 - bit 9
DPP2.DPP2PN_8     8   Data Page Number of DPP2 - bit 8
DPP2.DPP2PN_7     7   Data Page Number of DPP2 - bit 7
DPP2.DPP2PN_6     6   Data Page Number of DPP2 - bit 6
DPP2.DPP2PN_5     5   Data Page Number of DPP2 - bit 5
DPP2.DPP2PN_4     4   Data Page Number of DPP2 - bit 4
DPP2.DPP2PN_3     3   Data Page Number of DPP2 - bit 3
DPP2.DPP2PN_2     2   Data Page Number of DPP2 - bit 2
DPP2.DPP2PN_1     1   Data Page Number of DPP2 - bit 1
DPP2.DPP2PN_0     0   Data Page Number of DPP2 - bit 0
DPP3             0xFE06   CPU Data Page Pointer 3 Register (10 bits)
DPP3.DPP3PN_9     9   Data Page Number of DPP3 - bit 9
DPP3.DPP3PN_8     8   Data Page Number of DPP3 - bit 8
DPP3.DPP3PN_7     7   Data Page Number of DPP3 - bit 7
DPP3.DPP3PN_6     6   Data Page Number of DPP3 - bit 6
DPP3.DPP3PN_5     5   Data Page Number of DPP3 - bit 5
DPP3.DPP3PN_4     4   Data Page Number of DPP3 - bit 4
DPP3.DPP3PN_3     3   Data Page Number of DPP3 - bit 3
DPP3.DPP3PN_2     2   Data Page Number of DPP3 - bit 2
DPP3.DPP3PN_1     1   Data Page Number of DPP3 - bit 1
DPP3.DPP3PN_0     0   Data Page Number of DPP3 - bit 0
CSP              0xFE08   CPU Code Segment Pointer Register (8 bits)
CSP.SEGNR_7       7   Segment Number - bit 7
CSP.SEGNR_6       6   Segment Number - bit 6
CSP.SEGNR_5       5   Segment Number - bit 5
CSP.SEGNR_4       4   Segment Number - bit 4
CSP.SEGNR_3       3   Segment Number - bit 3
CSP.SEGNR_2       2   Segment Number - bit 2
CSP.SEGNR_1       1   Segment Number - bit 1
CSP.SEGNR_0       0   Segment Number - bit 0
EMUCON           0xFE0A   Emulation Control Register
MDH              0xFE0C   CPU Multiply Divide Register - High Word
MDH.mdh_15        15
MDH.mdh_14        14
MDH.mdh_13        13
MDH.mdh_12        12
MDH.mdh_11        11
MDH.mdh_10        10
MDH.mdh_9         9 
MDH.mdh_8         8 
MDH.mdh_7         7 
MDH.mdh_6         6 
MDH.mdh_5         5 
MDH.mdh_4         4 
MDH.mdh_3         3 
MDH.mdh_2         2 
MDH.mdh_1         1 
MDH.mdh_0         0 
MDL              0xFE0E   CPU Multiply Divide Register - Low Word
MDL.MDL_15        15
MDL.MDL_14        14
MDL.MDL_13        13
MDL.MDL_12        12
MDL.MDL_11        11
MDL.MDL_10        10
MDL.MDL_9         9 
MDL.MDL_8         8 
MDL.MDL_7         7 
MDL.MDL_6         6 
MDL.MDL_5         5 
MDL.MDL_4         4 
MDL.MDL_3         3 
MDL.MDL_2         2 
MDL.MDL_1         1 
MDL.MDL_0         0 
CP               0xFE10   CPU Context Pointer Register
CP.cp_11          11  Modifiable portion of register CP - bit 11
CP.cp_10          10  Modifiable portion of register CP - bit 10
CP.cp_9           9   Modifiable portion of register CP - bit 9
CP.cp_8           8   Modifiable portion of register CP - bit 8
CP.cp_7           7   Modifiable portion of register CP - bit 7
CP.cp_6           6   Modifiable portion of register CP - bit 6
CP.cp_5           5   Modifiable portion of register CP - bit 5
CP.cp_4           4   Modifiable portion of register CP - bit 4
CP.cp_3           3   Modifiable portion of register CP - bit 3
CP.cp_2           2   Modifiable portion of register CP - bit 2
CP.cp_1           1   Modifiable portion of register CP - bit 1
SP               0xFE12   CPU System Stack Pointer Register
SP.sp_11          11  Modifiable portion of register SP - bit 11
SP.sp_10          10  Modifiable portion of register SP - bit 10
SP.sp_9           9   Modifiable portion of register SP - bit 9
SP.sp_8           8   Modifiable portion of register SP - bit 8
SP.sp_7           7   Modifiable portion of register SP - bit 7
SP.sp_6           6   Modifiable portion of register SP - bit 6
SP.sp_5           5   Modifiable portion of register SP - bit 5
SP.sp_4           4   Modifiable portion of register SP - bit 4
SP.sp_3           3   Modifiable portion of register SP - bit 3
SP.sp_2           2   Modifiable portion of register SP - bit 2
SP.sp_1           1   Modifiable portion of register SP - bit 1
STKOV            0xFE14   CPU Stack Overflow Pointer Register
STKOV.stkov_11    11  Modifiable portion of register STKOV - bit 11
STKOV.stkov_10    10  Modifiable portion of register STKOV - bit 10
STKOV.stkov_9     9   Modifiable portion of register STKOV - bit 9
STKOV.stkov_8     8   Modifiable portion of register STKOV - bit 8
STKOV.stkov_7     7   Modifiable portion of register STKOV - bit 7
STKOV.stkov_6     6   Modifiable portion of register STKOV - bit 6
STKOV.stkov_5     5   Modifiable portion of register STKOV - bit 5
STKOV.stkov_4     4   Modifiable portion of register STKOV - bit 4
STKOV.stkov_3     3   Modifiable portion of register STKOV - bit 3
STKOV.stkov_2     2   Modifiable portion of register STKOV - bit 2
STKOV.stkov_1     1   Modifiable portion of register STKOV - bit 1
STKUN            0xFE16   CPU Stack Underflow Pointer Register
STKUN.stkun_11    11  Modifiable portion of register STKUN - bit 11
STKUN.stkun_10    10  Modifiable portion of register STKUN - bit 10
STKUN.stkun_9     9   Modifiable portion of register STKUN - bit 9
STKUN.stkun_8     8   Modifiable portion of register STKUN - bit 8
STKUN.stkun_7     7   Modifiable portion of register STKUN - bit 7
STKUN.stkun_6     6   Modifiable portion of register STKUN - bit 6
STKUN.stkun_5     5   Modifiable portion of register STKUN - bit 5
STKUN.stkun_4     4   Modifiable portion of register STKUN - bit 4
STKUN.stkun_3     3   Modifiable portion of register STKUN - bit 3
STKUN.stkun_2     2   Modifiable portion of register STKUN - bit 2
STKUN.stkun_1     1   Modifiable portion of register STKUN - bit 1
ADDRSEL1         0xFE18   Address Select Register 1
ADDRSEL1.RGSAD15  15  Range Start Address bit 15
ADDRSEL1.RGSAD14  14  Range Start Address bit 14
ADDRSEL1.RGSAD13  13  Range Start Address bit 13
ADDRSEL1.RGSAD12  12  Range Start Address bit 12
ADDRSEL1.RGSAD11  11  Range Start Address bit 11
ADDRSEL1.RGSAD10  10  Range Start Address bit 10
ADDRSEL1.RGSAD9   9   Range Start Address bit 9 
ADDRSEL1.RGSAD8   8   Range Start Address bit 8 
ADDRSEL1.RGSAD7   7   Range Start Address bit 7 
ADDRSEL1.RGSAD6   6   Range Start Address bit 6 
ADDRSEL1.RGSAD5   5   Range Start Address bit 5 
ADDRSEL1.RGSAD4   4   Range Start Address bit 4 
ADDRSEL1.RGSZ3    3   Range Size Selection bit 3
ADDRSEL1.RGSZ2    2   Range Size Selection bit 2
ADDRSEL1.RGSZ1    1   Range Size Selection bit 1
ADDRSEL1.RGSZ0    0   Range Size Selection bit 0
ADDRSEL2         0xFE1A   Address Select Register 2
ADDRSEL2.RGSAD15  15  Range Start Address bit 15
ADDRSEL2.RGSAD14  14  Range Start Address bit 14
ADDRSEL2.RGSAD13  13  Range Start Address bit 13
ADDRSEL2.RGSAD12  12  Range Start Address bit 12
ADDRSEL2.RGSAD11  11  Range Start Address bit 11
ADDRSEL2.RGSAD10  10  Range Start Address bit 10
ADDRSEL2.RGSAD9   9   Range Start Address bit 9 
ADDRSEL2.RGSAD8   8   Range Start Address bit 8 
ADDRSEL2.RGSAD7   7   Range Start Address bit 7 
ADDRSEL2.RGSAD6   6   Range Start Address bit 6 
ADDRSEL2.RGSAD5   5   Range Start Address bit 5 
ADDRSEL2.RGSAD4   4   Range Start Address bit 4 
ADDRSEL2.RGSZ3    3   Range Size Selection bit 3
ADDRSEL2.RGSZ2    2   Range Size Selection bit 2
ADDRSEL2.RGSZ1    1   Range Size Selection bit 1
ADDRSEL2.RGSZ0    0   Range Size Selection bit 0
ADDRSEL3         0xFE1C   Address Select Register 3
ADDRSEL3.RGSAD15  15  Range Start Address bit 15
ADDRSEL3.RGSAD14  14  Range Start Address bit 14
ADDRSEL3.RGSAD13  13  Range Start Address bit 13
ADDRSEL3.RGSAD12  12  Range Start Address bit 12
ADDRSEL3.RGSAD11  11  Range Start Address bit 11
ADDRSEL3.RGSAD10  10  Range Start Address bit 10
ADDRSEL3.RGSAD9   9   Range Start Address bit 9 
ADDRSEL3.RGSAD8   8   Range Start Address bit 8 
ADDRSEL3.RGSAD7   7   Range Start Address bit 7 
ADDRSEL3.RGSAD6   6   Range Start Address bit 6 
ADDRSEL3.RGSAD5   5   Range Start Address bit 5 
ADDRSEL3.RGSAD4   4   Range Start Address bit 4 
ADDRSEL3.RGSZ3    3   Range Size Selection bit 3
ADDRSEL3.RGSZ2    2   Range Size Selection bit 2
ADDRSEL3.RGSZ1    1   Range Size Selection bit 1
ADDRSEL3.RGSZ0    0   Range Size Selection bit 0
ADDRSEL4         0xFE1E   Address Select Register 4
ADDRSEL4.RGSAD15  15  Range Start Address bit 15
ADDRSEL4.RGSAD14  14  Range Start Address bit 14
ADDRSEL4.RGSAD13  13  Range Start Address bit 13
ADDRSEL4.RGSAD12  12  Range Start Address bit 12
ADDRSEL4.RGSAD11  11  Range Start Address bit 11
ADDRSEL4.RGSAD10  10  Range Start Address bit 10
ADDRSEL4.RGSAD9   9   Range Start Address bit 9 
ADDRSEL4.RGSAD8   8   Range Start Address bit 8 
ADDRSEL4.RGSAD7   7   Range Start Address bit 7 
ADDRSEL4.RGSAD6   6   Range Start Address bit 6 
ADDRSEL4.RGSAD5   5   Range Start Address bit 5 
ADDRSEL4.RGSAD4   4   Range Start Address bit 4 
ADDRSEL4.RGSZ3    3   Range Size Selection bit 3
ADDRSEL4.RGSZ2    2   Range Size Selection bit 2
ADDRSEL4.RGSZ1    1   Range Size Selection bit 1
ADDRSEL4.RGSZ0    0   Range Size Selection bit 0
ODP0H            0xFE22   Port 0 Open Drain Control Register High
ODP0H.ODP0H7      7   Port0H Open Drain control register bit 7
ODP0H.ODP0H6      6   Port0H Open Drain control register bit 6
ODP0H.ODP0H5      5   Port0H Open Drain control register bit 5
ODP0H.ODP0H4      4   Port0H Open Drain control register bit 4
ODP0H.ODP0H3      3   Port0H Open Drain control register bit 3
ODP0H.ODP0H2      2   Port0H Open Drain control register bit 2
ODP0H.ODP0H1      1   Port0H Open Drain control register bit 1
ODP0H.ODP0H0      0   Port0H Open Drain control register bit 0
ODP1L            0xFE24   Port 1 Open Drain Control Register Low
ODP1L.ODP1L7      7   Port1L Open Drain control register bit 7
ODP1L.ODP1L6      6   Port1L Open Drain control register bit 6
ODP1L.ODP1L5      5   Port1L Open Drain control register bit 5
ODP1L.ODP1L4      4   Port1L Open Drain control register bit 4
ODP1L.ODP1L3      3   Port1L Open Drain control register bit 3
ODP1L.ODP1L2      2   Port1L Open Drain control register bit 2
ODP1L.ODP1L1      1   Port1L Open Drain control register bit 1
ODP1L.ODP1L0      0   Port1L Open Drain control register bit 0
ODP1H            0xFE26   Port 1 Open Drain Control Register High
ODP1H.ODP1H7      7   Port1H Open Drain control register bit 7
ODP1H.ODP1H6      6   Port1H Open Drain control register bit 6
ODP1H.ODP1H5      5   Port1H Open Drain control register bit 5
ODP1H.ODP1H4      4   Port1H Open Drain control register bit 4
ODP1H.ODP1H3      3   Port1H Open Drain control register bit 3
ODP1H.ODP1H2      2   Port1H Open Drain control register bit 2
ODP1H.ODP1H1      1   Port1H Open Drain control register bit 1
ODP1H.ODP1H0      0   Port1H Open Drain control register bit 0
T2               0xFE40   GPT1 Timer 2 Register
T3               0xFE42   GPT1 Timer 3 Register
T4               0xFE44   GPT1 Timer 4 Register
T5               0xFE46   GPT2 Timer 5 Register
T6               0xFE48   GPT2 Timer 6 Register
CAPREL           0xFE4A   GPT1/2 Capture / Reload Register
GPTCLC           0xFE4C   GPT1/2 Clock Control Register
GPTCLC.EXDISR     3   External Disable Request
GPTCLC.SUSPEN     2   Peripheral Suspend Enable Bit for OCDS
GPTCLC.GPTDISS    1   GPT Disable Status Bit
GPTCLC.GPTDISR    0   GPT Disable Request Bit
P0LPUDSEL        0xFE60   Port 0 Low Pull-Up/Down Select Register
P0LPUDSEL.P0LPUDSEL7 7  Pulldown/Pullup Selection - bit 7
P0LPUDSEL.P0LPUDSEL6 6  Pulldown/Pullup Selection - bit 6
P0LPUDSEL.P0LPUDSEL5 5  Pulldown/Pullup Selection - bit 5
P0LPUDSEL.P0LPUDSEL4 4  Pulldown/Pullup Selection - bit 4
P0LPUDSEL.P0LPUDSEL3 3  Pulldown/Pullup Selection - bit 3
P0LPUDSEL.P0LPUDSEL2 2  Pulldown/Pullup Selection - bit 2
P0LPUDSEL.P0LPUDSEL1 1  Pulldown/Pullup Selection - bit 1
P0LPUDSEL.P0LPUDSEL0 0  Pulldown/Pullup Selection - bit 0
P0HPUDSEL         0xFE62   Port 0 High Pull-Up/Down Select Register
P0HPUDSEL.P0HPUDSEL7 7  Pulldown/Pullup Selection - bit 7
P0HPUDSEL.P0HPUDSEL6 6  Pulldown/Pullup Selection - bit 6
P0HPUDSEL.P0HPUDSEL5 5  Pulldown/Pullup Selection - bit 5
P0HPUDSEL.P0HPUDSEL4 4  Pulldown/Pullup Selection - bit 4
P0HPUDSEL.P0HPUDSEL3 3  Pulldown/Pullup Selection - bit 3
P0HPUDSEL.P0HPUDSEL2 2  Pulldown/Pullup Selection - bit 2
P0HPUDSEL.P0HPUDSEL1 1  Pulldown/Pullup Selection - bit 1
P0HPUDSEL.P0HPUDSEL0 0  Pulldown/Pullup Selection - bit 0
P0LPUDEN         0xFE64   Port 0 Low Pull Switch On/Off Register
P0LPUDEN.P0LPUDEN7 7 Pulldown/Pullup Enable - bit 7
P0LPUDEN.P0LPUDEN6 6 Pulldown/Pullup Enable - bit 6
P0LPUDEN.P0LPUDEN5 5 Pulldown/Pullup Enable - bit 5
P0LPUDEN.P0LPUDEN4 4 Pulldown/Pullup Enable - bit 4
P0LPUDEN.P0LPUDEN3 3 Pulldown/Pullup Enable - bit 3
P0LPUDEN.P0LPUDEN2 2 Pulldown/Pullup Enable - bit 2
P0LPUDEN.P0LPUDEN1 1 Pulldown/Pullup Enable - bit 1
P0LPUDEN.P0LPUDEN0 0 Pulldown/Pullup Enable - bit 0
P0HPUDEN         0xFE66   Port 0 High Pull Switch On/Off Register
P0HPUDEN.P0HPUDEN7 7 Pulldown/Pullup Enable - bit 7
P0HPUDEN.P0HPUDEN6 6 Pulldown/Pullup Enable - bit 6
P0HPUDEN.P0HPUDEN5 5 Pulldown/Pullup Enable - bit 5
P0HPUDEN.P0HPUDEN4 4 Pulldown/Pullup Enable - bit 4
P0HPUDEN.P0HPUDEN3 3 Pulldown/Pullup Enable - bit 3
P0HPUDEN.P0HPUDEN2 2 Pulldown/Pullup Enable - bit 2
P0HPUDEN.P0HPUDEN1 1 Pulldown/Pullup Enable - bit 1
P0HPUDEN.P0HPUDEN0 0 Pulldown/Pullup Enable - bit 0
P0LPHEN          0xFE68   Port 0 Low Pin Hold Enable Register
P0LPHEN.P0LPHEN7  7   Output Driver Enable in Power Down Mode - bit 7
P0LPHEN.P0LPHEN6  6   Output Driver Enable in Power Down Mode - bit 6
P0LPHEN.P0LPHEN5  5   Output Driver Enable in Power Down Mode - bit 5
P0LPHEN.P0LPHEN4  4   Output Driver Enable in Power Down Mode - bit 4
P0LPHEN.P0LPHEN3  3   Output Driver Enable in Power Down Mode - bit 3
P0LPHEN.P0LPHEN2  2   Output Driver Enable in Power Down Mode - bit 2
P0LPHEN.P0LPHEN1  1   Output Driver Enable in Power Down Mode - bit 1
P0LPHEN.P0LPHEN0  0   Output Driver Enable in Power Down Mode - bit 0
P0HPHEN          0xFE6A   Port 0 High Pin Hold Enable Register
P0HPHEN.P0HPHEN7  7   Output Driver Enable in Power Down Mode - bit 7
P0HPHEN.P0HPHEN6  6   Output Driver Enable in Power Down Mode - bit 6
P0HPHEN.P0HPHEN5  5   Output Driver Enable in Power Down Mode - bit 5
P0HPHEN.P0HPHEN4  4   Output Driver Enable in Power Down Mode - bit 4
P0HPHEN.P0HPHEN3  3   Output Driver Enable in Power Down Mode - bit 3
P0HPHEN.P0HPHEN2  2   Output Driver Enable in Power Down Mode - bit 2
P0HPHEN.P0HPHEN1  1   Output Driver Enable in Power Down Mode - bit 1
P0HPHEN.P0HPHEN0  0   Output Driver Enable in Power Down Mode - bit 0
P1LPUDSEL        0xFE6C   Port 1 Low Pull-Up/Down Select Register
P1LPUDSEL.P1LPUDSEL7 7  Pulldown/Pullup Selection - bit 7
P1LPUDSEL.P1LPUDSEL6 6  Pulldown/Pullup Selection - bit 6
P1LPUDSEL.P1LPUDSEL5 5  Pulldown/Pullup Selection - bit 5
P1LPUDSEL.P1LPUDSEL4 4  Pulldown/Pullup Selection - bit 4
P1LPUDSEL.P1LPUDSEL3 3  Pulldown/Pullup Selection - bit 3
P1LPUDSEL.P1LPUDSEL2 2  Pulldown/Pullup Selection - bit 2
P1LPUDSEL.P1LPUDSEL1 1  Pulldown/Pullup Selection - bit 1
P1LPUDSEL.P1LPUDSEL0 0  Pulldown/Pullup Selection - bit 0
P1HPUDSEL        0xFE6E   Port 1 High Pull-Up/Down Select Register
P1HPUDSEL.P1HPUDSEL7 7  Pulldown/Pullup Selection - bit 7
P1HPUDSEL.P1HPUDSEL6 6  Pulldown/Pullup Selection - bit 6
P1HPUDSEL.P1HPUDSEL5 5  Pulldown/Pullup Selection - bit 5
P1HPUDSEL.P1HPUDSEL4 4  Pulldown/Pullup Selection - bit 4
P1HPUDSEL.P1HPUDSEL3 3  Pulldown/Pullup Selection - bit 3
P1HPUDSEL.P1HPUDSEL2 2  Pulldown/Pullup Selection - bit 2
P1HPUDSEL.P1HPUDSEL1 1  Pulldown/Pullup Selection - bit 1
P1HPUDSEL.P1HPUDSEL0 0  Pulldown/Pullup Selection - bit 0
P1LPUDEN         0xFE70   Port 1 Low Pull Switch On/Off Register
P1LPUDEN.P1LPUDEN7 7 Pulldown/Pullup Enable - bit 7
P1LPUDEN.P1LPUDEN6 6 Pulldown/Pullup Enable - bit 6
P1LPUDEN.P1LPUDEN5 5 Pulldown/Pullup Enable - bit 5
P1LPUDEN.P1LPUDEN4 4 Pulldown/Pullup Enable - bit 4
P1LPUDEN.P1LPUDEN3 3 Pulldown/Pullup Enable - bit 3
P1LPUDEN.P1LPUDEN2 2 Pulldown/Pullup Enable - bit 2
P1LPUDEN.P1LPUDEN1 1 Pulldown/Pullup Enable - bit 1
P1LPUDEN.P1LPUDEN0 0 Pulldown/Pullup Enable - bit 0
P1HPUDEN         0xFE72   Port 1 High Pull Switch On/Off Register
P1HPUDEN.P1HPUDEN7 7 Pulldown/Pullup Enable - bit 7
P1HPUDEN.P1HPUDEN6 6 Pulldown/Pullup Enable - bit 6
P1HPUDEN.P1HPUDEN5 5 Pulldown/Pullup Enable - bit 5
P1HPUDEN.P1HPUDEN4 4 Pulldown/Pullup Enable - bit 4
P1HPUDEN.P1HPUDEN3 3 Pulldown/Pullup Enable - bit 3
P1HPUDEN.P1HPUDEN2 2 Pulldown/Pullup Enable - bit 2
P1HPUDEN.P1HPUDEN1 1 Pulldown/Pullup Enable - bit 1
P1HPUDEN.P1HPUDEN0 0 Pulldown/Pullup Enable - bit 0
P1LPHEN          0xFE74   Port 1 Low Pin Hold Enable Register
P1LPHEN.P1LPHEN7  7   Output Driver Enable in Power Down Mode - bit 7
P1LPHEN.P1LPHEN6  6   Output Driver Enable in Power Down Mode - bit 6
P1LPHEN.P1LPHEN5  5   Output Driver Enable in Power Down Mode - bit 5
P1LPHEN.P1LPHEN4  4   Output Driver Enable in Power Down Mode - bit 4
P1LPHEN.P1LPHEN3  3   Output Driver Enable in Power Down Mode - bit 3
P1LPHEN.P1LPHEN2  2   Output Driver Enable in Power Down Mode - bit 2
P1LPHEN.P1LPHEN1  1   Output Driver Enable in Power Down Mode - bit 1
P1LPHEN.P1LPHEN0  0   Output Driver Enable in Power Down Mode - bit 0
P1HPHEN          0xFE76   Port 1 High Pin Hold Enable Register
P1HPHEN.P1HPHEN7  7   Output Driver Enable in Power Down Mode - bit 7
P1HPHEN.P1HPHEN6  6   Output Driver Enable in Power Down Mode - bit 6
P1HPHEN.P1HPHEN5  5   Output Driver Enable in Power Down Mode - bit 5
P1HPHEN.P1HPHEN4  4   Output Driver Enable in Power Down Mode - bit 4
P1HPHEN.P1HPHEN3  3   Output Driver Enable in Power Down Mode - bit 3
P1HPHEN.P1HPHEN2  2   Output Driver Enable in Power Down Mode - bit 2
P1HPHEN.P1HPHEN1  1   Output Driver Enable in Power Down Mode - bit 1
P1HPHEN.P1HPHEN0  0   Output Driver Enable in Power Down Mode - bit 0
P2PUDSEL         0xFE78   Port 2 Pull-Up/Down Select Register
P2PUDSEL.P2PUDSEL1 1  Pulldown/Pullup Selection - bit 1
P2PUDSEL.P2PUDSEL0 0  Pulldown/Pullup Selection - bit 0
P2PUDEN          0xFE7A   Port 2 Pull Switch On/Off Register
P2PUDEN.P2PUDEN1  1   Pulldown/Pullup Enable - bit 1
P2PUDEN.P2PUDEN0  0   Pulldown/Pullup Enable - bit 0
P2PHEN           0xFE7C   Port 2 Pin Hold Enable Register
P2PHEN.P2PHEN1    1   Output Driver Enable in Power Down Mode - bit 1
P2PHEN.P2PHEN0    0   Output Driver Enable in Power Down Mode - bit 0
P3PUDSEL         0xFE7E   Port 3 Pull-Up/Down Select Register
P3PUDSEL.P3PUDSEL15 15  Pulldown/Pullup Selection - bit 15
P3PUDSEL.P3PUDSEL13 13  Pulldown/Pullup Selection - bit 13
P3PUDSEL.P3PUDSEL12 12  Pulldown/Pullup Selection - bit 12
P3PUDSEL.P3PUDSEL11 11  Pulldown/Pullup Selection - bit 11
P3PUDSEL.P3PUDSEL10 10  Pulldown/Pullup Selection - bit 10
P3PUDSEL.P3PUDSEL9  9   Pulldown/Pullup Selection - bit 9 
P3PUDSEL.P3PUDSEL8  8   Pulldown/Pullup Selection - bit 8 
P3PUDSEL.P3PUDSEL6  6   Pulldown/Pullup Selection - bit 6 
P3PUDSEL.P3PUDSEL5  5   Pulldown/Pullup Selection - bit 5 
P3PUDSEL.P3PUDSEL3  3   Pulldown/Pullup Selection - bit 3 
P3PUDEN          0xFE80   Port 3 Pull Switch On/Off Register
P3PUDEN.P3PUDEN15 15  Pulldown/Pullup Enable - bit 15
P3PUDEN.P3PUDEN13 13  Pulldown/Pullup Enable - bit 13
P3PUDEN.P3PUDEN12 12  Pulldown/Pullup Enable - bit 12
P3PUDEN.P3PUDEN11 11  Pulldown/Pullup Enable - bit 11
P3PUDEN.P3PUDEN10 10  Pulldown/Pullup Enable - bit 10
P3PUDEN.P3PUDEN9  9   Pulldown/Pullup Enable - bit 9
P3PUDEN.P3PUDEN8  8   Pulldown/Pullup Enable - bit 8
P3PUDEN.P3PUDEN6  6   Pulldown/Pullup Enable - bit 6
P3PUDEN.P3PUDEN5  5   Pulldown/Pullup Enable - bit 5
P3PUDEN.P3PUDEN3  3   Pulldown/Pullup Enable - bit 3
P3PHEN           0xFE82   Port 3 Pin Hold Enable Register
P3PHEN.P3PHEN15   15  Output Driver Enable in Power Down Mode - bit 15
P3PHEN.P3PHEN13   13  Output Driver Enable in Power Down Mode - bit 13
P3PHEN.P3PHEN12   12  Output Driver Enable in Power Down Mode - bit 12
P3PHEN.P3PHEN11   11  Output Driver Enable in Power Down Mode - bit 11
P3PHEN.P3PHEN10   10  Output Driver Enable in Power Down Mode - bit 10
P3PHEN.P3PHEN9    9   Output Driver Enable in Power Down Mode - bit 9 
P3PHEN.P3PHEN8    8   Output Driver Enable in Power Down Mode - bit 8 
P3PHEN.P3PHEN6    6   Output Driver Enable in Power Down Mode - bit 6 
P3PHEN.P3PHEN5    5   Output Driver Enable in Power Down Mode - bit 5 
P3PHEN.P3PHEN3    3   Output Driver Enable in Power Down Mode - bit 3 
P4PUDSEL         0xFE84   Port 4 Pull-Up/Down Select Register
P4PUDSEL.P4PUDSEL4 4  Pulldown/Pullup Selection - bit 4
P4PUDSEL.P4PUDSEL3 3  Pulldown/Pullup Selection - bit 3
P4PUDSEL.P4PUDSEL2 2  Pulldown/Pullup Selection - bit 2
P4PUDSEL.P4PUDSEL1 1  Pulldown/Pullup Selection - bit 1
P4PUDSEL.P4PUDSEL0 0  Pulldown/Pullup Selection - bit 0
P4PUDEN          0xFE86   Port 4 Pull Switch On/Off Register
P4PUDEN.P4PUDEN4  4   Pulldown/Pullup Enable - bit 4
P4PUDEN.P4PUDEN3  3   Pulldown/Pullup Enable - bit 3
P4PUDEN.P4PUDEN2  2   Pulldown/Pullup Enable - bit 2
P4PUDEN.P4PUDEN1  1   Pulldown/Pullup Enable - bit 1
P4PUDEN.P4PUDEN0  0   Pulldown/Pullup Enable - bit 0
P4PHEN           0xFE88   Port 4 Pin Hold Enable Register
P4PHEN.P4PHEN4    4   Output Driver Enable in Power Down Mode - bit 4
P4PHEN.P4PHEN3    3   Output Driver Enable in Power Down Mode - bit 3
P4PHEN.P4PHEN2    2   Output Driver Enable in Power Down Mode - bit 2
P4PHEN.P4PHEN1    1   Output Driver Enable in Power Down Mode - bit 1
P4PHEN.P4PHEN0    0   Output Driver Enable in Power Down Mode - bit 0
P6PUDSEL         0xFE90   Port 6 Pull-Up/Down Select Register
P6PUDSEL.P6PUDSEL7 7  Pulldown/Pullup Selection - bit 7
P6PUDSEL.P6PUDSEL6 6  Pulldown/Pullup Selection - bit 6
P6PUDSEL.P6PUDSEL5 5  Pulldown/Pullup Selection - bit 5
P6PUDSEL.P6PUDSEL3 3  Pulldown/Pullup Selection - bit 3
P6PUDSEL.P6PUDSEL2 2  Pulldown/Pullup Selection - bit 2
P6PUDSEL.P6PUDSEL1 1  Pulldown/Pullup Selection - bit 1
P6PUDSEL.P6PUDSEL0 0  Pulldown/Pullup Selection - bit 0
P6PUDEN          0xFE92   Port 6 Pull Switch On/Off Register
P6PUDEN.P6PUDEN7  7   Pulldown/Pullup Enable - bit 7
P6PUDEN.P6PUDEN6  6   Pulldown/Pullup Enable - bit 6
P6PUDEN.P6PUDEN5  5   Pulldown/Pullup Enable - bit 5
P6PUDEN.P6PUDEN3  3   Pulldown/Pullup Enable - bit 3
P6PUDEN.P6PUDEN2  2   Pulldown/Pullup Enable - bit 2
P6PUDEN.P6PUDEN1  1   Pulldown/Pullup Enable - bit 1
P6PUDEN.P6PUDEN0  0   Pulldown/Pullup Enable - bit 0
P6PHEN           0xFE94   Port 6 Pin Hold Enable Register
P6PHEN.P6PHEN7    7   Output Driver Enable in Power Down Mode - bit 7
P6PHEN.P6PHEN6    6   Output Driver Enable in Power Down Mode - bit 6
P6PHEN.P6PHEN5    5   Output Driver Enable in Power Down Mode - bit 5
P6PHEN.P6PHEN3    3   Output Driver Enable in Power Down Mode - bit 3
P6PHEN.P6PHEN2    2   Output Driver Enable in Power Down Mode - bit 2
P6PHEN.P6PHEN1    1   Output Driver Enable in Power Down Mode - bit 1
P6PHEN.P6PHEN0    0   Output Driver Enable in Power Down Mode - bit 0
S0PMW            0xFEAA   ASC IrDA PMW Control Register
S0PMW.IRPW        8   IrDA Pulse Width Mode Control
S0PMW.PW_VALUE_7  7   IrDA Pulse Width Value - bit 7
S0PMW.PW_VALUE_6  6   IrDA Pulse Width Value - bit 6
S0PMW.PW_VALUE_5  5   IrDA Pulse Width Value - bit 5
S0PMW.PW_VALUE_4  4   IrDA Pulse Width Value - bit 4
S0PMW.PW_VALUE_3  3   IrDA Pulse Width Value - bit 3
S0PMW.PW_VALUE_2  2   IrDA Pulse Width Value - bit 2
S0PMW.PW_VALUE_1  1   IrDA Pulse Width Value - bit 1
S0PMW.PW_VALUE_0  0   IrDA Pulse Width Value - bit 0
WDT              0xFEAE   Watchdog Timer Register (RO)
S0TBUF           0xFEB0   Serial Channel 0 Transmit Buffer Register (WO)
S0TBUF.TD_VALUE_8 8   Transmit Data Register Value - bit 8
S0TBUF.TD_VALUE_7 7   Transmit Data Register Value - bit 7
S0TBUF.TD_VALUE_6 6   Transmit Data Register Value - bit 6
S0TBUF.TD_VALUE_5 5   Transmit Data Register Value - bit 5
S0TBUF.TD_VALUE_4 4   Transmit Data Register Value - bit 4
S0TBUF.TD_VALUE_3 3   Transmit Data Register Value - bit 3
S0TBUF.TD_VALUE_2 2   Transmit Data Register Value - bit 2
S0TBUF.TD_VALUE_1 1   Transmit Data Register Value - bit 1
S0TBUF.TD_VALUE_0 0   Transmit Data Register Value - bit 0
S0RBUF           0xFEB2   Serial Channel 0 Receive Buffer Register (RO)
S0RBUF.RD_VALUE_8 8   Receive Data Register Value - bit 8
S0RBUF.RD_VALUE_7 7   Receive Data Register Value - bit 7
S0RBUF.RD_VALUE_6 6   Receive Data Register Value - bit 6
S0RBUF.RD_VALUE_5 5   Receive Data Register Value - bit 5
S0RBUF.RD_VALUE_4 4   Receive Data Register Value - bit 4
S0RBUF.RD_VALUE_3 3   Receive Data Register Value - bit 3
S0RBUF.RD_VALUE_2 2   Receive Data Register Value - bit 2
S0RBUF.RD_VALUE_1 1   Receive Data Register Value - bit 1
S0RBUF.RD_VALUE_0 0   Receive Data Register Value - bit 0
S0BG             0xFEB4   Serial Channel 0 Baud Rate Generator Reload Register
S0BG.BR_VALUE_12  12  Baudrate Timer/Reload Register Value - bit 12
S0BG.BR_VALUE_11  11  Baudrate Timer/Reload Register Value - bit 11
S0BG.BR_VALUE_10  10  Baudrate Timer/Reload Register Value - bit 10
S0BG.BR_VALUE_9   9   Baudrate Timer/Reload Register Value - bit 9 
S0BG.BR_VALUE_8   8   Baudrate Timer/Reload Register Value - bit 8 
S0BG.BR_VALUE_7   7   Baudrate Timer/Reload Register Value - bit 7 
S0BG.BR_VALUE_6   6   Baudrate Timer/Reload Register Value - bit 6 
S0BG.BR_VALUE_5   5   Baudrate Timer/Reload Register Value - bit 5 
S0BG.BR_VALUE_4   4   Baudrate Timer/Reload Register Value - bit 4 
S0BG.BR_VALUE_3   3   Baudrate Timer/Reload Register Value - bit 3 
S0BG.BR_VALUE_2   2   Baudrate Timer/Reload Register Value - bit 2 
S0BG.BR_VALUE_1   1   Baudrate Timer/Reload Register Value - bit 1 
S0BG.BR_VALUE_0   0   Baudrate Timer/Reload Register Value - bit 0 
S0FDV            0xFEB6   ASC Fractional Divide Register
S0FDV.FD_VALUE_8  8   Fractional Divider Register Value - bit 8
S0FDV.FD_VALUE_7  7   Fractional Divider Register Value - bit 7
S0FDV.FD_VALUE_6  6   Fractional Divider Register Value - bit 6
S0FDV.FD_VALUE_5  5   Fractional Divider Register Value - bit 5
S0FDV.FD_VALUE_4  4   Fractional Divider Register Value - bit 4
S0FDV.FD_VALUE_3  3   Fractional Divider Register Value - bit 3
S0FDV.FD_VALUE_2  2   Fractional Divider Register Value - bit 2
S0FDV.FD_VALUE_1  1   Fractional Divider Register Value - bit 1
S0FDV.FD_VALUE_0  0   Fractional Divider Register Value - bit 0
PECC0            0xFEC0   PEC Channel 0 Control Register
PECC0.PT          15  Package Transfer
PECC0.CLT         12  Channel Link Toggle State
PECC0.CL          11  Channel Link Control
PECC0.INC_10      10  Increment Control - bit 10
PECC0.INC_9       9   Increment Control - bit 9 
PECC0.BWT         8   Byte/Word Transfer Selection
PECC0.COUNT_7     7    PEC Transfer Count - bit 7
PECC0.COUNT_6     6    PEC Transfer Count - bit 6
PECC0.COUNT_5     5    PEC Transfer Count - bit 5
PECC0.COUNT_4     4    PEC Transfer Count - bit 4
PECC0.COUNT_3     3    PEC Transfer Count - bit 3
PECC0.COUNT_2     2    PEC Transfer Count - bit 2
PECC0.COUNT_1     1    PEC Transfer Count - bit 1
PECC0.COUNT_0     0    PEC Transfer Count - bit 0
PECC1            0xFEC2   PEC Channel 1 Control Register
PECC1.PT          15  Package Transfer
PECC1.CLT         12  Channel Link Toggle State
PECC1.CL          11  Channel Link Control
PECC1.INC_10      10  Increment Control - bit 10
PECC1.INC_9       9   Increment Control - bit 9 
PECC1.BWT         8   Byte/Word Transfer Selection
PECC1.COUNT_7     7    PEC Transfer Count - bit 7
PECC1.COUNT_6     6    PEC Transfer Count - bit 6
PECC1.COUNT_5     5    PEC Transfer Count - bit 5
PECC1.COUNT_4     4    PEC Transfer Count - bit 4
PECC1.COUNT_3     3    PEC Transfer Count - bit 3
PECC1.COUNT_2     2    PEC Transfer Count - bit 2
PECC1.COUNT_1     1    PEC Transfer Count - bit 1
PECC1.COUNT_0     0    PEC Transfer Count - bit 0
PECC2            0xFEC4   PEC Channel 2 Control Register
PECC2.PT          15  Package Transfer
PECC2.CLT         12  Channel Link Toggle State
PECC2.CL          11  Channel Link Control
PECC2.INC_10      10  Increment Control - bit 10
PECC2.INC_9       9   Increment Control - bit 9 
PECC2.BWT         8   Byte/Word Transfer Selection
PECC2.COUNT_7     7    PEC Transfer Count - bit 7
PECC2.COUNT_6     6    PEC Transfer Count - bit 6
PECC2.COUNT_5     5    PEC Transfer Count - bit 5
PECC2.COUNT_4     4    PEC Transfer Count - bit 4
PECC2.COUNT_3     3    PEC Transfer Count - bit 3
PECC2.COUNT_2     2    PEC Transfer Count - bit 2
PECC2.COUNT_1     1    PEC Transfer Count - bit 1
PECC2.COUNT_0     0    PEC Transfer Count - bit 0
PECC3            0xFEC6   PEC Channel 3 Control Register
PECC3.PT          15  Package Transfer
PECC3.CLT         12  Channel Link Toggle State
PECC3.CL          11  Channel Link Control
PECC3.INC_10      10  Increment Control - bit 10
PECC3.INC_9       9   Increment Control - bit 9 
PECC3.BWT         8   Byte/Word Transfer Selection
PECC3.COUNT_7     7    PEC Transfer Count - bit 7
PECC3.COUNT_6     6    PEC Transfer Count - bit 6
PECC3.COUNT_5     5    PEC Transfer Count - bit 5
PECC3.COUNT_4     4    PEC Transfer Count - bit 4
PECC3.COUNT_3     3    PEC Transfer Count - bit 3
PECC3.COUNT_2     2    PEC Transfer Count - bit 2
PECC3.COUNT_1     1    PEC Transfer Count - bit 1
PECC3.COUNT_0     0    PEC Transfer Count - bit 0
PECC4            0xFEC8   PEC Channel 4 Control Register
PECC4.PT          15  Package Transfer
PECC4.CLT         12  Channel Link Toggle State
PECC4.CL          11  Channel Link Control
PECC4.INC_10      10  Increment Control - bit 10
PECC4.INC_9       9   Increment Control - bit 9 
PECC4.BWT         8   Byte/Word Transfer Selection
PECC4.COUNT_7     7    PEC Transfer Count - bit 7
PECC4.COUNT_6     6    PEC Transfer Count - bit 6
PECC4.COUNT_5     5    PEC Transfer Count - bit 5
PECC4.COUNT_4     4    PEC Transfer Count - bit 4
PECC4.COUNT_3     3    PEC Transfer Count - bit 3
PECC4.COUNT_2     2    PEC Transfer Count - bit 2
PECC4.COUNT_1     1    PEC Transfer Count - bit 1
PECC4.COUNT_0     0    PEC Transfer Count - bit 0
PECC5            0xFECA   PEC Channel 5 Control Register
PECC5.PT          15  Package Transfer
PECC5.CLT         12  Channel Link Toggle State
PECC5.CL          11  Channel Link Control
PECC5.INC_10      10  Increment Control - bit 10
PECC5.INC_9       9   Increment Control - bit 9 
PECC5.BWT         8   Byte/Word Transfer Selection
PECC5.COUNT_7     7    PEC Transfer Count - bit 7
PECC5.COUNT_6     6    PEC Transfer Count - bit 6
PECC5.COUNT_5     5    PEC Transfer Count - bit 5
PECC5.COUNT_4     4    PEC Transfer Count - bit 4
PECC5.COUNT_3     3    PEC Transfer Count - bit 3
PECC5.COUNT_2     2    PEC Transfer Count - bit 2
PECC5.COUNT_1     1    PEC Transfer Count - bit 1
PECC5.COUNT_0     0    PEC Transfer Count - bit 0
PECC6            0xFECC   PEC Channel 6 Control Register
PECC6.PT          15  Package Transfer
PECC6.CLT         12  Channel Link Toggle State
PECC6.CL          11  Channel Link Control
PECC6.INC_10      10  Increment Control - bit 10
PECC6.INC_9       9   Increment Control - bit 9 
PECC6.BWT         8   Byte/Word Transfer Selection
PECC6.COUNT_7     7    PEC Transfer Count - bit 7
PECC6.COUNT_6     6    PEC Transfer Count - bit 6
PECC6.COUNT_5     5    PEC Transfer Count - bit 5
PECC6.COUNT_4     4    PEC Transfer Count - bit 4
PECC6.COUNT_3     3    PEC Transfer Count - bit 3
PECC6.COUNT_2     2    PEC Transfer Count - bit 2
PECC6.COUNT_1     1    PEC Transfer Count - bit 1
PECC6.COUNT_0     0    PEC Transfer Count - bit 0
PECC7            0xFECE   PEC Channel 7 Control Register
PECC7.PT          15  Package Transfer
PECC7.CLT         12  Channel Link Toggle State
PECC7.CL          11  Channel Link Control
PECC7.INC_10      10  Increment Control - bit 10
PECC7.INC_9       9   Increment Control - bit 9 
PECC7.BWT         8   Byte/Word Transfer Selection
PECC7.COUNT_7     7    PEC Transfer Count - bit 7
PECC7.COUNT_6     6    PEC Transfer Count - bit 6
PECC7.COUNT_5     5    PEC Transfer Count - bit 5
PECC7.COUNT_4     4    PEC Transfer Count - bit 4
PECC7.COUNT_3     3    PEC Transfer Count - bit 3
PECC7.COUNT_2     2    PEC Transfer Count - bit 2
PECC7.COUNT_1     1    PEC Transfer Count - bit 1
PECC7.COUNT_0     0    PEC Transfer Count - bit 0
PECSN0           0xFED0   PEC Segment No Register
PECSN0.PECDSN_15  15  PEC Destination Segment Number - bit 15
PECSN0.PECDSN_14  14  PEC Destination Segment Number - bit 14
PECSN0.PECDSN_13  13  PEC Destination Segment Number - bit 13
PECSN0.PECDSN_12  12  PEC Destination Segment Number - bit 12
PECSN0.PECDSN_11  11  PEC Destination Segment Number - bit 11
PECSN0.PECDSN_10  10  PEC Destination Segment Number - bit 10
PECSN0.PECDSN_9   9   PEC Destination Segment Number - bit 9 
PECSN0.PECDSN_8   8   PEC Destination Segment Number - bit 8 
PECSN0.PECSSN_7   7  PEC Source Segment Number - bit 7
PECSN0.PECSSN_6   6  PEC Source Segment Number - bit 6
PECSN0.PECSSN_5   5  PEC Source Segment Number - bit 5
PECSN0.PECSSN_4   4  PEC Source Segment Number - bit 4
PECSN0.PECSSN_3   3  PEC Source Segment Number - bit 3
PECSN0.PECSSN_2   2  PEC Source Segment Number - bit 2
PECSN0.PECSSN_1   1  PEC Source Segment Number - bit 1
PECSN0.PECSSN_0   0  PEC Source Segment Number - bit 0
PECSN1           0xFED2   PEC Segment No Register
PECSN1.PECDSN_15  15  PEC Destination Segment Number - bit 15
PECSN1.PECDSN_14  14  PEC Destination Segment Number - bit 14
PECSN1.PECDSN_13  13  PEC Destination Segment Number - bit 13
PECSN1.PECDSN_12  12  PEC Destination Segment Number - bit 12
PECSN1.PECDSN_11  11  PEC Destination Segment Number - bit 11
PECSN1.PECDSN_10  10  PEC Destination Segment Number - bit 10
PECSN1.PECDSN_9   9   PEC Destination Segment Number - bit 9 
PECSN1.PECDSN_8   8   PEC Destination Segment Number - bit 8 
PECSN1.PECSSN_7   7  PEC Source Segment Number - bit 7
PECSN1.PECSSN_6   6  PEC Source Segment Number - bit 6
PECSN1.PECSSN_5   5  PEC Source Segment Number - bit 5
PECSN1.PECSSN_4   4  PEC Source Segment Number - bit 4
PECSN1.PECSSN_3   3  PEC Source Segment Number - bit 3
PECSN1.PECSSN_2   2  PEC Source Segment Number - bit 2
PECSN1.PECSSN_1   1  PEC Source Segment Number - bit 1
PECSN1.PECSSN_0   0  PEC Source Segment Number - bit 0
PECSN2           0xFED4   PEC Segment No Register
PECSN2.PECDSN_15  15  PEC Destination Segment Number - bit 15
PECSN2.PECDSN_14  14  PEC Destination Segment Number - bit 14
PECSN2.PECDSN_13  13  PEC Destination Segment Number - bit 13
PECSN2.PECDSN_12  12  PEC Destination Segment Number - bit 12
PECSN2.PECDSN_11  11  PEC Destination Segment Number - bit 11
PECSN2.PECDSN_10  10  PEC Destination Segment Number - bit 10
PECSN2.PECDSN_9   9   PEC Destination Segment Number - bit 9 
PECSN2.PECDSN_8   8   PEC Destination Segment Number - bit 8 
PECSN2.PECSSN_7   7  PEC Source Segment Number - bit 7
PECSN2.PECSSN_6   6  PEC Source Segment Number - bit 6
PECSN2.PECSSN_5   5  PEC Source Segment Number - bit 5
PECSN2.PECSSN_4   4  PEC Source Segment Number - bit 4
PECSN2.PECSSN_3   3  PEC Source Segment Number - bit 3
PECSN2.PECSSN_2   2  PEC Source Segment Number - bit 2
PECSN2.PECSSN_1   1  PEC Source Segment Number - bit 1
PECSN2.PECSSN_0   0  PEC Source Segment Number - bit 0
PECSN3           0xFED6   PEC Segment No Register
PECSN3.PECDSN_15  15  PEC Destination Segment Number - bit 15
PECSN3.PECDSN_14  14  PEC Destination Segment Number - bit 14
PECSN3.PECDSN_13  13  PEC Destination Segment Number - bit 13
PECSN3.PECDSN_12  12  PEC Destination Segment Number - bit 12
PECSN3.PECDSN_11  11  PEC Destination Segment Number - bit 11
PECSN3.PECDSN_10  10  PEC Destination Segment Number - bit 10
PECSN3.PECDSN_9   9   PEC Destination Segment Number - bit 9 
PECSN3.PECDSN_8   8   PEC Destination Segment Number - bit 8 
PECSN3.PECSSN_7   7  PEC Source Segment Number - bit 7
PECSN3.PECSSN_6   6  PEC Source Segment Number - bit 6
PECSN3.PECSSN_5   5  PEC Source Segment Number - bit 5
PECSN3.PECSSN_4   4  PEC Source Segment Number - bit 4
PECSN3.PECSSN_3   3  PEC Source Segment Number - bit 3
PECSN3.PECSSN_2   2  PEC Source Segment Number - bit 2
PECSN3.PECSSN_1   1  PEC Source Segment Number - bit 1
PECSN3.PECSSN_0   0  PEC Source Segment Number - bit 0
PECSN4           0xFED8   PEC Segment No Register
PECSN4.PECDSN_15  15  PEC Destination Segment Number - bit 15
PECSN4.PECDSN_14  14  PEC Destination Segment Number - bit 14
PECSN4.PECDSN_13  13  PEC Destination Segment Number - bit 13
PECSN4.PECDSN_12  12  PEC Destination Segment Number - bit 12
PECSN4.PECDSN_11  11  PEC Destination Segment Number - bit 11
PECSN4.PECDSN_10  10  PEC Destination Segment Number - bit 10
PECSN4.PECDSN_9   9   PEC Destination Segment Number - bit 9 
PECSN4.PECDSN_8   8   PEC Destination Segment Number - bit 8 
PECSN4.PECSSN_7   7  PEC Source Segment Number - bit 7
PECSN4.PECSSN_6   6  PEC Source Segment Number - bit 6
PECSN4.PECSSN_5   5  PEC Source Segment Number - bit 5
PECSN4.PECSSN_4   4  PEC Source Segment Number - bit 4
PECSN4.PECSSN_3   3  PEC Source Segment Number - bit 3
PECSN4.PECSSN_2   2  PEC Source Segment Number - bit 2
PECSN4.PECSSN_1   1  PEC Source Segment Number - bit 1
PECSN4.PECSSN_0   0  PEC Source Segment Number - bit 0
PECSN5           0xFEDA   PEC Segment No Register
PECSN5.PECDSN_15  15  PEC Destination Segment Number - bit 15
PECSN5.PECDSN_14  14  PEC Destination Segment Number - bit 14
PECSN5.PECDSN_13  13  PEC Destination Segment Number - bit 13
PECSN5.PECDSN_12  12  PEC Destination Segment Number - bit 12
PECSN5.PECDSN_11  11  PEC Destination Segment Number - bit 11
PECSN5.PECDSN_10  10  PEC Destination Segment Number - bit 10
PECSN5.PECDSN_9   9   PEC Destination Segment Number - bit 9 
PECSN5.PECDSN_8   8   PEC Destination Segment Number - bit 8 
PECSN5.PECSSN_7   7  PEC Source Segment Number - bit 7
PECSN5.PECSSN_6   6  PEC Source Segment Number - bit 6
PECSN5.PECSSN_5   5  PEC Source Segment Number - bit 5
PECSN5.PECSSN_4   4  PEC Source Segment Number - bit 4
PECSN5.PECSSN_3   3  PEC Source Segment Number - bit 3
PECSN5.PECSSN_2   2  PEC Source Segment Number - bit 2
PECSN5.PECSSN_1   1  PEC Source Segment Number - bit 1
PECSN5.PECSSN_0   0  PEC Source Segment Number - bit 0
PECSN6           0xFEDC   PEC Segment No Register
PECSN6.PECDSN_15  15  PEC Destination Segment Number - bit 15
PECSN6.PECDSN_14  14  PEC Destination Segment Number - bit 14
PECSN6.PECDSN_13  13  PEC Destination Segment Number - bit 13
PECSN6.PECDSN_12  12  PEC Destination Segment Number - bit 12
PECSN6.PECDSN_11  11  PEC Destination Segment Number - bit 11
PECSN6.PECDSN_10  10  PEC Destination Segment Number - bit 10
PECSN6.PECDSN_9   9   PEC Destination Segment Number - bit 9 
PECSN6.PECDSN_8   8   PEC Destination Segment Number - bit 8 
PECSN6.PECSSN_7   7  PEC Source Segment Number - bit 7
PECSN6.PECSSN_6   6  PEC Source Segment Number - bit 6
PECSN6.PECSSN_5   5  PEC Source Segment Number - bit 5
PECSN6.PECSSN_4   4  PEC Source Segment Number - bit 4
PECSN6.PECSSN_3   3  PEC Source Segment Number - bit 3
PECSN6.PECSSN_2   2  PEC Source Segment Number - bit 2
PECSN6.PECSSN_1   1  PEC Source Segment Number - bit 1
PECSN6.PECSSN_0   0  PEC Source Segment Number - bit 0
PECSN7           0xFEDE   PEC Segment No Register
PECSN7.PECDSN_15  15  PEC Destination Segment Number - bit 15
PECSN7.PECDSN_14  14  PEC Destination Segment Number - bit 14
PECSN7.PECDSN_13  13  PEC Destination Segment Number - bit 13
PECSN7.PECDSN_12  12  PEC Destination Segment Number - bit 12
PECSN7.PECDSN_11  11  PEC Destination Segment Number - bit 11
PECSN7.PECDSN_10  10  PEC Destination Segment Number - bit 10
PECSN7.PECDSN_9   9   PEC Destination Segment Number - bit 9 
PECSN7.PECDSN_8   8   PEC Destination Segment Number - bit 8 
PECSN7.PECSSN_7   7  PEC Source Segment Number - bit 7
PECSN7.PECSSN_6   6  PEC Source Segment Number - bit 6
PECSN7.PECSSN_5   5  PEC Source Segment Number - bit 5
PECSN7.PECSSN_4   4  PEC Source Segment Number - bit 4
PECSN7.PECSSN_3   3  PEC Source Segment Number - bit 3
PECSN7.PECSSN_2   2  PEC Source Segment Number - bit 2
PECSN7.PECSSN_1   1  PEC Source Segment Number - bit 1
PECSN7.PECSSN_0   0  PEC Source Segment Number - bit 0
PECXC0           0xFEF0   PEC Channel 0 Extended Control Register
PECXC0.COUNT2_15  15  Extended PEC Transfer Count - bit 15
PECXC0.COUNT2_14  14  Extended PEC Transfer Count - bit 14
PECXC0.COUNT2_13  13  Extended PEC Transfer Count - bit 13
PECXC0.COUNT2_12  12  Extended PEC Transfer Count - bit 12
PECXC0.COUNT2_11  11  Extended PEC Transfer Count - bit 11
PECXC0.COUNT2_10  10  Extended PEC Transfer Count - bit 10
PECXC0.COUNT2_9   9   Extended PEC Transfer Count - bit 9 
PECXC0.COUNT2_8   8   Extended PEC Transfer Count - bit 8 
PECXC0.COUNT2_7   7   Extended PEC Transfer Count - bit 7 
PECXC0.COUNT2_6   6   Extended PEC Transfer Count - bit 6 
PECXC0.COUNT2_5   5   Extended PEC Transfer Count - bit 5 
PECXC0.COUNT2_4   4   Extended PEC Transfer Count - bit 4 
PECXC0.COUNT2_3   3   Extended PEC Transfer Count - bit 3 
PECXC0.COUNT2_2   2   Extended PEC Transfer Count - bit 2 
PECXC0.COUNT2_1   1   Extended PEC Transfer Count - bit 1 
PECXC0.COUNT2_0   0   Extended PEC Transfer Count - bit 0 
PECXC2           0xFEF2   PEC Channel 2 Extended Control Register
PECXC2.COUNT2_15  15  Extended PEC Transfer Count - bit 15
PECXC2.COUNT2_14  14  Extended PEC Transfer Count - bit 14
PECXC2.COUNT2_13  13  Extended PEC Transfer Count - bit 13
PECXC2.COUNT2_12  12  Extended PEC Transfer Count - bit 12
PECXC2.COUNT2_11  11  Extended PEC Transfer Count - bit 11
PECXC2.COUNT2_10  10  Extended PEC Transfer Count - bit 10
PECXC2.COUNT2_9   9   Extended PEC Transfer Count - bit 9 
PECXC2.COUNT2_8   8   Extended PEC Transfer Count - bit 8 
PECXC2.COUNT2_7   7   Extended PEC Transfer Count - bit 7 
PECXC2.COUNT2_6   6   Extended PEC Transfer Count - bit 6 
PECXC2.COUNT2_5   5   Extended PEC Transfer Count - bit 5 
PECXC2.COUNT2_4   4   Extended PEC Transfer Count - bit 4 
PECXC2.COUNT2_3   3   Extended PEC Transfer Count - bit 3 
PECXC2.COUNT2_2   2   Extended PEC Transfer Count - bit 2 
PECXC2.COUNT2_1   1   Extended PEC Transfer Count - bit 1 
PECXC2.COUNT2_0   0   Extended PEC Transfer Count - bit 0 
ABS0CON          0xFEF8   ASC Autobaud Control Register
ABS0CON.RXINV     11  Receive Inverter Enable
ABS0CON.TXINV     10  Transmit Inverter Enable
ABS0CON.ABEM_9    9   Autobaud Echo Mode Enable - bit 9
ABS0CON.ABEM_8    8   Autobaud Echo Mode Enable - bit 8
ABS0CON.FCDETEN   4   First Character of Two-Byte Frame Detected Enable
ABS0CON.ABDETEN   3   Autobaud Detection Interrupt Enable
ABS0CON.ABSTEN    2   Start of Autobaud Detection Interrupt Enable
ABS0CON.AUREN     1   Automatic Autobaud Control of CON_REN
ABS0CON.ABEN      0   Autobaud Detection Enable
ABSTAT           0xFEFE   ASC Autobaud Status Register
ABSTAT.DETWAIT    4   Autobaud Detection is Waiting
ABSTAT.SCCDET     3   Second Character with Capital Letter Detected
ABSTAT.SCSDET     2   Second Character with Small Letter Detected
ABSTAT.FCCDET     1   First Character with Capital Letter Detected
ABSTAT.FCSDET     0   First Character with Small Letter Detected
P0L              0xFF00   Port 0 Low Register (Lower half)
P0L.P0L7          7   Port data register P0L bit 7
P0L.P0L6          6   Port data register P0L bit 6
P0L.P0L5          5   Port data register P0L bit 5
P0L.P0L4          4   Port data register P0L bit 4
P0L.P0L3          3   Port data register P0L bit 3
P0L.P0L2          2   Port data register P0L bit 2
P0L.P0L1          1   Port data register P0L bit 1
P0L.P0L0          0   Port data register P0L bit 0
P0H              0xFF02   Port 0 High Register (Upper half)
P0H.P0H7          7   Port data register P0H bit 7
P0H.P0H6          6   Port data register P0H bit 6
P0H.P0H5          5   Port data register P0H bit 5
P0H.P0H4          4   Port data register P0H bit 4
P0H.P0H3          3   Port data register P0H bit 3
P0H.P0H2          2   Port data register P0H bit 2
P0H.P0H1          1   Port data register P0H bit 1
P0H.P0H0          0   Port data register P0H bit 0
P1L              0xFF04   Port 1 Low Register (Lower half)
P1L.P1L7          7   Port data register P1L bit 7
P1L.P1L6          6   Port data register P1L bit 6
P1L.P1L5          5   Port data register P1L bit 5
P1L.P1L4          4   Port data register P1L bit 4
P1L.P1L3          3   Port data register P1L bit 3
P1L.P1L2          2   Port data register P1L bit 2
P1L.P1L1          1   Port data register P1L bit 1
P1L.P1L0          0   Port data register P1L bit 0
P1H              0xFF06   Port 1 High Register (Upper half)
P1H.P1H7          7   Port data register P1H bit 7
P1H.P1H6          6   Port data register P1H bit 6
P1H.P1H5          5   Port data register P1H bit 5
P1H.P1H4          4   Port data register P1H bit 4
P1H.P1H3          3   Port data register P1H bit 3
P1H.P1H2          2   Port data register P1H bit 2
P1H.P1H1          1   Port data register P1H bit 1
P1H.P1H0          0   Port data register P1H bit 0
BUSCON0          0xFF0C   Bus Configuration Register 0
BUSCON0.CSWEN0    15  Write Chip Select Enable
BUSCON0.CSREN0    14  Read Chip Select Enable
BUSCON0.RDYEN0    12  READY Input Enable
BUSCON0.BUSACT0   10  Bus Active Control
BUSCON0.ALECTL0   9   ALE Lengthening Control
BUSCON0.EWEN0     8   Early Write Enable
BUSCON0.BTYP_7    7   External Bus Configuration - bit 7
BUSCON0.BTYP_6    6   External Bus Configuration - bit 6
BUSCON0.MTTC0     5   Memory Tristate Time Control
BUSCON0.RWDC0     4   Read/Write Delay Control for BUSCON
BUSCON0.MCTC_3    3   Memory Cycle Time Control - bit 3
BUSCON0.MCTC_2    2   Memory Cycle Time Control - bit 2
BUSCON0.MCTC_1    1   Memory Cycle Time Control - bit 1
BUSCON0.MCTC_0    0   Memory Cycle Time Control - bit 0
MDC              0xFF0E   CPU Multiply Divide Control Register
MDC.MDRIU         4   Multiply/Divide Register In Use
PSW              0xFF10   CPU Program Status Word
PSW.ILVL_15       15  Interrupt and EBC Control Field - bit 15
PSW.ILVL_14       14  Interrupt and EBC Control Field - bit 14
PSW.ILVL_13       13  Interrupt and EBC Control Field - bit 13
PSW.ILVL_12       12  Interrupt and EBC Control Field - bit 12
PSW.IEN           11  Interrupt and EBC Control Field
PSW.HLDEN         10  Interrupt and EBC Control Field
PSW.USR0          6   User General Purpose Flag
PSW.MULIP         5   Multiplication/Division In Progress
PSW.E             4   End of Table Flag
PSW.Z             3   Zero F lag
PSW.V             2   Overflow Result
PSW.C             1   Carry Flag
PSW.N             0   Negative Result
SYSCON           0xFF12   CPU System Configuration Register
SYSCON.STKSZ_15   15  System Stack Size - bit 15
SYSCON.STKSZ_14   14  System Stack Size - bit 14
SYSCON.STKSZ_13   13  System Stack Size - bit 13
SYSCON.ROMS1      12  Internal ROM Mapping
SYSCON.SGTDIS     11  Segmentation Disable/Enable Control (Cleared after reset)
SYSCON.ROMEN      10  Internal ROM Enable (Set according to pin EA during reset)
SYSCON.BYTDIS     9   Disable/Enable Control for Pin BHE (Set according to data bus width)
SYSCON.CLKEN      8   System Clock Output Enable (CLKOUT, cleared after reset)
SYSCON.WRCFG      7   Write Configuration Control (Set according to pin P0H.0 during reset)
SYSCON.CSCFG      6   Chip Select Configuration Control (Cleared after reset)
SYSCON.OSCENBL    4   Oscillator Watchdog Enable Bit
SYSCON.XPEN       2   Peripheral Enable Bit
SYSCON.VISIBLE    1   Visible Mode Control
SYSCON.XPER_SHARE 0   XBUS Peripheral Share Mode Control
BUSCON1          0xFF14   Bus Configuration Register 1
BUSCON1.CSWEN1    15  Write Chip Select Enable
BUSCON1.CSREN1    14  Read Chip Select Enable
BUSCON1.RDYEN1    12  READY Input Enable
BUSCON1.BUSACT1   10  Bus Active Control
BUSCON1.ALECTL1   9   ALE Lengthening Control
BUSCON1.EWEN1     8   Early Write Enable
BUSCON1.BTYP_7    7   External Bus Configuration - bit 7
BUSCON1.BTYP_6    6   External Bus Configuration - bit 6
BUSCON1.MTTC1     5   Memory Tristate Time Control
BUSCON1.RWDC1     4   Read/Write Delay Control for BUSCON
BUSCON1.MCTC_3    3   Memory Cycle Time Control - bit 3
BUSCON1.MCTC_2    2   Memory Cycle Time Control - bit 2
BUSCON1.MCTC_1    1   Memory Cycle Time Control - bit 1
BUSCON1.MCTC_0    0   Memory Cycle Time Control - bit 0
BUSCON2          0xFF16   Bus Configuration Register 2
BUSCON2.CSWEN2    15  Write Chip Select Enable
BUSCON2.CSREN2    14  Read Chip Select Enable
BUSCON2.RDYEN2    12  READY Input Enable
BUSCON2.BUSACT2   10  Bus Active Control
BUSCON2.ALECTL2   9   ALE Lengthening Control
BUSCON2.EWEN2     8   Early Write Enable
BUSCON2.BTYP_7    7   External Bus Configuration - bit 7
BUSCON2.BTYP_6    6   External Bus Configuration - bit 6
BUSCON2.MTTC2     5   Memory Tristate Time Control
BUSCON2.RWDC2     4   Read/Write Delay Control for BUSCON
BUSCON2.MCTC_3    3   Memory Cycle Time Control - bit 3
BUSCON2.MCTC_2    2   Memory Cycle Time Control - bit 2
BUSCON2.MCTC_1    1   Memory Cycle Time Control - bit 1
BUSCON2.MCTC_0    0   Memory Cycle Time Control - bit 0
BUSCON3          0xFF18   Bus Configuration Register 3
BUSCON3.CSWEN3    15  Write Chip Select Enable
BUSCON3.CSREN3    14  Read Chip Select Enable
BUSCON3.RDYEN3    12  READY Input Enable
BUSCON3.BUSACT3   10  Bus Active Control
BUSCON3.ALECTL3   9   ALE Lengthening Control
BUSCON3.EWEN3     8   Early Write Enable
BUSCON3.BTYP_7    7   External Bus Configuration - bit 7
BUSCON3.BTYP_6    6   External Bus Configuration - bit 6
BUSCON3.MTTC3     5   Memory Tristate Time Control
BUSCON3.RWDC3     4   Read/Write Delay Control for BUSCON
BUSCON3.MCTC_3    3   Memory Cycle Time Control - bit 3
BUSCON3.MCTC_2    2   Memory Cycle Time Control - bit 2
BUSCON3.MCTC_1    1   Memory Cycle Time Control - bit 1
BUSCON3.MCTC_0    0   Memory Cycle Time Control - bit 0
BUSCON4          0xFF1A   Bus Configuration Register 4
BUSCON4.CSWEN4    15  Write Chip Select Enable
BUSCON4.CSREN4    14  Read Chip Select Enable
BUSCON4.RDYEN4    12  READY Input Enable
BUSCON4.BUSACT4   10  Bus Active Control
BUSCON4.ALECTL4   9   ALE Lengthening Control
BUSCON4.EWEN4     8   Early Write Enable
BUSCON4.BTYP_7    7   External Bus Configuration - bit 7
BUSCON4.BTYP_6    6   External Bus Configuration - bit 6
BUSCON4.MTTC4     5   Memory Tristate Time Control
BUSCON4.RWDC4     4   Read/Write Delay Control for BUSCON
BUSCON4.MCTC_3    3   Memory Cycle Time Control - bit 3
BUSCON4.MCTC_2    2   Memory Cycle Time Control - bit 2
BUSCON4.MCTC_1    1   Memory Cycle Time Control - bit 1
BUSCON4.MCTC_0    0   Memory Cycle Time Control - bit 0
ZEROS            0xFF1C   Constant Value 0sRegister'
ONES             0xFF1E   Constant Value 1sRegister'
T2CON            0xFF40   GPT1 Timer 2 Control Register
T2CON.T2IREN      15  Timer 2 Interrupt Enable
T2CON.T2RDIR      14  Timer 2 Rotation Direction
T2CON.T2CHDIR     13  Timer 2 Count Direction Change
T2CON.T2EDGE      12  Timer 2 Edge Detection
T2CON.T2RC        9   Timer 2 Remote Control
T2CON.T2UDE       8   Timer 2 External Up/Down Enable
T2CON.T2UD        7   Timer 2 Up / Down Control
T2CON.T2R         6   Timer 2 Run Bit
T2CON.T2M_5       5   Timer 2 Mode Control - bit 5
T2CON.T2M_4       4   Timer 2 Mode Control - bit 4
T2CON.T2M_3       3   Timer 2 Mode Control - bit 3
T2CON.T2I_2       2   Timer 2 Input Selection - bit 2
T2CON.T2I_1       1   Timer 2 Input Selection - bit 1
T2CON.T2I_0       0   Timer 2 Input Selection - bit 0
T3CON            0xFF42   GPT1 Timer 3 Control Register
T3CON.T3IREN      15  Timer 3 Interrupt Enable
T3CON.T3RDIR      14  Timer 3 Rotation Direction
T3CON.T3CHDIR     13  Timer 3 Count Direction Change
T3CON.T3EDGE      12  Timer 3 Edge Detection
T3CON.FM1         11  Fast Mode for Timer Block 1
T3CON.T3OTL       10  Timer 3 Output Toggle Latch
T3CON.T3OE        9   Alternate Output Function Enable
T3CON.T3UDE       8   Timer 3 External Up/Down Enable
T3CON.T3UD        7   Timer 3 Up / Down Control
T3CON.T3R         6   Timer 3 Run Bit
T3CON.T3M_5       5   Timer 3 Mode Control - bit 5
T3CON.T3M_4       4   Timer 3 Mode Control - bit 4
T3CON.T3M_3       3   Timer 3 Mode Control - bit 3
T3CON.T3I_2       2   Timer 3 Input Selection - bit 2
T3CON.T3I_1       1   Timer 3 Input Selection - bit 1
T3CON.T3I_0       0   Timer 3 Input Selection - bit 0
T4CON            0xFF44   GPT1 Timer 4 Control Register
T4CON.T4IREN      15  Timer 4 Interrupt Enable
T4CON.T4RDIR      14  Timer 4 Rotation Direction
T4CON.T4CHDIR     13  Timer 4 Count Direction Change
T4CON.T4EDGE      12  Timer 4 Edge Detection
T4CON.T4RC        9   Timer 4 Remote Control
T4CON.T4UD        7   Timer 4 Up / Down Control
T4CON.T4R         6   Timer 4 Run Bit
T4CON.T4M_5       5   Timer 4 Mode Control - bit 5
T4CON.T4M_4       4   Timer 4 Mode Control - bit 4
T4CON.T4M_3       3   Timer 4 Mode Control - bit 3
T4CON.T4I_2       2   Timer 4 Input Selection - bit 2
T4CON.T4I_1       1   Timer 4 Input Selection - bit 1
T4CON.T4I_0       0   Timer 4 Input Selection - bit 0
T5CON            0xFF46   GPT2 Timer 5 Control Register
T5CON.T5SC        15  Timer 5 Capture Mode Enable
T5CON.T5CLR       14  Timer 5 Clear Bit
T5CON.CI_13       13  Register CAPREL Capture Trigger Selection - bit 13
T5CON.CI_12       12  Register CAPREL Capture Trigger Selection - bit 12
T5CON.CC          11  Capture Correction
T5CON.T4RC        9   Timer 4 Remote Control
T5CON.T4UD        7   Timer 4 Up / Down Control
T5CON.T4R         6   Timer 4 Run Bit
T5CON.T4M_5       5   Timer 4 Mode Control - bit 5
T5CON.T4M_4       4   Timer 4 Mode Control - bit 4
T5CON.T4M_3       3   Timer 4 Mode Control - bit 3
T5CON.T4I_2       2   Timer 4 Input Selection - bit 2
T5CON.T4I_1       1   Timer 4 Input Selection - bit 1
T5CON.T4I_0       0   Timer 4 Input Selection - bit 0
T6CON            0xFF48   GPT2 Timer 6 Control Register
T6CON.T6SR        15  Timer 6 Reload Mode Enable
T6CON.T6CLR       14  Timer 6 Clear Bit
T6CON.FM2         11  Fast Mode for Timer Block 2
T6CON.T6OTL       10  Timer 6 Output Toggle Latch
T6CON.T6UD        7   Timer 6 Up / Down Control
T6CON.T6R         6   Timer 6 Run Bit
T6CON.T6M_5       5   Timer 6 Mode Control - bit 5
T6CON.T6M_4       4   Timer 6 Mode Control - bit 4
T6CON.T6M_3       3   Timer 6 Mode Control - bit 3
T6CON.T6I_2       2   Timer 6 Input Selection - bit 2
T6CON.T6I_1       1   Timer 6 Input Selection - bit 1
T6CON.T6I_0       0   Timer 6 Input Selection - bit 0
T2IC             0xFF60   GPT1 Timer 2 Interrupt Control Register
T2IC.T2IR         7   Interrupt Request Flag
T2IC.T2IE         6   Interrupt Enable Control Bit (individually enables/disables a specific source)
T2IC.ILVL_5       5   Interrupt Priority Level - bit 5
T2IC.ILVL_4       4   Interrupt Priority Level - bit 4
T2IC.ILVL_3       3   Interrupt Priority Level - bit 3
T2IC.ILVL_2       2   Interrupt Priority Level - bit 2
T2IC.GLVL_1       1   Group Level - bit 1
T2IC.GLVL_0       0   Group Level - bit 0
T3IC             0xFF62   GPT1 Timer 3 Interrupt Control Register
T3IC.T3IR         7   Interrupt Request Flag
T3IC.T3IE         6   Interrupt Enable Control Bit (individually enables/disables a specific source)
T3IC.ILVL_5       5   Interrupt Priority Level - bit 5
T3IC.ILVL_4       4   Interrupt Priority Level - bit 4
T3IC.ILVL_3       3   Interrupt Priority Level - bit 3
T3IC.ILVL_2       2   Interrupt Priority Level - bit 2
T3IC.GLVL_1       1   Group Level - bit 1
T3IC.GLVL_0       0   Group Level - bit 0
T4IC             0xFF64   GPT1 Timer 4 Interrupt Control Register
T4IC.T4IR         7   Interrupt Request Flag
T4IC.T4IE         6   Interrupt Enable Control Bit (individually enables/disables a specific source)
T4IC.ILVL_5       5   Interrupt Priority Level - bit 5
T4IC.ILVL_4       4   Interrupt Priority Level - bit 4
T4IC.ILVL_3       3   Interrupt Priority Level - bit 3
T4IC.ILVL_2       2   Interrupt Priority Level - bit 2
T4IC.GLVL_1       1   Group Level - bit 1
T4IC.GLVL_0       0   Group Level - bit 0
T5IC             0xFF66   GPT2 Timer 5 Interrupt Control Register
T5IC.T5IR         7   Interrupt Request Flag
T5IC.T5IE         6   Interrupt Enable Control Bit (individually enables/disables a specific source)
T5IC.ILVL_5       5   Interrupt Priority Level - bit 5
T5IC.ILVL_4       4   Interrupt Priority Level - bit 4
T5IC.ILVL_3       3   Interrupt Priority Level - bit 3
T5IC.ILVL_2       2   Interrupt Priority Level - bit 2
T5IC.GLVL_1       1   Group Level - bit 1
T5IC.GLVL_0       0   Group Level - bit 0
T6IC             0xFF68   GPT2 Timer 6 Interrupt Control Register
T6IC.T2IR         7   Interrupt Request Flag
T6IC.T2IE         6   Interrupt Enable Control Bit (individually enables/disables a specific source)
T6IC.ILVL_5       5   Interrupt Priority Level - bit 5
T6IC.ILVL_4       4   Interrupt Priority Level - bit 4
T6IC.ILVL_3       3   Interrupt Priority Level - bit 3
T6IC.ILVL_2       2   Interrupt Priority Level - bit 2
T6IC.GLVL_1       1   Group Level - bit 1
T6IC.GLVL_0       0   Group Level - bit 0
CRIC             0xFF6A   GPT2 CAPREL Interrupt Control Register
CRIC.CRIR         7   Interrupt Request Flag
CRIC.CRIE         6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CRIC.ILVL_5       5   Interrupt Priority Level - bit 5
CRIC.ILVL_4       4   Interrupt Priority Level - bit 4
CRIC.ILVL_3       3   Interrupt Priority Level - bit 3
CRIC.ILVL_2       2   Interrupt Priority Level - bit 2
CRIC.GLVL_1       1   Group Level - bit 1
CRIC.GLVL_0       0   Group Level - bit 0
S0TIC            0xFF6C   Serial Channel 0 Transmit Interrupt Control Register
S0TIC.S0TIR       7   Interrupt Request Flag
S0TIC.S0TIE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
S0TIC.ILVL_5      5   Interrupt Priority Level - bit 5
S0TIC.ILVL_4      4   Interrupt Priority Level - bit 4
S0TIC.ILVL_3      3   Interrupt Priority Level - bit 3
S0TIC.ILVL_2      2   Interrupt Priority Level - bit 2
S0TIC.GLVL_1      1   Group Level - bit 1
S0TIC.GLVL_0      0   Group Level - bit 0
S0RIC            0xFF6E   Serial Channel 0 Receive Interrupt Control Register
S0RIC.S0RIR       7   Interrupt Request Flag
S0RIC.S0RIE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
S0RIC.ILVL_5      5   Interrupt Priority Level - bit 5
S0RIC.ILVL_4      4   Interrupt Priority Level - bit 4
S0RIC.ILVL_3      3   Interrupt Priority Level - bit 3
S0RIC.ILVL_2      2   Interrupt Priority Level - bit 2
S0RIC.GLVL_1      1   Group Level - bit 1
S0RIC.GLVL_0      0   Group Level - bit 0
S0EIC            0xFF70   Serial Channel 0 Error Interrupt Control Register
S0EIC.S0EIR       7   Interrupt Request Flag
S0EIC.S0EIE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
S0EIC.ILVL_5      5   Interrupt Priority Level - bit 5
S0EIC.ILVL_4      4   Interrupt Priority Level - bit 4
S0EIC.ILVL_3      3   Interrupt Priority Level - bit 3
S0EIC.ILVL_2      2   Interrupt Priority Level - bit 2
S0EIC.GLVL_1      1   Group Level - bit 1
S0EIC.GLVL_0      0   Group Level - bit 0
SSCTIC           0xFF72   SSC Transmit Interrupt Control Register
SSCTIC.SSCTIR     7   Interrupt Request Flag
SSCTIC.SSCTIE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
SSCTIC.ILVL_5     5   Interrupt Priority Level - bit 5
SSCTIC.ILVL_4     4   Interrupt Priority Level - bit 4
SSCTIC.ILVL_3     3   Interrupt Priority Level - bit 3
SSCTIC.ILVL_2     2   Interrupt Priority Level - bit 2
SSCTIC.GLVL_1     1   Group Level - bit 1
SSCTIC.GLVL_0     0   Group Level - bit 0
SSCRIC           0xFF74   SSC Receive Interrupt Control Register
SSCRIC.SSCRIR     7   Interrupt Request Flag
SSCRIC.SSCRIE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
SSCRIC.ILVL_5     5   Interrupt Priority Level - bit 5
SSCRIC.ILVL_4     4   Interrupt Priority Level - bit 4
SSCRIC.ILVL_3     3   Interrupt Priority Level - bit 3
SSCRIC.ILVL_2     2   Interrupt Priority Level - bit 2
SSCRIC.GLVL_1     1   Group Level - bit 1
SSCRIC.GLVL_0     0   Group Level - bit 0
SSCEIC           0xFF76   SSC Error Interrupt Control Register
SSCEIC.SSCEIR     7   Interrupt Request Flag
SSCEIC.SSCEIE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
SSCEIC.ILVL_5     5   Interrupt Priority Level - bit 5
SSCEIC.ILVL_4     4   Interrupt Priority Level - bit 4
SSCEIC.ILVL_3     3   Interrupt Priority Level - bit 3
SSCEIC.ILVL_2     2   Interrupt Priority Level - bit 2
SSCEIC.GLVL_1     1   Group Level - bit 1
SSCEIC.GLVL_0     0   Group Level - bit 0
URD3IC           0xFF78   UDC RX Done3  Interrupt Control Register
URD3IC.URD3IR     7   Interrupt Request Flag
URD3IC.URD3IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
URD3IC.ILVL_5     5   Interrupt Priority Level - bit 5
URD3IC.ILVL_4     4   Interrupt Priority Level - bit 4
URD3IC.ILVL_3     3   Interrupt Priority Level - bit 3
URD3IC.ILVL_2     2   Interrupt Priority Level - bit 2
URD3IC.GLVL_1     1   Group Level - bit 1
URD3IC.GLVL_0     0   Group Level - bit 0
URD4IC           0xFF7A   UDC RX Done4  Interrupt Control Register
URD4IC.URD4IR     7   Interrupt Request Flag
URD4IC.URD4IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
URD4IC.ILVL_5     5   Interrupt Priority Level - bit 5
URD4IC.ILVL_4     4   Interrupt Priority Level - bit 4
URD4IC.ILVL_3     3   Interrupt Priority Level - bit 3
URD4IC.ILVL_2     2   Interrupt Priority Level - bit 2
URD4IC.GLVL_1     1   Group Level - bit 1
URD4IC.GLVL_0     0   Group Level - bit 0
URD5IC           0xFF7C   UDC RX Done5  Interrupt Control Register
URD5IC.URD5IR     7   Interrupt Request Flag
URD5IC.URD5IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
URD5IC.ILVL_5     5   Interrupt Priority Level - bit 5
URD5IC.ILVL_4     4   Interrupt Priority Level - bit 4
URD5IC.ILVL_3     3   Interrupt Priority Level - bit 3
URD5IC.ILVL_2     2   Interrupt Priority Level - bit 2
URD5IC.GLVL_1     1   Group Level - bit 1
URD5IC.GLVL_0     0   Group Level - bit 0
URD6IC           0xFF7E   UDC RX Done6  Interrupt Control Register
URD6IC.URD6IR     7   Interrupt Request Flag
URD6IC.URD6IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
URD6IC.ILVL_5     5   Interrupt Priority Level - bit 5
URD6IC.ILVL_4     4   Interrupt Priority Level - bit 4
URD6IC.ILVL_3     3   Interrupt Priority Level - bit 3
URD6IC.ILVL_2     2   Interrupt Priority Level - bit 2
URD6IC.GLVL_1     1   Group Level - bit 1
URD6IC.GLVL_0     0   Group Level - bit 0
URD7IC           0xFF80   UDC RX Done7  Interrupt Control Register
URD7IC.URD7IR     7   Interrupt Request Flag
URD7IC.URD7IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
URD7IC.ILVL_5     5   Interrupt Priority Level - bit 5
URD7IC.ILVL_4     4   Interrupt Priority Level - bit 4
URD7IC.ILVL_3     3   Interrupt Priority Level - bit 3
URD7IC.ILVL_2     2   Interrupt Priority Level - bit 2
URD7IC.GLVL_1     1   Group Level - bit 1
URD7IC.GLVL_0     0   Group Level - bit 0
UTD0IC           0xFF82   UDC TX Done0  Interrupt Control Register
UTD0IC.UTD0IR     7   Interrupt Request Flag
UTD0IC.UTD0IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
UTD0IC.ILVL_5     5   Interrupt Priority Level - bit 5
UTD0IC.ILVL_4     4   Interrupt Priority Level - bit 4
UTD0IC.ILVL_3     3   Interrupt Priority Level - bit 3
UTD0IC.ILVL_2     2   Interrupt Priority Level - bit 2
UTD0IC.GLVL_1     1   Group Level - bit 1
UTD0IC.GLVL_0     0   Group Level - bit 0
UTD1IC           0xFF84   UDC TX Done1  Interrupt Control Register
UTD1IC.UTD1IR     7   Interrupt Request Flag
UTD1IC.UTD1IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
UTD1IC.ILVL_5     5   Interrupt Priority Level - bit 5
UTD1IC.ILVL_4     4   Interrupt Priority Level - bit 4
UTD1IC.ILVL_3     3   Interrupt Priority Level - bit 3
UTD1IC.ILVL_2     2   Interrupt Priority Level - bit 2
UTD1IC.GLVL_1     1   Group Level - bit 1
UTD1IC.GLVL_0     0   Group Level - bit 0
UTD2IC           0xFF86   UDC TX Done2  Interrupt Control Register
UTD2IC.UTD2IR     7   Interrupt Request Flag
UTD2IC.UTD2IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
UTD2IC.ILVL_5     5   Interrupt Priority Level - bit 5
UTD2IC.ILVL_4     4   Interrupt Priority Level - bit 4
UTD2IC.ILVL_3     3   Interrupt Priority Level - bit 3
UTD2IC.ILVL_2     2   Interrupt Priority Level - bit 2
UTD2IC.GLVL_1     1   Group Level - bit 1
UTD2IC.GLVL_0     0   Group Level - bit 0
FEI0IC           0xFF88   Fast External Interrupt 0 Control Register
FEI0IC.FEI0IR     7   Interrupt Request Flag
FEI0IC.FEI0IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
FEI0IC.ILVL_5     5   Interrupt Priority Level - bit 5
FEI0IC.ILVL_4     4   Interrupt Priority Level - bit 4
FEI0IC.ILVL_3     3   Interrupt Priority Level - bit 3
FEI0IC.ILVL_2     2   Interrupt Priority Level - bit 2
FEI0IC.GLVL_1     1   Group Level - bit 1
FEI0IC.GLVL_0     0   Group Level - bit 0
FEI1IC           0xFF8A   Fast External Interrupt 1 Control Register
FEI1IC.FEI1IR     7   Interrupt Request Flag
FEI1IC.FEI1IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
FEI1IC.ILVL_5     5   Interrupt Priority Level - bit 5
FEI1IC.ILVL_4     4   Interrupt Priority Level - bit 4
FEI1IC.ILVL_3     3   Interrupt Priority Level - bit 3
FEI1IC.ILVL_2     2   Interrupt Priority Level - bit 2
FEI1IC.GLVL_1     1   Group Level - bit 1
FEI1IC.GLVL_0     0   Group Level - bit 0
RES4IC           0xFF98   reserved
URD2IC           0xFF9C   UDC RX Done2  Interrupt Control Register
URD2IC.URD2IR     7   Interrupt Request Flag
URD2IC.URD2IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
URD2IC.ILVL_5     5   Interrupt Priority Level - bit 5
URD2IC.ILVL_4     4   Interrupt Priority Level - bit 4
URD2IC.ILVL_3     3   Interrupt Priority Level - bit 3
URD2IC.ILVL_2     2   Interrupt Priority Level - bit 2
URD2IC.GLVL_1     1   Group Level - bit 1
URD2IC.GLVL_0     0   Group Level - bit 0
URD1IC           0xFF9E   UDC RX Done1  Interrupt Control Register
URD1IC.URD1IR     7   Interrupt Request Flag
URD1IC.URD1IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
URD1IC.ILVL_5     5   Interrupt Priority Level - bit 5
URD1IC.ILVL_4     4   Interrupt Priority Level - bit 4
URD1IC.ILVL_3     3   Interrupt Priority Level - bit 3
URD1IC.ILVL_2     2   Interrupt Priority Level - bit 2
URD1IC.GLVL_1     1   Group Level - bit 1
URD1IC.GLVL_0     0   Group Level - bit 0
CLISNC           0xFFA8   The channel link interrupt subnode register
CLISNC.C6IR       13  Channel Service Request Flag
CLISNC.C6IE       12  Channel Link Interrupt Enable Bit
CLISNC.C4IR       9   Channel Service Request Flag
CLISNC.C4IE       8   Channel Link Interrupt Enable Bit
CLISNC.C2IR       5   Channel Service Request Flag
CLISNC.C2IE       4   Channel Link Interrupt Enable Bit
CLISNC.C0IR       1   Channel Service Request Flag
CLISNC.C0IE       0   Channel Link Interrupt Enable Bit
FOCON            0xFFAA   Frequency Output Control Register
FOCON.FOEN        15  Frequency Output Enable
FOCON.FOSS        14  Frequency Output Signal Select
FOCON.FORV_13     13  Frequency Output Reload Value - bit 13
FOCON.FORV_12     12  Frequency Output Reload Value - bit 12
FOCON.FORV_11     11  Frequency Output Reload Value - bit 11
FOCON.FORV_10     10  Frequency Output Reload Value - bit 10
FOCON.FORV_9      9   Frequency Output Reload Value - bit 9 
FOCON.FORV_8      8   Frequency Output Reload Value - bit 8 
FOCON.FOTL        6   Frequency Output Toggle Latch
FOCON.FOCNT_5     5   Frequency Output Counter - bit 5
FOCON.FOCNT_4     4   Frequency Output Counter - bit 4
FOCON.FOCNT_3     3   Frequency Output Counter - bit 3
FOCON.FOCNT_2     2   Frequency Output Counter - bit 2
FOCON.FOCNT_1     1   Frequency Output Counter - bit 1
FOCON.FOCNT_0     0   Frequency Output Counter - bit 0
TFR              0xFFAC   Trap Flag Register
TFR.NMI           15  Non Maskable Interrupt Flag
TFR.STKOF         14  Stack Overflow Flag
TFR.STKUF         13  Stack Underflow Flag
TFR.UNDOPC        7   Undefined Opcode Flag
TFR.PRTFLT        3   Protection Fault Flag
TFR.ILLOPA        2   Illegal Word Operand Access Flag
TFR.ILLINA        1   Illegal Instruction Access Flag
TFR.ILLBUS        0   Illegal External Bus Access Flag
WDTCON           0xFFAE   Watchdog Timer Control Register
WDTCON.WDTREL_15  15  Watchdog Timer Reload Value - bit 15
WDTCON.WDTREL_14  14  Watchdog Timer Reload Value - bit 14
WDTCON.WDTREL_13  13  Watchdog Timer Reload Value - bit 13
WDTCON.WDTREL_12  12  Watchdog Timer Reload Value - bit 12
WDTCON.WDTREL_11  11  Watchdog Timer Reload Value - bit 11
WDTCON.WDTREL_10  10  Watchdog Timer Reload Value - bit 10
WDTCON.WDTREL_9   9   Watchdog Timer Reload Value - bit 9 
WDTCON.WDTREL_8   8   Watchdog Timer Reload Value - bit 8 
WDTCON.LHWR       4   Long Hardware Reset Indication Flag
WDTCON.SHWR       3   Short Hardware Reset Indication Flag
WDTCON.SWR        2   Software Reset Indication Flag
WDTCON.WDTR       1   Watchdog Timer Reset Indication Flag
WDTCON.WDTIN      0   Watchdog Timer Input Frequency Select
S0CON            0xFFB0   Serial Channel 0 Control Register
S0CON.R         15  Baudrate Generator Run Bit
S0CON.LB        14  LoopBack Mode Enable Bit
S0CON.BRS       13  Baudrate Selection Bit
S0CON.ODD       12  Parity Selection Bit
S0CON.FDE       11  Fractional Divider Enable
S0CON.OE        10  Overrun Error Flag
S0CON.FE        9   Framing Error Flag
S0CON.PE        8   Parity Error Flag
S0CON.OEN       7   Overrun Check Enable Bit
S0CON.FEN       6   Framing Check Enable Bit
S0CON.PEN_RXDI  5   Parity Check Enable / IrDA Input Inverter Enable
S0CON.REN       4   Receiver Enable Bit
S0CON.STP       3   Number of Stop Bits Selection
S0CON.M_2       2   ASC0 Mode Control - bit 2
S0CON.M_1       1   ASC0 Mode Control - bit 1
S0CON.M_0       0   ASC0 Mode Control - bit 0
SSCCON           0xFFB2   SSC Control Register
S0CLC            0xFFBA   ASC Clock Control Register
S0CLC.EXDISR      3   External Disable Request
S0CLC.SUSPEN      2   Peripheral Suspend Enable Bit for OCDS
S0CLC.S0DISS      1   ASC Disable Status Bit
S0CLC.S0DISR      0   ASC Disable Request Bit
P2               0xFFC0   Port 2 Register
P2.P2_1           1   Port data register P2 bit 1 
P2.P2_0           0   Port data register P2 bit 0 
DP2              0xFFC2   Port 2 Direction Control Register
DP2.DP2_1         1   Port direction register DP2 bit 1
DP2.DP2_0         0   Port direction register DP2 bit 0
P3               0xFFC4   Port 3 Register
P3.P3_15          15  Port data register P3 bit 15
P3.P3_13          13  Port data register P3 bit 13
P3.P3_12          12  Port data register P3 bit 12
P3.P3_11          11  Port data register P3 bit 11
P3.P3_10          10  Port data register P3 bit 10
P3.P3_9           9   Port data register P3 bit 9 
P3.P3_8           8   Port data register P3 bit 8 
P3.P3_6           6   Port data register P3 bit 6 
P3.P3_5           5   Port data register P3 bit 5 
P3.P3_3           3   Port data register P3 bit 3 
DP3              0xFFC6   Port 3 Direction Control Register
DP3.DP3_15        15  Port direction register DP3 bit 15
DP3.DP3_13        13  Port direction register DP3 bit 13
DP3.DP3_12        12  Port direction register DP3 bit 12
DP3.DP3_11        11  Port direction register DP3 bit 11
DP3.DP3_10        10  Port direction register DP3 bit 10
DP3.DP3_9         9   Port direction register DP3 bit 9 
DP3.DP3_8         8   Port direction register DP3 bit 8 
DP3.DP3_6         6   Port direction register DP3 bit 6 
DP3.DP3_5         5   Port direction register DP3 bit 5 
DP3.DP3_3         3   Port direction register DP3 bit 3 
P4               0xFFC8   Port 4 Register (8 bits)
P4.P4_4           4   Port data register P4 bit 4 
P4.P4_3           3   Port data register P4 bit 3 
P4.P4_2           2   Port data register P4 bit 2 
P4.P4_1           1   Port data register P4 bit 1 
P4.P4_0           0   Port data register P4 bit 0 
DP4              0xFFCA   Port 4 Direction Control Register
DP4.DP4_4         4   Port direction register DP4 bit 4 
DP4.DP4_3         3   Port direction register DP4 bit 3 
DP4.DP4_2         2   Port direction register DP4 bit 2 
DP4.DP4_1         1   Port direction register DP4 bit 1 
DP4.DP4_0         0   Port direction register DP4 bit 0 
P6               0xFFCC   Port 6 Register (8 bits)
P6.P6_7           7   Port data register P6 bit 7 
P6.P6_6           6   Port data register P6 bit 6 
P6.P6_5           5   Port data register P6 bit 5 
P6.P6_3           3   Port data register P6 bit 3 
P6.P6_2           2   Port data register P6 bit 2 
P6.P6_1           1   Port data register P6 bit 1 
P6.P6_0           0   Port data register P6 bit 0 
DP6              0xFFCE   Port 6 Direction Control Register
DP6.DP6_7         7   Port direction register DP6 bit 7 
DP6.DP6_6         6   Port direction register DP6 bit 6 
DP6.DP6_5         5   Port direction register DP6 bit 5 
DP6.DP6_3         3   Port direction register DP6 bit 3 
DP6.DP6_2         2   Port direction register DP6 bit 2 
DP6.DP6_1         1   Port direction register DP6 bit 1 
DP6.DP6_0         0   Port direction register DP6 bit 0 


.C161V_K
; Register Declarations for C161V/K/O and C161SI/CI/RI Processor
; m161.pdf

; C161CS-32RF    (ROM 265 KB, RAM 10 KB)
; C161K-LM       (RAM 1 KB)
; C161O-LM       (RAM 2 KB)
; C161O-LM 3V    (RAM 2 KB)
; C161PI-LM      (RAM 3 KB)
; C161PI-LF      (RAM 3 KB)
; C161PI-LM 3V   (RAM 3 KB)
; C161PI-LF 3V   (RAM 3 KB)


; MEMORY MAP
area CODE ROM            0x0000:0x8000   Internal ROM Area
area CODE MEM_EXT        0x8000:0xF000   External Memory
area DATA E_SFR          0xF000:0xF200   ESFR Area
area BSS  RESERVED       0xF200:0xF600   
area CODE RAM            0xF600:0xFE00   External RAM
area DATA SFR            0xFE00:0x10000  SFR Area


; Interrupt and reset vector assignments
entry RESET     0x0000   RESET
entry NMITRAP   0x0008   NMITRAP Non-Maskable Interrupt (Class A Hardware Traps)
entry STOTRAP   0x0010   STOTRAP Stack Overflow (Class A Hardware Traps)
entry STUTRAP   0x0018   STUTRAP Stack Underflow (Class A Hardware Traps)
entry BTRAP     0x0028   BTRAP Class B Hardware Traps
entry CC9INT    0x0064   External Interrupt 1
entry CC10INT   0x0068   External Interrupt 2
entry CC11INT   0x006C   External Interrupt 3
entry CC12INT   0x0070   External Interrupt 4
entry CC13INT   0x0074   External Interrupt 5
entry CC14INT   0x0078   External Interrupt 6
entry CC15INT   0x007C   External Interrupt 7
entry T2INT     0x0088   GPT1 Timer 2 
entry T3INT     0x008C   GPT1 Timer 3 
entry T4INT     0x0090   GPT1 Timer 4 
entry T5INT     0x0094   GPT2 Timer 5 
entry T6INT     0x0098   GPT2 Timer 6 
entry CRINT     0x009C   GPT2 CAPREL Reg
entry S0TINT    0x00A8   ASC0 Transmit 
entry S0RINT    0x00AC   ASC0 Receive 
entry S0EINT    0x00B0   ASC0 Error 
entry SCTINT    0x00B4   SSC Transmit 
entry SCRINT    0x00B8   SSC Receive 
entry SCEINT    0x00BC   SSC Error 
entry S0TBINT   0x011C   ASC0 Transmit Buffer 


; INPUT/OUTPUT PORTS
SSCTB            0xF0B0 SSC Transmit Buffer
SSCRB            0xF0B2 SSC Receive Buffer
SSCBR            0xF0B4 SSC Baudrate Register
DP0L             0xF100 P0L Direction Control Register
DP0L.DP0L_7       7   Port direction register DP0L bit 7
DP0L.DP0L_6       6   Port direction register DP0L bit 6
DP0L.DP0L_5       5   Port direction register DP0L bit 5
DP0L.DP0L_4       4   Port direction register DP0L bit 4
DP0L.DP0L_3       3   Port direction register DP0L bit 3
DP0L.DP0L_2       2   Port direction register DP0L bit 2
DP0L.DP0L_1       1   Port direction register DP0L bit 1
DP0L.DP0L_0       0   Port direction register DP0L bit 0
DP0H             0xF102 P0H Direction Control Register
DP0H.DP0H_7       7   Port direction register DP0H bit 7
DP0H.DP0H_6       6   Port direction register DP0H bit 6
DP0H.DP0H_5       5   Port direction register DP0H bit 5
DP0H.DP0H_4       4   Port direction register DP0H bit 4
DP0H.DP0H_3       3   Port direction register DP0H bit 3
DP0H.DP0H_2       2   Port direction register DP0H bit 2
DP0H.DP0H_1       1   Port direction register DP0H bit 1
DP0H.DP0H_0       0   Port direction register DP0H bit 0
DP1L             0xF104 P1L Direction Control Register
DP1L.DP1L_7       7   Port direction register DP1L bit 7
DP1L.DP1L_6       6   Port direction register DP1L bit 6
DP1L.DP1L_5       5   Port direction register DP1L bit 5
DP1L.DP1L_4       4   Port direction register DP1L bit 4
DP1L.DP1L_3       3   Port direction register DP1L bit 3
DP1L.DP1L_2       2   Port direction register DP1L bit 2
DP1L.DP1L_1       1   Port direction register DP1L bit 1
DP1L.DP1L_0       0   Port direction register DP1L bit 0
DP1H             0xF106 P1H Direction Control Register
DP1H.DP1H_7       7   Port direction register DP1H bit 7
DP1H.DP1H_6       6   Port direction register DP1H bit 6
DP1H.DP1H_5       5   Port direction register DP1H bit 5
DP1H.DP1H_4       4   Port direction register DP1H bit 4
DP1H.DP1H_3       3   Port direction register DP1H bit 3
DP1H.DP1H_2       2   Port direction register DP1H bit 2
DP1H.DP1H_1       1   Port direction register DP1H bit 1
DP1H.DP1H_0       0   Port direction register DP1H bit 0
RP0H             0xF108 System Startup Configuration Register (read only)
RP0H.CLKCFG7      7   Clock Generation Mode Configuration bit 7
RP0H.CLKCFG6      6   Clock Generation Mode Configuration bit 6
RP0H.CLKCFG5      5   Clock Generation Mode Configuration bit 5
RP0H.SALSEL4      4   Segment Address Line Selection bit 4
RP0H.SALSEL3      3   Segment Address Line Selection bit 3
RP0H.CSSEL2       2   Chip Select Line Selection bit 2
RP0H.CSSEL1       1   Chip Select Line Selection bit 1
RP0H.WRC          0   Write Configuration
S0TBIC           0xF19C Serial Channel 0 Transmit Buffer Interrupt Control Register
S0TBIC.S0TBIR     7
S0TBIC.S0TBIE     6
S0TBIC.ILVL5      5
S0TBIC.ILVL4      4
S0TBIC.ILVL3      3
S0TBIC.ILVL2      2
S0TBIC.GLVL1      1
S0TBIC.GLVL0      0
EXICON           0xF1C0 External Interrupt Control Register
EXICON.EXI7ES15   15  External Interrupt 7 Edge Selection bit 15
EXICON.EXI7ES14   14  External Interrupt 7 Edge Selection bit 14
EXICON.EXI6ES13   13  External Interrupt 6 Edge Selection bit 13
EXICON.EXI6ES12   12  External Interrupt 6 Edge Selection bit 12
EXICON.EXI5ES11   11  External Interrupt 5 Edge Selection bit 11
EXICON.EXI5ES10   10  External Interrupt 5 Edge Selection bit 10
EXICON.EXI4ES9    9   External Interrupt 4 Edge Selection bit 9 
EXICON.EXI4ES8    8   External Interrupt 4 Edge Selection bit 8 
EXICON.EXI3ES7    7   External Interrupt 3 Edge Selection bit 7 
EXICON.EXI3ES6    6   External Interrupt 3 Edge Selection bit 6 
EXICON.EXI2ES5    5   External Interrupt 2 Edge Selection bit 5 
EXICON.EXI2ES4    4   External Interrupt 2 Edge Selection bit 4 
EXICON.EXI1ES3    3   External Interrupt 1 Edge Selection bit 3 
EXICON.EXI1ES2    2   External Interrupt 1 Edge Selection bit 2 
ODP2             0xF1C2 Port 2 Open Drain Control Register
ODP2.ODP2_15      15  Port 2 Open Drain control register bit 15
ODP2.ODP2_14      14  Port 2 Open Drain control register bit 14
ODP2.ODP2_13      13  Port 2 Open Drain control register bit 13
ODP2.ODP2_12      12  Port 2 Open Drain control register bit 12
ODP2.ODP2_11      11  Port 2 Open Drain control register bit 11
ODP2.ODP2_10      10  Port 2 Open Drain control register bit 10
ODP2.ODP2_9       9   Port 2 Open Drain control register bit 9 
ODP3             0xF1C6 Port 3 Open Drain Control Register
ODP3.ODP3_13      13  Port 3 Open Drain control register bit 13
ODP3.ODP3_11      11  Port 3 Open Drain control register bit 11
ODP3.ODP3_10      10  Port 3 Open Drain control register bit 10
ODP3.ODP3_9       9   Port 3 Open Drain control register bit 9 
ODP3.ODP3_8       8   Port 3 Open Drain control register bit 8 
ODP3.ODP3_7       7   Port 3 Open Drain control register bit 7 
ODP3.ODP3_6       6   Port 3 Open Drain control register bit 6 
ODP3.ODP3_5       5   Port 3 Open Drain control register bit 5 
ODP3.ODP3_4       4   Port 3 Open Drain control register bit 4 
ODP3.ODP3_3       3   Port 3 Open Drain control register bit 3 
ODP3.ODP3_2       2   Port 3 Open Drain control register bit 2 
ODP6             0xF1CE Port 6 Open Drain Control Register
ODP6.ODP6_3       3   Port 6 Open Drain control register bit 3
ODP6.ODP6_2       2   Port 6 Open Drain control register bit 2
ODP6.ODP6_1       1   Port 6 Open Drain control register bit 1
ODP6.ODP6_0       0   Port 6 Open Drain control register bit 0
DPP0             0xFE00 CPU Data Page Pointer 0 Register (10 bits)
DPP0.DPP0PN9      9   Data Page Number of DPP9
DPP0.DPP0PN8      8   Data Page Number of DPP8
DPP0.DPP0PN7      7   Data Page Number of DPP7
DPP0.DPP0PN6      6   Data Page Number of DPP6
DPP0.DPP0PN5      5   Data Page Number of DPP5
DPP0.DPP0PN4      4   Data Page Number of DPP4
DPP0.DPP0PN3      3   Data Page Number of DPP3
DPP0.DPP0PN2      2   Data Page Number of DPP2
DPP0.DPP0PN1      1   Data Page Number of DPP1
DPP0.DPP0PN0      0   Data Page Number of DPP0
DPP1             0xFE02 CPU Data Page Pointer 1 Register (10 bits)
DPP1.DPP1PN9      9   Data Page Number of DPP9
DPP1.DPP1PN8      8   Data Page Number of DPP8
DPP1.DPP1PN7      7   Data Page Number of DPP7
DPP1.DPP1PN6      6   Data Page Number of DPP6
DPP1.DPP1PN5      5   Data Page Number of DPP5
DPP1.DPP1PN4      4   Data Page Number of DPP4
DPP1.DPP1PN3      3   Data Page Number of DPP3
DPP1.DPP1PN2      2   Data Page Number of DPP2
DPP1.DPP1PN1      1   Data Page Number of DPP1
DPP1.DPP1PN0      0   Data Page Number of DPP0
DPP2             0xFE04 CPU Data Page Pointer 2 Register (10 bits)
DPP2.DPP2PN9      9   Data Page Number of DPP9
DPP2.DPP2PN8      8   Data Page Number of DPP8
DPP2.DPP2PN7      7   Data Page Number of DPP7
DPP2.DPP2PN6      6   Data Page Number of DPP6
DPP2.DPP2PN5      5   Data Page Number of DPP5
DPP2.DPP2PN4      4   Data Page Number of DPP4
DPP2.DPP2PN3      3   Data Page Number of DPP3
DPP2.DPP2PN2      2   Data Page Number of DPP2
DPP2.DPP2PN1      1   Data Page Number of DPP1
DPP2.DPP2PN0      0   Data Page Number of DPP0
DPP3             0xFE06 CPU Data Page Pointer 3 Register (10 bits)
DPP3.DPP3PN9      9   Data Page Number of DPP9
DPP3.DPP3PN8      8   Data Page Number of DPP8
DPP3.DPP3PN7      7   Data Page Number of DPP7
DPP3.DPP3PN6      6   Data Page Number of DPP6
DPP3.DPP3PN5      5   Data Page Number of DPP5
DPP3.DPP3PN4      4   Data Page Number of DPP4
DPP3.DPP3PN3      3   Data Page Number of DPP3
DPP3.DPP3PN2      2   Data Page Number of DPP2
DPP3.DPP3PN1      1   Data Page Number of DPP1
DPP3.DPP3PN0      0   Data Page Number of DPP0
CSP              0xFE08 CPU Code Segment Pointer Register (8 bits, not directly writeable)
CSP.SEGNR7        7   Segment Number 7
CSP.SEGNR6        6   Segment Number 6
CSP.SEGNR5        5   Segment Number 5
CSP.SEGNR4        4   Segment Number 4
CSP.SEGNR3        3   Segment Number 3
CSP.SEGNR2        2   Segment Number 2
CSP.SEGNR1        1   Segment Number 1
CSP.SEGNR0        0   Segment Number 0
MDH              0xFE0C CPU Multiply Divide Register - High Word
MDH.MDH15         15
MDH.MDH14         14
MDH.MDH13         13
MDH.MDH12         12
MDH.MDH11         11
MDH.MDH10         10
MDH.MDH9          9
MDH.MDH8          8
MDH.MDH7          7
MDH.MDH6          6
MDH.MDH5          5
MDH.MDH4          4
MDH.MDH3          3
MDH.MDH2          2
MDH.MDH1          1
MDH.MDH0          0
MDL              0xFE0E CPU Multiply Divide Register - Low Word
MDL.MDL15         15
MDL.MDL14         14
MDL.MDL13         13
MDL.MDL12         12
MDL.MDL11         11
MDL.MDL10         10
MDL.MDL9          9
MDL.MDL8          8
MDL.MDL7          7
MDL.MDL6          6
MDL.MDL5          5
MDL.MDL4          4
MDL.MDL3          3
MDL.MDL2          2
MDL.MDL1          1
MDL.MDL0          0
CP               0xFE10 CPU Context Pointer Register
CP.CP11           11  Modifiable portion of register CP bit 11
CP.CP10           10  Modifiable portion of register CP bit 10
CP.CP9            9   Modifiable portion of register CP bit 9 
CP.CP8            8   Modifiable portion of register CP bit 8 
CP.CP7            7   Modifiable portion of register CP bit 7 
CP.CP6            6   Modifiable portion of register CP bit 6 
CP.CP5            5   Modifiable portion of register CP bit 5 
CP.CP4            4   Modifiable portion of register CP bit 4 
CP.CP3            3   Modifiable portion of register CP bit 3 
CP.CP2            2   Modifiable portion of register CP bit 2 
CP.CP1            1   Modifiable portion of register CP bit 1 
SP               0xFE12 CPU System Stack Pointer Register
SP.SP11           11  Modifiable portion of register SP 11
SP.SP10           10  Modifiable portion of register SP 10
SP.SP9            9   Modifiable portion of register SP 9 
SP.SP8            8   Modifiable portion of register SP 8 
SP.SP7            7   Modifiable portion of register SP 7 
SP.SP6            6   Modifiable portion of register SP 6 
SP.SP5            5   Modifiable portion of register SP 5 
SP.SP4            4   Modifiable portion of register SP 4 
SP.SP3            3   Modifiable portion of register SP 3 
SP.SP2            2   Modifiable portion of register SP 2 
SP.SP1            1   Modifiable portion of register SP 1 
STKOV            0xFE14 CPU Stack Overflow Pointer Register
STKOV.STKOV11     11  Modifiable portion of register STKOV bit 11
STKOV.STKOV10     10  Modifiable portion of register STKOV bit 10
STKOV.STKOV9      9   Modifiable portion of register STKOV bit 9 
STKOV.STKOV8      8   Modifiable portion of register STKOV bit 8 
STKOV.STKOV7      7   Modifiable portion of register STKOV bit 7 
STKOV.STKOV6      6   Modifiable portion of register STKOV bit 6 
STKOV.STKOV5      5   Modifiable portion of register STKOV bit 5 
STKOV.STKOV4      4   Modifiable portion of register STKOV bit 4 
STKOV.STKOV3      3   Modifiable portion of register STKOV bit 3 
STKOV.STKOV2      2   Modifiable portion of register STKOV bit 2 
STKOV.STKOV1      1   Modifiable portion of register STKOV bit 1 
STKUN            0xFE16 CPU Stack Underflow Pointer Register
STKUN.STKUN11     11  Modifiable portion of register STKUN bit 11
STKUN.STKUN10     10  Modifiable portion of register STKUN bit 10
STKUN.STKUN9      9   Modifiable portion of register STKUN bit 9 
STKUN.STKUN8      8   Modifiable portion of register STKUN bit 8 
STKUN.STKUN7      7   Modifiable portion of register STKUN bit 7 
STKUN.STKUN6      6   Modifiable portion of register STKUN bit 6 
STKUN.STKUN5      5   Modifiable portion of register STKUN bit 5 
STKUN.STKUN4      4   Modifiable portion of register STKUN bit 4 
STKUN.STKUN3      3   Modifiable portion of register STKUN bit 3 
STKUN.STKUN2      2   Modifiable portion of register STKUN bit 2 
STKUN.STKUN1      1   Modifiable portion of register STKUN bit 1 
ADDRSEL1         0xFE18 Address Select Register 1
ADDRSEL1.RGSAD15  15  Range Start Address bit 15
ADDRSEL1.RGSAD14  14  Range Start Address bit 14
ADDRSEL1.RGSAD13  13  Range Start Address bit 13
ADDRSEL1.RGSAD12  12  Range Start Address bit 12
ADDRSEL1.RGSAD11  11  Range Start Address bit 11
ADDRSEL1.RGSAD10  10  Range Start Address bit 10
ADDRSEL1.RGSAD9   9   Range Start Address bit 9 
ADDRSEL1.RGSAD8   8   Range Start Address bit 8 
ADDRSEL1.RGSAD7   7   Range Start Address bit 7 
ADDRSEL1.RGSAD6   6   Range Start Address bit 6 
ADDRSEL1.RGSAD5   5   Range Start Address bit 5 
ADDRSEL1.RGSAD4   4   Range Start Address bit 4 
ADDRSEL1.RGSZ3    3   Range Size Selection bit 3
ADDRSEL1.RGSZ2    2   Range Size Selection bit 2
ADDRSEL1.RGSZ1    1   Range Size Selection bit 1
ADDRSEL1.RGSZ0    0   Range Size Selection bit 0
ADDRSEL2         0xFE1A Address Select Register 2
ADDRSEL2.RGSAD15  15  Range Start Address bit 15
ADDRSEL2.RGSAD14  14  Range Start Address bit 14
ADDRSEL2.RGSAD13  13  Range Start Address bit 13
ADDRSEL2.RGSAD12  12  Range Start Address bit 12
ADDRSEL2.RGSAD11  11  Range Start Address bit 11
ADDRSEL2.RGSAD10  10  Range Start Address bit 10
ADDRSEL2.RGSAD9   9   Range Start Address bit 9 
ADDRSEL2.RGSAD8   8   Range Start Address bit 8 
ADDRSEL2.RGSAD7   7   Range Start Address bit 7 
ADDRSEL2.RGSAD6   6   Range Start Address bit 6 
ADDRSEL2.RGSAD5   5   Range Start Address bit 5 
ADDRSEL2.RGSAD4   4   Range Start Address bit 4 
ADDRSEL2.RGSZ3    3   Range Size Selection bit 3
ADDRSEL2.RGSZ2    2   Range Size Selection bit 2
ADDRSEL2.RGSZ1    1   Range Size Selection bit 1
ADDRSEL2.RGSZ0    0   Range Size Selection bit 0
ADDRSEL3         0xFE1C Address Select Register 3
ADDRSEL3.RGSAD15  15  Range Start Address bit 15
ADDRSEL3.RGSAD14  14  Range Start Address bit 14
ADDRSEL3.RGSAD13  13  Range Start Address bit 13
ADDRSEL3.RGSAD12  12  Range Start Address bit 12
ADDRSEL3.RGSAD11  11  Range Start Address bit 11
ADDRSEL3.RGSAD10  10  Range Start Address bit 10
ADDRSEL3.RGSAD9   9   Range Start Address bit 9 
ADDRSEL3.RGSAD8   8   Range Start Address bit 8 
ADDRSEL3.RGSAD7   7   Range Start Address bit 7 
ADDRSEL3.RGSAD6   6   Range Start Address bit 6 
ADDRSEL3.RGSAD5   5   Range Start Address bit 5 
ADDRSEL3.RGSAD4   4   Range Start Address bit 4 
ADDRSEL3.RGSZ3    3   Range Size Selection bit 3
ADDRSEL3.RGSZ2    2   Range Size Selection bit 2
ADDRSEL3.RGSZ1    1   Range Size Selection bit 1
ADDRSEL3.RGSZ0    0   Range Size Selection bit 0
ADDRSEL4         0xFE1E Address Select Register 4
ADDRSEL4.RGSAD15  15  Range Start Address bit 15
ADDRSEL4.RGSAD14  14  Range Start Address bit 14
ADDRSEL4.RGSAD13  13  Range Start Address bit 13
ADDRSEL4.RGSAD12  12  Range Start Address bit 12
ADDRSEL4.RGSAD11  11  Range Start Address bit 11
ADDRSEL4.RGSAD10  10  Range Start Address bit 10
ADDRSEL4.RGSAD9   9   Range Start Address bit 9 
ADDRSEL4.RGSAD8   8   Range Start Address bit 8 
ADDRSEL4.RGSAD7   7   Range Start Address bit 7 
ADDRSEL4.RGSAD6   6   Range Start Address bit 6 
ADDRSEL4.RGSAD5   5   Range Start Address bit 5 
ADDRSEL4.RGSAD4   4   Range Start Address bit 4 
ADDRSEL4.RGSZ3    3   Range Size Selection bit 3
ADDRSEL4.RGSZ2    2   Range Size Selection bit 2
ADDRSEL4.RGSZ1    1   Range Size Selection bit 1
ADDRSEL4.RGSZ0    0   Range Size Selection bit 0
T2               0xFE40 GPT1 Timer 2 Register
T3               0xFE42 GPT1 Timer 3 Register
T4               0xFE44 GPT1 Timer 4 Register
WDT              0xFEAE Watchdog Timer Register (read only)
S0TBUF           0xFEB0 Serial Channel 0 Transmit Buffer Register
S0RBUF           0xFEB2 Serial Channel 0 Receive Buffer Register (read only)
S0BG             0xFEB4 Serial Channel 0 Baud Rate Generator Reload Register
PECC0            0xFEC0 PEC Channel 0 Control Register
PECC0.INC10       10  Increment Control bit 10
PECC0.INC9        9   Increment Control bit 9  
PECC0.BWT         8   Byte / Word Transfer Selection
PECC0.COUNT7      7   PEC Transfer Count bit 7
PECC0.COUNT6      6   PEC Transfer Count bit 6
PECC0.COUNT5      5   PEC Transfer Count bit 5
PECC0.COUNT4      4   PEC Transfer Count bit 4
PECC0.COUNT3      3   PEC Transfer Count bit 3
PECC0.COUNT2      2   PEC Transfer Count bit 2
PECC0.COUNT1      1   PEC Transfer Count bit 1
PECC0.COUNT0      0   PEC Transfer Count bit 0
PECC1            0xFEC2 PEC Channel 1 Control Register
PECC1.INC10       10  Increment Control bit 10
PECC1.INC9        9   Increment Control bit 9   
PECC1.BWT         8   Byte / Word Transfer Selection
PECC1.COUNT7      7   PEC Transfer Count bit 7
PECC1.COUNT6      6   PEC Transfer Count bit 6
PECC1.COUNT5      5   PEC Transfer Count bit 5
PECC1.COUNT4      4   PEC Transfer Count bit 4
PECC1.COUNT3      3   PEC Transfer Count bit 3
PECC1.COUNT2      2   PEC Transfer Count bit 2
PECC1.COUNT1      1   PEC Transfer Count bit 1
PECC1.COUNT0      0   PEC Transfer Count bit 0
PECC2            0xFEC4 PEC Channel 2 Control Register
PECC2.INC10       10  Increment Control bit 10
PECC2.INC9        9   Increment Control bit 9  
PECC2.BWT         8   Byte / Word Transfer Selection
PECC2.COUNT7      7   PEC Transfer Count bit 7
PECC2.COUNT6      6   PEC Transfer Count bit 6
PECC2.COUNT5      5   PEC Transfer Count bit 5
PECC2.COUNT4      4   PEC Transfer Count bit 4
PECC2.COUNT3      3   PEC Transfer Count bit 3
PECC2.COUNT2      2   PEC Transfer Count bit 2
PECC2.COUNT1      1   PEC Transfer Count bit 1
PECC2.COUNT0      0   PEC Transfer Count bit 0
PECC3            0xFEC6 PEC Channel 3 Control Register
PECC3.INC10       10  Increment Control bit 10
PECC3.INC9        9   Increment Control bit 9  
PECC3.BWT         8   Byte / Word Transfer Selection
PECC3.COUNT7      7   PEC Transfer Count bit 7
PECC3.COUNT6      6   PEC Transfer Count bit 6
PECC3.COUNT5      5   PEC Transfer Count bit 5
PECC3.COUNT4      4   PEC Transfer Count bit 4
PECC3.COUNT3      3   PEC Transfer Count bit 3
PECC3.COUNT2      2   PEC Transfer Count bit 2
PECC3.COUNT1      1   PEC Transfer Count bit 1
PECC3.COUNT0      0   PEC Transfer Count bit 0
PECC4            0xFEC8 PEC Channel 4 Control Register
PECC4.INC10       10  Increment Control bit 10
PECC4.INC9        9   Increment Control bit 9  
PECC4.BWT         8   Byte / Word Transfer Selection
PECC4.COUNT7      7   PEC Transfer Count bit 7
PECC4.COUNT6      6   PEC Transfer Count bit 6
PECC4.COUNT5      5   PEC Transfer Count bit 5
PECC4.COUNT4      4   PEC Transfer Count bit 4
PECC4.COUNT3      3   PEC Transfer Count bit 3
PECC4.COUNT2      2   PEC Transfer Count bit 2
PECC4.COUNT1      1   PEC Transfer Count bit 1
PECC4.COUNT0      0   PEC Transfer Count bit 0
PECC5            0xFECA PEC Channel 5 Control Register
PECC5.INC10       10  Increment Control bit 10
PECC5.INC9        9   Increment Control bit 9  
PECC5.BWT         8   Byte / Word Transfer Selection
PECC5.COUNT7      7   PEC Transfer Count bit 7
PECC5.COUNT6      6   PEC Transfer Count bit 6
PECC5.COUNT5      5   PEC Transfer Count bit 5
PECC5.COUNT4      4   PEC Transfer Count bit 4
PECC5.COUNT3      3   PEC Transfer Count bit 3
PECC5.COUNT2      2   PEC Transfer Count bit 2
PECC5.COUNT1      1   PEC Transfer Count bit 1
PECC5.COUNT0      0   PEC Transfer Count bit 0
PECC6            0xFECC PEC Channel 6 Control Register
PECC6.INC10       10  Increment Control bit 10
PECC6.INC9        9   Increment Control bit 9  
PECC6.BWT         8   Byte / Word Transfer Selection
PECC6.COUNT7      7   PEC Transfer Count bit 7
PECC6.COUNT6      6   PEC Transfer Count bit 6
PECC6.COUNT5      5   PEC Transfer Count bit 5
PECC6.COUNT4      4   PEC Transfer Count bit 4
PECC6.COUNT3      3   PEC Transfer Count bit 3
PECC6.COUNT2      2   PEC Transfer Count bit 2
PECC6.COUNT1      1   PEC Transfer Count bit 1
PECC6.COUNT0      0   PEC Transfer Count bit 0
PECC7            0xFECE PEC Channel 7 Control Register
PECC7.INC10       10  Increment Control bit 10
PECC7.INC9        9   Increment Control bit 9  
PECC7.BWT         8   Byte / Word Transfer Selection
PECC7.COUNT7      7   PEC Transfer Count bit 7
PECC7.COUNT6      6   PEC Transfer Count bit 6
PECC7.COUNT5      5   PEC Transfer Count bit 5
PECC7.COUNT4      4   PEC Transfer Count bit 4
PECC7.COUNT3      3   PEC Transfer Count bit 3
PECC7.COUNT2      2   PEC Transfer Count bit 2
PECC7.COUNT1      1   PEC Transfer Count bit 1
PECC7.COUNT0      0   PEC Transfer Count bit 0
P0L              0xFF00 Port 0 Low Register (Lower half of PORT0)
P0L.P0L_7         7   Port data register P0L bit 7
P0L.P0L_6         6   Port data register P0L bit 6
P0L.P0L_5         5   Port data register P0L bit 5
P0L.P0L_4         4   Port data register P0L bit 4
P0L.P0L_3         3   Port data register P0L bit 3
P0L.P0L_2         2   Port data register P0L bit 2
P0L.P0L_1         1   Port data register P0L bit 1
P0L.P0L_0         0   Port data register P0L bit 0
P0H              0xFF02 Port 0 High Register (Upper half of PORT0)
P0H.P0H_7         7   Port data register P0H bit 7
P0H.P0H_6         6   Port data register P0H bit 6
P0H.P0H_5         5   Port data register P0H bit 5
P0H.P0H_4         4   Port data register P0H bit 4
P0H.P0H_3         3   Port data register P0H bit 3
P0H.P0H_2         2   Port data register P0H bit 2
P0H.P0H_1         1   Port data register P0H bit 1
P0H.P0H_0         0   Port data register P0H bit 0
P1L              0xFF04 Port 1 Low Register (Lower half of PORT1)
P1L.P1L_7         7   Port data register P1L bit 7
P1L.P1L_6         6   Port data register P1L bit 6
P1L.P1L_5         5   Port data register P1L bit 5
P1L.P1L_4         4   Port data register P1L bit 4
P1L.P1L_3         3   Port data register P1L bit 3
P1L.P1L_2         2   Port data register P1L bit 2
P1L.P1L_1         1   Port data register P1L bit 1
P1L.P1L_0         0   Port data register P1L bit 0
P1H              0xFF06 Port 1 High Register (Upper half of PORT1)
P1H.P1H_7         7   Port data register P1H bit 7
P1H.P1H_6         6   Port data register P1H bit 6
P1H.P1H_5         5   Port data register P1H bit 5
P1H.P1H_4         4   Port data register P1H bit 4
P1H.P1H_3         3   Port data register P1H bit 3
P1H.P1H_2         2   Port data register P1H bit 2
P1H.P1H_1         1   Port data register P1H bit 1
P1H.P1H_0         0   Port data register P1H bit 0
BUSCON0          0xFF0C Bus Configuration Register 0
BUSCON0.CSWEN0    15  Write Chip Select Enable
BUSCON0.CSREN0    14  Read Chip Select Enable
BUSCON0.BUSACT0   10  Bus Active Control
BUSCON0.ALECTL0   9   ALE Lengthening Control
BUSCON0.BTYP7     7   External Bus Configuration bit 7
BUSCON0.BTYP6     6   External Bus Configuration bit 6
BUSCON0.MTTC0     5   Memory Tristate Time Control
BUSCON0.RWDC0     4   Read/Write Delay Control for BUSCON
BUSCON0.MCTC3     3   Memory Cycle Time Control bit 3
BUSCON0.MCTC2     2   Memory Cycle Time Control bit 2
BUSCON0.MCTC1     1   Memory Cycle Time Control bit 1
BUSCON0.MCTC0     0   Memory Cycle Time Control bit 0
MDC              0xFF0E CPU Multiply Divide Control Register
MDC.MDRIU         4   Multiply/Divide Register In Use
PSW              0xFF10 CPU Program Status Word
PSW.ILVL15        15  Interrupt Control Field 15
PSW.ILVL14        14  Interrupt Control Field 14
PSW.ILVL13        13  Interrupt Control Field 13
PSW.ILVL12        12  Interrupt Control Field 12
PSW.IEN           11  Interrupt Control Field
PSW.USR0          6   User General Purpose Flag
PSW.MULIP         5   Multiplication/Division In Progress
PSW.E             4   End of Table Flag
PSW.Z             3   Zero Flag
PSW.V             2   Overflow Result
PSW.C             1   Carry Flag
PSW.N             0   Negative Result
SYSCON           0xFF12 CPU System Configuration Register
SYSCON.STKSZ15    15  System Stack Size bit 15
SYSCON.STKSZ14    14  System Stack Size bit 14
SYSCON.STKSZ13    13  System Stack Size bit 13
SYSCON.ROMS1      12  Internal ROM Mapping
SYSCON.SGTDIS     11  Segmentation Disable/Enable Control
SYSCON.ROMEN      10  Internal ROM Enable
SYSCON.BYTDIS     9   Disable/Enable Control for Pin BHE
SYSCON.WRCFG      7   Write Configuration Control
SYSCON.XPEN       2   XBUS Peripheral Enable Bit
SYSCON.VISIBLE    1   Visible Mode Control
SYSCON.XPER_SHARE 0   XBUS Peripheral Share Mode Control
BUSCON1          0xFF14 Bus Configuration Register 1
BUSCON1.CSWEN1    15  Write Chip Select Enable
BUSCON1.CSREN1    14  Read Chip Select Enable
BUSCON1.BUSACT1   10  Bus Active Control
BUSCON1.ALECTL1   9   ALE Lengthening Control
BUSCON1.BTYP7     7   External Bus Configuration bit 7
BUSCON1.BTYP6     6   External Bus Configuration bit 6
BUSCON1.MTTC1     5   Memory Tristate Time Control
BUSCON1.RWDC1     4   Read/Write Delay Control for BUSCON
BUSCON1.MCTC3     3   Memory Cycle Time Control bit 3
BUSCON1.MCTC2     2   Memory Cycle Time Control bit 2
BUSCON1.MCTC1     1   Memory Cycle Time Control bit 1
BUSCON1.MCTC0     0   Memory Cycle Time Control bit 0
BUSCON2          0xFF16 Bus Configuration Register 2
BUSCON2.CSWEN2    15  Write Chip Select Enable
BUSCON2.CSREN2    14  Read Chip Select Enable
BUSCON2.BUSACT2   10  Bus Active Control
BUSCON2.ALECTL2   9   ALE Lengthening Control
BUSCON2.BTYP7     7   External Bus Configuration bit 7
BUSCON2.BTYP6     6   External Bus Configuration bit 6
BUSCON2.MTTC2     5   Memory Tristate Time Control
BUSCON2.RWDC2     4   Read/Write Delay Control for BUSCON
BUSCON2.MCTC3     3   Memory Cycle Time Control bit 3
BUSCON2.MCTC2     2   Memory Cycle Time Control bit 2
BUSCON2.MCTC1     1   Memory Cycle Time Control bit 1
BUSCON2.MCTC0     0   Memory Cycle Time Control bit 0
BUSCON3          0xFF18 Bus Configuration Register 3
BUSCON3.CSWEN3    15  Write Chip Select Enable
BUSCON3.CSREN3    14  Read Chip Select Enable
BUSCON3.BUSACT3   10  Bus Active Control
BUSCON3.ALECTL3   9   ALE Lengthening Control
BUSCON3.BTYP7     7   External Bus Configuration bit 7
BUSCON3.BTYP6     6   External Bus Configuration bit 6
BUSCON3.MTTC3     5   Memory Tristate Time Control
BUSCON3.RWDC3     4   Read/Write Delay Control for BUSCON
BUSCON3.MCTC3     3   Memory Cycle Time Control bit 3
BUSCON3.MCTC2     2   Memory Cycle Time Control bit 2
BUSCON3.MCTC1     1   Memory Cycle Time Control bit 1
BUSCON3.MCTC0     0   Memory Cycle Time Control bit 0
BUSCON4          0xFF1A Bus Configuration Register 4
BUSCON4.CSWEN4    15  Write Chip Select Enable
BUSCON4.CSREN4    14  Read Chip Select Enable
BUSCON4.BUSACT4   10  Bus Active Control
BUSCON4.ALECTL4   9   ALE Lengthening Control
BUSCON4.BTYP7     7   External Bus Configuration bit 7
BUSCON4.BTYP6     6   External Bus Configuration bit 6
BUSCON4.MTTC4     5   Memory Tristate Time Control
BUSCON4.RWDC4     4   Read/Write Delay Control for BUSCON
BUSCON4.MCTC3     3   Memory Cycle Time Control bit 3
BUSCON4.MCTC2     2   Memory Cycle Time Control bit 2
BUSCON4.MCTC1     1   Memory Cycle Time Control bit 1
BUSCON4.MCTC0     0   Memory Cycle Time Control bit 0
ZEROS            0xFF1C Constant Value 0's Register (read only)
ONES             0xFF1E Constant Value 1's Register (read only)
T2CON            0xFF40 GPT1 Timer 2 Control Register
T2CON.T2UDE       8   Timer 2 External Up/Down Enable
T2CON.T2UD        7   Timer 2 Up / Down Control
T2CON.T2R         6   Timer 2 Run Bit
T2CON.T2M5        5   Timer 2 Mode Control bit 5
T2CON.T2M4        4   Timer 2 Mode Control bit 4
T2CON.T2M3        3   Timer 2 Mode Control bit 3
T2CON.T2I2        2   Timer 2 Input Selection bit 2
T2CON.T2I1        1   Timer 2 Input Selection bit 1
T2CON.T2I0        0   Timer 2 Input Selection bit 0
T3CON            0xFF42 GPT1 Timer 3 Control Register
T3CON.T3OTL       10  Timer 3 Output Toggle Latch
T3CON.T3OE        9   Alternate Output Function Enable
T3CON.T3UDE       8   Timer 3 External Up/Down Enable
T3CON.T3UD        7   Timer 3 Up / Down Control
T3CON.T3R         6   Timer 3 Run Bit
T3CON.T3M5        5   Timer 3 Mode Control bit 5
T3CON.T3M4        4   Timer 3 Mode Control bit 4
T3CON.T3M3        3   Timer 3 Mode Control bit 3
T3CON.T3I2        2   Timer 3 Input Selection bit 2
T3CON.T3I1        1   Timer 3 Input Selection bit 1
T3CON.T3I0        0   Timer 3 Input Selection bit 0
T4CON            0xFF44 GPT1 Timer 4 Control Register
T4CON.T4UDE       8   Timer 4 External Up/Down Enable
T4CON.T4UD        7   Timer 4 Up / Down Control
T4CON.T4R         6   Timer 4 Run Bit
T4CON.T4M5        5   Timer 4 Mode Control bit 5
T4CON.T4M4        4   Timer 4 Mode Control bit 4
T4CON.T4M3        3   Timer 4 Mode Control bit 3
T4CON.T4I2        2   Timer 4 Input Selection bit 2
T4CON.T4I1        1   Timer 4 Input Selection bit 1
T4CON.T4I0        0   Timer 4 Input Selection bit 0
T2IC             0xFF60 GPT1 Timer 2 Interrupt Control Register
T2IC.T2IR         7
T2IC.T2IE         6
T2IC.ILVL5        5
T2IC.ILVL4        4
T2IC.ILVL3        3
T2IC.ILVL2        2
T2IC.GLVL1        1
T2IC.GLVL0        0
T3IC             0xFF62 GPT1 Timer 3 Interrupt Control Register
T3IC.T3IR         7
T3IC.T3IE         6
T3IC.ILVL5        5
T3IC.ILVL4        4
T3IC.ILVL3        3
T3IC.ILVL2        2
T3IC.GLVL1        1
T3IC.GLVL0        0
T4IC             0xFF64 GPT1 Timer 4 Interrupt Control Register
T4IC.T4IR         7
T4IC.T4IE         6
T4IC.ILVL5        5
T4IC.ILVL4        4
T4IC.ILVL3        3
T4IC.ILVL2        2
T4IC.GLVL1        1
T4IC.GLVL0        0
S0TIC            0xFF6C Serial Channel 0 Transmit Interrupt Control Register
S0TIC.S0TIR       7
S0TIC.S0TIE       6
S0TIC.ILVL5       5
S0TIC.ILVL4       4
S0TIC.ILVL3       3
S0TIC.ILVL2       2
S0TIC.GLVL1       1
S0TIC.GLVL0       0
S0RIC            0xFF6E Serial Channel 0 Receive Interrupt Control Register
S0RIC.S0RIR       7
S0RIC.S0RIE       6
S0RIC.ILVL5       5
S0RIC.ILVL4       4
S0RIC.ILVL3       3
S0RIC.ILVL2       2
S0RIC.GLVL1       1
S0RIC.GLVL0       0
S0EIC            0xFF70 Serial Channel 0 Error Interrupt Ctrl. Reg.
S0EIC.S0EIR       7
S0EIC.S0EIE       6
S0EIC.ILVL5       5
S0EIC.ILVL4       4
S0EIC.ILVL3       3
S0EIC.ILVL2       2
S0EIC.GLVL1       1
S0EIC.GLVL0       0
SSCTIC           0xFF72 SSC Transmit Interrupt Control Register
SSCTIC.SSCTIR     7
SSCTIC.SSCTIE     6
SSCTIC.ILVL5      5
SSCTIC.ILVL4      4
SSCTIC.ILVL3      3
SSCTIC.ILVL2      2
SSCTIC.GLVL1      1
SSCTIC.GLVL0      0
SSCRIC           0xFF74 SSC Receive Interrupt Control Register
SSCRIC.SSCRIR     7
SSCRIC.SSCRIE     6
SSCRIC.ILVL5      5
SSCRIC.ILVL4      4
SSCRIC.ILVL3      3
SSCRIC.ILVL2      2
SSCRIC.GLVL1      1
SSCRIC.GLVL0      0
SSCEIC           0xFF76 SSC Error Interrupt Control Register
SSCEIC.SSCEIR     7
SSCEIC.SSCEIE     6
SSCEIC.ILVL5      5
SSCEIC.ILVL4      4
SSCEIC.ILVL3      3
SSCEIC.ILVL2      2
SSCEIC.GLVL1      1
SSCEIC.GLVL0      0
CC9IC            0xFF8A External Interrupt 1 Control Register  
CC9IC.CC9IR       7
CC9IC.CC9IE       6
CC9IC.ILVL5       5
CC9IC.ILVL4       4
CC9IC.ILVL3       3
CC9IC.ILVL2       2
CC9IC.GLVL1       1
CC9IC.GLVL0       0
CC10IC           0xFF8C External Interrupt 2 Control Register  
CC10IC.CC10IR     7
CC10IC.CC10IE     6
CC10IC.ILVL5      5
CC10IC.ILVL4      4
CC10IC.ILVL3      3
CC10IC.ILVL2      2
CC10IC.GLVL1      1
CC10IC.GLVL0      0
CC11IC           0xFF8E External Interrupt 3 Control Register
CC11IC.CC11IR     7
CC11IC.CC11IE     6
CC11IC.ILVL5      5
CC11IC.ILVL4      4
CC11IC.ILVL3      3
CC11IC.ILVL2      2
CC11IC.GLVL1      1
CC11IC.GLVL0      0
CC12IC           0xFF90 External Interrupt 4 Control Register
CC12IC.CC12IR     7
CC12IC.CC12IE     6
CC12IC.ILVL5      5
CC12IC.ILVL4      4
CC12IC.ILVL3      3
CC12IC.ILVL2      2
CC12IC.GLVL1      1
CC12IC.GLVL0      0
P5               0xFFA2 Port 5 Register (read only)
P5.P5_15          15  Port data register P5 bit 15
P5.P5_14          14  Port data register P5 bit 14
TFR              0xFFAC Trap Flag Register
TFR.NMI           15  Non Maskable Interrupt Flag
TFR.STKOF         14  Stack Overflow Flag
TFR.STKUF         13  Stack Underflow Flag
TFR.UNDOPC        7   Undefined Opcode Flag
TFR.PRTFLT        3   Protection Fault Flag
TFR.ILLOPA        2   Illegal Word Operand Access Flag
TFR.ILLINA        1   Illegal Instruction Access Flag
TFR.ILLBUS        0   Illegal External Bus Access Flag
WDTCON           0xFFAE Watchdog Timer Control Register
WDTCON.WDTREL15   15  Watchdog Timer Reload Value bit 15
WDTCON.WDTREL14   14  Watchdog Timer Reload Value bit 14
WDTCON.WDTREL13   13  Watchdog Timer Reload Value bit 13
WDTCON.WDTREL12   12  Watchdog Timer Reload Value bit 12
WDTCON.WDTREL11   11  Watchdog Timer Reload Value bit 11
WDTCON.WDTREL10   10  Watchdog Timer Reload Value bit 10
WDTCON.WDTREL9    9   Watchdog Timer Reload Value bit 9 
WDTCON.WDTREL8    8   Watchdog Timer Reload Value bit 8 
WDTCON.WDTR       1   Watchdog Timer Reset Indication Flag
WDTCON.WDTIN      0   Watchdog Timer Input Frequency Selection
S0CON            0xFFB0 Serial Channel 0 Control Register
S0CON.S0R         15  Baudrate Generator Run Bit
S0CON.S0LB        14  LoopBack Mode Enable Bit
S0CON.S0BRS       13  Baudrate Selection Bit
S0CON.S0ODD       12  Parity Selection Bit
S0CON.S0OE        10  Overrun Error Flag
S0CON.S0FE        9   Framing Error Flag
S0CON.S0PE        8   Parity Error Flag
S0CON.S0OEN       7   Overrun Check Enable Bit
S0CON.S0FEN       6   Framing Check Enable Bit
S0CON.S0PEN       5   Parity Check Enable Bit
S0CON.S0REN       4   Receiver Enable Bit
S0CON.S0STP       3   Number of Stop Bits Selection
S0CON.S0M2        2   ASC0 Mode Control
S0CON.S0M1        1   ASC0 Mode Control
S0CON.S0M0        0   ASC0 Mode Control
SSCCON           0xFFB2 SSC Control Register
P2               0xFFC0 Port 2 Register
P2.P2_15          15  Port data register P2 bit 15
P2.P2_14          14  Port data register P2 bit 14
P2.P2_13          13  Port data register P2 bit 13
P2.P2_12          12  Port data register P2 bit 12
P2.P2_11          11  Port data register P2 bit 11
P2.P2_10          10  Port data register P2 bit 10
P2.P2_9           9   Port data register P2 bit 9 
DP2              0xFFC2 Port 2 Direction Control Register
DP2.DP2_15        15  Port direction register DP2 bit 15
DP2.DP2_14        14  Port direction register DP2 bit 14
DP2.DP2_13        13  Port direction register DP2 bit 13
DP2.DP2_12        12  Port direction register DP2 bit 12
DP2.DP2_11        11  Port direction register DP2 bit 11
DP2.DP2_10        10  Port direction register DP2 bit 10
DP2.DP2_9         9   Port direction register DP2 bit 9 
P3               0xFFC4 Port 3 Register
P3.P3_13          13  Port data register P3 bit 13
P3.P3_12          12  Port data register P3 bit 12
P3.P3_11          11  Port data register P3 bit 11
P3.P3_10          10  Port data register P3 bit 10
P3.P3_9           9   Port data register P3 bit 9 
P3.P3_8           8   Port data register P3 bit 8 
P3.P3_7           7   Port data register P3 bit 7 
P3.P3_6           6   Port data register P3 bit 6 
P3.P3_5           5   Port data register P3 bit 5 
P3.P3_4           4   Port data register P3 bit 4 
P3.P3_3           3   Port data register P3 bit 3 
P3.P3_2           2   Port data register P3 bit 2 
DP3              0xFFC6 Port 3 Direction Control Register
DP3.DP3_13        13  Port direction register DP3 bit 13
DP3.DP3_12        12  Port direction register DP3 bit 12
DP3.DP3_11        11  Port direction register DP3 bit 11
DP3.DP3_10        10  Port direction register DP3 bit 10
DP3.DP3_9         9   Port direction register DP3 bit 9 
DP3.DP3_8         8   Port direction register DP3 bit 8 
DP3.DP3_7         7   Port direction register DP3 bit 7 
DP3.DP3_6         6   Port direction register DP3 bit 6 
DP3.DP3_5         5   Port direction register DP3 bit 5 
DP3.DP3_4         4   Port direction register DP3 bit 4 
DP3.DP3_3         3   Port direction register DP3 bit 3 
DP3.DP3_2         2   Port direction register DP3 bit 2 
P4               0xFFC8 Port 4 Register
P4.P4_5           5   Port data register P4 bit 5
P4.P4_4           4   Port data register P4 bit 4
P4.P4_3           3   Port data register P4 bit 3
P4.P4_2           2   Port data register P4 bit 2
P4.P4_1           1   Port data register P4 bit 1
P4.P4_0           0   Port data register P4 bit 0
DP4              0xFFCA Port 4 Direction Control Register
DP4.DP4_5         5   Port direction register DP4 bit 5
DP4.DP4_4         4   Port direction register DP4 bit 4
DP4.DP4_3         3   Port direction register DP4 bit 3
DP4.DP4_2         2   Port direction register DP4 bit 2
DP4.DP4_1         1   Port direction register DP4 bit 1
DP4.DP4_0         0   Port direction register DP4 bit 0
P6               0xFFCC Port 6 Register (8 bits)
P6.P6_3           3   Port data register P6 bit 3
P6.P6_2           2   Port data register P6 bit 2
P6.P6_1           1   Port data register P6 bit 1
P6.P6_0           0   Port data register P6 bit 0
DP6              0xFFCE Port 6 Direction Control Register
DP6.DP6_3         3   Port direction register DP6 bit 3
DP6.DP6_2         2   Port direction register DP6 bit 2
DP6.DP6_1         1   Port direction register DP6 bit 1
DP6.DP6_0         0   Port direction register DP6 bit 0


.C163
; http://www.infineon.com/cmc_upload/0/000/015/402/c165_ds_v20_2000_12.pdf
; m165.pdf


; MEMORY MAP
area CODE ROM            0x0000:0x8000   Internal ROM Area
area CODE MEM_EXT        0x8000:0xC000   External Memory
area DATA XRAM_CAN       0xC000:0xF000   XRAM/CAN
area DATA E_SFR          0xF000:0xF200   ESFR Area
area BSS  RESERVED       0xF200:0xF600
area CODE RAM            0xF600:0xFE00   Internal RAM
area DATA SFR            0xFE00:0x10000  SFR Area


; Interrupt and reset vector assignments
entry RESET     0x0000   RESET
entry NMITRAP   0x0008   NMITRAP Non-Maskable Interrupt (Class A Hardware Traps)
entry STOTRAP   0x0010   STOTRAP Stack Overflow (Class A Hardware Traps)
entry STUTRAP   0x0018   STUTRAP Stack Underflow (Class A Hardware Traps)
entry BTRAP     0x0028   BTRAP Class B Hardware Traps
entry CC8INT    0x0060   External Interrupt 0
entry CC9INT    0x0064   External Interrupt 1
entry CC10INT   0x0068   External Interrupt 2
entry CC11INT   0x006C   External Interrupt 3
entry CC12INT   0x0070   External Interrupt 4
entry CC13INT   0x0074   External Interrupt 5
entry CC14INT   0x0078   External Interrupt 6
entry CC15INT   0x007C   External Interrupt 7
entry T2INT     0x0088   GPT1 Timer 2 
entry T3INT     0x008C   GPT1 Timer 3 
entry T4INT     0x0090   GPT1 Timer 4 
entry T5INT     0x0094   GPT2 Timer 5 
entry T6INT     0x0098   GPT2 Timer 6 
entry CRINT     0x009C   GPT2 CAPREL Reg
entry S0TINT    0x00A8   ASC0 Transmit 
entry S0RINT    0x00AC   ASC0 Receive 
entry S0EINT    0x00B0   ASC0 Error 
entry SCTINT    0x00B4   SSC Transmit 
entry SCRINT    0x00B8   SSC Receive 
entry SCEINT    0x00BC   SSC Error 
entry CC16INT   0x00C0   CAPCOM Register 16 
entry XP0INT    0x0100   CAN1 
entry XP1INT    0x0104   Unassigned node 
entry XP2INT    0x0108   Unassigned node 
entry XP3INT    0x010C   PLL/OWD 
entry CC29INT   0x0110   CAPCOM Register 29 
entry CC30INT   0x0114   CAPCOM Register 30 
entry CC31INT   0x0118   CAPCOM Register 31 
entry S0TBINT   0x011C   ASC0 Transmit Buffer 


; INPUT/OUTPUT PORTS
SSPCON0          0xEF00  SSP Control Register 0
SSPCON0.SSPBSY    15  SSP Busy Flag
SSPCON0.SSPCKP    9   SSP Clock Polarity Control Bit
SSPCON0.SSPCKE    8   SSP Clock Edge Control Bit
SSPCON0.SSPRW     7   SSP Read/Write Control Bit
SSPCON0.SSPHB     6   SSP Heading Control Bit
SSPCON0.SSPCM     5   SSP Continuous Mode Select
SSPCON0.SSPSEL1   4   SSP Chip Enable Selection 1
SSPCON0.SSPSEL0   3   SSP Chip Enable Selection 0
SSPCON0.SSPCKS2   2   SSP Clock Select (Baudrate) 2
SSPCON0.SSPCKS1   1   SSP Clock Select (Baudrate) 1
SSPCON0.SSPCKS0   0   SSP Clock Select (Baudrate) 0
SSPCON1          0xEF02  SSP Control Register 1
SSPCON1.SSPCEO1   4   SSP Chip Enable Output Enable 1
SSPCON1.SSPCEO0   3   SSP Chip Enable Output Enable 0
SSPCON1.SSPCKO    2   SSP Clock Output Enable
SSPCON1.SSPCEP1   1   SSP Chip Enable Polarity Control 1
SSPCON1.SSPCEP0   0   SSP Chip Enable Polarity Control 0
SSPRTB           0xEF04 SSP Receive/Transmit Buffer
SSPTBH           0xEF06 SSP Transmit Buffer High
DP0L             0xF100 P0L Direction Control Register
DP0L.DP0L7        7   Port direction register DP0L bit 7
DP0L.DP0L6        6   Port direction register DP0L bit 6
DP0L.DP0L5        5   Port direction register DP0L bit 5
DP0L.DP0L4        4   Port direction register DP0L bit 4
DP0L.DP0L3        3   Port direction register DP0L bit 3
DP0L.DP0L2        2   Port direction register DP0L bit 2
DP0L.DP0L1        1   Port direction register DP0L bit 1
DP0L.DP0L0        0   Port direction register DP0L bit 0
DP0H             0xF102 P0H Direction Control Register
DP0H.DP0H7        7   Port direction register DP0H bit 7
DP0H.DP0H6        6   Port direction register DP0H bit 6
DP0H.DP0H5        5   Port direction register DP0H bit 5
DP0H.DP0H4        4   Port direction register DP0H bit 4
DP0H.DP0H3        3   Port direction register DP0H bit 3
DP0H.DP0H2        2   Port direction register DP0H bit 2
DP0H.DP0H1        1   Port direction register DP0H bit 1
DP0H.DP0H0        0   Port direction register DP0H bit 0
DP1L             0xF104 P1L Direction Control Register
DP1L.P1L7         7   Port direction register DP1L bit 7
DP1L.P1L6         6   Port direction register DP1L bit 6
DP1L.P1L5         5   Port direction register DP1L bit 5
DP1L.P1L4         4   Port direction register DP1L bit 4
DP1L.P1L3         3   Port direction register DP1L bit 3
DP1L.P1L2         2   Port direction register DP1L bit 2
DP1L.P1L1         1   Port direction register DP1L bit 1
DP1L.P1L0         0   Port direction register DP1L bit 0
DP1H             0xF106 P1H Direction Control Register
DP1H.P1H7         7   Port direction register DP1H bit 7
DP1H.P1H6         6   Port direction register DP1H bit 6
DP1H.P1H5         5   Port direction register DP1H bit 5
DP1H.P1H4         4   Port direction register DP1H bit 4
DP1H.P1H3         3   Port direction register DP1H bit 3
DP1H.P1H2         2   Port direction register DP1H bit 2
DP1H.P1H1         1   Port direction register DP1H bit 1
DP1H.P1H0         0   Port direction register DP1H bit 0
RP0H             0xF108 System Startup Configuration Register (read only)
RP0H.CLKCFG7      7   Clock Generation Mode Configuration 7
RP0H.CLKCFG6      6   Clock Generation Mode Configuration 6
RP0H.CLKCFG5      5   Clock Generation Mode Configuration 5
RP0H.SALSEL4      4   Segment Address Line Selection 4
RP0H.SALSEL3      3   Segment Address Line Selection 3
RP0H.CSSEL2       2   Chip Select Line Selection 2
RP0H.CSSEL1       1   Chip Select Line Selection 1
RP0H.WRC          0   Write Configuration
CC29IC           0xF184 Software Node Interrupt Control Register
XP0IC            0xF186 X-Peripheral 0 Interrupt Control Register
CC30IC           0xF18C Software Node Interrupt Control Register
XP1IC            0xF18E X-Peripheral 1 Interrupt Control Register
XP1IC.XP1IR       7
XP1IC.XP1IE       6
XP1IC.ILVL5       5
XP1IC.ILVL4       4
XP1IC.ILVL3       3
XP1IC.ILVL2       2
XP1IC.GLVL1       1
XP1IC.GLVL0       0
CC31IC           0xF194 Software Node Interrupt Control Register
XP2IC            0xF196 X-Peripheral 2 Interrupt Control Register
S0TBIC           0xF19C Serial Channel 0 Transmit Buffer Interrupt Control Register
S0TBIC.S0TBIR     7
S0TBIC.S0TBIE     6
S0TBIC.ILVL       5
S0TBIC.ILVL       4
S0TBIC.ILVL       3
S0TBIC.ILVL       2
S0TBIC.GLVL       1
S0TBIC.GLVL       0
XP3IC            0xF19E X-Peripheral 3 Interrupt Control Register
EXICON           0xF1C0 External Interrupt Control Register
EXICON.EXI7ES     7   External Interrupt 7 Edge Selection Field
EXICON.EXI6ES     6   External Interrupt 6 Edge Selection Field
EXICON.EXI5ES     5   External Interrupt 5 Edge Selection Field
EXICON.EXI4ES     4   External Interrupt 4 Edge Selection Field
EXICON.EXI3ES     3   External Interrupt 3 Edge Selection Field
EXICON.EXI2ES     2   External Interrupt 2 Edge Selection Field
EXICON.EXI1ES     1   External Interrupt 1 Edge Selection Field
EXICON.EXI0ES     0   External Interrupt 0 Edge Selection Field
ODP2             0xF1C2 Port 2 Open Drain Control Register
ODP2.ODP2_15      15  Port 2 Open Drain control register bit 15
ODP2.ODP2_14      14  Port 2 Open Drain control register bit 14
ODP2.ODP2_13      13  Port 2 Open Drain control register bit 13
ODP2.ODP2_12      12  Port 2 Open Drain control register bit 12
ODP2.ODP2_11      11  Port 2 Open Drain control register bit 11
ODP2.ODP2_10      10  Port 2 Open Drain control register bit 10
ODP2.ODP2_9       9   Port 2 Open Drain control register bit 9 
ODP2.ODP2_8       8   Port 2 Open Drain control register bit 8 
ODP3             0xF1C6 Port 3 Open Drain Control Register
ODP3.ODP3_13      13  Port 3 Open Drain control register bit 13
ODP3.ODP3_11      11  Port 3 Open Drain control register bit 11
ODP3.ODP3_10      10  Port 3 Open Drain control register bit 10
ODP3.ODP3_9       9   Port 3 Open Drain control register bit 9 
ODP3.ODP3_8       8   Port 3 Open Drain control register bit 8 
ODP3.ODP3_7       7   Port 3 Open Drain control register bit 7 
ODP3.ODP3_6       6   Port 3 Open Drain control register bit 6 
ODP3.ODP3_5       5   Port 3 Open Drain control register bit 5 
ODP3.ODP3_4       4   Port 3 Open Drain control register bit 4 
ODP3.ODP3_3       3   Port 3 Open Drain control register bit 3 
ODP3.ODP3_2       2   Port 3 Open Drain control register bit 2 
ODP3.ODP3_1       1   Port 3 Open Drain control register bit 1 
ODP3.ODP3_0       0   Port 3 Open Drain control register bit 0 
ODP6             0xF1CE Port 6 Open Drain Control Register
ODP6.ODP6_7       7   Port 6 Open Drain control register bit 7 
ODP6.ODP6_6       6   Port 6 Open Drain control register bit 6 
ODP6.ODP6_5       5   Port 6 Open Drain control register bit 5 
ODP6.ODP6_4       4   Port 6 Open Drain control register bit 4 
ODP6.ODP6_3       3   Port 6 Open Drain control register bit 3 
ODP6.ODP6_2       2   Port 6 Open Drain control register bit 2 
ODP6.ODP6_1       1   Port 6 Open Drain control register bit 1 
ODP6.ODP6_0       0   Port 6 Open Drain control register bit 0 
DPP0             0xFE00 CPU Data Page Pointer 0 Register (10 bits)
DPP0.DPP0PN9      9   Data Page Number of DPP0 bit 9
DPP0.DPP0PN8      8   Data Page Number of DPP0 bit 8
DPP0.DPP0PN7      7   Data Page Number of DPP0 bit 7
DPP0.DPP0PN6      6   Data Page Number of DPP0 bit 6
DPP0.DPP0PN5      5   Data Page Number of DPP0 bit 5
DPP0.DPP0PN4      4   Data Page Number of DPP0 bit 4
DPP0.DPP0PN3      3   Data Page Number of DPP0 bit 3
DPP0.DPP0PN2      2   Data Page Number of DPP0 bit 2
DPP0.DPP0PN1      1   Data Page Number of DPP0 bit 1
DPP0.DPP0PN0      0   Data Page Number of DPP0 bit 0
DPP1             0xFE02 CPU Data Page Pointer 1 Register (10 bits)
DPP1.DPP1PN9      9   Data Page Number of DPP1 bit 9
DPP1.DPP1PN8      8   Data Page Number of DPP1 bit 8
DPP1.DPP1PN7      7   Data Page Number of DPP1 bit 7
DPP1.DPP1PN6      6   Data Page Number of DPP1 bit 6
DPP1.DPP1PN5      5   Data Page Number of DPP1 bit 5
DPP1.DPP1PN4      4   Data Page Number of DPP1 bit 4
DPP1.DPP1PN3      3   Data Page Number of DPP1 bit 3
DPP1.DPP1PN2      2   Data Page Number of DPP1 bit 2
DPP1.DPP1PN1      1   Data Page Number of DPP1 bit 1
DPP1.DPP1PN0      0   Data Page Number of DPP1 bit 0
DPP2             0xFE04 CPU Data Page Pointer 2 Register (10 bits)
DPP2.DPP2PN9      9   Data Page Number of DPP2 bit 9
DPP2.DPP2PN8      8   Data Page Number of DPP2 bit 8
DPP2.DPP2PN7      7   Data Page Number of DPP2 bit 7
DPP2.DPP2PN6      6   Data Page Number of DPP2 bit 6
DPP2.DPP2PN5      5   Data Page Number of DPP2 bit 5
DPP2.DPP2PN4      4   Data Page Number of DPP2 bit 4
DPP2.DPP2PN3      3   Data Page Number of DPP2 bit 3
DPP2.DPP2PN2      2   Data Page Number of DPP2 bit 2
DPP2.DPP2PN1      1   Data Page Number of DPP2 bit 1
DPP2.DPP2PN0      0   Data Page Number of DPP2 bit 0
DPP3             0xFE06 CPU Data Page Pointer 3 Register (10 bits)
DPP3.DPP3PN9      9   Data Page Number of DPP3 bit 9
DPP3.DPP3PN8      8   Data Page Number of DPP3 bit 8
DPP3.DPP3PN7      7   Data Page Number of DPP3 bit 7
DPP3.DPP3PN6      6   Data Page Number of DPP3 bit 6
DPP3.DPP3PN5      5   Data Page Number of DPP3 bit 5
DPP3.DPP3PN4      4   Data Page Number of DPP3 bit 4
DPP3.DPP3PN3      3   Data Page Number of DPP3 bit 3
DPP3.DPP3PN2      2   Data Page Number of DPP3 bit 2
DPP3.DPP3PN1      1   Data Page Number of DPP3 bit 1
DPP3.DPP3PN0      0   Data Page Number of DPP3 bit 0
CSP              0xFE08 CPU Code Segment Pointer Register (8 bits, not directly writeable)
CSP.SEGNR7        7   Segment Number 7
CSP.SEGNR6        6   Segment Number 6
CSP.SEGNR5        5   Segment Number 5
CSP.SEGNR4        4   Segment Number 4
CSP.SEGNR3        3   Segment Number 3
CSP.SEGNR2        2   Segment Number 2
CSP.SEGNR1        1   Segment Number 1
CSP.SEGNR0        0   Segment Number 0
MDH              0xFE0C CPU Multiply Divide Register - High Word
MDH.MDH15         15
MDH.MDH14         14
MDH.MDH13         13
MDH.MDH12         12
MDH.MDH11         11
MDH.MDH10         10
MDH.MDH9          9
MDH.MDH8          8
MDH.MDH7          7
MDH.MDH6          6
MDH.MDH5          5
MDH.MDH4          4
MDH.MDH3          3
MDH.MDH2          2
MDH.MDH1          1
MDH.MDH0          0
MDL              0xFE0E CPU Multiply Divide Register - Low Word
MDL.MDL15         15
MDL.MDL14         14
MDL.MDL13         13
MDL.MDL12         12
MDL.MDL11         11
MDL.MDL10         10
MDL.MDL9          9
MDL.MDL8          8
MDL.MDL7          7
MDL.MDL6          6
MDL.MDL5          5
MDL.MDL4          4
MDL.MDL3          3
MDL.MDL2          2
MDL.MDL1          1
MDL.MDL0          0
CP               0xFE10 CPU Context Pointer Register
SP               0xFE12 CPU System Stack Pointer Register
SP.SP11           11  Modifiable portion of register CP bit 11
SP.SP10           10  Modifiable portion of register CP bit 10
SP.SP9            9   Modifiable portion of register CP bit 9 
SP.SP8            8   Modifiable portion of register CP bit 8 
SP.SP7            7   Modifiable portion of register CP bit 7 
SP.SP6            6   Modifiable portion of register CP bit 6 
SP.SP5            5   Modifiable portion of register CP bit 5 
SP.SP4            4   Modifiable portion of register CP bit 4 
SP.SP3            3   Modifiable portion of register CP bit 3 
SP.SP2            2   Modifiable portion of register CP bit 2 
SP.SP1            1   Modifiable portion of register CP bit 1 
STKOV            0xFE14 CPU Stack Overflow Pointer Register
STKOV.STKOV11     11  Modifiable portion of register STKOV bit 11
STKOV.STKOV10     10  Modifiable portion of register STKOV bit 10
STKOV.STKOV9      9   Modifiable portion of register STKOV bit 9 
STKOV.STKOV8      8   Modifiable portion of register STKOV bit 8 
STKOV.STKOV7      7   Modifiable portion of register STKOV bit 7 
STKOV.STKOV6      6   Modifiable portion of register STKOV bit 6 
STKOV.STKOV5      5   Modifiable portion of register STKOV bit 5 
STKOV.STKOV4      4   Modifiable portion of register STKOV bit 4 
STKOV.STKOV3      3   Modifiable portion of register STKOV bit 3 
STKOV.STKOV2      2   Modifiable portion of register STKOV bit 2 
STKOV.STKOV1      1   Modifiable portion of register STKOV bit 1 
STKUN            0xFE16 CPU Stack Underflow Pointer Register
STKUN.STKUN11     11  Modifiable portion of register STKUN bit 11
STKUN.STKUN10     10  Modifiable portion of register STKUN bit 10
STKUN.STKUN9      9   Modifiable portion of register STKUN bit 9 
STKUN.STKUN8      8   Modifiable portion of register STKUN bit 8 
STKUN.STKUN7      7   Modifiable portion of register STKUN bit 7 
STKUN.STKUN6      6   Modifiable portion of register STKUN bit 6 
STKUN.STKUN5      5   Modifiable portion of register STKUN bit 5 
STKUN.STKUN4      4   Modifiable portion of register STKUN bit 4 
STKUN.STKUN3      3   Modifiable portion of register STKUN bit 3 
STKUN.STKUN2      2   Modifiable portion of register STKUN bit 2 
STKUN.STKUN1      1   Modifiable portion of register STKUN bit 1 
ADDRSEL1         0xFE18 Address Select Register 1
ADDRSEL1.RGSAD15  15  Range Start Address bit 15
ADDRSEL1.RGSAD14  14  Range Start Address bit 14
ADDRSEL1.RGSAD13  13  Range Start Address bit 13
ADDRSEL1.RGSAD12  12  Range Start Address bit 12
ADDRSEL1.RGSAD11  11  Range Start Address bit 11
ADDRSEL1.RGSAD10  10  Range Start Address bit 10
ADDRSEL1.RGSAD9   9   Range Start Address bit 9
ADDRSEL1.RGSAD8   8   Range Start Address bit 8
ADDRSEL1.RGSAD7   7   Range Start Address bit 7
ADDRSEL1.RGSAD6   6   Range Start Address bit 6
ADDRSEL1.RGSAD5   5   Range Start Address bit 5
ADDRSEL1.RGSAD4   4   Range Start Address bit 4
ADDRSEL1.RGSZ3    3   Range Size Selection bit 3
ADDRSEL1.RGSZ2    2   Range Size Selection bit 2
ADDRSEL1.RGSZ1    1   Range Size Selection bit 1
ADDRSEL1.RGSZ0    0   Range Size Selection bit 0
ADDRSEL2         0xFE1A Address Select Register 2
ADDRSEL2.RGSAD15  15  Range Start Address bit 15
ADDRSEL2.RGSAD14  14  Range Start Address bit 14
ADDRSEL2.RGSAD13  13  Range Start Address bit 13
ADDRSEL2.RGSAD12  12  Range Start Address bit 12
ADDRSEL2.RGSAD11  11  Range Start Address bit 11
ADDRSEL2.RGSAD10  10  Range Start Address bit 10
ADDRSEL2.RGSAD9   9   Range Start Address bit 9 
ADDRSEL2.RGSAD8   8   Range Start Address bit 8 
ADDRSEL2.RGSAD7   7   Range Start Address bit 7 
ADDRSEL2.RGSAD6   6   Range Start Address bit 6 
ADDRSEL2.RGSAD5   5   Range Start Address bit 5 
ADDRSEL2.RGSAD4   4   Range Start Address bit 4 
ADDRSEL2.RGSZ3    3   Range Size Selection bit 3
ADDRSEL2.RGSZ2    2   Range Size Selection bit 2
ADDRSEL2.RGSZ1    1   Range Size Selection bit 1
ADDRSEL2.RGSZ0    0   Range Size Selection bit 0     
ADDRSEL3         0xFE1C Address Select Register 3
ADDRSEL3.RGSAD15  15  Range Start Address bit 15
ADDRSEL3.RGSAD14  14  Range Start Address bit 14
ADDRSEL3.RGSAD13  13  Range Start Address bit 13
ADDRSEL3.RGSAD12  12  Range Start Address bit 12
ADDRSEL3.RGSAD11  11  Range Start Address bit 11
ADDRSEL3.RGSAD10  10  Range Start Address bit 10
ADDRSEL3.RGSAD9   9   Range Start Address bit 9 
ADDRSEL3.RGSAD8   8   Range Start Address bit 8 
ADDRSEL3.RGSAD7   7   Range Start Address bit 7 
ADDRSEL3.RGSAD6   6   Range Start Address bit 6 
ADDRSEL3.RGSAD5   5   Range Start Address bit 5 
ADDRSEL3.RGSAD4   4   Range Start Address bit 4 
ADDRSEL3.RGSZ3    3   Range Size Selection bit 3
ADDRSEL3.RGSZ2    2   Range Size Selection bit 2
ADDRSEL3.RGSZ1    1   Range Size Selection bit 1
ADDRSEL3.RGSZ0    0   Range Size Selection bit 0     
ADDRSEL4         0xFE1E Address Select Register 4
ADDRSEL4.RGSAD15  15  Range Start Address bit 15
ADDRSEL4.RGSAD14  14  Range Start Address bit 14
ADDRSEL4.RGSAD13  13  Range Start Address bit 13
ADDRSEL4.RGSAD12  12  Range Start Address bit 12
ADDRSEL4.RGSAD11  11  Range Start Address bit 11
ADDRSEL4.RGSAD10  10  Range Start Address bit 10
ADDRSEL4.RGSAD9   9   Range Start Address bit 9 
ADDRSEL4.RGSAD8   8   Range Start Address bit 8 
ADDRSEL4.RGSAD7   7   Range Start Address bit 7 
ADDRSEL4.RGSAD6   6   Range Start Address bit 6 
ADDRSEL4.RGSAD5   5   Range Start Address bit 5 
ADDRSEL4.RGSAD4   4   Range Start Address bit 4 
ADDRSEL4.RGSZ3    3   Range Size Selection bit 3
ADDRSEL4.RGSZ2    2   Range Size Selection bit 2
ADDRSEL4.RGSZ1    1   Range Size Selection bit 1
ADDRSEL4.RGSZ0    0   Range Size Selection bit 0     
T2               0xFE40 GPT1 Timer 2 Register
T3               0xFE42 GPT1 Timer 3 Register
T4               0xFE44 GPT1 Timer 4 Register
T5               0xFE46 GPT2 Timer 5 Register
T6               0xFE48 GPT2 Timer 6 Register
CAPREL           0xFE4A GPT2 Capture/Reload Register
WDT              0xFEAE Watchdog Timer Register (read only)
S0TBUF           0xFEB0 Serial Channel 0 Transmit Buffer Register
S0RBUF           0xFEB2 Serial Channel 0 Receive Buffer Register (read only)
S0BG             0xFEB4 Serial Channel 0 Baud Rate Generator Reload Register
PECC0            0xFEC0 PEC Channel 0 Control Register
PECC0.INC10       10  Increment Control bit 10
PECC0.INC9        9   Increment Control bit 9
PECC0.BWT         8   Byte / Word Transfer Selection
PECC0.COUNT7      7   PEC Transfer Count bit 7
PECC0.COUNT6      6   PEC Transfer Count bit 6
PECC0.COUNT5      5   PEC Transfer Count bit 5
PECC0.COUNT4      4   PEC Transfer Count bit 4
PECC0.COUNT3      3   PEC Transfer Count bit 3
PECC0.COUNT2      2   PEC Transfer Count bit 2
PECC0.COUNT1      1   PEC Transfer Count bit 1
PECC0.COUNT0      0   PEC Transfer Count bit 0
PECC1            0xFEC2 PEC Channel 1 Control Register
PECC1.INC10       10  Increment Control bit 10      
PECC1.INC9        9   Increment Control bit 9       
PECC1.BWT         8   Byte / Word Transfer Selection
PECC1.COUNT7      7   PEC Transfer Count bit 7      
PECC1.COUNT6      6   PEC Transfer Count bit 6      
PECC1.COUNT5      5   PEC Transfer Count bit 5      
PECC1.COUNT4      4   PEC Transfer Count bit 4      
PECC1.COUNT3      3   PEC Transfer Count bit 3      
PECC1.COUNT2      2   PEC Transfer Count bit 2      
PECC1.COUNT1      1   PEC Transfer Count bit 1      
PECC1.COUNT0      0   PEC Transfer Count bit 0      
PECC2            0xFEC4 PEC Channel 2 Control Register
PECC2.INC10       10  Increment Control bit 10      
PECC2.INC9        9   Increment Control bit 9       
PECC2.BWT         8   Byte / Word Transfer Selection
PECC2.COUNT7      7   PEC Transfer Count bit 7      
PECC2.COUNT6      6   PEC Transfer Count bit 6      
PECC2.COUNT5      5   PEC Transfer Count bit 5      
PECC2.COUNT4      4   PEC Transfer Count bit 4      
PECC2.COUNT3      3   PEC Transfer Count bit 3      
PECC2.COUNT2      2   PEC Transfer Count bit 2      
PECC2.COUNT1      1   PEC Transfer Count bit 1      
PECC2.COUNT0      0   PEC Transfer Count bit 0      
PECC3            0xFEC6 PEC Channel 3 Control Register
PECC3.INC10       10  Increment Control bit 10      
PECC3.INC9        9   Increment Control bit 9       
PECC3.BWT         8   Byte / Word Transfer Selection
PECC3.COUNT7      7   PEC Transfer Count bit 7      
PECC3.COUNT6      6   PEC Transfer Count bit 6      
PECC3.COUNT5      5   PEC Transfer Count bit 5      
PECC3.COUNT4      4   PEC Transfer Count bit 4      
PECC3.COUNT3      3   PEC Transfer Count bit 3      
PECC3.COUNT2      2   PEC Transfer Count bit 2      
PECC3.COUNT1      1   PEC Transfer Count bit 1      
PECC3.COUNT0      0   PEC Transfer Count bit 0      
PECC4            0xFEC8 PEC Channel 4 Control Register
PECC4.INC10       10  Increment Control bit 10      
PECC4.INC9        9   Increment Control bit 9       
PECC4.BWT         8   Byte / Word Transfer Selection
PECC4.COUNT7      7   PEC Transfer Count bit 7      
PECC4.COUNT6      6   PEC Transfer Count bit 6      
PECC4.COUNT5      5   PEC Transfer Count bit 5      
PECC4.COUNT4      4   PEC Transfer Count bit 4      
PECC4.COUNT3      3   PEC Transfer Count bit 3      
PECC4.COUNT2      2   PEC Transfer Count bit 2      
PECC4.COUNT1      1   PEC Transfer Count bit 1      
PECC4.COUNT0      0   PEC Transfer Count bit 0      
PECC5            0xFECA PEC Channel 5 Control Register
PECC5.INC10       10  Increment Control bit 10      
PECC5.INC9        9   Increment Control bit 9       
PECC5.BWT         8   Byte / Word Transfer Selection
PECC5.COUNT7      7   PEC Transfer Count bit 7      
PECC5.COUNT6      6   PEC Transfer Count bit 6      
PECC5.COUNT5      5   PEC Transfer Count bit 5      
PECC5.COUNT4      4   PEC Transfer Count bit 4      
PECC5.COUNT3      3   PEC Transfer Count bit 3      
PECC5.COUNT2      2   PEC Transfer Count bit 2      
PECC5.COUNT1      1   PEC Transfer Count bit 1      
PECC5.COUNT0      0   PEC Transfer Count bit 0      
PECC6            0xFECC PEC Channel 6 Control Register
PECC6.INC10       10  Increment Control bit 10      
PECC6.INC9        9   Increment Control bit 9       
PECC6.BWT         8   Byte / Word Transfer Selection
PECC6.COUNT7      7   PEC Transfer Count bit 7      
PECC6.COUNT6      6   PEC Transfer Count bit 6      
PECC6.COUNT5      5   PEC Transfer Count bit 5      
PECC6.COUNT4      4   PEC Transfer Count bit 4      
PECC6.COUNT3      3   PEC Transfer Count bit 3      
PECC6.COUNT2      2   PEC Transfer Count bit 2      
PECC6.COUNT1      1   PEC Transfer Count bit 1      
PECC6.COUNT0      0   PEC Transfer Count bit 0      
PECC7            0xFECE PEC Channel 7 Control Register
PECC7.INC10       10  Increment Control bit 10      
PECC7.INC9        9   Increment Control bit 9       
PECC7.BWT         8   Byte / Word Transfer Selection
PECC7.COUNT7      7   PEC Transfer Count bit 7      
PECC7.COUNT6      6   PEC Transfer Count bit 6      
PECC7.COUNT5      5   PEC Transfer Count bit 5      
PECC7.COUNT4      4   PEC Transfer Count bit 4      
PECC7.COUNT3      3   PEC Transfer Count bit 3      
PECC7.COUNT2      2   PEC Transfer Count bit 2      
PECC7.COUNT1      1   PEC Transfer Count bit 1      
PECC7.COUNT0      0   PEC Transfer Count bit 0      
P0L              0xFF00 Port 0 Low Register (Lower half of PORT0)
P0L.P0L7          7   Port data register P0L bit 7
P0L.P0L6          6   Port data register P0L bit 6
P0L.P0L5          5   Port data register P0L bit 5
P0L.P0L4          4   Port data register P0L bit 4
P0L.P0L3          3   Port data register P0L bit 3
P0L.P0L2          2   Port data register P0L bit 2
P0L.P0L1          1   Port data register P0L bit 1
P0L.P0L0          0   Port data register P0L bit 0
P0H              0xFF02 Port 0 High Register (Upper half of PORT0)
P0H.P0H7          7   Port data register P0H bit 7
P0H.P0H6          6   Port data register P0H bit 6
P0H.P0H5          5   Port data register P0H bit 5
P0H.P0H4          4   Port data register P0H bit 4
P0H.P0H3          3   Port data register P0H bit 3
P0H.P0H2          2   Port data register P0H bit 2
P0H.P0H1          1   Port data register P0H bit 1
P0H.P0H0          0   Port data register P0H bit 0
P1L              0xFF04 Port 1 Low Register (Lower half of PORT1)
P1L.P1L_7         7   Port data register P1L bit 7
P1L.P1L_6         6   Port data register P1L bit 6
P1L.P1L_5         5   Port data register P1L bit 5
P1L.P1L_4         4   Port data register P1L bit 4
P1L.P1L_3         3   Port data register P1L bit 3
P1L.P1L_2         2   Port data register P1L bit 2
P1L.P1L_1         1   Port data register P1L bit 1
P1L.P1L_0         0   Port data register P1L bit 0
P1H              0xFF06 Port 1 High Register (Upper half of PORT1)
P1H.P1H_7         7   Port data register P1H bit 7
P1H.P1H_6         6   Port data register P1H bit 6
P1H.P1H_5         5   Port data register P1H bit 5
P1H.P1H_4         4   Port data register P1H bit 4
P1H.P1H_3         3   Port data register P1H bit 3
P1H.P1H_2         2   Port data register P1H bit 2
P1H.P1H_1         1   Port data register P1H bit 1
P1H.P1H_0         0   Port data register P1H bit 0
BUSCON0          0xFF0C Bus Configuration Register 0
BUSCON0.CSWEN0    15  Write Chip Select Enable
BUSCON0.CSREN0    14  Read Chip Select Enable
BUSCON0.RDYEN0    12  READY Input Enable
BUSCON0.BUSACT0   10  Bus Active Control
BUSCON0.ALECTL0   9   ALE Lengthening Control
BUSCON0.BTYP1     7   External Bus Configuration bit 1
BUSCON0.BTYP0     6   External Bus Configuration bit 0
BUSCON0.MTTC0     5   Memory Tristate Time Control
BUSCON0.RWDC0     4   Read/Write Delay Control for BUSCON0
BUSCON0.MCTC3     3   Memory Cycle Time Control bit 3
BUSCON0.MCTC2     2   Memory Cycle Time Control bit 2
BUSCON0.MCTC1     1   Memory Cycle Time Control bit 1
BUSCON0.MCTC0     0   Memory Cycle Time Control bit 0    
MDC              0xFF0E CPU Multiply Divide Control Register
MDC.MDRIU         4   Multiply/Divide Register In Use
PSW              0xFF10 CPU Program Status Word
PSW.ILVL15        15  ILVL15 - Interrupt and EBC Control Fields
PSW.ILVL14        14  ILVL14 - Interrupt and EBC Control Fields
PSW.ILVL13        13  ILVL13 - Interrupt and EBC Control Fields
PSW.ILVL12        12  ILVL12 - Interrupt and EBC Control Fields
PSW.IEN           11  IEN - Interrupt and EBC Control Fields
PSW.HLDEN         10  HLDEN - Interrupt and EBC Control Fields
PSW.USR0          6   User General Purpose Flag
PSW.MULIP         5   Multiplication/Division In Progress
PSW.E             4   End of Table Flag
PSW.Z             3   Zero Flag
PSW.V             2   Overflow Result
PSW.C             1   Carry Flag
PSW.N             0   Negative Result
SYSCON           0xFF12 CPU System Configuration Register
SYSCON.STKSZ2     15  System Stack Size 2
SYSCON.STKSZ1     14  System Stack Size 1
SYSCON.STKSZ0     13  System Stack Size 0
SYSCON.ROMS1      12  Internal ROM Mapping
SYSCON.SGTEN      11  Segmentation Disable/Enable Control
SYSCON.ROMEN      10  Internal ROM Enable
SYSCON.BYTDIS     9   Disable/Enable Control for Pin BHE
SYSCON.CLKEN      8   System Clock Output Enable (CLKOUT)
SYSCON.WRCFG      7   Write Configuration Control
SYSCON.XPEN       2   XBUS Peripheral Enable Bit
SYSCON.VISIBLE    1   Visible Mode Control
SYSCON.XPERSHARE  0   XBUS Peripheral Share Mode Control
BUSCON1          0xFF14 Bus Configuration Register 1
BUSCON1.CSWEN1    15  Write Chip Select Enable            
BUSCON1.CSREN1    14  Read Chip Select Enable             
BUSCON1.RDYEN1    12  READY Input Enable                  
BUSCON1.BUSACT1   10  Bus Active Control                  
BUSCON1.ALECTL1   9   ALE Lengthening Control             
BUSCON1.BTYP1     7   External Bus Configuration bit 1    
BUSCON1.BTYP0     6   External Bus Configuration bit 0    
BUSCON1.MTTC1     5   Memory Tristate Time Control        
BUSCON1.RWDC1     4   Read/Write Delay Control for BUSCON0
BUSCON1.MCTC3     3   Memory Cycle Time Control bit 3     
BUSCON1.MCTC2     2   Memory Cycle Time Control bit 2     
BUSCON1.MCTC1     1   Memory Cycle Time Control bit 1     
BUSCON1.MCTC0     0   Memory Cycle Time Control bit 0     
BUSCON2          0xFF16 Bus Configuration Register 2
BUSCON2.CSWEN2    15  Write Chip Select Enable            
BUSCON2.CSREN2    14  Read Chip Select Enable             
BUSCON2.RDYEN2    12  READY Input Enable                  
BUSCON2.BUSACT2   10  Bus Active Control                  
BUSCON2.ALECTL2   9   ALE Lengthening Control             
BUSCON2.BTYP1     7   External Bus Configuration bit 1    
BUSCON2.BTYP0     6   External Bus Configuration bit 0    
BUSCON2.MTTC2     5   Memory Tristate Time Control        
BUSCON2.RWDC2     4   Read/Write Delay Control for BUSCON0
BUSCON2.MCTC3     3   Memory Cycle Time Control bit 3     
BUSCON2.MCTC2     2   Memory Cycle Time Control bit 2     
BUSCON2.MCTC1     1   Memory Cycle Time Control bit 1     
BUSCON2.MCTC0     0   Memory Cycle Time Control bit 0     
BUSCON3          0xFF18 Bus Configuration Register 3
BUSCON3.CSWEN3    15  Write Chip Select Enable            
BUSCON3.CSREN3    14  Read Chip Select Enable             
BUSCON3.RDYEN3    12  READY Input Enable                  
BUSCON3.BUSACT3   10  Bus Active Control                  
BUSCON3.ALECTL3   9   ALE Lengthening Control             
BUSCON3.BTYP1     7   External Bus Configuration bit 1    
BUSCON3.BTYP0     6   External Bus Configuration bit 0    
BUSCON3.MTTC3     5   Memory Tristate Time Control        
BUSCON3.RWDC3     4   Read/Write Delay Control for BUSCON0
BUSCON3.MCTC3     3   Memory Cycle Time Control bit 3     
BUSCON3.MCTC2     2   Memory Cycle Time Control bit 2     
BUSCON3.MCTC1     1   Memory Cycle Time Control bit 1     
BUSCON3.MCTC0     0   Memory Cycle Time Control bit 0     
BUSCON4          0xFF1A Bus Configuration Register 4
BUSCON4.CSWEN4    15  Write Chip Select Enable            
BUSCON4.CSREN4    14  Read Chip Select Enable             
BUSCON4.RDYEN4    12  READY Input Enable                  
BUSCON4.BUSACT4   10  Bus Active Control                  
BUSCON4.ALECTL4   9   ALE Lengthening Control             
BUSCON4.BTYP1     7   External Bus Configuration bit 1    
BUSCON4.BTYP0     6   External Bus Configuration bit 0    
BUSCON4.MTTC4     5   Memory Tristate Time Control        
BUSCON4.RWDC4     4   Read/Write Delay Control for BUSCON0
BUSCON4.MCTC3     3   Memory Cycle Time Control bit 3     
BUSCON4.MCTC2     2   Memory Cycle Time Control bit 2     
BUSCON4.MCTC1     1   Memory Cycle Time Control bit 1     
BUSCON4.MCTC0     0   Memory Cycle Time Control bit 0     
ZEROS            0xFF1C Constant Value 0's Register (read only)
ONES             0xFF1E Constant Value 1's Register (read only)
T2CON            0xFF40 GPT1 Timer 2 Control Register
T2CON.T2UDE       8   Timer 2 External Up/Down Enable
T2CON.T2UD        7   Timer 2 Up / Down Control
T2CON.T2R         6   Timer 2 Run Bit
T2CON.T2M5        5   Timer 2 Mode Control bit 5
T2CON.T2M4        4   Timer 2 Mode Control bit 4
T2CON.T2M3        3   Timer 2 Mode Control bit 3
T2CON.T2I2        2   Timer 2 Input Selection bit 2
T2CON.T2I1        1   Timer 2 Input Selection bit 1
T2CON.T2I0        0   Timer 2 Input Selection bit 0
T3CON            0xFF42 GPT1 Timer 3 Control Register
T3CON.T3OTL       10  Timer 3 Output Toggle Latch
T3CON.T3OE        9   Alternate Output Function Enable
T3CON.T3UDE       8   Timer 3 External Up/Down Enable
T3CON.T3UD        7   Timer 3 Up / Down Control
T3CON.T3R         6   Timer 3 Run Bit
T3CON.T3M2        5   Timer 3 Mode Control bit 2
T3CON.T3M1        4   Timer 3 Mode Control bit 1
T3CON.T3M0        3   Timer 3 Mode Control bit 0
T3CON.T3I2        2   Timer 3 Input Selection bit 2
T3CON.T3I1        1   Timer 3 Input Selection bit 1
T3CON.T3I0        0   Timer 3 Input Selection bit 0
T4CON            0xFF44 GPT1 Timer 4 Control Register
T4CON.T4UDE       8   Timer 4 External Up/Down Enable
T4CON.T4UD        7   Timer 4 Up / Down Control
T4CON.T4R         6   Timer 4 Run Bit
T4CON.T4M5        5   Timer 4 Mode Control bit 5
T4CON.T4M4        4   Timer 4 Mode Control bit 4
T4CON.T4M3        3   Timer 4 Mode Control bit 3
T4CON.T4I2        2   Timer 4 Input Selection bit 2
T4CON.T4I1        1   Timer 4 Input Selection bit 1
T4CON.T4I0        0   Timer 4 Input Selection bit 0
T5CON            0xFF46 GPT2 Timer 5 Control Register
T5CON.T5SC        15  Timer 5 Capture Mode Enable
T5CON.T5CLR       14  Timer 5 Clear Bit
T5CON.T5UDE       8   Timer 5 External Up/Down Enable
T5CON.T5UD        7   Timer 5 Up / Down Control
T5CON.T5R         6   Timer 5 Run Bit
T5CON.T5M4        4   Timer 5 Mode Control bit 4
T5CON.T5M3        3   Timer 5 Mode Control bit 3
T5CON.T5I2        2   Timer 5 Input Selection bit 2
T5CON.T5I1        1   Timer 5 Input Selection bit 1
T5CON.T5I0        0   Timer 5 Input Selection bit 0
T6CON            0xFF48 GPT2 Timer 6 Control Register
T6CON.T6SR        15  Timer 6 Reload Mode Enable
T6CON.T6OTL       10  Timer 6 Output Toggle Latch
T6CON.T6OE        9   Alternate Output Function Enable
T6CON.T6UDE       8   Timer 6 External Up/Down Enable
T6CON.T6UD        7   Timer 6 Up / Down Control
T6CON.T6R         6   Timer 6 Run Bit
T6CON.T6M2        5   Timer 6 Mode Control bit 2
T6CON.T6M1        4   Timer 6 Mode Control bit 1
T6CON.T6M0        3   Timer 6 Mode Control bit 0
T6CON.T6I2        2   Timer 6 Input Selection bit 2
T6CON.T6I1        1   Timer 6 Input Selection bit 1
T6CON.T6I0        0   Timer 6 Input Selection bit 0
T2IC             0xFF60 GPT1 Timer 2 Interrupt Control Register
T2IC.T2IR         7
T2IC.T2IE         6
T2IC.ILVL3        5
T2IC.ILVL2        4
T2IC.ILVL1        3
T2IC.ILVL0        2
T2IC.GLVL1        1
T2IC.GLVL0        0
T3IC             0xFF62 GPT1 Timer 3 Interrupt Control Register
T3IC.T3IR         7
T3IC.T3IE         6
T3IC.ILVL3        5
T3IC.ILVL2        4
T3IC.ILVL1        3
T3IC.ILVL0        2
T3IC.GLVL1        1
T3IC.GLVL0        0
T4IC             0xFF64 GPT1 Timer 4 Interrupt Control Register
T4IC.T4IR         7
T4IC.T4IE         6
T4IC.ILVL3        5
T4IC.ILVL2        4
T4IC.ILVL1        3
T4IC.ILVL0        2
T4IC.GLVL1        1
T4IC.GLVL0        0
T5IC             0xFF66 GPT2 Timer 5 Interrupt Control Register
T5IC.T5IR         7
T5IC.T5IE         6
T5IC.ILVL5        5
T5IC.ILVL4        4
T5IC.ILVL3        3
T5IC.ILVL2        2
T5IC.GLVL1        1
T5IC.GLVL0        0
T6IC             0xFF68 GPT2 Timer 6 Interrupt Control Register
T6IC.T6IR         7
T6IC.T6IE         6
T6IC.ILVL5        5
T6IC.ILVL4        4
T6IC.ILVL3        3
T6IC.ILVL2        2
T6IC.GLVL1        1
T6IC.GLVL0        0
CRIC             0xFF6A GPT2 CAPREL Interrupt Control Register
CRIC.CRIR         7
CRIC.CRIE         6
CRIC.ILVL5        5
CRIC.ILVL4        4
CRIC.ILVL3        3
CRIC.ILVL2        2
CRIC.GLVL1        1
CRIC.GLVL0        0
S0TIC            0xFF6C Serial Channel 0 Transmit Interrupt Control Register
S0TIC.S0TIR       7
S0TIC.S0TIE       6
S0TIC.ILVL5       5
S0TIC.ILVL4       4
S0TIC.ILVL3       3
S0TIC.ILVL2       2
S0TIC.GLVL1       1
S0TIC.GLVL0       0
S0RIC            0xFF6E Serial Channel 0 Receive Interrupt Control Register
S0RIC.S0RIR       7
S0RIC.S0RIE       6
S0RIC.ILVL5       5
S0RIC.ILVL4       4
S0RIC.ILVL3       3
S0RIC.ILVL2       2
S0RIC.GLVL1       1
S0RIC.GLVL0       0
S0EIC            0xFF70 Serial Channel 0 Error Interrupt Ctrl. Reg.
S0EIC.S0EIR       7
S0EIC.S0EIE       6
S0EIC.ILVL5       5
S0EIC.ILVL4       4
S0EIC.ILVL3       3
S0EIC.ILVL2       2
S0EIC.GLVL1       1
S0EIC.GLVL0       0
CC8IC            0xFF88 External Interrupt 0 Control Register
CC9IC            0xFF8A External Interrupt 1 Control Register
CC10IC           0xFF8C External Interrupt 2 Control Register
CC11IC           0xFF8E External Interrupt 3 Control Register
CC12IC           0xFF90 External Interrupt 4 Control Register
CC13IC           0xFF92 External Interrupt 5 Control Register
CC14IC           0xFF94 External Interrupt 6 Control Register
CC15IC           0xFF96 External Interrupt 7 Control Register
P5               0xFFA2 Port 5 Register (read only)
P5.P5_15          15  Port data register P5 bit 15
P5.P5_14          14  Port data register P5 bit 14
P5.P5_13          13  Port data register P5 bit 13
P5.P5_12          12  Port data register P5 bit 12
P5.P5_11          11  Port data register P5 bit 11
P5.P5_10          10  Port data register P5 bit 10
TFR              0xFFAC Trap Flag Register
TFR.NMI           15  Non Maskable Interrupt Flag
TFR.STKOF         14  Stack Overflow Flag
TFR.STKUF         13  Stack Underflow Flag
TFR.UNDOPC        7   Undefined Opcode Flag
TFR.PRTFLT        3   Protection Fault Flag
TFR.ILLOPA        2   Illegal Word Operand Access Flag
TFR.ILLINA        1   Illegal Instruction Access Flag
TFR.ILLBUS        0   Illegal External Bus Access Flag
WDTCON           0xFFAE Watchdog Timer Control Register
WDTCON.WDTREL15   15 Watchdog Timer Reload Value bit 15
WDTCON.WDTREL14   14 Watchdog Timer Reload Value bit 14
WDTCON.WDTREL13   13 Watchdog Timer Reload Value bit 13
WDTCON.WDTREL12   12 Watchdog Timer Reload Value bit 12
WDTCON.WDTREL11   11 Watchdog Timer Reload Value bit 11
WDTCON.WDTREL10   10 Watchdog Timer Reload Value bit 10
WDTCON.WDTREL9    9  Watchdog Timer Reload Value bit 9 
WDTCON.WDTREL8    8  Watchdog Timer Reload Value bit 8 
WDTCON.WDTR       1  Watchdog Timer Reset Indication Flag
WDTCON.WDTIN      0  Watchdog Timer Input Frequency Selection
S0CON            0xFFB0 Serial Channel 0 Control Register
S0CON.S0R         15 Baudrate Generator Run Bit
S0CON.S0LB        14 LoopBack Mode Enable Bit
S0CON.S0BRS       13 Baudrate Selection Bit
S0CON.S0ODD       12 Parity Selection Bit
S0CON.S0OE        10 Overrun Error Flag
S0CON.S0FE        9  Framing Error Flag
S0CON.S0PE        8  Parity Error Flag
S0CON.S0OEN       7  Overrun Check Enable Bit
S0CON.S0FEN       6  Framing Check Enable Bit
S0CON.S0PEN       5  Parity Check Enable Bit
S0CON.S0REN       4  Receiver Enable Bit
S0CON.S0STP       3  Number of Stop Bits Selection
S0CON.S0M2        2  ASC0 Mode Control bit 2
S0CON.S0M1        1  ASC0 Mode Control bit 1
S0CON.S0M0        0  ASC0 Mode Control bit 0
P2               0xFFC0 Port 2 Register
P2.P2_15          15  Port data register P2 bit 15
P2.P2_14          14  Port data register P2 bit 14
P2.P2_13          13  Port data register P2 bit 13
P2.P2_12          12  Port data register P2 bit 12
P2.P2_11          11  Port data register P2 bit 11
P2.P2_10          10  Port data register P2 bit 10
P2.P2_9           9   Port data register P2 bit 9 
P2.P2_8           8   Port data register P2 bit 8 
DP2              0xFFC2 Port 2 Direction Control Register
DP2.DP2_15        15  Port 2 Open Drain control register bit 15
DP2.DP2_14        14  Port 2 Open Drain control register bit 14
DP2.DP2_13        13  Port 2 Open Drain control register bit 13
DP2.DP2_12        12  Port 2 Open Drain control register bit 12
DP2.DP2_11        11  Port 2 Open Drain control register bit 11
DP2.DP2_10        10  Port 2 Open Drain control register bit 10
DP2.DP2_9         9   Port 2 Open Drain control register bit 9 
DP2.DP2_8         8   Port 2 Open Drain control register bit 8 
P3               0xFFC4 Port 3 Register
P3.P3_15          15  Port data register P3 bit 15
P3.P3_13          13  Port data register P3 bit 13
P3.P3_12          12  Port data register P3 bit 12
P3.P3_11          11  Port data register P3 bit 11
P3.P3_10          10  Port data register P3 bit 10
P3.P3_9           9   Port data register P3 bit 9 
P3.P3_8           8   Port data register P3 bit 8 
P3.P3_7           7   Port data register P3 bit 7 
P3.P3_6           6   Port data register P3 bit 6 
P3.P3_5           5   Port data register P3 bit 5 
P3.P3_4           4   Port data register P3 bit 4 
P3.P3_3           3   Port data register P3 bit 3 
P3.P3_2           2   Port data register P3 bit 2 
P3.P3_1           1   Port data register P3 bit 1 
DP3              0xFFC6 Port 3 Direction Control Register
DP3.DP3_15        15  Port direction register DP3 bit 15
DP3.DP3_13        13  Port direction register DP3 bit 13
DP3.DP3_12        12  Port direction register DP3 bit 12
DP3.DP3_11        11  Port direction register DP3 bit 11
DP3.DP3_10        10  Port direction register DP3 bit 10
DP3.DP3_9         9   Port direction register DP3 bit 9 
DP3.DP3_8         8   Port direction register DP3 bit 8 
DP3.DP3_7         7   Port direction register DP3 bit 7 
DP3.DP3_6         6   Port direction register DP3 bit 6 
DP3.DP3_5         5   Port direction register DP3 bit 5 
DP3.DP3_4         4   Port direction register DP3 bit 4 
DP3.DP3_3         3   Port direction register DP3 bit 3 
DP3.DP3_2         2   Port direction register DP3 bit 2 
DP3.DP3_1         1   Port direction register DP3 bit 1 
P4               0xFFC8 Port 4 Register (7 bits)
P4.P4_7           7   Port data register P4 bit 7 
P4.P4_6           6   Port data register P4 bit 6 
P4.P4_5           5   Port data register P4 bit 5 
P4.P4_4           4   Port data register P4 bit 4 
P4.P4_3           3   Port data register P4 bit 3 
P4.P4_2           2   Port data register P4 bit 2 
P4.P4_1           1   Port data register P4 bit 1 
P4.P4_0           0   Port data register P4 bit 0 
DP4              0xFFCA Port 4 Direction Control Register
DP4.DP4_7         7   Port direction register DP4 bit 7 
DP4.DP4_6         6   Port direction register DP4 bit 6 
DP4.DP4_5         5   Port direction register DP4 bit 5 
DP4.DP4_4         4   Port direction register DP4 bit 4 
DP4.DP4_3         3   Port direction register DP4 bit 3 
DP4.DP4_2         2   Port direction register DP4 bit 2 
DP4.DP4_1         1   Port direction register DP4 bit 1 
DP4.DP4_0         0   Port direction register DP4 bit 0 
P6               0xFFCC Port 6 Register (8 bits)
P6.P6_7           7   Port data register P6 bit 7
P6.P6_6           6   Port data register P6 bit 6
P6.P6_5           5   Port data register P6 bit 5
P6.P6_4           4   Port data register P6 bit 4
P6.P6_3           3   Port data register P6 bit 3
P6.P6_2           2   Port data register P6 bit 2
P6.P6_1           1   Port data register P6 bit 1
P6.P6_0           0   Port data register P6 bit 0
DP6              0xFFCE Port 6 Direction Control Register
DP6.DP6_7         7   Port direction register DP6 bit 7 
DP6.DP6_6         6   Port direction register DP6 bit 6 
DP6.DP6_5         5   Port direction register DP6 bit 5 
DP6.DP6_4         4   Port direction register DP6 bit 4 
DP6.DP6_3         3   Port direction register DP6 bit 3 
DP6.DP6_2         2   Port direction register DP6 bit 2 
DP6.DP6_1         1   Port direction register DP6 bit 1 
DP6.DP6_0         0   Port direction register DP6 bit 0 


.C163L
; 163L.pdf

; C163-LF    (RAM 1 KB)
; C163-L25F  (RAM 1 KB)


; MEMORY MAP
area CODE ROM            0x0000:0x8000   Internal ROM Area
area CODE MEM_EXT        0x8000:0xC000   External Memory
area DATA XRAM_CAN       0xC000:0xF000   XRAM/CAN
area DATA E_SFR          0xF000:0xF200   ESFR Area
area BSS  RESERVED       0xF200:0xF600
area CODE RAM            0xF600:0xFE00   Internal RAM
area DATA SFR            0xFE00:0x10000  SFR Area


; Interrupt and reset vector assignments
entry RESET     0x0000   RESET
entry NMITRAP   0x0008   NMITRAP Non-Maskable Interrupt (Class A Hardware Traps)
entry STOTRAP   0x0010   STOTRAP Stack Overflow (Class A Hardware Traps)
entry STUTRAP   0x0018   STUTRAP Stack Underflow (Class A Hardware Traps)
entry BTRAP     0x0028   BTRAP Class B Hardware Traps
entry CC8INT    0x0060   External Interrupt 0
entry CC9INT    0x0064   External Interrupt 1
entry CC10INT   0x0068   External Interrupt 2
entry CC11INT   0x006C   External Interrupt 3
entry CC12INT   0x0070   External Interrupt 4
entry CC13INT   0x0074   External Interrupt 5
entry CC14INT   0x0078   External Interrupt 6
entry CC15INT   0x007C   External Interrupt 7
entry T2INT     0x0088   GPT1 Timer 2 
entry T3INT     0x008C   GPT1 Timer 3 
entry T4INT     0x0090   GPT1 Timer 4 
entry T5INT     0x0094   GPT2 Timer 5 
entry T6INT     0x0098   GPT2 Timer 6 
entry CRINT     0x009C   GPT2 CAPREL Reg. 
entry S0TINT    0x00A8   ASC0 Transmit 
entry S0RINT    0x00AC   ASC0 Receive 
entry S0EINT    0x00B0   ASC0 Error 
entry XP1INT    0x0104   SSP Interrupt 
entry XP3INT    0x010C   PLL Unlock/OWD 
entry S0TBINT   0x011C   ASC0 Transmit Buffer 


; INPUT/OUTPUT PORTS
SSPCON0         0xEF00  SSP Control Register 0 
SSPCON1         0xEF02  SSP Control Register 1 
SSPRTB          0xEF04  SSP Receive/Transmit Buffer 
SSPTBH          0xEF06  SSP Transmit Buffer High 
DP0L            0xF100  P0L Direction Control Register 
DP0H            0xF102  P0H Direction Control Register 
DP1L            0xF104  P1L Direction Control Register 
DP1H            0xF106  P1H Direction Control Register 
RP0H            0xF108  System Startup Configuration Register (Rd. only) 
XP1IC           0xF18E  SSP Interrupt Control Register 
S0TBIC          0xF19C  Serial Channel 0 Transmit Buffer Interrupt Control Register
XP3IC           0xF19E  PLL/OWD Interrupt Control Register 
EXICON          0xF1C0  External Interrupt Control Register 
ODP2            0xF1C2  Port 2 Open Drain Control Register 
ODP3            0xF1C6  Port 3 Open Drain Control Register 
ODP6            0xF1CE  Port 6 Open Drain Control Register 
DPP0            0xFE00  CPU Data Page Pointer 0 Register (10 bits) 
DPP1            0xFE02  CPU Data Page Pointer 1 Register (10 bits) 
DPP2            0xFE04  CPU Data Page Pointer 2 Register (10 bits) 
DPP3            0xFE06  CPU Data Page Pointer 3 Register (10 bits) 
CSP             0xFE08  CPU Code Segment Pointer Register (read only)
MDH             0xFE0C  CPU Multiply Divide Register - High Word 
MDL             0xFE0E  CPU Multiply Divide Register - Low Word 
CP              0xFE10  CPU Context Pointer Register 
SP              0xFE12  CPU System Stack Pointer Register 
STKOV           0xFE14  CPU Stack Overflow Pointer Register
STKUN           0xFE16  CPU Stack Underflow Pointer Register 
ADDRSEL1        0xFE18  Address Select Register 1 
ADDRSEL2        0xFE1A  Address Select Register 2 
ADDRSEL3        0xFE1C  Address Select Register 3 
ADDRSEL4        0xFE1E  Address Select Register 4 
T2              0xFE40  GPT1 Timer 2 Register 
T3              0xFE42  GPT1 Timer 3 Register 
T4              0xFE44  GPT1 Timer 4 Register 
T5              0xFE46  GPT2 Timer 5 Register 
T6              0xFE48  GPT2 Timer 6 Register 
CAPREL          0xFE4A  GPT2 Capture/Reload Register 
WDT             0xFEAE  Watchdog Timer Register (read only) 
S0TBUF          0xFEB0  Serial Channel 0 Transmit Buffer Register (write only)
S0RBUF          0xFEB2  Serial Channel 0 Receive Buffer Register (read only)
S0BG            0xFEB4  Serial Channel 0 Baud Rate Generator Reload Register
PECC0           0xFEC0  PEC Channel 0 Control Register 
PECC1           0xFEC2  PEC Channel 1 Control Register 
PECC2           0xFEC4  PEC Channel 2 Control Register 
PECC3           0xFEC6  PEC Channel 3 Control Register 
PECC4           0xFEC8  PEC Channel 4 Control Register 
PECC5           0xFECA  PEC Channel 5 Control Register 
PECC6           0xFECC  PEC Channel 6 Control Register 
PECC7           0xFECE  PEC Channel 7 Control Register 
P0L             0xFF00  Port 0 Low Register (Lower half of PORT0) 
P0H             0xFF02  Port 0 High Register (Upper half of PORT0) 
P1L             0xFF04  Port 1 Low Register (Lower half of PORT1) 
P1H             0xFF06  Port 1 High Register (Upper half of PORT1) 
BUSCON0         0xFF0C  Bus Configuration Register 0 
MDC             0xFF0E  CPU Multiply Divide Control Register 
PSW             0xFF10  CPU Program Status Word 
SYSCON          0xFF12  CPU System Configuration Register 
BUSCON1         0xFF14  Bus Configuration Register 1 
BUSCON2         0xFF16  Bus Configuration Register 2 
BUSCON3         0xFF18  Bus Configuration Register 3 
BUSCON4         0xFF1A  Bus Configuration Register 4 
ZEROS           0xFF1C  Constant Value 0's Register (read only)
ONES            0xFF1E  Constant Value 1's Register (read only) 
T2CON           0xFF40  GPT1 Timer 2 Control Register 
T3CON           0xFF42  GPT1 Timer 3 Control Register 
T4CON           0xFF44  GPT1 Timer 4 Control Register 
T5CON           0xFF46  GPT2 Timer 5 Control Register 
T6CON           0xFF48  GPT2 Timer 6 Control Register 
T2IC            0xFF60  GPT1 Timer 2 Interrupt Control Register 
T3IC            0xFF62  GPT1 Timer 3 Interrupt Control Register 
T4IC            0xFF64  GPT1 Timer 4 Interrupt Control Register 
T5IC            0xFF66  GPT2 Timer 5 Interrupt Control Register 
T6IC            0xFF68  GPT2 Timer 6 Interrupt Control Register 
CRIC            0xFF6A  GPT2 CAPREL Interrupt Control Register 
S0TIC           0xFF6C  Serial Channel 0 Transmit Interrupt Control Register
S0RIC           0xFF6E  Serial Channel 0 Receive Interrupt Control Register
S0EIC           0xFF70  Serial Channel 0 Error Interrupt Control Register 
CC8IC           0xFF88  EX0IN Interrupt Control Register 
CC9IC           0xFF8A  EX1IN Interrupt Control Register 
CC10IC          0xFF8C  EX2IN Interrupt Control Register 
CC11IC          0xFF8E  EX3IN Interrupt Control Register 
CC12IC          0xFF90  EX4IN Interrupt Control Register 
CC13IC          0xFF92  EX5IN Interrupt Control Register 
CC14IC          0xFF94  EX6IN Interrupt Control Register 
CC15IC          0xFF96  EX7IN Interrupt Control Register 
P5              0xFFA2  Port 5 Register (read only)
TFR             0xFFAC  Trap Flag Register 
WDTCON          0xFFAE  Watchdog Timer Control Register 
S0CON           0xFFB0  Serial Channel 0 Control Register 
P2              0xFFC0  Port 2 Register 
DP2             0xFFC2  Port 2 Direction Control Register 
P3              0xFFC4  Port 3 Register 
DP3             0xFFC6  Port 3 Direction Control Register 
P4              0xFFC8  Port 4 Register (8 bits) 
DP4             0xFFCA  Port 4 Direction Control Register 
P6              0xFFCC  Port 6 Register (8 bits) 
DP6             0xFFCE  Port 6 Direction Control Register 


.C164CI_SI
; C164.pdf

; C164CI-LM    (RAM 4 KB)
; C164CI-8EM   (RAM 2 KB)
; C164CI-4RM   (ROM 32 KB, RAM 4 KB)
; C164CI-8RM   (ROM 64 KB, RAM 4 KB)
; C164CL-4RM   (ROM 32 KB, RAM 4 KB)
; C164CL-8RM   (ROM 64 KB, RAM 4 KB)
; C164SI-8RM   (ROM 64 KB, RAM 4 KB)


; MEMORY MAP


; Interrupt and reset vector assignments
entry RESET     0x0000   RESET
entry NMITRAP   0x0008   NMITRAP Non-Maskable Interrupt (Class A Hardware Traps)
entry STOTRAP   0x0010   STOTRAP Stack Overflow (Class A Hardware Traps)
entry STUTRAP   0x0018   STUTRAP Stack Underflow (Class A Hardware Traps)
entry BTRAP     0x0028   BTRAP Class B Hardware Traps
entry CC8INT    0x0060   CAPCOM Register 8
entry CC9INT    0x0064   CAPCOM Register 9
entry CC10INT   0x0068   CAPCOM Register 10
entry CC11INT   0x006C   CAPCOM Register 11
entry T2INT     0x0088   GPT1 Timer 2 
entry T3INT     0x008C   GPT1 Timer 3 
entry T4INT     0x0090   GPT1 Timer 4 
entry ADCINT    0x00A0   A/D Conversion Complete 
entry ADEINT    0x00A4   A/D Overrun Error 
entry S0TINT    0x00A8   ASC0 Transmit 
entry S0RINT    0x00AC   ASC0 Receive 
entry S0EINT    0x00B0   ASC0 Error 
entry SCTINT    0x00B4   SSC Transmit 
entry SCRINT    0x00B8   SSC Receive 
entry SCEINT    0x00BC   SSC Error 
entry CC16INT   0x00C0   CAPCOM Register 16 
entry CC17INT   0x00C4   CAPCOM Register 17 
entry CC18INT   0x00C8   CAPCOM Register 18 
entry CC19INT   0x00CC   CAPCOM Register 19 
entry CC24INT   0x00E0   CAPCOM Register 24 
entry CC25INT   0x00E4   CAPCOM Register 25 
entry CC26INT   0x00E8   CAPCOM Register 26 
entry CC27INT   0x00EC   CAPCOM Register 27 
entry T7INT     0x00F4   CAPCOM Timer 7 
entry T8INT     0x00F8   CAPCOM Timer 8 
entry PWMINT    0x00FC   PWM Channel 0_3 
entry XP0INT    0x0100   CAN1 
entry XP3INT    0x010C   PLL/OWD 
entry S0TBINT   0x011C   ASC0 Transmit Buffer 
entry T12INT    0x0134   Timer 12 
entry T13INT    0x0138   CAPCOM 6 Timer 13 
entry CC6EINT   0x013C   CAPCOM 6 Emergency 


; INPUT/OUTPUT PORTS
OPCTRL          0xEDC0  OTP Progr. Interface Control Register 
OPAD            0xEDC2  OTP Progr. Interface Address Register 
OPDAT           0xEDC4  OTP Progr. Interface Data Register 
C1CSR           0xEF00  CAN1 Control / Status Register 
C1PCIR          0xEF02  CAN1 Port Control / Interrupt Register 
C1BTR           0xEF04  CAN1 Bit Timing Register 
C1GMS           0xEF06  CAN1 Global Mask Short 
C1UGML          0xEF08  CAN Upper Global Mask Long 
C1LGML          0xEF0A  CAN Lower Global Mask Long 
C1UMLM          0xEF0C  CAN Upper Mask of Last Message 
C1LMLM          0xEF0E  CAN Lower Mask of Last Message
C1MCR1          0xEF10  CAN Message Control Register (msg. n) 
C1UAR1          0xEF12  CAN Upper Arbitration Register (msg. n) 
C1LAR1          0xEF14  CAN Lower Arbitration Register (msg. n) 
C1MCFG1         0xEF16  CAN Message Configuration Register (msg. n)
C1MCR2          0xEF20  CAN Message Control Register (msg. n) 
C1UAR2          0xEF22  CAN Upper Arbitration Register (msg. n) 
C1LAR2          0xEF24  CAN Lower Arbitration Register (msg. n) 
C1MCFG2         0xEF26  CAN Message Configuration Register (msg. n)
C1MCR3          0xEF30  CAN Message Control Register (msg. n) 
C1UAR3          0xEF32  CAN Upper Arbitration Register (msg. n) 
C1LAR3          0xEF34  CAN Lower Arbitration Register (msg. n) 
C1MCFG3         0xEF36  CAN Message Configuration Register (msg. n)
C1MCR4          0xEF40  CAN Message Control Register (msg. n) 
C1UAR4          0xEF42  CAN Upper Arbitration Register (msg. n) 
C1LAR4          0xEF44  CAN Lower Arbitration Register (msg. n) 
C1MCFG4         0xEF46  CAN Message Configuration Register (msg. n)
C1MCR5          0xEF50  CAN Message Control Register (msg. n) 
C1UAR5          0xEF52  CAN Upper Arbitration Register (msg. n) 
C1LAR5          0xEF54  CAN Lower Arbitration Register (msg. n) 
C1MCFG5         0xEF56  CAN Message Configuration Register (msg. n)
C1MCR6          0xEF60  CAN Message Control Register (msg. n) 
C1UAR6          0xEF62  CAN Upper Arbitration Register (msg. n) 
C1LAR6          0xEF64  CAN Lower Arbitration Register (msg. n) 
C1MCFG6         0xEF66  CAN Message Configuration Register (msg. n)
C1MCR7          0xEF70  CAN Message Control Register (msg. n) 
C1UAR7          0xEF72  CAN Upper Arbitration Register (msg. n) 
C1LAR7          0xEF74  CAN Lower Arbitration Register (msg. n) 
C1MCFG7         0xEF76  CAN Message Configuration Register (msg. n)
C1MCR8          0xEF80  CAN Message Control Register (msg. n) 
C1UAR8          0xEF82  CAN Upper Arbitration Register (msg. n) 
C1LAR8          0xEF84  CAN Lower Arbitration Register (msg. n) 
C1MCFG8         0xEF86  CAN Message Configuration Register (msg. n)
C1MCR9          0xEF90  CAN Message Control Register (msg. n) 
C1UAR9          0xEF92  CAN Upper Arbitration Register (msg. n) 
C1LAR9          0xEF94  CAN Lower Arbitration Register (msg. n) 
C1MCFG9         0xEF96  CAN Message Configuration Register (msg. n)
C1MCRA          0xEFA0  CAN Message Control Register (msg. n) 
C1UARA          0xEFA2  CAN Upper Arbitration Register (msg. n) 
C1LARA          0xEFA4  CAN Lower Arbitration Register (msg. n) 
C1MCFGA         0xEFA6  CAN Message Configuration Register (msg. n)
C1MCRB          0xEFB0  CAN Message Control Register (msg. n) 
C1UARB          0xEFB2  CAN Upper Arbitration Register (msg. n) 
C1LARB          0xEFB4  CAN Lower Arbitration Register (msg. n) 
C1MCFGB         0xEFB6  CAN Message Configuration Register (msg. n)
C1MCRC          0xEFC0  CAN Message Control Register (msg. n) 
C1UARC          0xEFC2  CAN Upper Arbitration Register (msg. n) 
C1LARC          0xEFC4  CAN Lower Arbitration Register (msg. n) 
C1MCFGC         0xEFC6  CAN Message Configuration Register (msg. n)
C1MCRD          0xEFD0  CAN Message Control Register (msg. n) 
C1UARD          0xEFD2  CAN Upper Arbitration Register (msg. n) 
C1LARD          0xEFD4  CAN Lower Arbitration Register (msg. n) 
C1MCFGD         0xEFD6  CAN Message Configuration Register (msg. n)
C1MCRE          0xEFE0  CAN Message Control Register (msg. n) 
C1UARE          0xEFE2  CAN Upper Arbitration Register (msg. n) 
C1LARE          0xEFE4  CAN Lower Arbitration Register (msg. n) 
C1MCFGE         0xEFE6  CAN Message Configuration Register (msg. n)
C1MCRF          0xEFF0  CAN Message Control Register (msg. n) 
C1UARF          0xEFF2  CAN Upper Arbitration Register (msg. n) 
C1LARF          0xEFF4  CAN Lower Arbitration Register (msg. n) 
C1MCFGF         0xEFF6  CAN Message Configuration Register (msg. n)
T12P            0xF030  CAPCOM 6 Timer 12 Period Register 
T13P            0xF032  CAPCOM 6 Timer 13 Period Register 
T12OF           0xF034  CAPCOM 6 Timer 12 Offset Register 
CC6MSEL         0xF036  CAPCOM 6 Mode Select Register 
T7              0xF050  CAPCOM Timer 7 Register 
T8              0xF052  CAPCOM Timer 8 Register 
T7REL           0xF054  CAPCOM Timer 7 Reload Register 
T8REL           0xF056  CAPCOM Timer 8 Reload Register 
IDMEM2          0xF076  Identifier 
IDPROG          0xF078  Identifier 
IDMEM           0xF07A  Identifier 
IDCHIP          0xF07C  Identifier 
IDMANUF         0xF07E  Identifier 
POCON0L         0xF080  Port P0L Output Control Register 
POCON0H         0xF082  Port P0H Output Control Register 
POCON1L         0xF084  Port P1L Output Control Register 
POCON1H         0xF086  Port P1H Output Control Register 
POCON3          0xF08A  Port P3 Output Control Register 
POCON4          0xF08C  Port P4 Output Control Register 
POCON8          0xF092  Port P8 Output Control Register 
ADDAT2          0xF0A0  A/D Converter 2 Result Register 
POCON20         0xF0AA  Dedicated Pin Output Control Register 
SSCTB           0xF0B0  SSC Transmit Buffer 
SSCRB           0xF0B2  SSC Receive Buffer 
SSCBR           0xF0B4  SSC Baudrate Register 
T14REL          0xF0D0  RTC Timer 14 Reload Register 
T14             0xF0D2  RTC Timer 14 Register 
RTCL            0xF0D4  RTC Low Register 
RTCH            0xF0D6  RTC High Register 
DP0L            0xF100  P0L Direction Control Register 
DP0H            0xF102  P0H Direction Control Register 
DP1L            0xF104  P1L Direction Control Register 
DP1H            0xF106  P1H Direction Control Register 
RP0H            0xF108  System Startup Config. Reg. (Rd. only) 
CC16IC          0xF160  CAPCOM Reg. 16 Interrupt Ctrl. Reg. 
CC17IC          0xF162  CAPCOM Reg. 17 Interrupt Ctrl. Reg. 
CC18IC          0xF164  CAPCOM Reg. 18 Interrupt Ctrl. Reg. 
CC19IC          0xF166  CAPCOM Reg. 19 Interrupt Ctrl. Reg. 
CC20IC          0xF168  CAPCOM Reg. 20 Interrupt Ctrl. Reg. 
CC21IC          0xF16A  CAPCOM Reg. 21 Interrupt Ctrl. Reg. 
CC22IC          0xF16C  CAPCOM Reg. 22 Interrupt Ctrl. Reg. 
CC23IC          0xF16E  CAPCOM Reg. 23 Interrupt Ctrl. Reg. 
CC24IC          0xF170  CAPCOM Reg. 24 Interrupt Ctrl. Reg. 
CC25IC          0xF172  CAPCOM Reg. 25 Interrupt Ctrl. Reg. 
CC26IC          0xF174  CAPCOM Reg. 26 Interrupt Ctrl. Reg. 
CC27IC          0xF176  CAPCOM Reg. 27 Interrupt Ctrl. Reg. 
CC28IC          0xF178  CAPCOM Reg. 28 Interrupt Ctrl. Reg. 
T7IC            0xF17A  CAPCOM Timer 7 Interrupt Ctrl. Reg. 
T8IC            0xF17C  CAPCOM Timer 8 Interrupt Ctrl. Reg. 
CC6CIC          0xF17E  CAPCOM 6 Interrupt Control Register 
CC29IC          0xF184  CAPCOM Reg. 29 Interrupt Ctrl. Reg. 
XP0IC           0xF186  CAN1 Module Interrupt Control Register 
CC6EIC          0xF188  CAPCOM 6 Emergency Interrrupt Control Register
CC30IC          0xF18C  CAPCOM Reg. 30 Interrupt Ctrl. Reg. 
XP1IC           0xF18E  Unassigned Interrupt Control Reg.
T12IC           0xF190  CAPCOM 6 Timer 12 Interrupt Ctrl. Reg. 
CC31IC          0xF194  CAPCOM Reg. 31 Interrupt Ctrl. Reg. 
T13IC           0xF198  CAPCOM 6 Timer 13 Interrupt Ctrl. Reg. 
S0TBIC          0xF19C  Serial Channel 0 Transmit Buffer Interrupt Control Register
XP3IC           0xF19E  PLL/RTC Interrupt Control Register 
EXICON          0xF1C0  External Interrupt Control Register 
PICON           0xF1C4  Port Input Threshold Control Register 
ODP3            0xF1C6  Port 3 Open Drain Control Register 
ODP4            0xF1CA  Port 4 Open Drain Control Register 
SYSCON2         0xF1D0  CPU System Configuration Register 2 
SYSCON3         0xF1D4  CPU System Configuration Register
ODP8            0xF1D6  Port 8 Open Drain Control Register 
EXISEL          0xF1DA  External Interrupt Source Select Reg. 
SYSCON1         0xF1DC  CPU System Configuration Register 1 
ISNC            0xF1DE  Interrupt Subnode Control Register 
RSTCON          0xF1E0  Reset Control Register
DPP0            0xFE00  CPU Data Page Pointer 0 Reg. (10 bits) 
DPP1            0xFE02  CPU Data Page Pointer 1 Reg. (10 bits) 
DPP2            0xFE04  CPU Data Page Pointer 2 Reg. (10 bits) 
DPP3            0xFE06  CPU Data Page Pointer 3 Reg. (10 bits) 
CSP             0xFE08  CPU Code Segment Pointer Register (8 bits, not directly writeable)
MDH             0xFE0C  CPU Multiply Divide Reg. - High Word 
MDL             0xFE0E  CPU Multiply Divide Reg. - Low Word 
CP              0xFE10  CPU Context Pointer Register 
SP              0xFE12  CPU System Stack Pointer Register 
STKOV           0xFE14  CPU Stack Overflow Pointer Register 
STKUN           0xFE16  CPU Stack Underflow Pointer Register 
ADDRSEL1        0xFE18  Address Select Register 1 
ADDRSEL2        0xFE1A  Address Select Register 2 
ADDRSEL3        0xFE1C  Address Select Register 3 
ADDRSEL4        0xFE1E  Address Select Register 4 
CC60            0xFE30  CAPCOM 6 Register 0 
CC61            0xFE32  CAPCOM 6 Register 1 
CC62            0xFE34  CAPCOM 6 Register 2 
CMP13           0xFE36  CAPCOM 6 Timer 13 Compare Reg. 
T2              0xFE40  GPT1 Timer 2 Register 
T3              0xFE42  GPT1 Timer 3 Register 
T4              0xFE44  GPT1 Timer 4 Register 
CC16            0xFE60  CAPCOM Register 16 
CC17            0xFE62  CAPCOM Register 17 
CC18            0xFE64  CAPCOM Register 18 
CC19            0xFE66  CAPCOM Register 19 
CC20            0xFE68  CAPCOM Register 20 
CC21            0xFE6A  CAPCOM Register 21 
CC22            0xFE6C  CAPCOM Register 22 
CC23            0xFE6E  CAPCOM Register 23 
CC24            0xFE70  CAPCOM Register 24 
CC25            0xFE72  CAPCOM Register 25 
CC26            0xFE74  CAPCOM Register 26
CC27            0xFE76  CAPCOM Register 27 
CC28            0xFE78  CAPCOM Register 28 
CC29            0xFE7A  CAPCOM Register 29 
CC30            0xFE7C  CAPCOM Register 30 
CC31            0xFE7E  CAPCOM Register 31 
ADDAT           0xFEA0  A/D Converter Result Register 
WDT             0xFEAE  Watchdog Timer Register (read only) 
S0TBUF          0xFEB0  Serial Channel 0 Transmit Buffer Reg. (write only)
S0RBUF          0xFEB2  Serial Channel 0 Receive Buffer Reg. (read only)
S0BG            0xFEB4  Serial Channel 0 Baud Rate Generator Reload Register
PECC0           0xFEC0  PEC Channel 0 Control Register 
PECC1           0xFEC2  PEC Channel 1 Control Register 
PECC2           0xFEC4  PEC Channel 2 Control Register 
PECC3           0xFEC6  PEC Channel 3 Control Register 
PECC4           0xFEC8  PEC Channel 4 Control Register 
PECC5           0xFECA  PEC Channel 5 Control Register 
PECC6           0xFECC  PEC Channel 6 Control Register 
PECC7           0xFECE  PEC Channel 7 Control Register 
P0L             0xFF00  Port 0 Low Reg. (Lower half of PORT0) 
P0H             0xFF02  Port 0 High Reg. (Upper half of PORT0) 
P1L             0xFF04  Port 1 Low Reg. (Lower half of PORT1) 
P1H             0xFF06  Port 1 High Reg. (Upper half of PORT1) 
BUSCON0         0xFF0C  Bus Configuration Register 0 
MDC             0xFF0E  CPU Multiply Divide Control Register 
PSW             0xFF10  CPU Program Status Word 
SYSCON          0xFF12  CPU System Configuration Register 
BUSCON1         0xFF14  Bus Configuration Register 1 
BUSCON2         0xFF16  Bus Configuration Register 2 
BUSCON3         0xFF18  Bus Configuration Register 3 
BUSCON4         0xFF1A  Bus Configuration Register 4 
ZEROS           0xFF1C  Constant Value 0's Register (read only)
ONES            0xFF1E  Constant Value 1's Register (read only) 
T78CON          0xFF20  CAPCOM Timer 7 and 8 Ctrl. Reg. 
CCM4            0xFF22  CAPCOM Mode Control Register 4 
CCM5            0xFF24  CAPCOM Mode Control Register 5 
CCM6            0xFF26  CAPCOM Mode Control Register 6 
CCM7            0xFF28  CAPCOM Mode Control Register 7 
CTCON           0xFF30  CAPCOM 6 Compare Timer Ctrl. Reg. 
CC6MCON         0xFF32  CAPCOM 6 Mode Control Register 
TRCON           0xFF34  CAPCOM 6 Trap Enable Ctrl. Reg. 
CC6MIC          0xFF36  CAPCOM 6 Mode Interrupt Ctrl. Reg. 
T2CON           0xFF40  GPT1 Timer 2 Control Register 
T3CON           0xFF42  GPT1 Timer 3 Control Register 
T4CON           0xFF44  GPT1 Timer 4 Control Register 
T2IC            0xFF60  GPT1 Timer 2 Interrupt Control Register 
T3IC            0xFF62  GPT1 Timer 3 Interrupt Control Register 
T4IC            0xFF64  GPT1 Timer 4 Interrupt Control Register 
S0TIC           0xFF6C  Serial Channel 0 Transmit Interrupt Control Register
S0RIC           0xFF6E  Serial Channel 0 Receive Interrupt Control Register
S0EIC           0xFF70  Serial Channel 0 Error Interrupt Ctrl. Reg.
SSCTIC          0xFF72  SSC Transmit Interrupt Control Register 
SSCRIC          0xFF74  SSC Receive Interrupt Control Register 
SSCEIC          0xFF76  SSC Error Interrupt Control Register 
CC8IC           0xFF88  External Interrupt 0 Control Register 
CC9IC           0xFF8A  External Interrupt 1 Control Register 
CC10IC          0xFF8C  External Interrupt 2 Control Register 
CC11IC          0xFF8E  External Interrupt 3 Control Register 
ADCIC           0xFF98  A/D Converter End of Conversion Interrupt Control Register
ADEIC           0xFF9A  A/D Converter Overrun Error Interrupt Control Register
ADCON           0xFFA0  A/D Converter Control Register 
P5              0xFFA2  Port 5 Register (read only) 
P5DIDIS         0xFFA4  Port 5 Digital Input Disable Register 
FOCON           0xFFAA  Frequency Output Control Register 
TFR             0xFFAC  Trap Flag Register 
WDTCON          0xFFAE  Watchdog Timer Control Register 
S0CON           0xFFB0  Serial Channel 0 Control Register 
SSCCON          0xFFB2  SSC Control Register 
P3              0xFFC4  Port 3 Register 
DP3             0xFFC6  Port 3 Direction Control Register 
P4              0xFFC8  Port 4 Register (7 bits) 
DP4             0xFFCA  Port 4 Direction Control Register 
P8              0xFFD4  Port 8 Register (8 bits) 
DP8             0xFFD6  Port 8 Direction Control Register 


.C164CM_SM
; c164cm_ds_v1.0_2001_05.pdf
; C164CM/SM


; MEMORY MAP


; Interrupt and reset vector assignments
entry RESET     0x0000   RESET
entry NMITRAP   0x0008   NMITRAP Non-Maskable Interrupt (Class A Hardware Traps)
entry STOTRAP   0x0010   STOTRAP Stack Overflow (Class A Hardware Traps)
entry STUTRAP   0x0018   STUTRAP Stack Underflow (Class A Hardware Traps)
entry BTRAP     0x0028   BTRAP Class B Hardware Traps
entry CC8INT    0x0060   Fast External Interrupt 0
entry CC9INT    0x0064   Fast External Interrupt 1
entry CC10INT   0x0068   Fast External Interrupt 2
entry CC11INT   0x006C   Fast External Interrupt 3
entry T2INT     0x0088   GPT1 Timer 2 
entry T3INT     0x008C   GPT1 Timer 3 
entry T4INT     0x0090   GPT1 Timer 4 
entry ADCINT    0x00A0   A/D Conversion Complete 
entry ADEINT    0x00A4   A/D Overrun Error 
entry S0TINT    0x00A8   ASC0 Transmit 
entry S0RINT    0x00AC   ASC0 Receive 
entry S0EINT    0x00B0   ASC0 Error 
entry SCTINT    0x00B4   SSC Transmit 
entry SCRINT    0x00B8   SSC Receive 
entry SCEINT    0x00BC   SSC Error 
entry CC16INT   0x00C0   CAPCOM Register 16 
entry CC17INT   0x00C4   CAPCOM Register 17 
entry CC18INT   0x00C8   CAPCOM Register 18 
entry CC19INT   0x00CC   CAPCOM Register 19 
entry CC24INT   0x00E0   CAPCOM Register 24 
entry CC25INT   0x00E4   CAPCOM Register 25 
entry CC26INT   0x00E8   CAPCOM Register 26 
entry CC27INT   0x00EC   CAPCOM Register 27 
entry T7INT     0x00F4   CAPCOM Timer 7 
entry T8INT     0x00F8   CAPCOM Timer 8 
entry PWMINT    0x00FC   PWM Channel 0_3 
entry XP0INT    0x0100   CAN1 
entry XP3INT    0x010C   PLL/OWD 
entry S0TBINT   0x011C   ASC0 Transmit Buffer 
entry T12INT    0x0134   Timer 12 
entry T13INT    0x0138   CAPCOM 6 Timer 13 
entry CC6EINT   0x013C   CAPCOM 6 Emergency 


; INPUT/OUTPUT PORTS
OPCTRL          0xEDC0  OTP Progr. Interface Control Register 
OPAD            0xEDC2  OTP Progr. Interface Address Register 
OPDAT           0xEDC4  OTP Progr. Interface Data Register 
C1CSR           0xEF00  CAN1 Control / Status Register 
C1PCIR          0xEF02  CAN1 Port Control / Interrupt Register 
C1BTR           0xEF04  CAN1 Bit Timing Register 
C1GMS           0xEF06  CAN1 Global Mask Short 
C1UGML          0xEF08  CAN Upper Global Mask Long 
C1LGML          0xEF0A  CAN Lower Global Mask Long 
C1UMLM          0xEF0C  CAN Upper Mask of Last Message 
C1LMLM          0xEF0E  CAN Lower Mask of Last Message
C1MCR1          0xEF10  CAN Message Control Register (msg. n) 
C1UAR1          0xEF12  CAN Upper Arbitration Register (msg. n) 
C1LAR1          0xEF14  CAN Lower Arbitration Register 
C1MCFG1         0xEF16  CAN Message Configuration Register (msg. n)
C1MCR2          0xEF20  CAN Message Control Register (msg. n) 
C1UAR2          0xEF22  CAN Upper Arbitration Register (msg. n) 
C1LAR2          0xEF24  CAN Lower Arbitration Register 
C1MCFG2         0xEF26  CAN Message Configuration Register (msg. n)
C1MCR3          0xEF30  CAN Message Control Register (msg. n) 
C1UAR3          0xEF32  CAN Upper Arbitration Register (msg. n) 
C1LAR3          0xEF34  CAN Lower Arbitration Register 
C1MCFG3         0xEF36  CAN Message Configuration Register (msg. n)
C1MCR4          0xEF40  CAN Message Control Register (msg. n) 
C1UAR4          0xEF42  CAN Upper Arbitration Register (msg. n) 
C1LAR4          0xEF44  CAN Lower Arbitration Register 
C1MCFG4         0xEF46  CAN Message Configuration Register (msg. n)
C1MCR5          0xEF50  CAN Message Control Register (msg. n) 
C1UAR5          0xEF52  CAN Upper Arbitration Register (msg. n) 
C1LAR5          0xEF54  CAN Lower Arbitration Register 
C1MCFG5         0xEF56  CAN Message Configuration Register (msg. n)
C1MCR6          0xEF60  CAN Message Control Register (msg. n) 
C1UAR6          0xEF62  CAN Upper Arbitration Register (msg. n) 
C1LAR6          0xEF64  CAN Lower Arbitration Register 
C1MCFG6         0xEF66  CAN Message Configuration Register (msg. n)
C1MCR7          0xEF70  CAN Message Control Register (msg. n) 
C1UAR7          0xEF72  CAN Upper Arbitration Register (msg. n) 
C1LAR7          0xEF74  CAN Lower Arbitration Register 
C1MCFG7         0xEF76  CAN Message Configuration Register (msg. n)
C1MCR8          0xEF80  CAN Message Control Register (msg. n) 
C1UAR8          0xEF82  CAN Upper Arbitration Register (msg. n) 
C1LAR8          0xEF84  CAN Lower Arbitration Register 
C1MCFG8         0xEF86  CAN Message Configuration Register (msg. n)
C1MCR9          0xEF90  CAN Message Control Register (msg. n) 
C1UAR9          0xEF92  CAN Upper Arbitration Register (msg. n) 
C1LAR9          0xEF94  CAN Lower Arbitration Register 
C1MCFG9         0xEF96  CAN Message Configuration Register (msg. n)
C1MCRA          0xEFA0  CAN Message Control Register (msg. n) 
C1UARA          0xEFA2  CAN Upper Arbitration Register (msg. n) 
C1LARA          0xEFA4  CAN Lower Arbitration Register 
C1MCFGA         0xEFA6  CAN Message Configuration Register (msg. n)
C1MCRB          0xEFB0  CAN Message Control Register (msg. n) 
C1UARB          0xEFB2  CAN Upper Arbitration Register (msg. n) 
C1LARB          0xEFB4  CAN Lower Arbitration Register 
C1MCFGB         0xEFB6  CAN Message Configuration Register (msg. n)
C1MCRC          0xEFC0  CAN Message Control Register (msg. n) 
C1UARC          0xEFC2  CAN Upper Arbitration Register (msg. n) 
C1LARC          0xEFC4  CAN Lower Arbitration Register 
C1MCFGC         0xEFC6  CAN Message Configuration Register (msg. n)
C1MCRD          0xEFD0  CAN Message Control Register (msg. n) 
C1UARD          0xEFD2  CAN Upper Arbitration Register (msg. n) 
C1LARD          0xEFD4  CAN Lower Arbitration Register 
C1MCFGD         0xEFD6  CAN Message Configuration Register (msg. n)
C1MCRE          0xEFE0  CAN Message Control Register (msg. n) 
C1UARE          0xEFE2  CAN Upper Arbitration Register (msg. n) 
C1LARE          0xEFE4  CAN Lower Arbitration Register 
C1MCFGE         0xEFE6  CAN Message Configuration Register (msg. n)
C1MCRF          0xEFF0  CAN Message Control Register (msg. n) 
C1UARF          0xEFF2  CAN Upper Arbitration Register (msg. n) 
C1LARF          0xEFF4  CAN Lower Arbitration Register 
C1MCFGF         0xEFF6  CAN Message Configuration Register (msg. n)
T12P            0xF030  CAPCOM 6 Timer 12 Period Register 
T13P            0xF032  CAPCOM 6 Timer 13 Period Register 
T12OF           0xF034  CAPCOM 6 Timer 12 Offset Register 
CC6MSEL         0xF036  CAPCOM 6 Mode Select Register 
T7              0xF050  CAPCOM Timer 7 Register 
T8              0xF052  CAPCOM Timer 8 Register 
T7REL           0xF054  CAPCOM Timer 7 Reload Register 
T8REL           0xF056  CAPCOM Timer 8 Reload Register 
IDMEM2          0xF076  Identifier 
IDPROG          0xF078  Identifier 
IDMEM           0xF07A  Identifier 
IDCHIP          0xF07C  Identifier 
IDMANUF         0xF07E  Identifier 
POCON0L         0xF080  Port P0L Output Control Register 
POCON0H         0xF082  Port P0H Output Control Register 
POCON1L         0xF084  Port P1L Output Control Register 
POCON1H         0xF086  Port P1H Output Control Register 
POCON8          0xF092  Port P8 Output Control Register 
ADDAT2          0xF0A0  A/D Converter 2 Result Register 
POCON20         0xF0AA  Port P20 Output Control Register 
SSCTB           0xF0B0  SSC Transmit Buffer 
SSCRB           0xF0B2  SSC Receive Buffer 
SSCBR           0xF0B4  SSC Baudrate Register 
T14REL          0xF0D0  RTC Timer 14 Reload Register 
T14             0xF0D2  RTC Timer 14 Register 
RTCL            0xF0D4  RTC Low Register 
RTCH            0xF0D6  RTC High Register 
DP0L            0xF100  P0L Direction Control Register 
DP0H            0xF102  P0H Direction Control Register
DP1L            0xF104  P1L Direction Control Register 
DP1H            0xF106  P1H Direction Control Register 
RP0H            0xF108  System Startup Config. Reg. (Rd. only) 
CC16IC          0xF160  CAPCOM Reg. 16 Interrupt Ctrl. Reg. 
CC17IC          0xF162  CAPCOM Reg. 17 Interrupt Ctrl. Reg. 
CC18IC          0xF164  CAPCOM Reg. 18 Interrupt Ctrl. Reg. 
CC19IC          0xF166  CAPCOM Reg. 19 Interrupt Ctrl. Reg. 
CC20IC          0xF168  CAPCOM Reg. 20 Interrupt Ctrl. Reg. 
CC21IC          0xF16A  CAPCOM Reg. 21 Interrupt Ctrl. Reg. 
CC22IC          0xF16C  CAPCOM Reg. 22 Interrupt Ctrl. Reg. 
CC23IC          0xF16E  CAPCOM Reg. 23 Interrupt Ctrl. Reg.
CC24IC          0xF170  CAPCOM Reg. 24 Interrupt Ctrl. Reg. 
CC25IC          0xF172  CAPCOM Reg. 25 Interrupt Ctrl. Reg. 
CC26IC          0xF174  CAPCOM Reg. 26 Interrupt Ctrl. Reg. 
CC27IC          0xF176  CAPCOM Reg. 27 Interrupt Ctrl. Reg. 
CC28IC          0xF178  CAPCOM Reg. 28 Interrupt Ctrl. Reg. 
T7IC            0xF17A  CAPCOM Timer 7 Interrupt Ctrl. Reg. 
T8IC            0xF17C  CAPCOM Timer 8 Interrupt Ctrl. Reg. 
CC6CIC          0xF17E  CAPCOM 6 Interrupt Control Register 
CC29IC          0xF184  CAPCOM Reg. 29 Interrupt Ctrl. Reg. 
XP0IC           0xF186  CAN1 Module Interrupt Control Register 
CC6EIC          0xF188  CAPCOM 6 Emergency Interrupt Control Register
CC30IC          0xF18C  CAPCOM Reg. 30 Interrupt Ctrl. Reg. 
XP1IC           0xF18E  Unassigned Interrupt Control Reg. 
T12IC           0xF190  CAPCOM 6 Timer 12 Interrupt Ctrl. Reg. 
CC31IC          0xF194  CAPCOM Reg. 31 Interrupt Ctrl. Reg. 
T13IC           0xF198  CAPCOM 6 Timer 13 Interrupt Ctrl. Reg. 
S0TBIC          0xF19C  Serial Channel 0 Transmit Buffer Interrupt Control Register
XP3IC           0xF19E  PLL/RTC Interrupt Control Register 
EXICON          0xF1C0  External Interrupt Control Register 
SYSCON2         0xF1D0  CPU System Configuration Register 2 
SYSCON3         0xF1D4  CPU System Configuration Register 3 
ODP8            0xF1D6  Port 8 Open Drain Control Register 
EXISEL          0xF1DA  External Interrupt Source Select Reg. 
SYSCON1         0xF1DC  CPU System Configuration Register 1 
ISNC            0xF1DE  Interrupt Subnode Control Register 
RSTCON          0xF1E0  Reset Control Register 
DPP0            0xFE00  CPU Data Page Pointer 0 Reg. (10 bits) 
DPP1            0xFE02  CPU Data Page Pointer 1 Reg. (10 bits) 
DPP2            0xFE04  CPU Data Page Pointer 2 Reg. (10 bits) 
DPP3            0xFE06  CPU Data Page Pointer 3 Reg. (10 bits) 
CSP             0xFE08  CPU Code Segment Pointer Register (8 bits, not directly writeable)
MDH             0xFE0C  CPU Multiply Divide Reg. - High Word 
MDL             0xFE0E  CPU Multiply Divide Reg. - Low Word 
CP              0xFE10  CPU Context Pointer Register 
SP              0xFE12  CPU System Stack Pointer Register 
STKOV           0xFE14  CPU Stack Overflow Pointer Register 
STKUN           0xFE16  CPU Stack Underflow Pointer Register 
ADDRSEL1        0xFE18  Address Select Register 1 
ADDRSEL2        0xFE1A  Address Select Register 2 
ADDRSEL3        0xFE1C  Address Select Register 3 
ADDRSEL4        0xFE1E  Address Select Register 4 
CC60            0xFE30  CAPCOM 6 Register 0 
CC61            0xFE32  CAPCOM 6 Register 1 
CC62            0xFE34  CAPCOM 6 Register 2 
CMP13           0xFE36  CAPCOM 6 Timer 13 Compare Reg. 
T2              0xFE40  GPT1 Timer 2 Register 
T3              0xFE42  GPT1 Timer 3 Register 
T4              0xFE44  GPT1 Timer 4 Register 
CC16            0xFE60  CAPCOM Register 16 
CC17            0xFE62  CAPCOM Register 17 
CC18            0xFE64  CAPCOM Register 18 
CC19            0xFE66  CAPCOM Register 19 
CC20            0xFE68  CAPCOM Register 20 
CC21            0xFE6A  CAPCOM Register 21 
CC22            0xFE6C  CAPCOM Register 22 
CC23            0xFE6E  CAPCOM Register 23 
CC24            0xFE70  CAPCOM Register 24 
CC25            0xFE72  CAPCOM Register 25 
CC26            0xFE74  CAPCOM Register 26 
CC27            0xFE76  CAPCOM Register 27
CC28            0xFE78  CAPCOM Register 28 
CC29            0xFE7A  CAPCOM Register 29 
CC30            0xFE7C  CAPCOM Register 30 
CC31            0xFE7E  CAPCOM Register 31 
ADDAT           0xFEA0  A/D Converter Result Register 
WDT             0xFEAE  Watchdog Timer Register (read only) 
S0TBUF          0xFEB0  Serial Channel 0 Transmit Buffer Reg. (write only)
S0RBUF          0xFEB2  Serial Channel 0 Receive Buffer Reg. (read only)
S0BG            0xFEB4  Serial Channel 0 Baud Rate Generator Reload Register
PECC0           0xFEC0  PEC Channel 0 Control Register 
PECC1           0xFEC2  PEC Channel 1 Control Register 
PECC2           0xFEC4  PEC Channel 2 Control Register 
PECC3           0xFEC6  PEC Channel 3 Control Register 
PECC4           0xFEC8  PEC Channel 4 Control Register 
PECC5           0xFECA  PEC Channel 5 Control Register 
PECC6           0xFECC  PEC Channel 6 Control Register 
PECC7           0xFECE  PEC Channel 7 Control Register 
P0L             0xFF00  Port 0 Low Reg. (Lower half of PORT0) 
P0H             0xFF02  Port 0 High Reg. (Upper half of PORT0) 
P1L             0xFF04  Port 1 Low Reg. (Lower half of PORT1)
P1H             0xFF06  Port 1 High Reg. (Upper half of PORT1) 
BUSCON0         0xFF0C  Bus Configuration Register 0 
MDC             0xFF0E  CPU Multiply Divide Control Register 
PSW             0xFF10  CPU Program Status Word 
SYSCON          0xFF12  CPU System Configuration Register 
BUSCON1         0xFF14  Bus Configuration Register 1 
BUSCON2         0xFF16  Bus Configuration Register 2 
BUSCON3         0xFF18  Bus Configuration Register 3 
BUSCON4         0xFF1A  Bus Configuration Register 4 
ZEROS           0xFF1C  Constant Value 0's Register (read only)
ONES            0xFF1E  Constant Value 1's Register (read only) 
T78CON          0xFF20  CAPCOM Timer 7 and 8 Ctrl. Reg. 
CCM4            0xFF22  CAPCOM Mode Control Register 4 
CCM5            0xFF24  CAPCOM Mode Control Register 5 
CCM6            0xFF26  CAPCOM Mode Control Register 6 
CCM7            0xFF28  CAPCOM Mode Control Register 7 
CTCON           0xFF30  CAPCOM 6 Compare Timer Ctrl. Reg. 
CC6MCON         0xFF32  CAPCOM 6 Mode Control Register 
TRCON           0xFF34  CAPCOM 6 Trap Enable Ctrl. Reg. 
CC6MIC          0xFF36  CAPCOM 6 Mode Interrupt Ctrl. Reg. 
T2CON           0xFF40  GPT1 Timer 2 Control Register
T3CON           0xFF42  GPT1 Timer 3 Control Register 
T4CON           0xFF44  GPT1 Timer 4 Control Register 
T2IC            0xFF60  GPT1 Timer 2 Interrupt Control Register 
T3IC            0xFF62  GPT1 Timer 3 Interrupt Control Register 
T4IC            0xFF64  GPT1 Timer 4 Interrupt Control Register 
S0TIC           0xFF6C  Serial Channel 0 Transmit Interrupt Control Register
S0RIC           0xFF6E  Serial Channel 0 Receive Interrupt Control Register
S0EIC           0xFF70  Serial Channel 0 Error Interrupt Ctrl. Reg.
SSCTIC          0xFF72  SSC Transmit Interrupt Control Register 
SSCRIC          0xFF74  SSC Receive Interrupt Control Register 
SSCEIC          0xFF76  SSC Error Interrupt Control Register 
CC8IC           0xFF88  External Interrupt 0 Control Register 
CC9IC           0xFF8A  External Interrupt 1 Control Register 
ADCIC           0xFF98  Converter End of Conversion Interrupt Control Register
ADEIC           0xFF9A  A/D Converter Overrun Error Interrupt Control Register
ADCON           0xFFA0  A/D Converter Control Register 
P5              0xFFA2  Port 5 Register (read only) 
P5DIDIS         0xFFA4  Port 5 Digital Input Disable Register 
FOCON           0xFFAA  Frequency Output Control Register 
TFR             0xFFAC  Trap Flag Register 
WDTCON          0xFFAE  Watchdog Timer Control Register 
S0CON           0xFFB0  Serial Channel 0 Control Register 
SSCCON          0xFFB2  SSC Control Register 
P20             0xFFB4  Port 20 Register (6 bits) 
DP20            0xFFB6  Port 20 Direction Control Register 
P8              0xFFD4  Port 8 Register (4 bits) 
DP8             0xFFD6  Port 8 Direction Control Register 


.C164CXSX


; MEMORY MAP


; Interrupt and reset vector assignments
entry RESET     0x0000   RESET
entry NMITRAP   0x0008   NMITRAP Non-Maskable Interrupt (Class A Hardware Traps)
entry STOTRAP   0x0010   STOTRAP Stack Overflow (Class A Hardware Traps)
entry STUTRAP   0x0018   STUTRAP Stack Underflow (Class A Hardware Traps)
entry BTRAP     0x0028   BTRAP Class B Hardware Traps
entry CC8INT    0x0060   Fast External Interrupt 0
entry CC9INT    0x0064   Fast External Interrupt 1
entry CC10INT   0x0068   Fast External Interrupt 2
entry CC11INT   0x006C   Fast External Interrupt 3
entry T2INT     0x0088   GPT1 Timer 2 
entry T3INT     0x008C   GPT1 Timer 3 
entry T4INT     0x0090   GPT1 Timer 4 
entry ADCINT    0x00A0   A/D Conversion Complete 
entry ADEINT    0x00A4   A/D Overrun Error 
entry S0TINT    0x00A8   ASC0 Transmit 
entry S0RINT    0x00AC   ASC0 Receive 
entry S0EINT    0x00B0   ASC0 Error 
entry SCTINT    0x00B4   SSC Transmit 
entry SCRINT    0x00B8   SSC Receive 
entry SCEINT    0x00BC   SSC Error 
entry CC16INT   0x00C0   CAPCOM Register 16 
entry CC17INT   0x00C4   CAPCOM Register 17 
entry CC18INT   0x00C8   CAPCOM Register 18 
entry CC19INT   0x00CC   CAPCOM Register 19 
entry CC24INT   0x00E0   CAPCOM Register 24 
entry CC25INT   0x00E4   CAPCOM Register 25 
entry CC26INT   0x00E8   CAPCOM Register 26 
entry CC27INT   0x00EC   CAPCOM Register 27 
entry T7INT     0x00F4   CAPCOM Timer 7 
entry T8INT     0x00F8   CAPCOM Timer 8 
entry PWMINT    0x00FC   PWM Channel 0_3 
entry XP0INT    0x0100   CAN1 
entry XP3INT    0x010C   PLL/OWD 
entry S0TBINT   0x011C   ASC0 Transmit Buffer 
entry T12INT    0x0134   Timer 12 
entry T13INT    0x0138   CAPCOM 6 Timer 13 
entry CC6EINT   0x013C   CAPCOM 6 Emergency 


; INPUT/OUTPUT PORTS
T12P             0xF030 T12P   
T13P             0xF032 T13P   
T12OF            0xF034 T12OF  
CC6MSEL          0xF036 CC6MSEL
T7               0xF050 CAPCOM Timer 7 Register
T8               0xF052 CAPCOM Timer 8 Register
T7REL            0xF054 CAPCOM Timer 7 Reload Register
T8REL            0xF056 CAPCOM Timer 8 Reload Register
IDPROG           0xF078 IDPROG 
IDMEM            0xF07A IDMEM  
IDCHIP           0xF07C IDCHIP 
IDMANUF          0xF07E IDMANUF
POCON0L          0xF080 POCON0L
POCON0H          0xF082 POCON0H
POCON1L          0xF084 POCON1L
POCON1H          0xF086 POCON1H
POCON3           0xF08A POCON3 
POCON4           0xF08C POCON4 
POCON8           0xF092 POCON8 
ADDAT2           0xF0A0 A/D Converter 2 Result Register
POCON20          0xF0AA POCON20
PTCR             0xF0AE PTCR   
SSCTB            0xF0B0 SSC Transmit Buffer
SSCRB            0xF0B2 SSC Receive Buffer
SSCBR            0xF0B4 SSC Baudrate Register
T14REL           0xF0D0 T14REL
T14              0xF0D2 T14   
RTCL             0xF0D4 RTCL
RTCH             0xF0D6 RTCH
DP0L             0xF100 P0L Direction Control Register
DP0H             0xF102 P0H Direction Control Register
DP1L             0xF104 P1L Direction Control Register
DP1H             0xF106 P1H Direction Control Register
RP0H             0xF108 System Startup Configuration Register (read only)
CC16IC           0xF160 CAPCOM Register 16 Interrupt Ctrl. Reg.
CC16IC.CC16IR         7
CC16IC.CC16IE         6
CC17IC           0xF162 CAPCOM Register 17 Interrupt Ctrl. Reg.
CC17IC.CC17IR         7
CC17IC.CC17IE         6
CC18IC           0xF164 CAPCOM Register 18 Interrupt Ctrl. Reg.
CC18IC.CC18IR         7
CC18IC.CC18IE         6
CC19IC           0xF166 CAPCOM Register 19 Interrupt Ctrl. Reg.
CC19IC.CC19IR         7
CC19IC.CC19IE         6
CC20IC           0xF168 CAPCOM Register 20 Interrupt Ctrl. Reg.
CC20IC.CC20IR         7
CC20IC.CC20IE         6
CC21IC           0xF16A CAPCOM Register 21 Interrupt Ctrl. Reg.
CC21IC.CC21IR         7
CC21IC.CC21IE         6
CC22IC           0xF16C CAPCOM Register 22 Interrupt Ctrl. Reg.
CC22IC.CC22IR         7
CC22IC.CC22IE         6
CC23IC           0xF16E CAPCOM Register 23 Interrupt Ctrl. Reg.
CC23IC.CC23IR         7
CC23IC.CC23IE         6
CC24IC           0xF170 CAPCOM Register 24 Interrupt Ctrl. Reg.
CC24IC.CC24IR         7
CC24IC.CC24IE         6
CC25IC           0xF172 CAPCOM Register 25 Interrupt Ctrl. Reg.
CC25IC.CC25IR         7
CC25IC.CC25IE         6
CC26IC           0xF174 CAPCOM Register 26 Interrupt Ctrl. Reg.
CC26IC.CC26IR         7
CC26IC.CC26IE         6
CC27IC           0xF176 CAPCOM Register 27 Interrupt Ctrl. Reg.
CC27IC.CC27IR         7
CC27IC.CC27IE         6
CC28IC           0xF178 CAPCOM Register 28 Interrupt Ctrl. Reg.
CC28IC.CC28IR         7
CC28IC.CC28IE         6
T7IC             0xF17A CAPCOM Timer 7 Interrupt Ctrl. Reg.
T7IC.T7IR             7
T7IC.T7IE             6
T8IC             0xF17C CAPCOM Timer 8 Interrupt Ctrl. Reg.
T8IC.T8IR             7
T8IC.T8IE             6
CC6IC            0xF17E CAPCOM Register 6Interrupt Ctrl. Reg.
CC6IC.CC6IR           7
CC6IC.CC6IE           6
CC29IC           0xF184 CAPCOM Register 29 Interrupt Ctrl. Reg.
CC29IC.CC29IR         7
CC29IC.CC29IE         6
XP0IC            0xF186 CAN1 Interrupt Control Register
CC6EIC           0xF188 CC6EIC
CC6EIC.CC6EIR         7
CC6EIC.CC6EIE         6
CC30IC           0xF18C CAPCOM Register 30 Interrupt Ctrl. Reg.
CC30IC.CC30IR         7
CC30IC.CC30IE         6
XP1IC            0xF18E Unassigned Interrupt Control Register
T12IC            0xF190 T12IC
T12IC.T12IR           7
T12IC.T12IE           6
CC31IC           0xF194 CAPCOM Register 31 Interrupt Ctrl. Reg.
CC31IC.CC31IR         7
CC31IC.CC31IE         6
T13IC            0xF198 T13IC
T13IC.T13IR           7
T13IC.T13IE           6
S0TBIC           0xF19C Serial Channel 0 Transmit Buffer Interrupt Control Register
S0TBIC.S0TBIR         7
S0TBIC.S0TBIE         6
XP3IC            0xF19E PLL/OWD Interrupt Control Register
EXICON           0xF1C0 External Interrupt Control Register
PICON            0xF1C4 Port Input Threshold Control Register
PICON.P8LIN           7
PICON.P4LIN           4
PICON.P3HIN           3
PICON.P3LIN           2
ODP3             0xF1C6 Port 3 Open Drain Control Register
ODP4             0xF1CA ODP4
SYSCON2          0xF1D0 SYSCON2
SYSCON2.CLKLOCK      15
SYSCON2.SCS           7
SYSCON2.RCS           6
SYSCON3          0xF1D4 SYSCON3
SYSCON3.PCDDIS       15
SYSCON3.CAN1DIS      13
SYSCON3.CC6DIS        8
SYSCON3.CC2DIS        7
SYSCON3.PFMDIS        5
SYSCON3.DFMDIS        4
SYSCON3.GPT1DIS       3
SYSCON3.SSCDIS        2
SYSCON3.ASC0DIS       1
SYSCON3.ADCDIS        0
ODP8             0xF1D6 Port 8 Open Drain Control Register
EXISEL           0xF1DA EXISEL
SYSCON1          0xF1DC SYSCON1
ISNC             0xF1DE ISNC
ISNC.PLLIE            3
ISNC.PLLIR            2
ISNC.RTCIE            1
ISNC.RTCIR            0
MDH              0xFE0C CPU Multiply Divide Register - High Word
MDL              0xFE0E CPU Multiply Divide Register - Low Word
SP               0xFE12 CPU System Stack Pointer Register
STKOV            0xFE14 CPU Stack Overflow Pointer Register
STKUN            0xFE16 CPU Stack Underflow Pointer Register
ADDRSEL1         0xFE18 Address Select Register 1
ADDRSEL2         0xFE1A Address Select Register 2
ADDRSEL3         0xFE1C Address Select Register 3
ADDRSEL4         0xFE1E Address Select Register 4
CC60             0xFE30 CC60
CC61             0xFE32 CC61
CC62             0xFE34 CC62
CMP13            0xFE36 CMP13
T2               0xFE40 GPT1 Timer 2 Register
T3               0xFE42 GPT1 Timer 3 Register
T4               0xFE44 GPT1 Timer 4 Register
T5               0xFE46 GPT2 Timer 5 Register
T6               0xFE48 GPT2 Timer 6 Register
CAPREL           0xFE4A GPT2 Capture/Reload Register
CC16             0xFE60 CAPCOM Register 16
CC17             0xFE62 CAPCOM Register 17
CC18             0xFE64 CAPCOM Register 18
CC19             0xFE66 CAPCOM Register 19
CC20             0xFE68 CAPCOM Register 20
CC21             0xFE6A CAPCOM Register 21
CC22             0xFE6C CAPCOM Register 22
CC23             0xFE6E CAPCOM Register 23
CC24             0xFE70 CAPCOM Register 24
CC25             0xFE72 CAPCOM Register 25
CC26             0xFE74 CAPCOM Register 26
CC27             0xFE76 CAPCOM Register 27
CC28             0xFE78 CAPCOM Register 28
CC29             0xFE7A CAPCOM Register 29
CC30             0xFE7C CAPCOM Register 30
CC31             0xFE7E CAPCOM Register 31
ADDAT            0xFEA0 A/D Converter Result Register
WDT              0xFEAE Watchdog Timer Register (read only)
S0TBUF           0xFEB0 Serial Channel 0 Transmit Buffer Register
S0RBUF           0xFEB2 Serial Channel 0 Receive Buffer Register (read only)
S0BG             0xFEB4 Serial Channel 0 Baud Rate Generator Reload Register
PECC0            0xFEC0 PEC Channel 0 Control Register
PECC1            0xFEC2 PEC Channel 1 Control Register
PECC2            0xFEC4 PEC Channel 2 Control Register
PECC3            0xFEC6 PEC Channel 3 Control Register
PECC4            0xFEC8 PEC Channel 4 Control Register
PECC5            0xFECA PEC Channel 5 Control Register
PECC6            0xFECC PEC Channel 6 Control Register
PECC7            0xFECE PEC Channel 7 Control Register
P0L              0xFF00 Port 0 Low Register (Lower half of PORT0)
P0H              0xFF02 Port 0 High Register (Upper half of PORT0)
P1L              0xFF04 Port 1 Low Register (Lower half of PORT1)
P1H              0xFF06 Port 1 High Register (Upper half of PORT1)
BUSCON0          0xFF0C Bus Configuration Register 0
BUSCON0.RDYEN0       12
BUSCON0.BUSACT0      10
BUSCON0.ALECTL0       9
BUSCON0.MTTC0         5
BUSCON0.RWDC0         4
MDC              0xFF0E CPU Multiply Divide Control Register
MDC.MDRIU             4
PSW              0xFF10 CPU Program Status Word
PSW.IEN              11
PSW.HLDEN            10
PSW.USR0              6
PSW.MULIP             5
PSW.E                 4
PSW.Z                 3
PSW.V                 2
PSW.C                 1
PSW.N                 0
SYSCON           0xFF12 CPU System Configuration Register
SYSCON.ROMS1         12
SYSCON.SGTDIS        11
SYSCON.ROMEN         10
SYSCON.BYTDIS         9
SYSCON.CLKEN          8
SYSCON.WRCFG          7
SYSCON.CSSFG          6
SYSCON.OWDDIS         4
SYSCON.BDRSTEN        3
SYSCON.XPEN           2
SYSCON.VISIBLE        1
BUSCON1          0xFF14 Bus Configuration Register 1
BUSCON1.CSWEN1       15
BUSCON1.CSREN1       14
BUSCON1.RDYEN1       12
BUSCON1.BUSACT1      10
BUSCON1.ALECTL1       9
BUSCON1.MTTC1         5
BUSCON1.RWDC1         4
BUSCON2          0xFF16 Bus Configuration Register 2
BUSCON2.CSWEN2       15
BUSCON2.CSREN2       14
BUSCON2.RDYEN2       12
BUSCON2.BUSACT2      10
BUSCON2.ALECTL2       9
BUSCON2.MTTC2         5
BUSCON2.RWDC2         4
BUSCON3          0xFF18 Bus Configuration Register 3
BUSCON3.CSWEN3       15
BUSCON3.CSREN3       14
BUSCON3.RDYEN3       12
BUSCON3.BUSACT3      10
BUSCON3.ALECTL3       9
BUSCON3.MTTC3         5
BUSCON3.RWDC3         4
BUSCON4          0xFF1A Bus Configuration Register 4
BUSCON4.CSWEN4       15
BUSCON4.CSREN4       14
BUSCON4.RDYEN4       12
BUSCON4.BUSACT4      10
BUSCON4.ALECTL4       9
BUSCON4.MTTC4         5
BUSCON4.RWDC4         4
ZEROS            0xFF1C Constant Value 0 s Register (read only)
ONES             0xFF1E Constant Value 1's Register (read only)
T78CON           0xFF20 CAPCOM Timer 7 and 8 Control Register
T78CON.T8R           14
T78CON.T8M           11
T78CON.T7R            6
T78CON.T7M            3
CCM4             0xFF22 CAPCOM Mode Control Register 4
CCM4.ACC19           15
CCM4.ACC18           11
CCM4.ACC17            7
CCM4.ACC16            3
CCM5             0xFF24 CAPCOM Mode Control Register 5
CCM5.ACC23           15
CCM5.ACC22           11
CCM5.ACC21            7
CCM5.ACC20            3
CCM6             0xFF26 CAPCOM Mode Control Register 6
CCM6.ACC27           15
CCM6.ACC26           11
CCM6.ACC25            7
CCM6.ACC24            3
CCM7             0xFF28 CAPCOM Mode Control Register 7
CCM7.ACC31           15
CCM7.ACC30           11
CCM7.ACC29            7
CCM7.ACC28            3
CTCON            0xFF30 CTCON
CTCON.CT13P          15
CTCON.ECT13O         14
CTCON.STE13          13
CTCON.CT13RES        12
CTCON.CT13R          11
CTCON.CTM             7
CTCON.ETRP            6
CTCON.STE12           5
CTCON.CT12RES         4
CTCON.CT12R           3
CC6MCON          0xFF32 CC6MCON
CC6MCON.BCEM         15
CC6MCON.EBCE         12
CC6MCON.BCERR        11
CC6MCON.BCEN         10
CC6MCON.COUT3I        7
CC6MCON.COUTXI        6
CC6MCON.COUT2I        5
CC6MCON.CC2I          4
CC6MCON.COUT1I        3
CC6MCON.CC1I          2
CC6MCON.COUT0I        1
CC6MCON.CC0I          0
TRCON            0xFF34 TRCON
TRCON.TRPEN          15
TRCON.TRF            14
TRCON.TREN5          13
TRCON.TREN4          12
TRCON.TREN3          11
TRCON.TREN2          10
TRCON.TREN1           9
TRCON.TREN0           8
CC6MIC           0xFF36 CC6MIC
CC6MIC.CT12FP        15
CC6MIC.CT12FC        14
CC6MIC.CC2F          13
CC6MIC.CC2R          12
CC6MIC.CC1F          11
CC6MIC.CC1R          10
CC6MIC.CC0F           9
CC6MIC.CC0R           8
CC6MIC.ECTP           7
CC6MIC.ECTC           6
CC6MIC.CC2FEN         5
CC6MIC.CC2REN         4
CC6MIC.CC1FEN         3
CC6MIC.CC1REN         2
CC6MIC.CC0FEN         1
CC6MIC.CC0REN         0
T2CON            0xFF40 GPT1 Timer 2 Control Register
T2CON.T2UDE           8
T2CON.T2UD            7
T2CON.T2R             6
T3CON            0xFF42 GPT1 Timer 3 Control Register
T3CON.T3OTL          10
T3CON.T3OE            9
T3CON.T3UDE           8
T3CON.T3UD            7
T3CON.T3R             6
T4CON            0xFF44 GPT1 Timer 4 Control Register
T4CON.T4UDE           8
T4CON.T4UD            7
T4CON.T4R             6
T5CON            0xFF46 GPT2 Timer 5 Control Register
T5CON.T5SC           15
T5CON.T5CLR          14
T5CON.T5UDE           8
T5CON.T5UD            7
T5CON.T5R             6
T6CON            0xFF48 GPT2 Timer 6 Control Register
T6CON.T6SR           15
T6CON.T6OTL          10
T6CON.T6OE            9
T6CON.T6UDE           8
T6CON.T6UD            7
T6CON.T6R             6
T2IC             0xFF60 GPT1 Timer 2 Interrupt Control Register
T2IC.T2IR             7
T2IC.T2IE             6
T3IC             0xFF62 GPT1 Timer 3 Interrupt Control Register
T3IC.T3IR             7
T3IC.T3IE             6
T4IC             0xFF64 GPT1 Timer 4 Interrupt Control Register
T4IC.T4IR             7
T4IC.T4IE             6
T5IC             0xFF66 GPT2 Timer 5 Interrupt Control Register
T5IC.T5IR             7
T5IC.T5IE             6
T6IC             0xFF68 GPT2 Timer 6 Interrupt Control Register
T6IC.T6IR             7
T6IC.T6IE             6
CRIC             0xFF6A GPT2 CAPREL Interrupt Control Register
CRIC.CRIR             7
CRIC.CRIE             6
S0TIC            0xFF6C Serial Channel 0 Transmit Interrupt Control Register
S0TIC.S0TIR           7
S0TIC.S0TIE           6
S0RIC            0xFF6E Serial Channel 0 Receive Interrupt Control Register
S0RIC.S0RIR           7
S0RIC.S0RIE           6
S0EIC            0xFF70 Serial Channel 0 Error Interrupt Ctrl. Reg.
S0EIC.S0EIR           7
S0EIC.S0EIE           6
SSCTIC           0xFF72 SSC Transmit Interrupt Control Register
SSCTIC.SSCTIR         7
SSCTIC.SSCTIE         6
SSCRIC           0xFF74 SSC Receive Interrupt Control Register
SSCRIC.SSCRIR         7
SSCRIC.SSCRIE         6
SSCEIC           0xFF76 SSC Error Interrupt Control Register
SSCEIC.SSCEIR         7
SSCEIC.SSCEIE         6
CC8IC            0xFF88 CAPCOM Register 8 Interrupt Ctrl. Reg.
CC8IC.CC8IR           7
CC8IC.CC8IE           6
CC9IC            0xFF8A CAPCOM Register 9 Interrupt Ctrl. Reg.
CC9IC.CC9IR           7
CC9IC.CC9IE           6
CC10IC           0xFF8C CAPCOM Register 10 Interrupt Ctrl. Reg.
CC10IC.CC10IR         7
CC10IC.CC10IE         6
CC11IC           0xFF8E CAPCOM Register 11 Interrupt Ctrl. Reg.
CC11IC.CC11IR         7
CC11IC.CC11IE         6
ADCIC            0xFF98 A/D Converter End of Conversion Interrupt Control Register
ADCIC.ADCIR           7
ADCIC.ADCIE           6
ADEIC            0xFF9A A/D Converter Overrun Error Interrupt Control Register
ADEIC.ADEIR           7
ADEIC.ADEIE           6
ADCON            0xFFA0 A/D Converter Control Register
ADCON.ADCRQ          11
ADCON.ADCIN          10
ADCON.ADWR            9
ADCON.ADBSY           8
ADCON.ADST            7
P5               0xFFA2 Port 5 Register (read only)
P5.T2EUD             15
P5.T4EUD             14
P5.T5IN              13
P5.T6IN              12
P5.T5EUD             11
P5.T6EUD             10
P5DIDIS          0xFFA4 Port 5 Digital Input Disable Register
TFR              0xFFAC Trap Flag Register
TFR.NMI              15
TFR.STKOF            14
TFR.STKUF            13
TFR.UNDOPC            7
TFR.PRTFLT            3
TFR.ILLOPA            2
TFR.ILLINA            1
TFR.ILLBUS            0
WDTCON           0xFFAE Watchdog Timer Control Register
WDTCON.WDTPRE         7
WDTCON.LHWR           4
WDTCON.SHWR           3
WDTCON.SWR            2
WDTCON.WDTR           1
WDTCON.WDTIN          0
S0CON            0xFFB0 Serial Channel 0 Control Register
S0CON.S0R            15
S0CON.S0LB           14
S0CON.S0BRS          13
S0CON.S0ODD          12
S0CON.S0OE           10
S0CON.S0FE            9
S0CON.S0PE            8
S0CON.S0OEN           7
S0CON.S0FEN           6
S0CON.S0PEN           5
S0CON.S0REN           4
S0CON.S0STP           3
SSCCON           0xFFB2 SSC Control Register
SSCCON.SSCEN         15
SSCCON.SSCMS         14
SSCCON.SSCBSY        12
SSCCON.SSCBE         11
SSCCON.SSCPE         10
SSCCON.SSCRE          9
SSCCON.SSCTE          8
SSCCON.SSCPO          6
SSCCON.SSCPH          5
SSCCON.SSCHB          4
P3               0xFFC4 Port 3 Register
P3.T3IN               6
P3.T3EUD              4
P3.T3OUT              3
P3.CAPIN              2
P3.T6OUT              1
DP3              0xFFC6 Port 3 Direction Control Register
P4               0xFFC8 Port 4 Register (7 bits)
DP4              0xFFCA Port 4 Direction Control Register
P8               0xFFD4 Port 8 Register (8 bits)
P8.CC23IO             7
P8.CC22IO             6
P8.CC21IO             5
P8.CC20IO             4
DP8              0xFFD6 Port 8 Direction Control Register


.C165
; http://www.infineon.com/cmc_upload/0/000/015/402/c165_ds_v20_2000_12.pdf
; m165.pdf


; C165-LM 3V    (RAM 2 KB)
; C165-L25M     (RAM 2 KB)
; C165-LF 3V    (RAM 2 KB)
; C165L-25F     (RAM 2 KB)
; C165UTAH-LF   (RAM 3 KB)
; C165H-LF      (RAM 3 KB)


; MEMORY MAP
area CODE ROM            0x0000:0x8000   Internal ROM Area
area CODE MEM_EXT        0x8000:0xC000   External Memory
area DATA XRAM_CAN       0xC000:0xF000   XRAM/CAN
area DATA E_SFR          0xF000:0xF200   ESFR Area
area BSS  RESERVED       0xF200:0xF600
area CODE RAM            0xF600:0xFE00   Internal RAM
area DATA SFR            0xFE00:0x10000  SFR Area


; Interrupt and reset vector assignments
entry RESET     0x0000   RESET
entry NMITRAP   0x0008   NMITRAP Non-Maskable Interrupt (Class A Hardware Traps)
entry STOTRAP   0x0010   STOTRAP Stack Overflow (Class A Hardware Traps)
entry STUTRAP   0x0018   STUTRAP Stack Underflow (Class A Hardware Traps)
entry BTRAP     0x0028   BTRAP Class B Hardware Traps
entry CC8INT    0x0060   External Interrupt 0
entry CC9INT    0x0064   External Interrupt 1
entry CC10INT   0x0068   External Interrupt 2
entry CC11INT   0x006C   External Interrupt 3
entry CC12INT   0x0070   External Interrupt 4
entry CC13INT   0x0074   External Interrupt 5
entry CC14INT   0x0078   External Interrupt 6
entry CC15INT   0x007C   External Interrupt 7
entry T2INT     0x0088   GPT1 Timer 2 
entry T3INT     0x008C   GPT1 Timer 3 
entry T4INT     0x0090   GPT1 Timer 4 
entry T5INT     0x0094   GPT2 Timer 5 
entry T6INT     0x0098   GPT2 Timer 6 
entry CRINT     0x009C   GPT2 CAPREL Reg
entry S0TINT    0x00A8   ASC0 Transmit 
entry S0RINT    0x00AC   ASC0 Receive 
entry S0EINT    0x00B0   ASC0 Error 
entry SCTINT    0x00B4   SSC Transmit 
entry SCRINT    0x00B8   SSC Receive 
entry SCEINT    0x00BC   SSC Error 
entry CC16INT   0x00C0   CAPCOM Register 16 
entry XP0INT    0x0100   CAN1 
entry XP1INT    0x0104   Unassigned node 
entry XP2INT    0x0108   Unassigned node 
entry XP3INT    0x010C   PLL/OWD 
entry CC29INT   0x0110   CAPCOM Register 29 
entry CC30INT   0x0114   CAPCOM Register 30 
entry CC31INT   0x0118   CAPCOM Register 31 
entry S0TBINT   0x011C   ASC0 Transmit Buffer 


; INPUT/OUTPUT PORTS
SSCTB            0xF0B0 SSC Transmit Buffer
SSCRB            0xF0B2 SSC Receive Buffer
SSCBR            0xF0B4 SSC Baudrate Register
DP0L             0xF100 P0L Direction Control Register
DP0L.DP0L7        7   Port direction register DP0L bit 7
DP0L.DP0L6        6   Port direction register DP0L bit 6
DP0L.DP0L5        5   Port direction register DP0L bit 5
DP0L.DP0L4        4   Port direction register DP0L bit 4
DP0L.DP0L3        3   Port direction register DP0L bit 3
DP0L.DP0L2        2   Port direction register DP0L bit 2
DP0L.DP0L1        1   Port direction register DP0L bit 1
DP0L.DP0L0        0   Port direction register DP0L bit 0
DP0H             0xF102 P0H Direction Control Register
DP0H.DP0H7        7   Port direction register DP0H bit 7
DP0H.DP0H6        6   Port direction register DP0H bit 6
DP0H.DP0H5        5   Port direction register DP0H bit 5
DP0H.DP0H4        4   Port direction register DP0H bit 4
DP0H.DP0H3        3   Port direction register DP0H bit 3
DP0H.DP0H2        2   Port direction register DP0H bit 2
DP0H.DP0H1        1   Port direction register DP0H bit 1
DP0H.DP0H0        0   Port direction register DP0H bit 0
DP1L             0xF104 P1L Direction Control Register
DP1L.P1L7         7   Port direction register DP1L bit 7
DP1L.P1L6         6   Port direction register DP1L bit 6
DP1L.P1L5         5   Port direction register DP1L bit 5
DP1L.P1L4         4   Port direction register DP1L bit 4
DP1L.P1L3         3   Port direction register DP1L bit 3
DP1L.P1L2         2   Port direction register DP1L bit 2
DP1L.P1L1         1   Port direction register DP1L bit 1
DP1L.P1L0         0   Port direction register DP1L bit 0
DP1H             0xF106 P1H Direction Control Register
DP1H.P1H7         7   Port direction register DP1H bit 7
DP1H.P1H6         6   Port direction register DP1H bit 6
DP1H.P1H5         5   Port direction register DP1H bit 5
DP1H.P1H4         4   Port direction register DP1H bit 4
DP1H.P1H3         3   Port direction register DP1H bit 3
DP1H.P1H2         2   Port direction register DP1H bit 2
DP1H.P1H1         1   Port direction register DP1H bit 1
DP1H.P1H0         0   Port direction register DP1H bit 0
RP0H             0xF108 System Startup Configuration Register (read only)
RP0H.CLKCFG7      7   Clock Generation Mode Configuration 7
RP0H.CLKCFG6      6   Clock Generation Mode Configuration 6
RP0H.CLKCFG5      5   Clock Generation Mode Configuration 5
RP0H.SALSEL4      4   Segment Address Line Selection 4
RP0H.SALSEL3      3   Segment Address Line Selection 3
RP0H.CSSEL2       2   Chip Select Line Selection 2
RP0H.CSSEL1       1   Chip Select Line Selection 1
RP0H.WRC          0   Write Configuration
CC29IC           0xF184 Software Node Interrupt Control Register
XP0IC            0xF186 X-Peripheral 0 Interrupt Control Register
CC30IC           0xF18C Software Node Interrupt Control Register
XP1IC            0xF18E X-Peripheral 1 Interrupt Control Register
XP1IC.XP1IR       7
XP1IC.XP1IE       6
XP1IC.ILVL5       5
XP1IC.ILVL4       4
XP1IC.ILVL3       3
XP1IC.ILVL2       2
XP1IC.GLVL1       1
XP1IC.GLVL0       0
CC31IC           0xF194 Software Node Interrupt Control Register
XP2IC            0xF196 X-Peripheral 2 Interrupt Control Register
S0TBIC           0xF19C Serial Channel 0 Transmit Buffer Interrupt Control Register
S0TBIC.S0TBIR     7
S0TBIC.S0TBIE     6
S0TBIC.ILVL       5
S0TBIC.ILVL       4
S0TBIC.ILVL       3
S0TBIC.ILVL       2
S0TBIC.GLVL       1
S0TBIC.GLVL       0
XP3IC            0xF19E X-Peripheral 3 Interrupt Control Register
EXICON           0xF1C0 External Interrupt Control Register
EXICON.EXI7ES     7   External Interrupt 7 Edge Selection Field
EXICON.EXI6ES     6   External Interrupt 6 Edge Selection Field
EXICON.EXI5ES     5   External Interrupt 5 Edge Selection Field
EXICON.EXI4ES     4   External Interrupt 4 Edge Selection Field
EXICON.EXI3ES     3   External Interrupt 3 Edge Selection Field
EXICON.EXI2ES     2   External Interrupt 2 Edge Selection Field
EXICON.EXI1ES     1   External Interrupt 1 Edge Selection Field
EXICON.EXI0ES     0   External Interrupt 0 Edge Selection Field
ODP2             0xF1C2 Port 2 Open Drain Control Register
ODP2.ODP2_15      15  Port 2 Open Drain control register bit 15
ODP2.ODP2_14      14  Port 2 Open Drain control register bit 14
ODP2.ODP2_13      13  Port 2 Open Drain control register bit 13
ODP2.ODP2_12      12  Port 2 Open Drain control register bit 12
ODP2.ODP2_11      11  Port 2 Open Drain control register bit 11
ODP2.ODP2_10      10  Port 2 Open Drain control register bit 10
ODP2.ODP2_9       9   Port 2 Open Drain control register bit 9 
ODP2.ODP2_8       8   Port 2 Open Drain control register bit 8 
ODP3             0xF1C6 Port 3 Open Drain Control Register
ODP3.ODP3_13      13  Port 3 Open Drain control register bit 13
ODP3.ODP3_11      11  Port 3 Open Drain control register bit 11
ODP3.ODP3_10      10  Port 3 Open Drain control register bit 10
ODP3.ODP3_9       9   Port 3 Open Drain control register bit 9 
ODP3.ODP3_8       8   Port 3 Open Drain control register bit 8 
ODP3.ODP3_7       7   Port 3 Open Drain control register bit 7 
ODP3.ODP3_6       6   Port 3 Open Drain control register bit 6 
ODP3.ODP3_5       5   Port 3 Open Drain control register bit 5 
ODP3.ODP3_4       4   Port 3 Open Drain control register bit 4 
ODP3.ODP3_3       3   Port 3 Open Drain control register bit 3 
ODP3.ODP3_2       2   Port 3 Open Drain control register bit 2 
ODP3.ODP3_1       1   Port 3 Open Drain control register bit 1 
ODP3.ODP3_0       0   Port 3 Open Drain control register bit 0 
ODP6             0xF1CE Port 6 Open Drain Control Register
ODP6.ODP6_7       7   Port 6 Open Drain control register bit 7 
ODP6.ODP6_6       6   Port 6 Open Drain control register bit 6 
ODP6.ODP6_5       5   Port 6 Open Drain control register bit 5 
ODP6.ODP6_4       4   Port 6 Open Drain control register bit 4 
ODP6.ODP6_3       3   Port 6 Open Drain control register bit 3 
ODP6.ODP6_2       2   Port 6 Open Drain control register bit 2 
ODP6.ODP6_1       1   Port 6 Open Drain control register bit 1 
ODP6.ODP6_0       0   Port 6 Open Drain control register bit 0 
DPP0             0xFE00 CPU Data Page Pointer 0 Register (10 bits)
DPP0.DPP0PN9      9   Data Page Number of DPP0 bit 9
DPP0.DPP0PN8      8   Data Page Number of DPP0 bit 8
DPP0.DPP0PN7      7   Data Page Number of DPP0 bit 7
DPP0.DPP0PN6      6   Data Page Number of DPP0 bit 6
DPP0.DPP0PN5      5   Data Page Number of DPP0 bit 5
DPP0.DPP0PN4      4   Data Page Number of DPP0 bit 4
DPP0.DPP0PN3      3   Data Page Number of DPP0 bit 3
DPP0.DPP0PN2      2   Data Page Number of DPP0 bit 2
DPP0.DPP0PN1      1   Data Page Number of DPP0 bit 1
DPP0.DPP0PN0      0   Data Page Number of DPP0 bit 0
DPP1             0xFE02 CPU Data Page Pointer 1 Register (10 bits)
DPP1.DPP1PN9      9   Data Page Number of DPP1 bit 9
DPP1.DPP1PN8      8   Data Page Number of DPP1 bit 8
DPP1.DPP1PN7      7   Data Page Number of DPP1 bit 7
DPP1.DPP1PN6      6   Data Page Number of DPP1 bit 6
DPP1.DPP1PN5      5   Data Page Number of DPP1 bit 5
DPP1.DPP1PN4      4   Data Page Number of DPP1 bit 4
DPP1.DPP1PN3      3   Data Page Number of DPP1 bit 3
DPP1.DPP1PN2      2   Data Page Number of DPP1 bit 2
DPP1.DPP1PN1      1   Data Page Number of DPP1 bit 1
DPP1.DPP1PN0      0   Data Page Number of DPP1 bit 0
DPP2             0xFE04 CPU Data Page Pointer 2 Register (10 bits)
DPP2.DPP2PN9      9   Data Page Number of DPP2 bit 9
DPP2.DPP2PN8      8   Data Page Number of DPP2 bit 8
DPP2.DPP2PN7      7   Data Page Number of DPP2 bit 7
DPP2.DPP2PN6      6   Data Page Number of DPP2 bit 6
DPP2.DPP2PN5      5   Data Page Number of DPP2 bit 5
DPP2.DPP2PN4      4   Data Page Number of DPP2 bit 4
DPP2.DPP2PN3      3   Data Page Number of DPP2 bit 3
DPP2.DPP2PN2      2   Data Page Number of DPP2 bit 2
DPP2.DPP2PN1      1   Data Page Number of DPP2 bit 1
DPP2.DPP2PN0      0   Data Page Number of DPP2 bit 0
DPP3             0xFE06 CPU Data Page Pointer 3 Register (10 bits)
DPP3.DPP3PN9      9   Data Page Number of DPP3 bit 9
DPP3.DPP3PN8      8   Data Page Number of DPP3 bit 8
DPP3.DPP3PN7      7   Data Page Number of DPP3 bit 7
DPP3.DPP3PN6      6   Data Page Number of DPP3 bit 6
DPP3.DPP3PN5      5   Data Page Number of DPP3 bit 5
DPP3.DPP3PN4      4   Data Page Number of DPP3 bit 4
DPP3.DPP3PN3      3   Data Page Number of DPP3 bit 3
DPP3.DPP3PN2      2   Data Page Number of DPP3 bit 2
DPP3.DPP3PN1      1   Data Page Number of DPP3 bit 1
DPP3.DPP3PN0      0   Data Page Number of DPP3 bit 0
CSP              0xFE08 CPU Code Segment Pointer Register (8 bits, not directly writeable)
CSP.SEGNR7        7   Segment Number 7
CSP.SEGNR6        6   Segment Number 6
CSP.SEGNR5        5   Segment Number 5
CSP.SEGNR4        4   Segment Number 4
CSP.SEGNR3        3   Segment Number 3
CSP.SEGNR2        2   Segment Number 2
CSP.SEGNR1        1   Segment Number 1
CSP.SEGNR0        0   Segment Number 0
MDH              0xFE0C CPU Multiply Divide Register - High Word
MDH.MDH15         15
MDH.MDH14         14
MDH.MDH13         13
MDH.MDH12         12
MDH.MDH11         11
MDH.MDH10         10
MDH.MDH9          9
MDH.MDH8          8
MDH.MDH7          7
MDH.MDH6          6
MDH.MDH5          5
MDH.MDH4          4
MDH.MDH3          3
MDH.MDH2          2
MDH.MDH1          1
MDH.MDH0          0
MDL              0xFE0E CPU Multiply Divide Register - Low Word
MDL.MDL15         15
MDL.MDL14         14
MDL.MDL13         13
MDL.MDL12         12
MDL.MDL11         11
MDL.MDL10         10
MDL.MDL9          9
MDL.MDL8          8
MDL.MDL7          7
MDL.MDL6          6
MDL.MDL5          5
MDL.MDL4          4
MDL.MDL3          3
MDL.MDL2          2
MDL.MDL1          1
MDL.MDL0          0
CP               0xFE10 CPU Context Pointer Register
SP               0xFE12 CPU System Stack Pointer Register
SP.SP11           11  Modifiable portion of register CP bit 11
SP.SP10           10  Modifiable portion of register CP bit 10
SP.SP9            9   Modifiable portion of register CP bit 9 
SP.SP8            8   Modifiable portion of register CP bit 8 
SP.SP7            7   Modifiable portion of register CP bit 7 
SP.SP6            6   Modifiable portion of register CP bit 6 
SP.SP5            5   Modifiable portion of register CP bit 5 
SP.SP4            4   Modifiable portion of register CP bit 4 
SP.SP3            3   Modifiable portion of register CP bit 3 
SP.SP2            2   Modifiable portion of register CP bit 2 
SP.SP1            1   Modifiable portion of register CP bit 1 
STKOV            0xFE14 CPU Stack Overflow Pointer Register
STKOV.STKOV11     11  Modifiable portion of register STKOV bit 11
STKOV.STKOV10     10  Modifiable portion of register STKOV bit 10
STKOV.STKOV9      9   Modifiable portion of register STKOV bit 9 
STKOV.STKOV8      8   Modifiable portion of register STKOV bit 8 
STKOV.STKOV7      7   Modifiable portion of register STKOV bit 7 
STKOV.STKOV6      6   Modifiable portion of register STKOV bit 6 
STKOV.STKOV5      5   Modifiable portion of register STKOV bit 5 
STKOV.STKOV4      4   Modifiable portion of register STKOV bit 4 
STKOV.STKOV3      3   Modifiable portion of register STKOV bit 3 
STKOV.STKOV2      2   Modifiable portion of register STKOV bit 2 
STKOV.STKOV1      1   Modifiable portion of register STKOV bit 1 
STKUN            0xFE16 CPU Stack Underflow Pointer Register
STKUN.STKUN11     11  Modifiable portion of register STKUN bit 11
STKUN.STKUN10     10  Modifiable portion of register STKUN bit 10
STKUN.STKUN9      9   Modifiable portion of register STKUN bit 9 
STKUN.STKUN8      8   Modifiable portion of register STKUN bit 8 
STKUN.STKUN7      7   Modifiable portion of register STKUN bit 7 
STKUN.STKUN6      6   Modifiable portion of register STKUN bit 6 
STKUN.STKUN5      5   Modifiable portion of register STKUN bit 5 
STKUN.STKUN4      4   Modifiable portion of register STKUN bit 4 
STKUN.STKUN3      3   Modifiable portion of register STKUN bit 3 
STKUN.STKUN2      2   Modifiable portion of register STKUN bit 2 
STKUN.STKUN1      1   Modifiable portion of register STKUN bit 1 
ADDRSEL1         0xFE18 Address Select Register 1
ADDRSEL1.RGSAD15  15  Range Start Address bit 15
ADDRSEL1.RGSAD14  14  Range Start Address bit 14
ADDRSEL1.RGSAD13  13  Range Start Address bit 13
ADDRSEL1.RGSAD12  12  Range Start Address bit 12
ADDRSEL1.RGSAD11  11  Range Start Address bit 11
ADDRSEL1.RGSAD10  10  Range Start Address bit 10
ADDRSEL1.RGSAD9   9   Range Start Address bit 9
ADDRSEL1.RGSAD8   8   Range Start Address bit 8
ADDRSEL1.RGSAD7   7   Range Start Address bit 7
ADDRSEL1.RGSAD6   6   Range Start Address bit 6
ADDRSEL1.RGSAD5   5   Range Start Address bit 5
ADDRSEL1.RGSAD4   4   Range Start Address bit 4
ADDRSEL1.RGSZ3    3   Range Size Selection bit 3
ADDRSEL1.RGSZ2    2   Range Size Selection bit 2
ADDRSEL1.RGSZ1    1   Range Size Selection bit 1
ADDRSEL1.RGSZ0    0   Range Size Selection bit 0
ADDRSEL2         0xFE1A Address Select Register 2
ADDRSEL2.RGSAD15  15  Range Start Address bit 15
ADDRSEL2.RGSAD14  14  Range Start Address bit 14
ADDRSEL2.RGSAD13  13  Range Start Address bit 13
ADDRSEL2.RGSAD12  12  Range Start Address bit 12
ADDRSEL2.RGSAD11  11  Range Start Address bit 11
ADDRSEL2.RGSAD10  10  Range Start Address bit 10
ADDRSEL2.RGSAD9   9   Range Start Address bit 9 
ADDRSEL2.RGSAD8   8   Range Start Address bit 8 
ADDRSEL2.RGSAD7   7   Range Start Address bit 7 
ADDRSEL2.RGSAD6   6   Range Start Address bit 6 
ADDRSEL2.RGSAD5   5   Range Start Address bit 5 
ADDRSEL2.RGSAD4   4   Range Start Address bit 4 
ADDRSEL2.RGSZ3    3   Range Size Selection bit 3
ADDRSEL2.RGSZ2    2   Range Size Selection bit 2
ADDRSEL2.RGSZ1    1   Range Size Selection bit 1
ADDRSEL2.RGSZ0    0   Range Size Selection bit 0     
ADDRSEL3         0xFE1C Address Select Register 3
ADDRSEL3.RGSAD15  15  Range Start Address bit 15
ADDRSEL3.RGSAD14  14  Range Start Address bit 14
ADDRSEL3.RGSAD13  13  Range Start Address bit 13
ADDRSEL3.RGSAD12  12  Range Start Address bit 12
ADDRSEL3.RGSAD11  11  Range Start Address bit 11
ADDRSEL3.RGSAD10  10  Range Start Address bit 10
ADDRSEL3.RGSAD9   9   Range Start Address bit 9 
ADDRSEL3.RGSAD8   8   Range Start Address bit 8 
ADDRSEL3.RGSAD7   7   Range Start Address bit 7 
ADDRSEL3.RGSAD6   6   Range Start Address bit 6 
ADDRSEL3.RGSAD5   5   Range Start Address bit 5 
ADDRSEL3.RGSAD4   4   Range Start Address bit 4 
ADDRSEL3.RGSZ3    3   Range Size Selection bit 3
ADDRSEL3.RGSZ2    2   Range Size Selection bit 2
ADDRSEL3.RGSZ1    1   Range Size Selection bit 1
ADDRSEL3.RGSZ0    0   Range Size Selection bit 0     
ADDRSEL4         0xFE1E Address Select Register 4
ADDRSEL4.RGSAD15  15  Range Start Address bit 15
ADDRSEL4.RGSAD14  14  Range Start Address bit 14
ADDRSEL4.RGSAD13  13  Range Start Address bit 13
ADDRSEL4.RGSAD12  12  Range Start Address bit 12
ADDRSEL4.RGSAD11  11  Range Start Address bit 11
ADDRSEL4.RGSAD10  10  Range Start Address bit 10
ADDRSEL4.RGSAD9   9   Range Start Address bit 9 
ADDRSEL4.RGSAD8   8   Range Start Address bit 8 
ADDRSEL4.RGSAD7   7   Range Start Address bit 7 
ADDRSEL4.RGSAD6   6   Range Start Address bit 6 
ADDRSEL4.RGSAD5   5   Range Start Address bit 5 
ADDRSEL4.RGSAD4   4   Range Start Address bit 4 
ADDRSEL4.RGSZ3    3   Range Size Selection bit 3
ADDRSEL4.RGSZ2    2   Range Size Selection bit 2
ADDRSEL4.RGSZ1    1   Range Size Selection bit 1
ADDRSEL4.RGSZ0    0   Range Size Selection bit 0     
T2               0xFE40 GPT1 Timer 2 Register
T3               0xFE42 GPT1 Timer 3 Register
T4               0xFE44 GPT1 Timer 4 Register
T5               0xFE46 GPT2 Timer 5 Register
T6               0xFE48 GPT2 Timer 6 Register
CAPREL           0xFE4A GPT2 Capture/Reload Register
WDT              0xFEAE Watchdog Timer Register (read only)
S0TBUF           0xFEB0 Serial Channel 0 Transmit Buffer Register
S0RBUF           0xFEB2 Serial Channel 0 Receive Buffer Register (read only)
S0BG             0xFEB4 Serial Channel 0 Baud Rate Generator Reload Register
PECC0            0xFEC0 PEC Channel 0 Control Register
PECC0.INC10       10  Increment Control bit 10
PECC0.INC9        9   Increment Control bit 9
PECC0.BWT         8   Byte / Word Transfer Selection
PECC0.COUNT7      7   PEC Transfer Count bit 7
PECC0.COUNT6      6   PEC Transfer Count bit 6
PECC0.COUNT5      5   PEC Transfer Count bit 5
PECC0.COUNT4      4   PEC Transfer Count bit 4
PECC0.COUNT3      3   PEC Transfer Count bit 3
PECC0.COUNT2      2   PEC Transfer Count bit 2
PECC0.COUNT1      1   PEC Transfer Count bit 1
PECC0.COUNT0      0   PEC Transfer Count bit 0
PECC1            0xFEC2 PEC Channel 1 Control Register
PECC1.INC10       10  Increment Control bit 10      
PECC1.INC9        9   Increment Control bit 9       
PECC1.BWT         8   Byte / Word Transfer Selection
PECC1.COUNT7      7   PEC Transfer Count bit 7      
PECC1.COUNT6      6   PEC Transfer Count bit 6      
PECC1.COUNT5      5   PEC Transfer Count bit 5      
PECC1.COUNT4      4   PEC Transfer Count bit 4      
PECC1.COUNT3      3   PEC Transfer Count bit 3      
PECC1.COUNT2      2   PEC Transfer Count bit 2      
PECC1.COUNT1      1   PEC Transfer Count bit 1      
PECC1.COUNT0      0   PEC Transfer Count bit 0      
PECC2            0xFEC4 PEC Channel 2 Control Register
PECC2.INC10       10  Increment Control bit 10      
PECC2.INC9        9   Increment Control bit 9       
PECC2.BWT         8   Byte / Word Transfer Selection
PECC2.COUNT7      7   PEC Transfer Count bit 7      
PECC2.COUNT6      6   PEC Transfer Count bit 6      
PECC2.COUNT5      5   PEC Transfer Count bit 5      
PECC2.COUNT4      4   PEC Transfer Count bit 4      
PECC2.COUNT3      3   PEC Transfer Count bit 3      
PECC2.COUNT2      2   PEC Transfer Count bit 2      
PECC2.COUNT1      1   PEC Transfer Count bit 1      
PECC2.COUNT0      0   PEC Transfer Count bit 0      
PECC3            0xFEC6 PEC Channel 3 Control Register
PECC3.INC10       10  Increment Control bit 10      
PECC3.INC9        9   Increment Control bit 9       
PECC3.BWT         8   Byte / Word Transfer Selection
PECC3.COUNT7      7   PEC Transfer Count bit 7      
PECC3.COUNT6      6   PEC Transfer Count bit 6      
PECC3.COUNT5      5   PEC Transfer Count bit 5      
PECC3.COUNT4      4   PEC Transfer Count bit 4      
PECC3.COUNT3      3   PEC Transfer Count bit 3      
PECC3.COUNT2      2   PEC Transfer Count bit 2      
PECC3.COUNT1      1   PEC Transfer Count bit 1      
PECC3.COUNT0      0   PEC Transfer Count bit 0      
PECC4            0xFEC8 PEC Channel 4 Control Register
PECC4.INC10       10  Increment Control bit 10      
PECC4.INC9        9   Increment Control bit 9       
PECC4.BWT         8   Byte / Word Transfer Selection
PECC4.COUNT7      7   PEC Transfer Count bit 7      
PECC4.COUNT6      6   PEC Transfer Count bit 6      
PECC4.COUNT5      5   PEC Transfer Count bit 5      
PECC4.COUNT4      4   PEC Transfer Count bit 4      
PECC4.COUNT3      3   PEC Transfer Count bit 3      
PECC4.COUNT2      2   PEC Transfer Count bit 2      
PECC4.COUNT1      1   PEC Transfer Count bit 1      
PECC4.COUNT0      0   PEC Transfer Count bit 0      
PECC5            0xFECA PEC Channel 5 Control Register
PECC5.INC10       10  Increment Control bit 10      
PECC5.INC9        9   Increment Control bit 9       
PECC5.BWT         8   Byte / Word Transfer Selection
PECC5.COUNT7      7   PEC Transfer Count bit 7      
PECC5.COUNT6      6   PEC Transfer Count bit 6      
PECC5.COUNT5      5   PEC Transfer Count bit 5      
PECC5.COUNT4      4   PEC Transfer Count bit 4      
PECC5.COUNT3      3   PEC Transfer Count bit 3      
PECC5.COUNT2      2   PEC Transfer Count bit 2      
PECC5.COUNT1      1   PEC Transfer Count bit 1      
PECC5.COUNT0      0   PEC Transfer Count bit 0      
PECC6            0xFECC PEC Channel 6 Control Register
PECC6.INC10       10  Increment Control bit 10      
PECC6.INC9        9   Increment Control bit 9       
PECC6.BWT         8   Byte / Word Transfer Selection
PECC6.COUNT7      7   PEC Transfer Count bit 7      
PECC6.COUNT6      6   PEC Transfer Count bit 6      
PECC6.COUNT5      5   PEC Transfer Count bit 5      
PECC6.COUNT4      4   PEC Transfer Count bit 4      
PECC6.COUNT3      3   PEC Transfer Count bit 3      
PECC6.COUNT2      2   PEC Transfer Count bit 2      
PECC6.COUNT1      1   PEC Transfer Count bit 1      
PECC6.COUNT0      0   PEC Transfer Count bit 0      
PECC7            0xFECE PEC Channel 7 Control Register
PECC7.INC10       10  Increment Control bit 10      
PECC7.INC9        9   Increment Control bit 9       
PECC7.BWT         8   Byte / Word Transfer Selection
PECC7.COUNT7      7   PEC Transfer Count bit 7      
PECC7.COUNT6      6   PEC Transfer Count bit 6      
PECC7.COUNT5      5   PEC Transfer Count bit 5      
PECC7.COUNT4      4   PEC Transfer Count bit 4      
PECC7.COUNT3      3   PEC Transfer Count bit 3      
PECC7.COUNT2      2   PEC Transfer Count bit 2      
PECC7.COUNT1      1   PEC Transfer Count bit 1      
PECC7.COUNT0      0   PEC Transfer Count bit 0      
P0L              0xFF00 Port 0 Low Register (Lower half of PORT0)
P0L.P0L7          7   Port data register P0L bit 7
P0L.P0L6          6   Port data register P0L bit 6
P0L.P0L5          5   Port data register P0L bit 5
P0L.P0L4          4   Port data register P0L bit 4
P0L.P0L3          3   Port data register P0L bit 3
P0L.P0L2          2   Port data register P0L bit 2
P0L.P0L1          1   Port data register P0L bit 1
P0L.P0L0          0   Port data register P0L bit 0
P0H              0xFF02 Port 0 High Register (Upper half of PORT0)
P0H.P0H7          7   Port data register P0H bit 7
P0H.P0H6          6   Port data register P0H bit 6
P0H.P0H5          5   Port data register P0H bit 5
P0H.P0H4          4   Port data register P0H bit 4
P0H.P0H3          3   Port data register P0H bit 3
P0H.P0H2          2   Port data register P0H bit 2
P0H.P0H1          1   Port data register P0H bit 1
P0H.P0H0          0   Port data register P0H bit 0
P1L              0xFF04 Port 1 Low Register (Lower half of PORT1)
P1L.P1L_7         7   Port data register P1L bit 7
P1L.P1L_6         6   Port data register P1L bit 6
P1L.P1L_5         5   Port data register P1L bit 5
P1L.P1L_4         4   Port data register P1L bit 4
P1L.P1L_3         3   Port data register P1L bit 3
P1L.P1L_2         2   Port data register P1L bit 2
P1L.P1L_1         1   Port data register P1L bit 1
P1L.P1L_0         0   Port data register P1L bit 0
P1H              0xFF06 Port 1 High Register (Upper half of PORT1)
P1H.P1H_7         7   Port data register P1H bit 7
P1H.P1H_6         6   Port data register P1H bit 6
P1H.P1H_5         5   Port data register P1H bit 5
P1H.P1H_4         4   Port data register P1H bit 4
P1H.P1H_3         3   Port data register P1H bit 3
P1H.P1H_2         2   Port data register P1H bit 2
P1H.P1H_1         1   Port data register P1H bit 1
P1H.P1H_0         0   Port data register P1H bit 0
BUSCON0          0xFF0C Bus Configuration Register 0
BUSCON0.CSWEN0    15  Write Chip Select Enable
BUSCON0.CSREN0    14  Read Chip Select Enable
BUSCON0.RDYEN0    12  READY Input Enable
BUSCON0.BUSACT0   10  Bus Active Control
BUSCON0.ALECTL0   9   ALE Lengthening Control
BUSCON0.BTYP1     7   External Bus Configuration bit 1
BUSCON0.BTYP0     6   External Bus Configuration bit 0
BUSCON0.MTTC0     5   Memory Tristate Time Control
BUSCON0.RWDC0     4   Read/Write Delay Control for BUSCON0
BUSCON0.MCTC3     3   Memory Cycle Time Control bit 3
BUSCON0.MCTC2     2   Memory Cycle Time Control bit 2
BUSCON0.MCTC1     1   Memory Cycle Time Control bit 1
BUSCON0.MCTC0     0   Memory Cycle Time Control bit 0    
MDC              0xFF0E CPU Multiply Divide Control Register
MDC.MDRIU         4   Multiply/Divide Register In Use
PSW              0xFF10 CPU Program Status Word
PSW.ILVL15        15  ILVL15 - Interrupt and EBC Control Fields
PSW.ILVL14        14  ILVL14 - Interrupt and EBC Control Fields
PSW.ILVL13        13  ILVL13 - Interrupt and EBC Control Fields
PSW.ILVL12        12  ILVL12 - Interrupt and EBC Control Fields
PSW.IEN           11  IEN - Interrupt and EBC Control Fields
PSW.HLDEN         10  HLDEN - Interrupt and EBC Control Fields
PSW.USR0          6   User General Purpose Flag
PSW.MULIP         5   Multiplication/Division In Progress
PSW.E             4   End of Table Flag
PSW.Z             3   Zero Flag
PSW.V             2   Overflow Result
PSW.C             1   Carry Flag
PSW.N             0   Negative Result
SYSCON           0xFF12 CPU System Configuration Register
SYSCON.STKSZ2     15  System Stack Size 2
SYSCON.STKSZ1     14  System Stack Size 1
SYSCON.STKSZ0     13  System Stack Size 0
SYSCON.ROMS1      12  Internal ROM Mapping
SYSCON.SGTEN      11  Segmentation Disable/Enable Control
SYSCON.ROMEN      10  Internal ROM Enable
SYSCON.BYTDIS     9   Disable/Enable Control for Pin BHE
SYSCON.CLKEN      8   System Clock Output Enable (CLKOUT)
SYSCON.WRCFG      7   Write Configuration Control
SYSCON.XPEN       2   XBUS Peripheral Enable Bit
SYSCON.VISIBLE    1   Visible Mode Control
SYSCON.XPERSHARE  0   XBUS Peripheral Share Mode Control
BUSCON1          0xFF14 Bus Configuration Register 1
BUSCON1.CSWEN1    15  Write Chip Select Enable            
BUSCON1.CSREN1    14  Read Chip Select Enable             
BUSCON1.RDYEN1    12  READY Input Enable                  
BUSCON1.BUSACT1   10  Bus Active Control                  
BUSCON1.ALECTL1   9   ALE Lengthening Control             
BUSCON1.BTYP1     7   External Bus Configuration bit 1    
BUSCON1.BTYP0     6   External Bus Configuration bit 0    
BUSCON1.MTTC1     5   Memory Tristate Time Control        
BUSCON1.RWDC1     4   Read/Write Delay Control for BUSCON0
BUSCON1.MCTC3     3   Memory Cycle Time Control bit 3     
BUSCON1.MCTC2     2   Memory Cycle Time Control bit 2     
BUSCON1.MCTC1     1   Memory Cycle Time Control bit 1     
BUSCON1.MCTC0     0   Memory Cycle Time Control bit 0     
BUSCON2          0xFF16 Bus Configuration Register 2
BUSCON2.CSWEN2    15  Write Chip Select Enable            
BUSCON2.CSREN2    14  Read Chip Select Enable             
BUSCON2.RDYEN2    12  READY Input Enable                  
BUSCON2.BUSACT2   10  Bus Active Control                  
BUSCON2.ALECTL2   9   ALE Lengthening Control             
BUSCON2.BTYP1     7   External Bus Configuration bit 1    
BUSCON2.BTYP0     6   External Bus Configuration bit 0    
BUSCON2.MTTC2     5   Memory Tristate Time Control        
BUSCON2.RWDC2     4   Read/Write Delay Control for BUSCON0
BUSCON2.MCTC3     3   Memory Cycle Time Control bit 3     
BUSCON2.MCTC2     2   Memory Cycle Time Control bit 2     
BUSCON2.MCTC1     1   Memory Cycle Time Control bit 1     
BUSCON2.MCTC0     0   Memory Cycle Time Control bit 0     
BUSCON3          0xFF18 Bus Configuration Register 3
BUSCON3.CSWEN3    15  Write Chip Select Enable            
BUSCON3.CSREN3    14  Read Chip Select Enable             
BUSCON3.RDYEN3    12  READY Input Enable                  
BUSCON3.BUSACT3   10  Bus Active Control                  
BUSCON3.ALECTL3   9   ALE Lengthening Control             
BUSCON3.BTYP1     7   External Bus Configuration bit 1    
BUSCON3.BTYP0     6   External Bus Configuration bit 0    
BUSCON3.MTTC3     5   Memory Tristate Time Control        
BUSCON3.RWDC3     4   Read/Write Delay Control for BUSCON0
BUSCON3.MCTC3     3   Memory Cycle Time Control bit 3     
BUSCON3.MCTC2     2   Memory Cycle Time Control bit 2     
BUSCON3.MCTC1     1   Memory Cycle Time Control bit 1     
BUSCON3.MCTC0     0   Memory Cycle Time Control bit 0     
BUSCON4          0xFF1A Bus Configuration Register 4
BUSCON4.CSWEN4    15  Write Chip Select Enable            
BUSCON4.CSREN4    14  Read Chip Select Enable             
BUSCON4.RDYEN4    12  READY Input Enable                  
BUSCON4.BUSACT4   10  Bus Active Control                  
BUSCON4.ALECTL4   9   ALE Lengthening Control             
BUSCON4.BTYP1     7   External Bus Configuration bit 1    
BUSCON4.BTYP0     6   External Bus Configuration bit 0    
BUSCON4.MTTC4     5   Memory Tristate Time Control        
BUSCON4.RWDC4     4   Read/Write Delay Control for BUSCON0
BUSCON4.MCTC3     3   Memory Cycle Time Control bit 3     
BUSCON4.MCTC2     2   Memory Cycle Time Control bit 2     
BUSCON4.MCTC1     1   Memory Cycle Time Control bit 1     
BUSCON4.MCTC0     0   Memory Cycle Time Control bit 0     
ZEROS            0xFF1C Constant Value 0's Register (read only)
ONES             0xFF1E Constant Value 1's Register (read only)
T2CON            0xFF40 GPT1 Timer 2 Control Register
T2CON.T2UDE       8   Timer 2 External Up/Down Enable
T2CON.T2UD        7   Timer 2 Up / Down Control
T2CON.T2R         6   Timer 2 Run Bit
T2CON.T2M5        5   Timer 2 Mode Control bit 5
T2CON.T2M4        4   Timer 2 Mode Control bit 4
T2CON.T2M3        3   Timer 2 Mode Control bit 3
T2CON.T2I2        2   Timer 2 Input Selection bit 2
T2CON.T2I1        1   Timer 2 Input Selection bit 1
T2CON.T2I0        0   Timer 2 Input Selection bit 0
T3CON            0xFF42 GPT1 Timer 3 Control Register
T3CON.T3OTL       10  Timer 3 Output Toggle Latch
T3CON.T3OE        9   Alternate Output Function Enable
T3CON.T3UDE       8   Timer 3 External Up/Down Enable
T3CON.T3UD        7   Timer 3 Up / Down Control
T3CON.T3R         6   Timer 3 Run Bit
T3CON.T3M2        5   Timer 3 Mode Control bit 2
T3CON.T3M1        4   Timer 3 Mode Control bit 1
T3CON.T3M0        3   Timer 3 Mode Control bit 0
T3CON.T3I2        2   Timer 3 Input Selection bit 2
T3CON.T3I1        1   Timer 3 Input Selection bit 1
T3CON.T3I0        0   Timer 3 Input Selection bit 0
T4CON            0xFF44 GPT1 Timer 4 Control Register
T4CON.T4UDE       8   Timer 4 External Up/Down Enable
T4CON.T4UD        7   Timer 4 Up / Down Control
T4CON.T4R         6   Timer 4 Run Bit
T4CON.T4M5        5   Timer 4 Mode Control bit 5
T4CON.T4M4        4   Timer 4 Mode Control bit 4
T4CON.T4M3        3   Timer 4 Mode Control bit 3
T4CON.T4I2        2   Timer 4 Input Selection bit 2
T4CON.T4I1        1   Timer 4 Input Selection bit 1
T4CON.T4I0        0   Timer 4 Input Selection bit 0
T5CON            0xFF46 GPT2 Timer 5 Control Register
T5CON.T5SC        15  Timer 5 Capture Mode Enable
T5CON.T5CLR       14  Timer 5 Clear Bit
T5CON.T5UDE       8   Timer 5 External Up/Down Enable
T5CON.T5UD        7   Timer 5 Up / Down Control
T5CON.T5R         6   Timer 5 Run Bit
T5CON.T5M4        4   Timer 5 Mode Control bit 4
T5CON.T5M3        3   Timer 5 Mode Control bit 3
T5CON.T5I2        2   Timer 5 Input Selection bit 2
T5CON.T5I1        1   Timer 5 Input Selection bit 1
T5CON.T5I0        0   Timer 5 Input Selection bit 0
T6CON            0xFF48 GPT2 Timer 6 Control Register
T6CON.T6SR        15  Timer 6 Reload Mode Enable
T6CON.T6OTL       10  Timer 6 Output Toggle Latch
T6CON.T6OE        9   Alternate Output Function Enable
T6CON.T6UDE       8   Timer 6 External Up/Down Enable
T6CON.T6UD        7   Timer 6 Up / Down Control
T6CON.T6R         6   Timer 6 Run Bit
T6CON.T6M2        5   Timer 6 Mode Control bit 2
T6CON.T6M1        4   Timer 6 Mode Control bit 1
T6CON.T6M0        3   Timer 6 Mode Control bit 0
T6CON.T6I2        2   Timer 6 Input Selection bit 2
T6CON.T6I1        1   Timer 6 Input Selection bit 1
T6CON.T6I0        0   Timer 6 Input Selection bit 0
T2IC             0xFF60 GPT1 Timer 2 Interrupt Control Register
T2IC.T2IR         7
T2IC.T2IE         6
T2IC.ILVL3        5
T2IC.ILVL2        4
T2IC.ILVL1        3
T2IC.ILVL0        2
T2IC.GLVL1        1
T2IC.GLVL0        0
T3IC             0xFF62 GPT1 Timer 3 Interrupt Control Register
T3IC.T3IR         7
T3IC.T3IE         6
T3IC.ILVL3        5
T3IC.ILVL2        4
T3IC.ILVL1        3
T3IC.ILVL0        2
T3IC.GLVL1        1
T3IC.GLVL0        0
T4IC             0xFF64 GPT1 Timer 4 Interrupt Control Register
T4IC.T4IR         7
T4IC.T4IE         6
T4IC.ILVL3        5
T4IC.ILVL2        4
T4IC.ILVL1        3
T4IC.ILVL0        2
T4IC.GLVL1        1
T4IC.GLVL0        0
T5IC             0xFF66 GPT2 Timer 5 Interrupt Control Register
T5IC.T5IR         7
T5IC.T5IE         6
T5IC.ILVL5        5
T5IC.ILVL4        4
T5IC.ILVL3        3
T5IC.ILVL2        2
T5IC.GLVL1        1
T5IC.GLVL0        0
T6IC             0xFF68 GPT2 Timer 6 Interrupt Control Register
T6IC.T6IR         7
T6IC.T6IE         6
T6IC.ILVL5        5
T6IC.ILVL4        4
T6IC.ILVL3        3
T6IC.ILVL2        2
T6IC.GLVL1        1
T6IC.GLVL0        0
CRIC             0xFF6A GPT2 CAPREL Interrupt Control Register
CRIC.CRIR         7
CRIC.CRIE         6
CRIC.ILVL5        5
CRIC.ILVL4        4
CRIC.ILVL3        3
CRIC.ILVL2        2
CRIC.GLVL1        1
CRIC.GLVL0        0
S0TIC            0xFF6C Serial Channel 0 Transmit Interrupt Control Register
S0TIC.S0TIR       7
S0TIC.S0TIE       6
S0TIC.ILVL5       5
S0TIC.ILVL4       4
S0TIC.ILVL3       3
S0TIC.ILVL2       2
S0TIC.GLVL1       1
S0TIC.GLVL0       0
S0RIC            0xFF6E Serial Channel 0 Receive Interrupt Control Register
S0RIC.S0RIR       7
S0RIC.S0RIE       6
S0RIC.ILVL5       5
S0RIC.ILVL4       4
S0RIC.ILVL3       3
S0RIC.ILVL2       2
S0RIC.GLVL1       1
S0RIC.GLVL0       0
S0EIC            0xFF70 Serial Channel 0 Error Interrupt Ctrl. Reg.
S0EIC.S0EIR       7
S0EIC.S0EIE       6
S0EIC.ILVL5       5
S0EIC.ILVL4       4
S0EIC.ILVL3       3
S0EIC.ILVL2       2
S0EIC.GLVL1       1
S0EIC.GLVL0       0
SSCTIC           0xFF72 SSC Transmit Interrupt Control Register
SSCTIC.SSCTIR     7
SSCTIC.SSCTIE     6
SSCTIC.ILVL5      5
SSCTIC.ILVL4      4
SSCTIC.ILVL3      3
SSCTIC.ILVL2      2
SSCTIC.GLVL1      1
SSCTIC.GLVL0      0
SSCRIC           0xFF74 SSC Receive Interrupt Control Register
SSCRIC.SSCRIR     7
SSCRIC.SSCRIE     6
SSCRIC.ILVL5      5
SSCRIC.ILVL4      4
SSCRIC.ILVL3      3
SSCRIC.ILVL2      2
SSCRIC.GLVL1      1
SSCRIC.GLVL0      0
SSCEIC           0xFF76 SSC Error Interrupt Control Register
SSCEIC.SSCEIR     7
SSCEIC.SSCEIE     6
SSCEIC.ILVL5      5
SSCEIC.ILVL4      4
SSCEIC.ILVL3      3
SSCEIC.ILVL2      2
SSCEIC.GLVL1      1
SSCEIC.GLVL0      0
CC8IC            0xFF88 External Interrupt 0 Control Register
CC9IC            0xFF8A External Interrupt 1 Control Register
CC10IC           0xFF8C External Interrupt 2 Control Register
CC11IC           0xFF8E External Interrupt 3 Control Register
CC12IC           0xFF90 External Interrupt 4 Control Register
CC13IC           0xFF92 External Interrupt 5 Control Register
CC14IC           0xFF94 External Interrupt 6 Control Register
CC15IC           0xFF96 External Interrupt 7 Control Register
P5               0xFFA2 Port 5 Register (read only)
P5.P5_15          15  Port data register P5 bit 15
P5.P5_14          14  Port data register P5 bit 14
P5.P5_13          13  Port data register P5 bit 13
P5.P5_12          12  Port data register P5 bit 12
P5.P5_11          11  Port data register P5 bit 11
P5.P5_10          10  Port data register P5 bit 10
TFR              0xFFAC Trap Flag Register
TFR.NMI           15  Non Maskable Interrupt Flag
TFR.STKOF         14  Stack Overflow Flag
TFR.STKUF         13  Stack Underflow Flag
TFR.UNDOPC        7   Undefined Opcode Flag
TFR.PRTFLT        3   Protection Fault Flag
TFR.ILLOPA        2   Illegal Word Operand Access Flag
TFR.ILLINA        1   Illegal Instruction Access Flag
TFR.ILLBUS        0   Illegal External Bus Access Flag
WDTCON           0xFFAE Watchdog Timer Control Register
WDTCON.WDTREL15   15 Watchdog Timer Reload Value bit 15
WDTCON.WDTREL14   14 Watchdog Timer Reload Value bit 14
WDTCON.WDTREL13   13 Watchdog Timer Reload Value bit 13
WDTCON.WDTREL12   12 Watchdog Timer Reload Value bit 12
WDTCON.WDTREL11   11 Watchdog Timer Reload Value bit 11
WDTCON.WDTREL10   10 Watchdog Timer Reload Value bit 10
WDTCON.WDTREL9    9  Watchdog Timer Reload Value bit 9 
WDTCON.WDTREL8    8  Watchdog Timer Reload Value bit 8 
WDTCON.WDTR       1  Watchdog Timer Reset Indication Flag
WDTCON.WDTIN      0  Watchdog Timer Input Frequency Selection
S0CON            0xFFB0 Serial Channel 0 Control Register
S0CON.S0R         15 Baudrate Generator Run Bit
S0CON.S0LB        14 LoopBack Mode Enable Bit
S0CON.S0BRS       13 Baudrate Selection Bit
S0CON.S0ODD       12 Parity Selection Bit
S0CON.S0OE        10 Overrun Error Flag
S0CON.S0FE        9  Framing Error Flag
S0CON.S0PE        8  Parity Error Flag
S0CON.S0OEN       7  Overrun Check Enable Bit
S0CON.S0FEN       6  Framing Check Enable Bit
S0CON.S0PEN       5  Parity Check Enable Bit
S0CON.S0REN       4  Receiver Enable Bit
S0CON.S0STP       3  Number of Stop Bits Selection
S0CON.S0M2        2  ASC0 Mode Control bit 2
S0CON.S0M1        1  ASC0 Mode Control bit 1
S0CON.S0M0        0  ASC0 Mode Control bit 0
SSCCON           0xFFB2 SSC Control Register
P2               0xFFC0 Port 2 Register
P2.P2_15          15  Port data register P2 bit 15
P2.P2_14          14  Port data register P2 bit 14
P2.P2_13          13  Port data register P2 bit 13
P2.P2_12          12  Port data register P2 bit 12
P2.P2_11          11  Port data register P2 bit 11
P2.P2_10          10  Port data register P2 bit 10
P2.P2_9           9   Port data register P2 bit 9 
P2.P2_8           8   Port data register P2 bit 8 
DP2              0xFFC2 Port 2 Direction Control Register
DP2.DP2_15        15  Port 2 Open Drain control register bit 15
DP2.DP2_14        14  Port 2 Open Drain control register bit 14
DP2.DP2_13        13  Port 2 Open Drain control register bit 13
DP2.DP2_12        12  Port 2 Open Drain control register bit 12
DP2.DP2_11        11  Port 2 Open Drain control register bit 11
DP2.DP2_10        10  Port 2 Open Drain control register bit 10
DP2.DP2_9         9   Port 2 Open Drain control register bit 9 
DP2.DP2_8         8   Port 2 Open Drain control register bit 8 
P3               0xFFC4 Port 3 Register
P3.P3_15          15  Port data register P3 bit 15
P3.P3_13          13  Port data register P3 bit 13
P3.P3_12          12  Port data register P3 bit 12
P3.P3_11          11  Port data register P3 bit 11
P3.P3_10          10  Port data register P3 bit 10
P3.P3_9           9   Port data register P3 bit 9 
P3.P3_8           8   Port data register P3 bit 8 
P3.P3_7           7   Port data register P3 bit 7 
P3.P3_6           6   Port data register P3 bit 6 
P3.P3_5           5   Port data register P3 bit 5 
P3.P3_4           4   Port data register P3 bit 4 
P3.P3_3           3   Port data register P3 bit 3 
P3.P3_2           2   Port data register P3 bit 2 
P3.P3_1           1   Port data register P3 bit 1 
DP3              0xFFC6 Port 3 Direction Control Register
DP3.DP3_15        15  Port direction register DP3 bit 15
DP3.DP3_13        13  Port direction register DP3 bit 13
DP3.DP3_12        12  Port direction register DP3 bit 12
DP3.DP3_11        11  Port direction register DP3 bit 11
DP3.DP3_10        10  Port direction register DP3 bit 10
DP3.DP3_9         9   Port direction register DP3 bit 9 
DP3.DP3_8         8   Port direction register DP3 bit 8 
DP3.DP3_7         7   Port direction register DP3 bit 7 
DP3.DP3_6         6   Port direction register DP3 bit 6 
DP3.DP3_5         5   Port direction register DP3 bit 5 
DP3.DP3_4         4   Port direction register DP3 bit 4 
DP3.DP3_3         3   Port direction register DP3 bit 3 
DP3.DP3_2         2   Port direction register DP3 bit 2 
DP3.DP3_1         1   Port direction register DP3 bit 1 
P4               0xFFC8 Port 4 Register (7 bits)
P4.P4_7           7   Port data register P4 bit 7 
P4.P4_6           6   Port data register P4 bit 6 
P4.P4_5           5   Port data register P4 bit 5 
P4.P4_4           4   Port data register P4 bit 4 
P4.P4_3           3   Port data register P4 bit 3 
P4.P4_2           2   Port data register P4 bit 2 
P4.P4_1           1   Port data register P4 bit 1 
P4.P4_0           0   Port data register P4 bit 0 
DP4              0xFFCA Port 4 Direction Control Register
DP4.DP4_7         7   Port direction register DP4 bit 7 
DP4.DP4_6         6   Port direction register DP4 bit 6 
DP4.DP4_5         5   Port direction register DP4 bit 5 
DP4.DP4_4         4   Port direction register DP4 bit 4 
DP4.DP4_3         3   Port direction register DP4 bit 3 
DP4.DP4_2         2   Port direction register DP4 bit 2 
DP4.DP4_1         1   Port direction register DP4 bit 1 
DP4.DP4_0         0   Port direction register DP4 bit 0 
P6               0xFFCC Port 6 Register (8 bits)
P6.P6_7           7   Port data register P6 bit 7
P6.P6_6           6   Port data register P6 bit 6
P6.P6_5           5   Port data register P6 bit 5
P6.P6_4           4   Port data register P6 bit 4
P6.P6_3           3   Port data register P6 bit 3
P6.P6_2           2   Port data register P6 bit 2
P6.P6_1           1   Port data register P6 bit 1
P6.P6_0           0   Port data register P6 bit 0
DP6              0xFFCE Port 6 Direction Control Register
DP6.DP6_7         7   Port direction register DP6 bit 7 
DP6.DP6_6         6   Port direction register DP6 bit 6 
DP6.DP6_5         5   Port direction register DP6 bit 5 
DP6.DP6_4         4   Port direction register DP6 bit 4 
DP6.DP6_3         3   Port direction register DP6 bit 3 
DP6.DP6_2         2   Port direction register DP6 bit 2 
DP6.DP6_1         1   Port direction register DP6 bit 1 
DP6.DP6_0         0   Port direction register DP6 bit 0 


.C165_H
; http://www.infineon.com/cgi/ecrm.dll/ecrm/scripts/public_download.jsp?oid=22594&parent_oid=13619


; MEMORY MAP
area DATA INT_PROG_MEM   0x0000:0x8000   Internal Program Memory Area
area BSS  RESERVED       0x8000:0xA000   Reserved for XFLASH
area BSS  RESERVED       0xA000:0xE000   Reserved for XRAM
area BSS  RESERVED       0xE000:0xE800   Reserved for Compatible XRAM
area BSS  RESERVED       0xE800:0xEF00   Reserved for XPERs
area DATA IOM-2          0xEF00:0xF000
area DATA E_SFR          0xF000:0xF200   ESFR Area
area DATA IRAM           0xF200:0xFE00   IRAM Area
area DATA SFR            0xFE00:0x10000  SFR Area 


; Interrupt and reset vector assignments
entry RESET     0x0000   RESET
entry NMITRAP   0x0008   NMITRAP Non-Maskable Interrupt (Class A Hardware Traps)
entry STOTRAP   0x0010   STOTRAP Stack Overflow (Class A Hardware Traps)
entry STUTRAP   0x0018   STUTRAP Stack Underflow (Class A Hardware Traps)
entry DEBTRAP   0x0020   Debug Trap
entry BTRAP     0x0028   BTRAP Class B Hardware Traps
entry URD3IE    0x0040   UDC RX Done3
entry URD4IE    0x0044   UDC RX Done4
entry URD5IE    0x0048   UDC RX Done5
entry URD6IE    0x004C   UDC RX Done6
entry URD7IE    0x0050   UDC RX Done7
entry UTD0IE    0x0054   UDC TX Done0
entry UTD1IE    0x0058   UDC TX Done1
entry UTD2IE    0x005C   UDC TX Done2
entry EX0IE     0x0060   Fast ext. Interrupt
entry EX1IE     0x0064   Fast ext. Interrupt
entry EX2IE     0x0068   Fast ext. Interrupt
entry EX3IE     0x006C   Fast ext. Interrupt
entry EX4IE     0x0070   Fast ext. Interrupt
entry EX5IE     0x0074   Fast ext. Interrupt
entry EX6IE     0x0078   Fast ext. Interrupt
entry EX7IE     0x007C   Fast ext. Interrupt
entry URD2IE    0x0080   UDC RX Done2
entry URD1IE    0x0084   UDC RX Done1
entry T2IE      0x0088   GPT Timer 2
entry T3IE      0x008C   GPT Timer 3
entry T4IE      0x0090   GPT Timer 4
entry T5IE      0x0094   GPT Timer 5
entry T6IE      0x0098   GPT Timer 6
entry CRIE      0x009C   GPT CAPREL Register
entry IOMIOIE   0x00A4   IOM-2 I/O
entry S0TIE     0x00A8   ASC Transmit
entry S0RIE     0x00AC   ASC Receive
entry S0EIE     0x00B0   ASC Error
entry SSCTIE    0x00B4   SSC Transmit
entry SSCRIE    0x00B8   SSC Receive
entry SSCEIE    0x00BC   SSC Error
entry UTD3IE    0x00C0   UDC TX Done3
entry UTD4IE    0x00C4   UDC TX Done4
entry UTD5IE    0x00C8   UDC TX Done5
entry UTD6IE    0x00CC   UDC TX Done6
entry UTD7IE    0x00D0   UDC TX Done7
entry URXRIE    0x00D4   UDC RXRR
entry UTXRIE    0x00D8   UDC TXWR
entry UCFGVIE   0x00DC   UDC Config Val
entry USOFIE    0x00E0   UDC Start of Frame
entry USSOIE    0x00E4   UDC Suspend off
entry USSIE     0x00E8   UDC Suspend
entry ULCDIE    0x00EC   UDC Load Config Done
entry USETIE    0x00F0   UDC SETUP
entry URD0IE    0x00F4   UDC RX Done0
entry IOMC0TIE  0x00FC   IOM-2 Channel0 TX
entry UTXRIE    0x0100   UDC TXWR
entry IOMIOIE   0x0108   IOM-2 IO
entry XP3IE     0x010C   Internal PLL Lock / RTC
entry RTCIE     0x0110   rRTC Interrupt
entry ABENDIE   0x0114   ASC Autobaud End
entry ABSTIE    0x0118   ASC Autobaud Start
entry S0TBIE    0x011C   ASC Transmit Buffer
entry IOMC0RIE  0x0120   IOM-2 Channel0 RX
entry IOMC1TIE  0x0124   IOM-2 Channel1 TX
entry IOMC1RIE  0x0128   IOM-2 Channel1 RX
entry CLISNIE   0x0130   CLISN Interrupt


; INPUT/OUTPUT PORTS

; IOM-2 Registers
IOMCLC                 0xEF00   IOM-2 Clock Control Register
IOMCLC.IOMEX_DIS        3   IOM-2 Controller Clock Disable
IOMCLC.IOMGPSEN         2   IOM-2 Controller Clock OCDS Disable
IOMCLC.IOMDIS           1   IOM-2 Controller Clock Status
IOMCLC.IOMDISR          0   IOM-2 Controller Clock Disable
reserv_EF02            0xEF02   RESERVED
reserv_EF04            0xEF04   RESERVED
reserv_EF06            0xEF06   RESERVED
IOMID                  0xEF08   IOM-2 Identification Register
IOMID.ID_15             15  IOM-2 Identification Register - bit 15
IOMID.ID_14             14  IOM-2 Identification Register - bit 14
IOMID.ID_13             13  IOM-2 Identification Register - bit 13
IOMID.ID_12             12  IOM-2 Identification Register - bit 12
IOMID.ID_11             11  IOM-2 Identification Register - bit 11
IOMID.ID_10             10  IOM-2 Identification Register - bit 10
IOMID.ID_9              9   IOM-2 Identification Register - bit 9 
IOMID.ID_8              8   IOM-2 Identification Register - bit 8 
IOMID.ID_7              7   IOM-2 Identification Register - bit 7 
IOMID.ID_6              6   IOM-2 Identification Register - bit 6 
IOMID.ID_5              5   IOM-2 Identification Register - bit 5 
IOMID.ID_4              4   IOM-2 Identification Register - bit 4 
IOMID.ID_3              3   IOM-2 Identification Register - bit 3 
IOMID.ID_2              2   IOM-2 Identification Register - bit 2 
IOMID.ID_1              1   IOM-2 Identification Register - bit 1 
IOMID.ID_0              0   IOM-2 Identification Register - bit 0 
reserv_EF0A            0xEF0A   RESERVED
reserv_EF0C            0xEF0C   RESERVED
reserv_EF0E            0xEF0E   RESERVED
CDA_10                 0xEF10   Controller Data Access Register 10
CDA_10.CDA_10_7         7    H Data register which can be accessed from the CPU - bit 7
CDA_10.CDA_10_6         6    H Data register which can be accessed from the CPU - bit 6
CDA_10.CDA_10_5         5    H Data register which can be accessed from the CPU - bit 5
CDA_10.CDA_10_4         4    H Data register which can be accessed from the CPU - bit 4
CDA_10.CDA_10_3         3    H Data register which can be accessed from the CPU - bit 3
CDA_10.CDA_10_2         2    H Data register which can be accessed from the CPU - bit 2
CDA_10.CDA_10_1         1    H Data register which can be accessed from the CPU - bit 1
CDA_10.CDA_10_0         0    H Data register which can be accessed from the CPU - bit 0
CDA_11                 0xEF12   Controller Data Access Register 11
CDA_11.CDA_11_7         7    H Data register which can be accessed from the CPU - bit 7
CDA_11.CDA_11_6         6    H Data register which can be accessed from the CPU - bit 6
CDA_11.CDA_11_5         5    H Data register which can be accessed from the CPU - bit 5
CDA_11.CDA_11_4         4    H Data register which can be accessed from the CPU - bit 4
CDA_11.CDA_11_3         3    H Data register which can be accessed from the CPU - bit 3
CDA_11.CDA_11_2         2    H Data register which can be accessed from the CPU - bit 2
CDA_11.CDA_11_1         1    H Data register which can be accessed from the CPU - bit 1
CDA_11.CDA_11_0         0    H Data register which can be accessed from the CPU - bit 0
CDA_20                 0xEF14   Controller Data Access Register 21
CDA_20.CDA_20_7         7    H Data register which can be accessed from the CPU - bit 7
CDA_20.CDA_20_6         6    H Data register which can be accessed from the CPU - bit 6
CDA_20.CDA_20_5         5    H Data register which can be accessed from the CPU - bit 5
CDA_20.CDA_20_4         4    H Data register which can be accessed from the CPU - bit 4
CDA_20.CDA_20_3         3    H Data register which can be accessed from the CPU - bit 3
CDA_20.CDA_20_2         2    H Data register which can be accessed from the CPU - bit 2
CDA_20.CDA_20_1         1    H Data register which can be accessed from the CPU - bit 1
CDA_20.CDA_20_0         0    H Data register which can be accessed from the CPU - bit 0
CDA_21                 0xEF16   Controller Data Access Register 22
CDA_21.CDA_21_7         7    H Data register which can be accessed from the CPU - bit 7
CDA_21.CDA_21_6         6    H Data register which can be accessed from the CPU - bit 6
CDA_21.CDA_21_5         5    H Data register which can be accessed from the CPU - bit 5
CDA_21.CDA_21_4         4    H Data register which can be accessed from the CPU - bit 4
CDA_21.CDA_21_3         3    H Data register which can be accessed from the CPU - bit 3
CDA_21.CDA_21_2         2    H Data register which can be accessed from the CPU - bit 2
CDA_21.CDA_21_1         1    H Data register which can be accessed from the CPU - bit 1
CDA_21.CDA_21_0         0    H Data register which can be accessed from the CPU - bit 0
CDA_TSDP10             0xEF18   Time Slot and Data Port Selection for CDA 10
CDA_TSDP10.DPS          15  Data Port Selection
CDA_TSDP10.TSS_4        4   Time Slot Selection - bit 4
CDA_TSDP10.TSS_3        3   Time Slot Selection - bit 3
CDA_TSDP10.TSS_2        2   Time Slot Selection - bit 2
CDA_TSDP10.TSS_1        1   Time Slot Selection - bit 1
CDA_TSDP10.TSS_0        0   Time Slot Selection - bit 0
CDA_TSDP11             0xEF1A   Time Slot and Data Port Selection for CDA 11
CDA_TSDP11.DPS          15  Data Port Selection
CDA_TSDP11.TSS_4        4   Time Slot Selection - bit 4
CDA_TSDP11.TSS_3        3   Time Slot Selection - bit 3
CDA_TSDP11.TSS_2        2   Time Slot Selection - bit 2
CDA_TSDP11.TSS_1        1   Time Slot Selection - bit 1
CDA_TSDP11.TSS_0        0   Time Slot Selection - bit 0
CDA_TSDP20             0xEF1C   Time Slot and Data Port Selection for CDA 20
CDA_TSDP20.DPS          15  Data Port Selection
CDA_TSDP20.TSS_4        4   Time Slot Selection - bit 4
CDA_TSDP20.TSS_3        3   Time Slot Selection - bit 3
CDA_TSDP20.TSS_2        2   Time Slot Selection - bit 2
CDA_TSDP20.TSS_1        1   Time Slot Selection - bit 1
CDA_TSDP20.TSS_0        0   Time Slot Selection - bit 0
CDA_TSDP21             0xEF1E   Time Slot and Data Port Selection for CDA 21
CDA_TSDP21.DPS          15  Data Port Selection
CDA_TSDP21.TSS_4        4   Time Slot Selection - bit 4
CDA_TSDP21.TSS_3        3   Time Slot Selection - bit 3
CDA_TSDP21.TSS_2        2   Time Slot Selection - bit 2
CDA_TSDP21.TSS_1        1   Time Slot Selection - bit 1
CDA_TSDP21.TSS_0        0   Time Slot Selection - bit 0
B1_TSDP                0xEF20   Time Slot and Data Port Selection for B1
B1_TSDP.DPS             15  Data Port Selection
B1_TSDP.TSS_4           4   Time Slot Selection - bit 4
B1_TSDP.TSS_3           3   Time Slot Selection - bit 3
B1_TSDP.TSS_2           2   Time Slot Selection - bit 2
B1_TSDP.TSS_1           1   Time Slot Selection - bit 1
B1_TSDP.TSS_0           0   Time Slot Selection - bit 0
B2_TSDP                0xEF22   Time Slot and Data Port Selection for B2
B2_TSDP.DPS             15  Data Port Selection
B2_TSDP.TSS_4           4   Time Slot Selection - bit 4
B2_TSDP.TSS_3           3   Time Slot Selection - bit 3
B2_TSDP.TSS_2           2   Time Slot Selection - bit 2
B2_TSDP.TSS_1           1   Time Slot Selection - bit 1
B2_TSDP.TSS_0           0   Time Slot Selection - bit 0
D1_TSDP                0xEF24   Time Slot and Data Port Selection for D1
D1_TSDP.DPS             15  Data Port Selection        
D1_TSDP.TSS_4           4   Time Slot Selection - bit 4
D1_TSDP.TSS_3           3   Time Slot Selection - bit 3
D1_TSDP.TSS_2           2   Time Slot Selection - bit 2
D1_TSDP.TSS_1           1   Time Slot Selection - bit 1
D1_TSDP.TSS_0           0   Time Slot Selection - bit 0
D2_TSDP                0xEF26   Time Slot and Data Port Selection for D2
D2_TSDP.DPS             15  Data Port Selection        
D2_TSDP.TSS_4           4   Time Slot Selection - bit 4
D2_TSDP.TSS_3           3   Time Slot Selection - bit 3
D2_TSDP.TSS_2           2   Time Slot Selection - bit 2
D2_TSDP.TSS_1           1   Time Slot Selection - bit 1
D2_TSDP.TSS_0           0   Time Slot Selection - bit 0
reserv_EF28            0xEF28   RESERVED
reserv_EF2A            0xEF2A   RESERVED
reserv_EF2C            0xEF2C   RESERVED
reserv_EF2E            0xEF2E   RESERVED
ISTA                   0xEF30   Interrupt Status Register
ISTA.RPF3               15  Receive Pool Full for HDLC channel 3
ISTA.RPF2               14  Receive Pool Full for HDLC channel 2
ISTA.RPF1               13  Receive Pool Full for HDLC channel 1
ISTA.RPF0               12  Receive Pool Full for HDLC channel 0
ISTA.XPR3               11  Transmit Pool Ready for HDLC channel 3
ISTA.XPR2               10  Transmit Pool Ready for HDLC channel 2
ISTA.XPR1               9   Transmit Pool Ready for HDLC channel 1
ISTA.XPR0               8   Transmit Pool Ready for HDLC channel 0
ISTA.DCSI               7   Clock STATUS Interrupt
ISTA.ST                 6   Synchronous Transfer
ISTA.CIC                5   Channel Change
ISTA.MOS                4   Monitor Status
ISTA.HDLC3              3   HDLC Channel Interrupts - bit 3
ISTA.HDLC2              2   HDLC Channel Interrupts - bit 2
ISTA.HDLC1              1   HDLC Channel Interrupts - bit 1
ISTA.HDLC0              0   HDLC Channel Interrupts - bit 0
MASK                   0xEF32   Interrupt Mask Register
MASK.RPF3               15  Receive Pool Full for HDLC channel 3
MASK.RPF2               14  Receive Pool Full for HDLC channel 2
MASK.RPF1               13  Receive Pool Full for HDLC channel 1
MASK.RPF0               12  Receive Pool Full for HDLC channel 0
MASK.XPR3               11  Transmit Pool Ready for HDLC channel 3
MASK.XPR2               10  Transmit Pool Ready for HDLC channel 2
MASK.XPR1               9   Transmit Pool Ready for HDLC channel 1
MASK.XPR0               8   Transmit Pool Ready for HDLC channel 0
MASK.DCSI               7   Clock STATUS Interrupt
MASK.ST                 6   Synchronous Transfer
MASK.CIC                5   Channel Change
MASK.MOS                4   Monitor Status
MASK.HDLC3              3   HDLC Channel Interrupts - bit 3
MASK.HDLC2              2   HDLC Channel Interrupts - bit 2
MASK.HDLC1              1   HDLC Channel Interrupts - bit 1
MASK.HDLC0              0   HDLC Channel Interrupts - bit 0
CDA1_CR                0xEF34   Control Register for CDA Channel 1
CDA1_CR.EN_I1           4   Enable Input CDA11
CDA1_CR.EN_I0           3   Enable Input CDA10
CDA1_CR.EN_O1           2   Enable Output CDA11
CDA1_CR.EN_O0           1   Enable Output CDA10
CDA1_CR.SWAP            0   Swap Inputs
CDA2_CR                0xEF36   Control Register for CDA Channel 2
CDA2_CR.EN_I1           4   Enable Input CDA21
CDA2_CR.EN_I0           3   Enable Input CDA20
CDA2_CR.EN_O1           2   Enable Output CDA21
CDA2_CR.EN_O0           1   Enable Output CDA20
CDA2_CR.SWAP            0   Swap Inputs
CIC_CR                 0xEF38   Control Register for Control/Indication Channel
CIC_CR.DPS_CI1          15  Data Port Selection CI1 Data
CIC_CR.EN_CI1           14  Enable CI1 Data
CIC_CR.DPS_CI0          7   Data Port Selection CI0 Data
CIC_CR.EN_CI0           6   Enable CI0 Data
MON_CR                 0xEF3A   Control Register for Monitor Channel
MON_CR.EN_MON           15  Enable Output
MON_CR.DPS              7   Data Port Selection
MON_CR.MCS_2            2   Monitor Channel Selection - bit 2
MON_CR.MCS_1            1   Monitor Channel Selection - bit 1
MON_CR.MCS_0            0   Monitor Channel Selection - bit 0
IOM_CR                 0xEF3C   Control Register for IOM Interface
IOM_CR.SPU              3   Software Power UP
IOM_CR.DIS_OD           2   Open_Drain
IOM_CR.CLKM             1   Clock Mode
IOM_CR.DIS_IOM          0   Disable IOM
reserv_EF3E            0xEF3E   RESERVED
STI                    0xEF40   Synchronous Transfer Interrupt
STI.STOV21              7   Synchronous Transfer Overflow Interrupt
STI.STOV20              6   Synchronous Transfer Overflow Interrupt
STI.STOV11              5   Synchronous Transfer Overflow Interrupt
STI.STOV10              4   Synchronous Transfer Overflow Interrupt
STI.STI21               3   Synchronous Transfer Interrupt
STI.STI20               2   Synchronous Transfer Interrupt
STI.STI11               1   Synchronous Transfer Interrupt
STI.STI10               0   Synchronous Transfer Interrupt
MSTI                   0xEF42   Mask Synchronous Transfer Interrupt
MSTI.STOV21             7   Synchronous Transfer Overflow for STI 21
MSTI.STOV20             6   Synchronous Transfer Overflow for STI 20
MSTI.STOV11             5   Synchronous Transfer Overflow for STI 11
MSTI.STOV10             4   Synchronous Transfer Overflow for STI 10
MSTI.STI21              3   Synchronous Transfer Interrupt 21
MSTI.STI20              2   Synchronous Transfer Interrupt 20
MSTI.STI11              1   Synchronous Transfer Interrupt 11
MSTI.STI10              0   Synchronous Transfer Interrupt 10
ASTI                   0xEF44   Acknowledge Synchronous Transfer Interrupt
ASTI.ACK21              3   Acknowledge Synchronous Transfer Interrupt
ASTI.ACK20              2   Acknowledge Synchronous Transfer Interrupt
ASTI.ACK11              1   Acknowledge Synchronous Transfer Interrupt
ASTI.ACK10              0   Acknowledge Synchronous Transfer Interrupt
reserv_EF46            0xEF46   RESERVED
reserv_EF48            0xEF48   RESERVED
reserv_EF4A            0xEF4A   RESERVED
reserv_EF4C            0xEF4C   RESERVED
reserv_EF4E            0xEF4E   RESERVED
MOR                    0xEF50   Monitor Receive Channel
MOR.MOR_7               7   MONITOR Data Received - bit 7
MOR.MOR_6               6   MONITOR Data Received - bit 6
MOR.MOR_5               5   MONITOR Data Received - bit 5
MOR.MOR_4               4   MONITOR Data Received - bit 4
MOR.MOR_3               3   MONITOR Data Received - bit 3
MOR.MOR_2               2   MONITOR Data Received - bit 2
MOR.MOR_1               1   MONITOR Data Received - bit 1
MOR.MOR_0               0   MONITOR Data Received - bit 0
MOX                    0xEF52   Monitor Transmit Channel
MOX.MOX_7               7   MONITOR Data Transmitted - bit 7
MOX.MOX_6               6   MONITOR Data Transmitted - bit 6
MOX.MOX_5               5   MONITOR Data Transmitted - bit 5
MOX.MOX_4               4   MONITOR Data Transmitted - bit 4
MOX.MOX_3               3   MONITOR Data Transmitted - bit 3
MOX.MOX_2               2   MONITOR Data Transmitted - bit 2
MOX.MOX_1               1   MONITOR Data Transmitted - bit 1
MOX.MOX_0               0   MONITOR Data Transmitted - bit 0
MOCR                   0xEF54   Monitor Control Register
MOCR.MRE                3   MONITOR Receive Interrupt Enable
MOCR.MRC                2   MR Bit Control
MOCR.MIE                1   MONITOR Interrupt Enable
MOCR.MXC                0   MX Bit Control
MSTA                   0xEF56   Monitor Status Register
MSTA.MAC                15  MONITOR Transmit Channel Active
MOSR                   0xEF58   Monitor Interrupt Status Register
MOSR.MDR                3   MONITOR channel Data Received
MOSR.MER                2   MONITOR channel End of Reception
MOSR.MDA                1   MONITOR Channel Data Acknowledge
MOSR.MAB                0   MONITOR Channel Data Abort
MCDA                   0xEF5A   MCDA - Monitoring CDA Bits
MCDA.MCDA21_7           7    Monitoring CDA21 Bit
MCDA.MCDA21_6           6    Monitoring CDA21 Bit
MCDA.MCDA20_5           5    Monitoring CDA20 Bit
MCDA.MCDA20_4           4    Monitoring CDA20 Bit
MCDA.MCDA11_3           3    Monitoring CDA11 Bit
MCDA.MCDA11_2           2    Monitoring CDA11 Bit
MCDA.MCDA10_1           1    Monitoring CDA10 Bit
MCDA.MCDA10_0           0    Monitoring CDA10 Bit
reserv_EF5C            0xEF5C   RESERVED
reserv_EF5E            0xEF5E   RESERVED
CIC0_D                 0xEF60   Command/Indication Channel 0 Data
CIC0_D.CODR0_11         11  C/I Code 0 Receive - bit 11
CIC0_D.CODR0_10         10  C/I Code 0 Receive - bit 10
CIC0_D.CODR0_9          9   C/I Code 0 Receive - bit 9 
CIC0_D.CODR0_8          8   C/I Code 0 Receive - bit 8 
CIC0_D.CODX0_3          3   C/I-Code 0 Transmit - bit 3
CIC0_D.CODX0_2          2   C/I-Code 0 Transmit - bit 2
CIC0_D.CODX0_1          1   C/I-Code 0 Transmit - bit 1
CIC0_D.CODX0_0          0   C/I-Code 0 Transmit - bit 0
CIC1_D                 0xEF62   Command/Indication Channel 1 Data
CIC1_D.CODR1_13         13  C/I-Code 1 Receive - bit 13
CIC1_D.CODR1_12         12  C/I-Code 1 Receive - bit 12
CIC1_D.CODR1_11         11  C/I-Code 1 Receive - bit 11
CIC1_D.CODR1_10         10  C/I-Code 1 Receive - bit 10
CIC1_D.CODR1_9          9   C/I-Code 1 Receive - bit 9 
CIC1_D.CODR1_8          8   C/I-Code 1 Receive - bit 8 
CIC1_D.CODX1_5          5   C/I-Code 1 Transmit - bit 5
CIC1_D.CODX1_4          4   C/I-Code 1 Transmit - bit 4
CIC1_D.CODX1_3          3   C/I-Code 1 Transmit - bit 3
CIC1_D.CODX1_2          2   C/I-Code 1 Transmit - bit 2
CIC1_D.CODX1_1          1   C/I-Code 1 Transmit - bit 1
CIC1_D.CODX1_0          0   C/I-Code 1 Transmit - bit 0
CIC_CMD                0xEF64   Command/Indication Channel Command Register
CIC_CMD.EXCERPT_10      10  Digital Interface Modes - bit 10
CIC_CMD.EXCERPT_9       9   Digital Interface Modes - bit 9 
CIC_CMD.EXCERPT_8       8   Digital Interface Modes - bit 8 
CIC_CMD.TIC_DIS         6   TIC Bus Disable
CIC_CMD.CI1E            5   C/I-channel 1 interrupt enable
CIC_CMD.CICW            4   W 1 C/I-Channel Width
CIC_CMD.BAC             3   W 0 Bus Access Control
CIC_CMD.TBA_2           2   TIC Bus Addres - bit 2
CIC_CMD.TBA_1           1   TIC Bus Addres - bit 1
CIC_CMD.TBA_0           0   TIC Bus Addres - bit 0
CIC_ST                 0xEF66   Command/Indication Channel Status Register
CIC_ST.CIC0             15  C/I Code 0 Change
CIC_ST.CIC1             14  C/I Code 1 Change
CIC_ST.S_G              13  Stop/Go Bit Monitoring
CIC_ST.BAS              12  Bus Access Status
CIC_ST.DCOD             7   DCL Clock Off Detection
DCSI                   0xEF68   DCL Clock Supervision Interval
DCSI.DCSI_VAL_10        10  DCL Clock Supervision Interval Value - bit 10
DCSI.DCSI_VAL_9         9   DCL Clock Supervision Interval Value - bit 9 
DCSI.DCSI_VAL_8         8   DCL Clock Supervision Interval Value - bit 8 
DCSI.DCSI_VAL_7         7   DCL Clock Supervision Interval Value - bit 7 
DCSI.DCSI_VAL_6         6   DCL Clock Supervision Interval Value - bit 6 
DCSI.DCSI_VAL_5         5   DCL Clock Supervision Interval Value - bit 5 
DCSI.DCSI_VAL_4         4   DCL Clock Supervision Interval Value - bit 4 
DCSI.DCSI_VAL_3         3   DCL Clock Supervision Interval Value - bit 3 
DCSI.DCSI_VAL_2         2   DCL Clock Supervision Interval Value - bit 2 
DCSI.DCSI_VAL_1         1   DCL Clock Supervision Interval Value - bit 1 
DCSI.DCSI_VAL_0         0   DCL Clock Supervision Interval Value - bit 0 
reserv_EF6A            0xEF6A   RESERVED
reserv_EF6C            0xEF6C   RESERVED
reserv_EF6E            0xEF6E   RESERVED
reserv_EF70            0xEF70   RESERVED
reserv_EF72            0xEF72   RESERVED
reserv_EF74            0xEF74   RESERVED
reserv_EF76            0xEF76   RESERVED
reserv_EF78            0xEF78   RESERVED
reserv_EF7A            0xEF7A   RESERVED
reserv_EF7C            0xEF7C   RESERVED
reserv_EF7E            0xEF7E   RESERVED
RFIFO_0                0xEF80   Receive FIFO (HDLC-Channel 0)
RFIFO_0.DATA_15         15
RFIFO_0.DATA_14         14
RFIFO_0.DATA_13         13
RFIFO_0.DATA_12         12
RFIFO_0.DATA_11         11
RFIFO_0.DATA_10         10
RFIFO_0.DATA_9          9 
RFIFO_0.DATA_8          8 
RFIFO_0.DATA_7          7 
RFIFO_0.DATA_6          6 
RFIFO_0.DATA_5          5 
RFIFO_0.DATA_4          4 
RFIFO_0.DATA_3          3 
RFIFO_0.DATA_2          2 
RFIFO_0.DATA_1          1 
RFIFO_0.DATA_0          0 
TFIFO_0                0xEF82   Transmit FIFO (HDLC-Channel 0)
TFIFO_0.DATA_15         15
TFIFO_0.DATA_14         14
TFIFO_0.DATA_13         13
TFIFO_0.DATA_12         12
TFIFO_0.DATA_11         11
TFIFO_0.DATA_10         10
TFIFO_0.DATA_9          9 
TFIFO_0.DATA_8          8 
TFIFO_0.DATA_7          7 
TFIFO_0.DATA_6          6 
TFIFO_0.DATA_5          5 
TFIFO_0.DATA_4          4 
TFIFO_0.DATA_3          3 
TFIFO_0.DATA_2          2 
TFIFO_0.DATA_1          1 
TFIFO_0.DATA_0          0 
ISTAH_0                0xEF84   Interrupt Status Register (HDLC-Channel 0)
ISTAH_0.RME             15  Receive Message End
ISTAH_0.RPF             14  Receive Pool Full
ISTAH_0.RFO             13  Receive Frame Overflow
ISTAH_0.FFO             12  Following Frame Overflow
ISTAH_0.XPR             7   Transmit Pool Ready
ISTAH_0.XMR             6   Transmit Message Repeat
ISTAH_0.XDU             5   Transmit Data Underrun
ISTAH_0.XDOV            4   Transmit Data Overflow
MASKH_0                0xEF86   Interrupt Mask Register (HDLC-Channel 0)
MASKH_0.RME             15
MASKH_0.RPF             14
MASKH_0.RFO             13
MASKH_0.FFO             12
MASKH_0.XPR             7
MASKH_0.XMR             6
MASKH_0.XDU             5
MASKH_0.XDOV            4
STAR_0                 0xEF88   Status Register (HDLC-Channel 0)
STAR_0.VFR              15  Valid Frame
STAR_0.RDO              14  Receive Data Overflow
STAR_0.CRC              13  CRC Check
STAR_0.RAB              12  Receive Message Aborted
STAR_0.SA1              11  SAPI Address Identification
STAR_0.SA0              10  SAPI Address Identification
STAR_0.C_R              9   Command/Response
STAR_0.TA               8   TEI Address Identification
STAR_0.RACI             7   Receiver Active Indication
CMDR_0                 0xEF8A   Command Register (HDLC-Channel 0)
CMDR_0.RRES             15  Receiver Reset
CMDR_0.XRES             7   Transmitter Reset
CMDR_0.XME              6   Transmit Message End
CMDR_0.XTF              5   Transmit Transparent Frame
IOMSEL_0               0xEF8C   IOM-2 Channel Selection (HDLC-Channel 0)
IOMSEL_0.EN_D2          3   Select second 2-bit IOM-2 Channel (D2)
IOMSEL_0.EN_D1          2   Select first 2-bit IOM-2 Channel (D1)
IOMSEL_0.EN_B2          1   Select second 8-bit IOM-2 Channel (B2)
IOMSEL_0.EN_B1          0   Select first 8-bit IOM-2 Channel (B1)
MODEH_0                0xEF8E   Mode Register (HDLC-Channel 0)
MODEH_0.RPE             15  Receive PEC Enable
MODEH_0.XPE             14  Transmit PEC Enable
MODEH_0.SRA             12  Store Receive Address
MODEH_0.XCRC            11  Transmit CRC
MODEH_0.RCRC            10  Receive CRC
MODEH_0.ITF             8   Interframe Time Fill
MODEH_0.MDS_7           7   0 Mode Select - bit 7
MODEH_0.MDS_6           6   0 Mode Select - bit 6
MODEH_0.MDS_5           5   0 Mode Select - bit 5
MODEH_0.RAC             3   Receiver Active
SAP1_0                 0xEF90   SAPI1 Register (HDLC-Channel 0)
SAP1_0.SAPI1_7          7   SAPI1 value - bit 7
SAP1_0.SAPI1_6          6   SAPI1 value - bit 6
SAP1_0.SAPI1_5          5   SAPI1 value - bit 5
SAP1_0.SAPI1_4          4   SAPI1 value - bit 4
SAP1_0.SAPI1_3          3   SAPI1 value - bit 3
SAP1_0.SAPI1_2          2   SAPI1 value - bit 2
SAP1_0.MHA              0   Mask High Address
SAP2_0                 0xEF92   SAPI2 Register (HDLC-Channel 0)
SAP2_0.SAPI2_7          7   SAPI2 value - bit 7
SAP2_0.SAPI2_6          6   SAPI2 value - bit 6
SAP2_0.SAPI2_5          5   SAPI2 value - bit 5
SAP2_0.SAPI2_4          4   SAPI2 value - bit 4
SAP2_0.SAPI2_3          3   SAPI2 value - bit 3
SAP2_0.SAPI2_2          2   SAPI2 value - bit 2
SAP2_0.MLA              0   Mask Low Address
RBC_0                  0xEF94   Receive Frame Byte Count (HDLC-Channel 0)
RBC_0.OV                12  Overflow
RBC_0.RBC_11            11
RBC_0.RBC_10            10
RBC_0.RBC_9             9 
RBC_0.RBC_8             8 
RBC_0.RBC_7             7 
RBC_0.RBC_6             6 
RBC_0.RBC_5             5 
RBC_0.RBC_4             4 
RBC_0.RBC_3             3 
RBC_0.RBC_2             2 
RBC_0.RBC_1             1 
RBC_0.RBC_0             0 
TEI1_0                 0xEF96   TEI1 Register (HDLC-Channel 0)
TEI1_0.TEI1_7           7   Terminal Endpoint Identifier - bit 7
TEI1_0.TEI1_6           6   Terminal Endpoint Identifier - bit 6
TEI1_0.TEI1_5           5   Terminal Endpoint Identifier - bit 5
TEI1_0.TEI1_4           4   Terminal Endpoint Identifier - bit 4
TEI1_0.TEI1_3           3   Terminal Endpoint Identifier - bit 3
TEI1_0.TEI1_2           2   Terminal Endpoint Identifier - bit 2
TEI1_0.TEI1_1           1   Terminal Endpoint Identifier - bit 1
TEI1_0.EA               0   Address field Extension bit
TEI2_0                 0xEF98   TEI2 Register (HDLC-Channel 0)
TEI2_0.TEI1_7           7   Terminal Endpoint Identifier - bit 7
TEI2_0.TEI1_6           6   Terminal Endpoint Identifier - bit 6
TEI2_0.TEI1_5           5   Terminal Endpoint Identifier - bit 5
TEI2_0.TEI1_4           4   Terminal Endpoint Identifier - bit 4
TEI2_0.TEI1_3           3   Terminal Endpoint Identifier - bit 3
TEI2_0.TEI1_2           2   Terminal Endpoint Identifier - bit 2
TEI2_0.TEI1_1           1   Terminal Endpoint Identifier - bit 1
TEI2_0.EA               0   Address field Extension bit
LOOP_0                 0xEF9A   Looping Register (HDLC-Channel 0)
LOOP_0.ELP              2   External Loop
LOOP_0.FAST             1   Fast Looping
LOOP_0.TLP              0   Transmit Loop
reserv_EF9C            0xEF9C   RESERVED
reserv_EF9E            0xEF9E   RESERVED
RFIFO_1                0xEFA0   Receive FIFO (HDLC-Channel 1)
RFIFO_1.DATA_15         15
RFIFO_1.DATA_14         14
RFIFO_1.DATA_13         13
RFIFO_1.DATA_12         12
RFIFO_1.DATA_11         11
RFIFO_1.DATA_10         10
RFIFO_1.DATA_9          9 
RFIFO_1.DATA_8          8 
RFIFO_1.DATA_7          7 
RFIFO_1.DATA_6          6 
RFIFO_1.DATA_5          5 
RFIFO_1.DATA_4          4 
RFIFO_1.DATA_3          3 
RFIFO_1.DATA_2          2 
RFIFO_1.DATA_1          1 
RFIFO_1.DATA_0          0 
TFIFO_1                0xEFA2   Transmit FIFO (HDLC-Channel 1)
TFIFO_1.DATA_15         15
TFIFO_1.DATA_14         14
TFIFO_1.DATA_13         13
TFIFO_1.DATA_12         12
TFIFO_1.DATA_11         11
TFIFO_1.DATA_10         10
TFIFO_1.DATA_9          9 
TFIFO_1.DATA_8          8 
TFIFO_1.DATA_7          7 
TFIFO_1.DATA_6          6 
TFIFO_1.DATA_5          5 
TFIFO_1.DATA_4          4 
TFIFO_1.DATA_3          3 
TFIFO_1.DATA_2          2 
TFIFO_1.DATA_1          1 
TFIFO_1.DATA_0          0 
ISTAH_1                0xEFA4   Interrupt Status Register (HDLC-Channel 1)
ISTAH_1.RME             15  Receive Message End
ISTAH_1.RPF             14  Receive Pool Full
ISTAH_1.RFO             13  Receive Frame Overflow
ISTAH_1.FFO             12  Following Frame Overflow
ISTAH_1.XPR             7   Transmit Pool Ready
ISTAH_1.XMR             6   Transmit Message Repeat
ISTAH_1.XDU             5   Transmit Data Underrun
ISTAH_1.XDOV            4   Transmit Data Overflow
MASKH_1                0xEFA6   Interrupt Mask Register (HDLC-Channel 1)
MASKH_1.RME             15
MASKH_1.RPF             14
MASKH_1.RFO             13
MASKH_1.FFO             12
MASKH_1.XPR             7
MASKH_1.XMR             6
MASKH_1.XDU             5
MASKH_1.XDOV            4
STAR_1                 0xEFA8   Status Register (HDLC-Channel 1)
STAR_1.VFR              15  Valid Frame
STAR_1.RDO              14  Receive Data Overflow
STAR_1.CRC              13  CRC Check
STAR_1.RAB              12  Receive Message Aborted
STAR_1.SA1              11  SAPI Address Identification
STAR_1.SA0              10  SAPI Address Identification
STAR_1.C_R              9   Command/Response
STAR_1.TA               8   TEI Address Identification
STAR_1.RACI             7   Receiver Active Indication
CMDR_1                 0xEFAA   Command Register (HDLC-Channel 1)
CMDR_1.RRES             15  Receiver Reset
CMDR_1.XRES             7   Transmitter Reset
CMDR_1.XME              6   Transmit Message End
CMDR_1.XTF              5   Transmit Transparent Frame
IOMSEL_1               0xEFAC   IOM-2 Channel Selection (HDLC-Channel 1)
IOMSEL_1.EN_D2          3   Select second 2-bit IOM-2 Channel (D2)
IOMSEL_1.EN_D1          2   Select first 2-bit IOM-2 Channel (D1)
IOMSEL_1.EN_B2          1   Select second 8-bit IOM-2 Channel (B2)
IOMSEL_1.EN_B1          0   Select first 8-bit IOM-2 Channel (B1)
MODEH_1                0xEFAE   Mode Register (HDLC-Channel 1)
MODEH_1.RPE             15  Receive PEC Enable
MODEH_1.XPE             14  Transmit PEC Enable
MODEH_1.SRA             12  Store Receive Address
MODEH_1.XCRC            11  Transmit CRC
MODEH_1.RCRC            10  Receive CRC
MODEH_1.ITF             8   Interframe Time Fill
MODEH_1.MDS_7           7   0 Mode Select - bit 7
MODEH_1.MDS_6           6   0 Mode Select - bit 6
MODEH_1.MDS_5           5   0 Mode Select - bit 5
MODEH_1.RAC             3   Receiver Active
SAP1_1                 0xEFB0   SAPI1 Register (HDLC-Channel 1)
SAP1_1.SAPI1_7          7   SAPI1 value - bit 7
SAP1_1.SAPI1_6          6   SAPI1 value - bit 6
SAP1_1.SAPI1_5          5   SAPI1 value - bit 5
SAP1_1.SAPI1_4          4   SAPI1 value - bit 4
SAP1_1.SAPI1_3          3   SAPI1 value - bit 3
SAP1_1.SAPI1_2          2   SAPI1 value - bit 2
SAP1_1.MHA              0   Mask High Address
SAP2_1                 0xEFB2   SAPI2 Register (HDLC-Channel 1)
SAP2_1.SAPI2_7          7   SAPI2 value - bit 7
SAP2_1.SAPI2_6          6   SAPI2 value - bit 6
SAP2_1.SAPI2_5          5   SAPI2 value - bit 5
SAP2_1.SAPI2_4          4   SAPI2 value - bit 4
SAP2_1.SAPI2_3          3   SAPI2 value - bit 3
SAP2_1.SAPI2_2          2   SAPI2 value - bit 2
SAP2_1.MLA              0   Mask Low Address
RBC_1                  0xEFB4   Receive Frame Byte Count (HDLC-Channel 1)
RBC_1.OV                12  Overflow
RBC_1.RBC_11            11
RBC_1.RBC_10            10
RBC_1.RBC_9             9 
RBC_1.RBC_8             8 
RBC_1.RBC_7             7 
RBC_1.RBC_6             6 
RBC_1.RBC_5             5 
RBC_1.RBC_4             4 
RBC_1.RBC_3             3 
RBC_1.RBC_2             2 
RBC_1.RBC_1             1 
RBC_1.RBC_0             0 
TEI1_1                 0xEFB6   TEI1 Register (HDLC-Channel 1)
TEI1_1.TEI1_7           7   Terminal Endpoint Identifier - bit 7
TEI1_1.TEI1_6           6   Terminal Endpoint Identifier - bit 6
TEI1_1.TEI1_5           5   Terminal Endpoint Identifier - bit 5
TEI1_1.TEI1_4           4   Terminal Endpoint Identifier - bit 4
TEI1_1.TEI1_3           3   Terminal Endpoint Identifier - bit 3
TEI1_1.TEI1_2           2   Terminal Endpoint Identifier - bit 2
TEI1_1.TEI1_1           1   Terminal Endpoint Identifier - bit 1
TEI1_1.EA               0   Address field Extension bit
TEI2_1                 0xEFB8   TEI2 Register (HDLC-Channel 1)
TEI2_1.TEI1_7           7   Terminal Endpoint Identifier - bit 7
TEI2_1.TEI1_6           6   Terminal Endpoint Identifier - bit 6
TEI2_1.TEI1_5           5   Terminal Endpoint Identifier - bit 5
TEI2_1.TEI1_4           4   Terminal Endpoint Identifier - bit 4
TEI2_1.TEI1_3           3   Terminal Endpoint Identifier - bit 3
TEI2_1.TEI1_2           2   Terminal Endpoint Identifier - bit 2
TEI2_1.TEI1_1           1   Terminal Endpoint Identifier - bit 1
TEI2_1.EA               0   Address field Extension bit
LOOP_1                 0xEFBA   Looping Register (HDLC-Channel 1)
LOOP_1.ELP              2   External Loop
LOOP_1.FAST             1   Fast Looping
LOOP_1.TLP              0   Transmit Loop
reserv_EFBC            0xEFBC   RESERVED
reserv_EFBE            0xEFBE   RESERVED
RFIFO_2                0xEFC0   Receive FIFO (HDLC-Channel 2)
RFIFO_2.DATA_15         15
RFIFO_2.DATA_14         14
RFIFO_2.DATA_13         13
RFIFO_2.DATA_12         12
RFIFO_2.DATA_11         11
RFIFO_2.DATA_10         10
RFIFO_2.DATA_9          9 
RFIFO_2.DATA_8          8 
RFIFO_2.DATA_7          7 
RFIFO_2.DATA_6          6 
RFIFO_2.DATA_5          5 
RFIFO_2.DATA_4          4 
RFIFO_2.DATA_3          3 
RFIFO_2.DATA_2          2 
RFIFO_2.DATA_1          1 
RFIFO_2.DATA_0          0 
TFIFO_2                0xEFC2   Transmit FIFO (HDLC-Channel 2)
TFIFO_2.DATA_15         15
TFIFO_2.DATA_14         14
TFIFO_2.DATA_13         13
TFIFO_2.DATA_12         12
TFIFO_2.DATA_11         11
TFIFO_2.DATA_10         10
TFIFO_2.DATA_9          9 
TFIFO_2.DATA_8          8 
TFIFO_2.DATA_7          7 
TFIFO_2.DATA_6          6 
TFIFO_2.DATA_5          5 
TFIFO_2.DATA_4          4 
TFIFO_2.DATA_3          3 
TFIFO_2.DATA_2          2 
TFIFO_2.DATA_1          1 
TFIFO_2.DATA_0          0 
ISTAH_2                0xEFC4   Interrupt Status Register (HDLC-Channel 2)
ISTAH_2.RME             15  Receive Message End
ISTAH_2.RPF             14  Receive Pool Full
ISTAH_2.RFO             13  Receive Frame Overflow
ISTAH_2.FFO             12  Following Frame Overflow
ISTAH_2.XPR             7   Transmit Pool Ready
ISTAH_2.XMR             6   Transmit Message Repeat
ISTAH_2.XDU             5   Transmit Data Underrun
ISTAH_2.XDOV            4   Transmit Data Overflow
MASKH_2                0xEFC6   Interrupt Mask Register (HDLC-Channel 2)
MASKH_2.RME             15
MASKH_2.RPF             14
MASKH_2.RFO             13
MASKH_2.FFO             12
MASKH_2.XPR             7
MASKH_2.XMR             6
MASKH_2.XDU             5
MASKH_2.XDOV            4
STAR_2                 0xEFC8   Status Register (HDLC-Channel 2)
STAR_2.VFR              15  Valid Frame
STAR_2.RDO              14  Receive Data Overflow
STAR_2.CRC              13  CRC Check
STAR_2.RAB              12  Receive Message Aborted
STAR_2.SA1              11  SAPI Address Identification
STAR_2.SA0              10  SAPI Address Identification
STAR_2.C_R              9   Command/Response
STAR_2.TA               8   TEI Address Identification
STAR_2.RACI             7   Receiver Active Indication
CMDR_2                 0xEFCA   Comm ERer (HDLC-Channel 2)
CMDR_2.RRES             15  Receiver Reset
CMDR_2.XRES             7   Transmitter Reset
CMDR_2.XME              6   Transmit Message End
CMDR_2.XTF              5   Transmit Transparent Frame
IOMSEL_2               0xEFCC   IOM-2 Channel Selection (HDLC-Channel 2)
IOMSEL_2.EN_D2          3   Select second 2-bit IOM-2 Channel (D2)
IOMSEL_2.EN_D1          2   Select first 2-bit IOM-2 Channel (D1)
IOMSEL_2.EN_B2          1   Select second 8-bit IOM-2 Channel (B2)
IOMSEL_2.EN_B1          0   Select first 8-bit IOM-2 Channel (B1)
MODEH_2                0xEFCE   Mode Register (HDLC-Channel 2)
MODEH_2.RPE             15  Receive PEC Enable
MODEH_2.XPE             14  Transmit PEC Enable
MODEH_2.SRA             12  Store Receive Address
MODEH_2.XCRC            11  Transmit CRC
MODEH_2.RCRC            10  Receive CRC
MODEH_2.ITF             8   Interframe Time Fill
MODEH_2.MDS_7           7   0 Mode Select - bit 7
MODEH_2.MDS_6           6   0 Mode Select - bit 6
MODEH_2.MDS_5           5   0 Mode Select - bit 5
MODEH_2.RAC             3   Receiver Active
SAP1_2                 0xEFD0   SAPI1 Register (HDLC-Channel 2)
SAP1_2.SAPI1_7          7   SAPI1 value - bit 7
SAP1_2.SAPI1_6          6   SAPI1 value - bit 6
SAP1_2.SAPI1_5          5   SAPI1 value - bit 5
SAP1_2.SAPI1_4          4   SAPI1 value - bit 4
SAP1_2.SAPI1_3          3   SAPI1 value - bit 3
SAP1_2.SAPI1_2          2   SAPI1 value - bit 2
SAP1_2.MHA              0   Mask High Address
SAP2_2                 0xEFD2   SAPI2 Register (HDLC-Channel 2)
SAP2_2.SAPI2_7          7   SAPI2 value - bit 7
SAP2_2.SAPI2_6          6   SAPI2 value - bit 6
SAP2_2.SAPI2_5          5   SAPI2 value - bit 5
SAP2_2.SAPI2_4          4   SAPI2 value - bit 4
SAP2_2.SAPI2_3          3   SAPI2 value - bit 3
SAP2_2.SAPI2_2          2   SAPI2 value - bit 2
SAP2_2.MLA              0   Mask Low Address
RBC_2                  0xEFD4   Receive Frame Byte Count (HDLC-Channel 2)
RBC_2.OV                12  Overflow
RBC_2.RBC_11            11
RBC_2.RBC_10            10
RBC_2.RBC_9             9 
RBC_2.RBC_8             8 
RBC_2.RBC_7             7 
RBC_2.RBC_6             6 
RBC_2.RBC_5             5 
RBC_2.RBC_4             4 
RBC_2.RBC_3             3 
RBC_2.RBC_2             2 
RBC_2.RBC_1             1 
RBC_2.RBC_0             0 
TEI1_2                 0xEFD6   TEI1 Register (HDLC-Channel 2)
TEI1_2.TEI1_7           7   Terminal Endpoint Identifier - bit 7
TEI1_2.TEI1_6           6   Terminal Endpoint Identifier - bit 6
TEI1_2.TEI1_5           5   Terminal Endpoint Identifier - bit 5
TEI1_2.TEI1_4           4   Terminal Endpoint Identifier - bit 4
TEI1_2.TEI1_3           3   Terminal Endpoint Identifier - bit 3
TEI1_2.TEI1_2           2   Terminal Endpoint Identifier - bit 2
TEI1_2.TEI1_1           1   Terminal Endpoint Identifier - bit 1
TEI1_2.EA               0   Address field Extension bit
TEI2_2                 0xEFD8   TEI2 Register (HDLC-Channel 2)
TEI2_2.TEI1_7           7   Terminal Endpoint Identifier - bit 7
TEI2_2.TEI1_6           6   Terminal Endpoint Identifier - bit 6
TEI2_2.TEI1_5           5   Terminal Endpoint Identifier - bit 5
TEI2_2.TEI1_4           4   Terminal Endpoint Identifier - bit 4
TEI2_2.TEI1_3           3   Terminal Endpoint Identifier - bit 3
TEI2_2.TEI1_2           2   Terminal Endpoint Identifier - bit 2
TEI2_2.TEI1_1           1   Terminal Endpoint Identifier - bit 1
TEI2_2.EA               0   Address field Extension bit
LOOP_2                 0xEFDA   Looping Register (HDLC-Channel 2)
LOOP_2.ELP              2   External Loop
LOOP_2.FAST             1   Fast Looping
LOOP_2.TLP              0   Transmit Loop
reserv_EFDC            0xEFDC   RESERVED
reserv_EFDE            0xEFDE   RESERVED
RFIFO_3                0xEFE0   Receive FIFO (HDLC-Channel 3)
RFIFO_3.DATA_15         15
RFIFO_3.DATA_14         14
RFIFO_3.DATA_13         13
RFIFO_3.DATA_12         12
RFIFO_3.DATA_11         11
RFIFO_3.DATA_10         10
RFIFO_3.DATA_9          9 
RFIFO_3.DATA_8          8 
RFIFO_3.DATA_7          7 
RFIFO_3.DATA_6          6 
RFIFO_3.DATA_5          5 
RFIFO_3.DATA_4          4 
RFIFO_3.DATA_3          3 
RFIFO_3.DATA_2          2 
RFIFO_3.DATA_1          1 
RFIFO_3.DATA_0          0 
TFIFO_3                0xEFE2   Transmit FIFO (HDLC-Channel 3)
TFIFO_3.DATA_15         15
TFIFO_3.DATA_14         14
TFIFO_3.DATA_13         13
TFIFO_3.DATA_12         12
TFIFO_3.DATA_11         11
TFIFO_3.DATA_10         10
TFIFO_3.DATA_9          9 
TFIFO_3.DATA_8          8 
TFIFO_3.DATA_7          7 
TFIFO_3.DATA_6          6 
TFIFO_3.DATA_5          5 
TFIFO_3.DATA_4          4 
TFIFO_3.DATA_3          3 
TFIFO_3.DATA_2          2 
TFIFO_3.DATA_1          1 
TFIFO_3.DATA_0          0 
ISTAH_3                0xEFE4   Interrupt Status Register (HDLC-Channel 3)
ISTAH_3.RME             15  Receive Message End
ISTAH_3.RPF             14  Receive Pool Full
ISTAH_3.RFO             13  Receive Frame Overflow
ISTAH_3.FFO             12  Following Frame Overflow
ISTAH_3.XPR             7   Transmit Pool Ready
ISTAH_3.XMR             6   Transmit Message Repeat
ISTAH_3.XDU             5   Transmit Data Underrun
ISTAH_3.XDOV            4   Transmit Data Overflow
MASKH_3                0xEFE6   Interrupt Mask Register (HDLC-Channel 3)
MASKH_3.RME             15
MASKH_3.RPF             14
MASKH_3.RFO             13
MASKH_3.FFO             12
MASKH_3.XPR             7
MASKH_3.XMR             6
MASKH_3.XDU             5
MASKH_3.XDOV            4
STAR_3                 0xEFE8   Status Register (HDLC-Channel 3)
STAR_3.VFR              15  Valid Frame
STAR_3.RDO              14  Receive Data Overflow
STAR_3.CRC              13  CRC Check
STAR_3.RAB              12  Receive Message Aborted
STAR_3.SA1              11  SAPI Address Identification
STAR_3.SA0              10  SAPI Address Identification
STAR_3.C_R              9   Command/Response
STAR_3.TA               8   TEI Address Identification
STAR_3.RACI             7   Receiver Active Indication
CMDR_3                 0xEFEA   Command Register (HDLC-Channel 3)
CMDR_3.RRES             15  Receiver Reset
CMDR_3.XRES             7   Transmitter Reset
CMDR_3.XME              6   Transmit Message End
CMDR_3.XTF              5   Transmit Transparent Frame
IOMSEL_3               0xEFEC   IOM-2 Channel Selection (HDLC-Channel 3)
IOMSEL_3.EN_D2          3   Select second 2-bit IOM-2 Channel (D2)
IOMSEL_3.EN_D1          2   Select first 2-bit IOM-2 Channel (D1)
IOMSEL_3.EN_B2          1   Select second 8-bit IOM-2 Channel (B2)
IOMSEL_3.EN_B1          0   Select first 8-bit IOM-2 Channel (B1)
MODEH_3                0xEFEE   Mode Register (HDLC-Channel 3)
MODEH_3.RPE             15  Receive PEC Enable
MODEH_3.XPE             14  Transmit PEC Enable
MODEH_3.SRA             12  Store Receive Address
MODEH_3.XCRC            11  Transmit CRC
MODEH_3.RCRC            10  Receive CRC
MODEH_3.ITF             8   Interframe Time Fill
MODEH_3.MDS_7           7   0 Mode Select - bit 7
MODEH_3.MDS_6           6   0 Mode Select - bit 6
MODEH_3.MDS_5           5   0 Mode Select - bit 5
MODEH_3.RAC             3   Receiver Active
SAP1_3                 0xEFF0   SAPI1 Register (HDLC-Channel 3)
SAP1_3.SAPI1_7          7   SAPI1 value - bit 7
SAP1_3.SAPI1_6          6   SAPI1 value - bit 6
SAP1_3.SAPI1_5          5   SAPI1 value - bit 5
SAP1_3.SAPI1_4          4   SAPI1 value - bit 4
SAP1_3.SAPI1_3          3   SAPI1 value - bit 3
SAP1_3.SAPI1_2          2   SAPI1 value - bit 2
SAP1_3.MHA              0   Mask High Address
SAP2_3                 0xEFF2   SAPI2 Register (HDLC-Channel 3)
SAP2_3.SAPI2_7          7   SAPI2 value - bit 7
SAP2_3.SAPI2_6          6   SAPI2 value - bit 6
SAP2_3.SAPI2_5          5   SAPI2 value - bit 5
SAP2_3.SAPI2_4          4   SAPI2 value - bit 4
SAP2_3.SAPI2_3          3   SAPI2 value - bit 3
SAP2_3.SAPI2_2          2   SAPI2 value - bit 2
SAP2_3.MLA              0   Mask Low Address
RBC_3                  0xEFF4   Receive Frame Byte Count (HDLC-Channel 3)
RBC_3.OV                12  Overflow
RBC_3.RBC_11            11
RBC_3.RBC_10            10
RBC_3.RBC_9             9 
RBC_3.RBC_8             8 
RBC_3.RBC_7             7 
RBC_3.RBC_6             6 
RBC_3.RBC_5             5 
RBC_3.RBC_4             4 
RBC_3.RBC_3             3 
RBC_3.RBC_2             2 
RBC_3.RBC_1             1 
RBC_3.RBC_0             0 
TEI1_3                 0xEFF6   TEI1 Register (HDLC-Channel 3)
TEI1_3.TEI1_7           7   Terminal Endpoint Identifier - bit 7
TEI1_3.TEI1_6           6   Terminal Endpoint Identifier - bit 6
TEI1_3.TEI1_5           5   Terminal Endpoint Identifier - bit 5
TEI1_3.TEI1_4           4   Terminal Endpoint Identifier - bit 4
TEI1_3.TEI1_3           3   Terminal Endpoint Identifier - bit 3
TEI1_3.TEI1_2           2   Terminal Endpoint Identifier - bit 2
TEI1_3.TEI1_1           1   Terminal Endpoint Identifier - bit 1
TEI1_3.EA               0   Address field Extension bit
TEI2_3                 0xEFF8   TEI2 Register (HDLC-Channel 3)
TEI2_3.TEI1_7           7   Terminal Endpoint Identifier - bit 7
TEI2_3.TEI1_6           6   Terminal Endpoint Identifier - bit 6
TEI2_3.TEI1_5           5   Terminal Endpoint Identifier - bit 5
TEI2_3.TEI1_4           4   Terminal Endpoint Identifier - bit 4
TEI2_3.TEI1_3           3   Terminal Endpoint Identifier - bit 3
TEI2_3.TEI1_2           2   Terminal Endpoint Identifier - bit 2
TEI2_3.TEI1_1           1   Terminal Endpoint Identifier - bit 1
TEI2_3.EA               0   Address field Extension bit
LOOP_3                 0xEFFA   Looping Register (HDLC-Channel 3)
LOOP_3.ELP              2   External Loop
LOOP_3.FAST             1   Fast Looping
LOOP_3.TLP              0   Transmit Loop
reserv_EFFC            0xEFFC   RESERVED
reserv_EFFE            0xEFFE   RESERVED

; E_SFR and SFR Registers
XADRS1           0xF014   XBUS Address Select Register 1
XADRS1.RGSAD15    15  Range Start Address bit 15
XADRS1.RGSAD14    14  Range Start Address bit 14
XADRS1.RGSAD13    13  Range Start Address bit 13
XADRS1.RGSAD12    12  Range Start Address bit 12
XADRS1.RGSAD11    11  Range Start Address bit 11
XADRS1.RGSAD10    10  Range Start Address bit 10
XADRS1.RGSAD9     9   Range Start Address bit 9
XADRS1.RGSAD8     8   Range Start Address bit 8
XADRS1.RGSAD7     7   Range Start Address bit 7
XADRS1.RGSAD6     6   Range Start Address bit 6
XADRS1.RGSAD5     5   Range Start Address bit 5
XADRS1.RGSAD4     4   Range Start Address bit 4
XADRS1.RGSZ3      3   Range Size Selection bit 3
XADRS1.RGSZ2      2   Range Size Selection bit 2
XADRS1.RGSZ1      1   Range Size Selection bit 1
XADRS1.RGSZ0      0   Range Size Selection bit 0
XADRS2           0xF016   XBUS Address Select Register 2
XADRS2.RGSAD15    15  Range Start Address bit 15
XADRS2.RGSAD14    14  Range Start Address bit 14
XADRS2.RGSAD13    13  Range Start Address bit 13
XADRS2.RGSAD12    12  Range Start Address bit 12
XADRS2.RGSAD11    11  Range Start Address bit 11
XADRS2.RGSAD10    10  Range Start Address bit 10
XADRS2.RGSAD9     9   Range Start Address bit 9
XADRS2.RGSAD8     8   Range Start Address bit 8
XADRS2.RGSAD7     7   Range Start Address bit 7
XADRS2.RGSAD6     6   Range Start Address bit 6
XADRS2.RGSAD5     5   Range Start Address bit 5
XADRS2.RGSAD4     4   Range Start Address bit 4
XADRS2.RGSZ3      3   Range Size Selection bit 3
XADRS2.RGSZ2      2   Range Size Selection bit 2
XADRS2.RGSZ1      1   Range Size Selection bit 1
XADRS2.RGSZ0      0   Range Size Selection bit 0
XADRS3           0xF018   XBUS Address Select Register 3
XADRS3.RGSAD15    15  Range Start Address bit 15
XADRS3.RGSAD14    14  Range Start Address bit 14
XADRS3.RGSAD13    13  Range Start Address bit 13
XADRS3.RGSAD12    12  Range Start Address bit 12
XADRS3.RGSAD11    11  Range Start Address bit 11
XADRS3.RGSAD10    10  Range Start Address bit 10
XADRS3.RGSAD9     9   Range Start Address bit 9
XADRS3.RGSAD8     8   Range Start Address bit 8
XADRS3.RGSAD7     7   Range Start Address bit 7
XADRS3.RGSAD6     6   Range Start Address bit 6
XADRS3.RGSAD5     5   Range Start Address bit 5
XADRS3.RGSAD4     4   Range Start Address bit 4
XADRS3.RGSZ3      3   Range Size Selection bit 3
XADRS3.RGSZ2      2   Range Size Selection bit 2
XADRS3.RGSZ1      1   Range Size Selection bit 1
XADRS3.RGSZ0      0   Range Size Selection bit 0
XADRS4           0xF01A   XBUS Address Select Register 4
XADRS4.RGSAD15    15  Range Start Address bit 15
XADRS4.RGSAD14    14  Range Start Address bit 14
XADRS4.RGSAD13    13  Range Start Address bit 13
XADRS4.RGSAD12    12  Range Start Address bit 12
XADRS4.RGSAD11    11  Range Start Address bit 11
XADRS4.RGSAD10    10  Range Start Address bit 10
XADRS4.RGSAD9     9   Range Start Address bit 9
XADRS4.RGSAD8     8   Range Start Address bit 8
XADRS4.RGSAD7     7   Range Start Address bit 7
XADRS4.RGSAD6     6   Range Start Address bit 6
XADRS4.RGSAD5     5   Range Start Address bit 5
XADRS4.RGSAD4     4   Range Start Address bit 4
XADRS4.RGSZ3      3   Range Size Selection bit 3
XADRS4.RGSZ2      2   Range Size Selection bit 2
XADRS4.RGSZ1      1   Range Size Selection bit 1
XADRS4.RGSZ0      0   Range Size Selection bit 0
XADRS5           0xF01C   XBUS Address Select Register 5
XADRS5.RGSAD15    15  Range Start Address bit 15
XADRS5.RGSAD14    14  Range Start Address bit 14
XADRS5.RGSAD13    13  Range Start Address bit 13
XADRS5.RGSAD12    12  Range Start Address bit 12
XADRS5.RGSAD11    11  Range Start Address bit 11
XADRS5.RGSAD10    10  Range Start Address bit 10
XADRS5.RGSAD9     9   Range Start Address bit 9
XADRS5.RGSAD8     8   Range Start Address bit 8
XADRS5.RGSAD7     7   Range Start Address bit 7
XADRS5.RGSAD6     6   Range Start Address bit 6
XADRS5.RGSAD5     5   Range Start Address bit 5
XADRS5.RGSAD4     4   Range Start Address bit 4
XADRS5.RGSZ3      3   Range Size Selection bit 3
XADRS5.RGSZ2      2   Range Size Selection bit 2
XADRS5.RGSZ1      1   Range Size Selection bit 1
XADRS5.RGSZ0      0   Range Size Selection bit 0
XADRS6           0xF01E   XBUS Address Select Register 6
XADRS6.RGSAD15    15  Range Start Address bit 15
XADRS6.RGSAD14    14  Range Start Address bit 14
XADRS6.RGSAD13    13  Range Start Address bit 13
XADRS6.RGSAD12    12  Range Start Address bit 12
XADRS6.RGSAD11    11  Range Start Address bit 11
XADRS6.RGSAD10    10  Range Start Address bit 10
XADRS6.RGSAD9     9   Range Start Address bit 9
XADRS6.RGSAD8     8   Range Start Address bit 8
XADRS6.RGSAD7     7   Range Start Address bit 7
XADRS6.RGSAD6     6   Range Start Address bit 6
XADRS6.RGSAD5     5   Range Start Address bit 5
XADRS6.RGSAD4     4   Range Start Address bit 4
XADRS6.RGSZ3      3   Range Size Selection bit 3
XADRS6.RGSZ2      2   Range Size Selection bit 2
XADRS6.RGSZ1      1   Range Size Selection bit 1
XADRS6.RGSZ0      0   Range Size Selection bit 0
XPERCON          0xF024   XBUS Peripheral Control Register
XPERCON.XPER7     7
XPERCON.XPER6     6
XPERCON.XPER5     5
IDMEM2           0xF076   Identifier
IDPROG           0xF078   Identifier
IDPROG.PROGVPP_15 15  Programming VPP Voltage - bit 15
IDPROG.PROGVPP_14 14  Programming VPP Voltage - bit 14
IDPROG.PROGVPP_13 13  Programming VPP Voltage - bit 13
IDPROG.PROGVPP_12 12  Programming VPP Voltage - bit 12
IDPROG.PROGVPP_11 11  Programming VPP Voltage - bit 11
IDPROG.PROGVPP_10 10  Programming VPP Voltage - bit 10
IDPROG.PROGVPP_9  9   Programming VPP Voltage - bit 9 
IDPROG.PROGVPP_8  8   Programming VPP Voltage - bit 8 
IDPROG.PROGVDD_7  7   Programming VDD Voltage - bit 7 
IDPROG.PROGVDD_6  6   Programming VDD Voltage - bit 6 
IDPROG.PROGVDD_5  5   Programming VDD Voltage - bit 5 
IDPROG.PROGVDD_4  4   Programming VDD Voltage - bit 4 
IDPROG.PROGVDD_3  3   Programming VDD Voltage - bit 3 
IDPROG.PROGVDD_2  2   Programming VDD Voltage - bit 2 
IDPROG.PROGVDD_1  1   Programming VDD Voltage - bit 1 
IDPROG.PROGVDD_0  0   Programming VDD Voltage - bit 0 
IDMEM            0xF07A   Identifier
IDMEM.Type_15     15  Type of on-chip Program Memory - bit 15
IDMEM.Type_14     14  Type of on-chip Program Memory - bit 14
IDMEM.Type_13     13  Type of on-chip Program Memory - bit 13
IDMEM.Type_12     12  Type of on-chip Program Memory - bit 12
IDMEM.Size_11     11  Size of on-chip Program Memory - bit 11
IDMEM.Size_10     10  Size of on-chip Program Memory - bit 10
IDMEM.Size_9      9   Size of on-chip Program Memory - bit 9 
IDMEM.Size_8      8   Size of on-chip Program Memory - bit 8 
IDMEM.Size_7      7   Size of on-chip Program Memory - bit 7 
IDMEM.Size_6      6   Size of on-chip Program Memory - bit 6 
IDMEM.Size_5      5   Size of on-chip Program Memory - bit 5 
IDMEM.Size_4      4   Size of on-chip Program Memory - bit 4 
IDMEM.Size_3      3   Size of on-chip Program Memory - bit 3 
IDMEM.Size_2      2   Size of on-chip Program Memory - bit 2 
IDMEM.Size_1      1   Size of on-chip Program Memory - bit 1 
IDMEM.Size_0      0   Size of on-chip Program Memory - bit 0 
IDCHIP           0xF07C   Identifier
IDCHIP.CHIPID_15  15  Device Identification - bit 15
IDCHIP.CHIPID_14  14  Device Identification - bit 14
IDCHIP.CHIPID_13  13  Device Identification - bit 13
IDCHIP.CHIPID_12  12  Device Identification - bit 12
IDCHIP.CHIPID_11  11  Device Identification - bit 11
IDCHIP.CHIPID_10  10  Device Identification - bit 10
IDCHIP.CHIPID_9   9   Device Identification - bit 9
IDCHIP.CHIPID_8   8   Device Identification - bit 8
IDCHIP.Revision_7 7   Device Revision Code - bit 7
IDCHIP.Revision_6 6   Device Revision Code - bit 6
IDCHIP.Revision_5 5   Device Revision Code - bit 5
IDCHIP.Revision_4 4   Device Revision Code - bit 4
IDCHIP.Revision_3 3   Device Revision Code - bit 3
IDCHIP.Revision_2 2   Device Revision Code - bit 2
IDCHIP.Revision_1 1   Device Revision Code - bit 1
IDCHIP.Revision_0 0   Device Revision Code - bit 0
IDMANUF          0xF07E   Identifier
IDMANUF.MANUF_15  15  Manufacturer - bit 15
IDMANUF.MANUF_14  14  Manufacturer - bit 14
IDMANUF.MANUF_13  13  Manufacturer - bit 13
IDMANUF.MANUF_12  12  Manufacturer - bit 12
IDMANUF.MANUF_11  11  Manufacturer - bit 11
IDMANUF.MANUF_10  10  Manufacturer - bit 10
IDMANUF.MANUF_9   9   Manufacturer - bit 9 
IDMANUF.MANUF_8   8   Manufacturer - bit 8 
IDMANUF.MANUF_7   7   Manufacturer - bit 7 
IDMANUF.MANUF_6   6   Manufacturer - bit 6 
IDMANUF.MANUF_5   5   Manufacturer - bit 5 
IDMANUF.DEPT_4    4   Department - bit 4 
IDMANUF.DEPT_3    3   Department - bit 3 
IDMANUF.DEPT_2    2   Department - bit 2 
IDMANUF.DEPT_1    1   Department - bit 1 
IDMANUF.DEPT_0    0   Department - bit 0 
SSCTB            0xF0B0   SSC Transmit Buffer (WO)
SSCRB            0xF0B2   SSC Receive Buffer (RO)
SSCBR            0xF0B4   SSC Baudrate Register
SSCCLC           0xF0B6   SSC Clock Control Register
SSCCLC.EXDISR     3   External Disable Request
SSCCLC.SUSPEN     2   Peripheral Suspend Enable Bit for OCDS
SSCCLC.SSCDISS    1   SSC Disable Status Bit
SSCCLC.SSCDISR    0   SSC Disable Request Bit
SCUSLC           0xF0C0   Security Level Control Register
SCUSLC.COMMAND_15 15
SCUSLC.COMMAND_14 14
SCUSLC.COMMAND_13 13
SCUSLC.COMMAND_12 12
SCUSLC.COMMAND_11 11
SCUSLC.COMMAND_10 10
SCUSLC.COMMAND_9  9 
SCUSLC.COMMAND_8  8 
SCUSLC.COMMAND_7  7 
SCUSLC.COMMAND_6  6 
SCUSLC.COMMAND_5  5 
SCUSLC.COMMAND_4  4 
SCUSLC.COMMAND_3  3 
SCUSLC.COMMAND_2  2 
SCUSLC.COMMAND_1  1 
SCUSLC.COMMAND_0  0 
SCUSLS           0xF0C2   Security Level Status Register
SCUSLS.STATE_15   15  Actual State - bit 15
SCUSLS.STATE_14   14  Actual State - bit 14
SCUSLS.STATE_13   13  Actual State - bit 13
SCUSLS.SL_12      12  Security Level - bit 12
SCUSLS.SL_11      11  Security Level - bit 11
SCUSLS.PASSWORD_7 7   Current Password - bit 7
SCUSLS.PASSWORD_6 6   Current Password - bit 6
SCUSLS.PASSWORD_5 5   Current Password - bit 5
SCUSLS.PASSWORD_4 4   Current Password - bit 4
SCUSLS.PASSWORD_3 3   Current Password - bit 3
SCUSLS.PASSWORD_2 2   Current Password - bit 2
SCUSLS.PASSWORD_1 1   Current Password - bit 1
SCUSLS.PASSWORD_0 0   Current Password - bit 0
RTCCLC           0xF0C8   RTC Clock Control Register
RTCCLC.EXDISR     3   External Disable Request
RTCCLC.SUSPEN     2   Peripheral Suspend Enable Bit for OCDS
RTCCLC.RTCDISS    1   RTC Disable Status Bit
RTCCLC.RTCDISR    0   RTC Disable Request Bit
RTCRELL          0xF0CC   RTC Timer Reload Register Low
RTCRELH          0xF0CE   RTC Timer Reload Register High
T14REL           0xF0D0   Timer 14 Reload Register
T14              0xF0D2   Timer 14 Register
RTCL             0xF0D4   RTC Timer Register Low
RTCH             0xF0D6   RTC Timer Register High
DTIDR            0xF0D8   Task ID register1)
DP0L             0xF100   P0L Direction Control Register
DP0L.DP0L7        7   Port direction register DP0L bit 7
DP0L.DP0L6        6   Port direction register DP0L bit 6
DP0L.DP0L5        5   Port direction register DP0L bit 5
DP0L.DP0L4        4   Port direction register DP0L bit 4
DP0L.DP0L3        3   Port direction register DP0L bit 3
DP0L.DP0L2        2   Port direction register DP0L bit 2
DP0L.DP0L1        1   Port direction register DP0L bit 1
DP0L.DP0L0        0   Port direction register DP0L bit 0
DP0H             0xF102   P0H Direction Control Register
DP0H.DP0H7        7   Port direction register DP0H bit 7
DP0H.DP0H6        6   Port direction register DP0H bit 6
DP0H.DP0H5        5   Port direction register DP0H bit 5
DP0H.DP0H4        4   Port direction register DP0H bit 4
DP0H.DP0H3        3   Port direction register DP0H bit 3
DP0H.DP0H2        2   Port direction register DP0H bit 2
DP0H.DP0H1        1   Port direction register DP0H bit 1
DP0H.DP0H0        0   Port direction register DP0H bit 0
DP1L             0xF104   P1L Direction Control Register
DP1L.DP1L7        7   Port direction register DP1L bit 7
DP1L.DP1L6        6   Port direction register DP1L bit 6
DP1L.DP1L5        5   Port direction register DP1L bit 5
DP1L.DP1L4        4   Port direction register DP1L bit 4
DP1L.DP1L3        3   Port direction register DP1L bit 3
DP1L.DP1L2        2   Port direction register DP1L bit 2
DP1L.DP1L1        1   Port direction register DP1L bit 1
DP1L.DP1L0        0   Port direction register DP1L bit 0
DP1H             0xF106   P1H Direction Control Register
DP1H.DP1H7        7   Port direction register DP1H bit 7
DP1H.DP1H6        6   Port direction register DP1H bit 6
DP1H.DP1H5        5   Port direction register DP1H bit 5
DP1H.DP1H4        4   Port direction register DP1H bit 4
DP1H.DP1H3        3   Port direction register DP1H bit 3
DP1H.DP1H2        2   Port direction register DP1H bit 2
DP1H.DP1H1        1   Port direction register DP1H bit 1
DP1H.DP1H0        0   Port direction register DP1L bit 0
RP0H             0xF108   System Startup Configuration
RP0H.CLKCFG_7     7   Clock Generation Mode Configuration - bit 7
RP0H.CLKCFG_6     6   Clock Generation Mode Configuration - bit 6
RP0H.CLKCFG_5     5   Clock Generation Mode Configuration - bit 5
RP0H.SALSEL_4     4   Segment Address Line Selection - bit 4
RP0H.SALSEL_3     3   Segment Address Line Selection - bit 3
RP0H.CSSEL_2      2   Chip Select Line Selection - bit 2
RP0H.CSSEL_1      1   Chip Select Line Selection - bit 1
RP0H.WRC          0   Write Configuration
XBCON1           0xF114   XBUS Control register 1: IOM-2 module
XBCON1.RDYEN1     12  READY Enable
XBCON1.BSWC1      11  BUSCON Switch Control
XBCON1.BUSACT1    10  Bus Active Control
XBCON1.ALECTL1    9   ALE Lengthening Control Bit
XBCON1.EWEN1      8   Early Write Enable
XBCON1.BTYP1_7    7   Bus Type Selection - bit 7
XBCON1.BTYP1_6    6   Bus Type Selection - bit 6
XBCON1.MTTC1      5   Memory Tri-state Time Control
XBCON1.RWDC1      4   READ/WRITE Delay Control
XBCON1.MCTC1_3    3   Memory Cycle Time Control - bit 3
XBCON1.MCTC1_2    2   Memory Cycle Time Control - bit 2
XBCON1.MCTC1_1    1   Memory Cycle Time Control - bit 1
XBCON1.MCTC1_0    0   Memory Cycle Time Control - bit 0
XBCON2           0xF116   XBUS Control register 2: reserved
XBCON2.RDYEN2     12  READY Enable
XBCON2.BSWC2      11  BUSCON Switch Control
XBCON2.BUSACT2    10  Bus Active Control
XBCON2.ALECTL2    9   ALE Lengthening Control Bit
XBCON2.EWEN2      8   Early Write Enable
XBCON2.BTYP2_7    7   Bus Type Selection - bit 7
XBCON2.BTYP2_6    6   Bus Type Selection - bit 6
XBCON2.MTTC2      5   Memory Tri-state Time Control
XBCON2.RWDC2      4   READ/WRITE Delay Control
XBCON2.MCTC2_3    3   Memory Cycle Time Control - bit 3
XBCON2.MCTC2_2    2   Memory Cycle Time Control - bit 2
XBCON2.MCTC2_1    1   Memory Cycle Time Control - bit 1
XBCON2.MCTC2_0    0   Memory Cycle Time Control - bit 0
XBCON3           0xF118   XBUS Control register 3: reserved
XBCON3.RDYEN3     12  READY Enable
XBCON3.BSWC3      11  BUSCON Switch Control
XBCON3.BUSACT3    10  Bus Active Control
XBCON3.ALECTL3    9   ALE Lengthening Control Bit
XBCON3.EWEN3      8   Early Write Enable
XBCON3.BTYP3_7    7   Bus Type Selection - bit 7
XBCON3.BTYP3_6    6   Bus Type Selection - bit 6
XBCON3.MTTC3      5   Memory Tri-state Time Control
XBCON3.RWDC3      4   READ/WRITE Delay Control
XBCON3.MCTC3_3    3   Memory Cycle Time Control - bit 3
XBCON3.MCTC3_2    2   Memory Cycle Time Control - bit 2
XBCON3.MCTC3_1    1   Memory Cycle Time Control - bit 1
XBCON3.MCTC3_0    0   Memory Cycle Time Control - bit 0
XBCON4           0xF11A   XBUS Control register 3: reserved
XBCON5           0xF11C   XBUS Control register 5: reserved
XBCON6           0xF11E   XBUS Control register 6: reserved
UTD3IC           0xF160   UDC TX Done3  Interrupt Control Register
UTD3IC.UTD3IR     7   Interrupt Request Flag
UTD3IC.UTD3IE     6   Interrupt Enable Control Bit
UTD3IC.ILVL_5     5   Interrupt Priority Level - bit 5
UTD3IC.ILVL_4     4   Interrupt Priority Level - bit 4
UTD3IC.ILVL_3     3   Interrupt Priority Level - bit 3
UTD3IC.ILVL_2     2   Interrupt Priority Level - bit 2
UTD3IC.GLVL_1     1   Group Level - bit 1
UTD3IC.GLVL_0     0   Group Level - bit 0
UTD4IC           0xF162   UDC TX Done4  Interrupt Control Register
UTD4IC.UTD4IR     7   Interrupt Request Flag
UTD4IC.UTD4IE     6   Interrupt Enable Control Bit
UTD4IC.ILVL_5     5   Interrupt Priority Level - bit 5
UTD4IC.ILVL_4     4   Interrupt Priority Level - bit 4
UTD4IC.ILVL_3     3   Interrupt Priority Level - bit 3
UTD4IC.ILVL_2     2   Interrupt Priority Level - bit 2
UTD4IC.GLVL_1     1   Group Level - bit 1
UTD4IC.GLVL_0     0   Group Level - bit 0
UTD5IC           0xF164   UDC TX Done5  Interrupt Control Register
UTD5IC.UTD5IR     7   Interrupt Request Flag
UTD5IC.UTD5IE     6   Interrupt Enable Control Bit
UTD5IC.ILVL_5     5   Interrupt Priority Level - bit 5
UTD5IC.ILVL_4     4   Interrupt Priority Level - bit 4
UTD5IC.ILVL_3     3   Interrupt Priority Level - bit 3
UTD5IC.ILVL_2     2   Interrupt Priority Level - bit 2
UTD5IC.GLVL_1     1   Group Level - bit 1
UTD5IC.GLVL_0     0   Group Level - bit 0
UTD6IC           0xF166   UDC TX Done6  Interrupt Control Register
UTD6IC.UTD6IR     7   Interrupt Request Flag
UTD6IC.UTD6IE     6   Interrupt Enable Control Bit
UTD6IC.ILVL_5     5   Interrupt Priority Level - bit 5
UTD6IC.ILVL_4     4   Interrupt Priority Level - bit 4
UTD6IC.ILVL_3     3   Interrupt Priority Level - bit 3
UTD6IC.ILVL_2     2   Interrupt Priority Level - bit 2
UTD6IC.GLVL_1     1   Group Level - bit 1
UTD6IC.GLVL_0     0   Group Level - bit 0
UTD7IC           0xF168   UDC TX Done7  Interrupt Control Register
UTD7IC.UTD7IR     7   Interrupt Request Flag
UTD7IC.UTD7IE     6   Interrupt Enable Control Bit
UTD7IC.ILVL_5     5   Interrupt Priority Level - bit 5
UTD7IC.ILVL_4     4   Interrupt Priority Level - bit 4
UTD7IC.ILVL_3     3   Interrupt Priority Level - bit 3
UTD7IC.ILVL_2     2   Interrupt Priority Level - bit 2
UTD7IC.GLVL_1     1   Group Level - bit 1
UTD7IC.GLVL_0     0   Group Level - bit 0
URXRIC           0xF16A   UDC RXRR  Interrupt Control Register
URXRIC.URXRIR     7   Interrupt Request Flag          
URXRIC.URXRIE     6   Interrupt Enable Control Bit    
URXRIC.ILVL_5     5   Interrupt Priority Level - bit 5
URXRIC.ILVL_4     4   Interrupt Priority Level - bit 4
URXRIC.ILVL_3     3   Interrupt Priority Level - bit 3
URXRIC.ILVL_2     2   Interrupt Priority Level - bit 2
URXRIC.GLVL_1     1   Group Level - bit 1             
URXRIC.GLVL_0     0   Group Level - bit 0             
UTXRIC           0xF16C   UDC TXWR  Interrupt Control Register
UTXRIC.UTXRIR     7   Interrupt Request Flag          
UTXRIC.UTXRIE     6   Interrupt Enable Control Bit    
UTXRIC.ILVL_5     5   Interrupt Priority Level - bit 5
UTXRIC.ILVL_4     4   Interrupt Priority Level - bit 4
UTXRIC.ILVL_3     3   Interrupt Priority Level - bit 3
UTXRIC.ILVL_2     2   Interrupt Priority Level - bit 2
UTXRIC.GLVL_1     1   Group Level - bit 1             
UTXRIC.GLVL_0     0   Group Level - bit 0
UCFGVIC          0xF16E   UDC Config Val Interrupt Control Register
UCFGVIC.UCFGVIR   7   Interrupt Request Flag          
UCFGVIC.UCFGVIE   6   Interrupt Enable Control Bit    
UCFGVIC.ILVL_5    5   Interrupt Priority Level - bit 5
UCFGVIC.ILVL_4    4   Interrupt Priority Level - bit 4
UCFGVIC.ILVL_3    3   Interrupt Priority Level - bit 3
UCFGVIC.ILVL_2    2   Interrupt Priority Level - bit 2
UCFGVIC.GLVL_1    1   Group Level - bit 1             
UCFGVIC.GLVL_0    0   Group Level - bit 0
USOFIC           0xF170   UDC Start of Frame Interrupt Control Register
USOFIC.USOFIR     7   Interrupt Request Flag          
USOFIC.USOFIE     6   Interrupt Enable Control Bit    
USOFIC.ILVL_5     5   Interrupt Priority Level - bit 5
USOFIC.ILVL_4     4   Interrupt Priority Level - bit 4
USOFIC.ILVL_3     3   Interrupt Priority Level - bit 3
USOFIC.ILVL_2     2   Interrupt Priority Level - bit 2
USOFIC.GLVL_1     1   Group Level - bit 1             
USOFIC.GLVL_0     0   Group Level - bit 0
USSOIC           0xF172   UDC Suspend  off Interrupt Control Register
USSOIC.USSOIR     7   Interrupt Request Flag          
USSOIC.USSOIE     6   Interrupt Enable Control Bit    
USSOIC.ILVL_5     5   Interrupt Priority Level - bit 5
USSOIC.ILVL_4     4   Interrupt Priority Level - bit 4
USSOIC.ILVL_3     3   Interrupt Priority Level - bit 3
USSOIC.ILVL_2     2   Interrupt Priority Level - bit 2
USSOIC.GLVL_1     1   Group Level - bit 1             
USSOIC.GLVL_0     0   Group Level - bit 0
USSIC            0xF174   UDC Suspend  Interrupt Control Register
USSIC.USSIR       7   Interrupt Request Flag
USSIC.USSIE       6   Interrupt Enable Control Bit
USSIC.ILVL_5      5   Interrupt Priority Level - bit 5
USSIC.ILVL_4      4   Interrupt Priority Level - bit 4
USSIC.ILVL_3      3   Interrupt Priority Level - bit 3
USSIC.ILVL_2      2   Interrupt Priority Level - bit 2
USSIC.GLVL_1      1   Group Level - bit 1
USSIC.GLVL_0      0   Group Level - bit 0
ULCDIC           0xF176   UDC Load Config Done  Interrupt Control Register
ULCDIC.ULCDIR     7   Interrupt Request Flag          
ULCDIC.ULCDIE     6   Interrupt Enable Control Bit    
ULCDIC.ILVL_5     5   Interrupt Priority Level - bit 5
ULCDIC.ILVL_4     4   Interrupt Priority Level - bit 4
ULCDIC.ILVL_3     3   Interrupt Priority Level - bit 3
ULCDIC.ILVL_2     2   Interrupt Priority Level - bit 2
ULCDIC.GLVL_1     1   Group Level - bit 1             
ULCDIC.GLVL_0     0   Group Level - bit 0
USETIC           0xF178   UDC SETUP Interrupt Control Register
USETIC.USETIR     7   Interrupt Request Flag          
USETIC.USETIE     6   Interrupt Enable Control Bit    
USETIC.ILVL_5     5   Interrupt Priority Level - bit 5
USETIC.ILVL_4     4   Interrupt Priority Level - bit 4
USETIC.ILVL_3     3   Interrupt Priority Level - bit 3
USETIC.ILVL_2     2   Interrupt Priority Level - bit 2
USETIC.GLVL_1     1   Group Level - bit 1             
USETIC.GLVL_0     0   Group Level - bit 0
URD0IC           0xF17A   UDC RX Done0  Interrupt Control Register
URD0IC.URD0IR     7   Interrupt Request Flag          
URD0IC.URD0IE     6   Interrupt Enable Control Bit    
URD0IC.ILVL_5     5   Interrupt Priority Level - bit 5
URD0IC.ILVL_4     4   Interrupt Priority Level - bit 4
URD0IC.ILVL_3     3   Interrupt Priority Level - bit 3
URD0IC.ILVL_2     2   Interrupt Priority Level - bit 2
URD0IC.GLVL_1     1   Group Level - bit 1             
URD0IC.GLVL_0     0   Group Level - bit 0
IOMC0TIC         0xF17E   IOM-2 Channel0 TX Interrupt Control Register
IOMC0TIC.IOMC0TIR 7   Interrupt Request Flag          
IOMC0TIC.IOMC0TIE 6   Interrupt Enable Control Bit    
IOMC0TIC.ILVL_5   5   Interrupt Priority Level - bit 5
IOMC0TIC.ILVL_4   4   Interrupt Priority Level - bit 4
IOMC0TIC.ILVL_3   3   Interrupt Priority Level - bit 3
IOMC0TIC.ILVL_2   2   Interrupt Priority Level - bit 2
IOMC0TIC.GLVL_1   1   Group Level - bit 1             
IOMC0TIC.GLVL_0   0   Group Level - bit 0             
PECCLIC          0xF180   PEC Channel Link Interrupt Control Register
PECCLIC.PECCLIR   7   Interrupt Request Flag          
PECCLIC.PECCLIE   6   Interrupt Enable Control Bit    
PECCLIC.ILVL_5    5   Interrupt Priority Level - bit 5
PECCLIC.ILVL_4    4   Interrupt Priority Level - bit 4
PECCLIC.ILVL_3    3   Interrupt Priority Level - bit 3
PECCLIC.ILVL_2    2   Interrupt Priority Level - bit 2
PECCLIC.GLVL_1    1   Group Level - bit 1             
PECCLIC.GLVL_0    0   Group Level - bit 0
IOMC0RIC         0xF182   IOM-2 Channel0 RX Interrupt Control Register
IOMC0RIC.IOMC0RIR 7   Interrupt Request Flag          
IOMC0RIC.IOMC0RIE 6   Interrupt Enable Control Bit    
IOMC0RIC.ILVL_5   5   Interrupt Priority Level - bit 5
IOMC0RIC.ILVL_4   4   Interrupt Priority Level - bit 4
IOMC0RIC.ILVL_3   3   Interrupt Priority Level - bit 3
IOMC0RIC.ILVL_2   2   Interrupt Priority Level - bit 2
IOMC0RIC.GLVL_1   1   Group Level - bit 1             
IOMC0RIC.GLVL_0   0   Group Level - bit 0             
RTC_INTIC        0xF184   RTC_INT Sub Node Interrupt Register
RTC_INTIC.RTC_INTIR 7 Interrupt Request Flag          
RTC_INTIC.RTC_INTIE 6 Interrupt Enable Control Bit    
RTC_INTIC.ILVL_5   5  Interrupt Priority Level - bit 5
RTC_INTIC.ILVL_4   4  Interrupt Priority Level - bit 4
RTC_INTIC.ILVL_3   3  Interrupt Priority Level - bit 3
RTC_INTIC.ILVL_2   2  Interrupt Priority Level - bit 2
RTC_INTIC.GLVL_1   1  Group Level - bit 1             
RTC_INTIC.GLVL_0   0  Group Level - bit 0             
XP0IC            0xF186   X-Bus Peripheral 0 UDC TXWR Interrupt Control Register
XP0IC.XP0IR       7   Interrupt Request Flag
XP0IC.XP0IE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
XP0IC.ILVL_5      5   Interrupt Priority Level - bit 5
XP0IC.ILVL_4      4   Interrupt Priority Level - bit 4
XP0IC.ILVL_3      3   Interrupt Priority Level - bit 3
XP0IC.ILVL_2      2   Interrupt Priority Level - bit 2
XP0IC.GLVL_1      1   Group Level - bit 1
XP0IC.GLVL_0      0   Group Level - bit 0
IOMC1TIC         0xF18A   IOM-2 Channel1 TX Interrupt Control Register
IOMC1TIC.IOMC1TIR 7   Interrupt Request Flag
IOMC1TIC.IOMC1TIE 6   Interrupt Enable Control Bit
IOMC1TIC.ILVL_5   5   Interrupt Priority Level - bit 5
IOMC1TIC.ILVL_4   4   Interrupt Priority Level - bit 4
IOMC1TIC.ILVL_3   3   Interrupt Priority Level - bit 3
IOMC1TIC.ILVL_2   2   Interrupt Priority Level - bit 2
IOMC1TIC.GLVL_1   1   Group Level - bit 1
IOMC1TIC.GLVL_0   0   Group Level - bit 0
ABENDIC          0xF18C   ASC Autobaud End Interrupt Control Register
ABENDIC.ABENDIR   7   Interrupt Request Flag
ABENDIC.ABENDIE   6   Interrupt Enable Control Bit (individually enables/disables a specific source)
ABENDIC.ILVL_5    5   Interrupt Priority Level - bit 5
ABENDIC.ILVL_4    4   Interrupt Priority Level - bit 4
ABENDIC.ILVL_3    3   Interrupt Priority Level - bit 3
ABENDIC.ILVL_2    2   Interrupt Priority Level - bit 2
ABENDIC.GLVL_1    1   Group Level - bit 1
ABENDIC.GLVL_0    0   Group Level - bit 0
XP1IC            0xF18E   X-Bus Peripheral 1 Register
IOMC1RIC         0xF192   IOM-2 Channel1 RX Interrupt Control Register
IOMC1RIC.IOMC1RIR 7   Interrupt Request Flag          
IOMC1RIC.IOMC1RIE 6   Interrupt Enable Control Bit    
IOMC1RIC.ILVL_5   5   Interrupt Priority Level - bit 5
IOMC1RIC.ILVL_4   4   Interrupt Priority Level - bit 4
IOMC1RIC.ILVL_3   3   Interrupt Priority Level - bit 3
IOMC1RIC.ILVL_2   2   Interrupt Priority Level - bit 2
IOMC1RIC.GLVL_1   1   Group Level - bit 1             
IOMC1RIC.GLVL_0   0   Group Level - bit 0             
ABSTIC           0xF194   ASC Autobaud Start Interrupt Control Register
ABSTIC.ABSTIR     7   Interrupt Request Flag
ABSTIC.ABSTIE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
ABSTIC.ILVL_5     5   Interrupt Priority Level - bit 5
ABSTIC.ILVL_4     4   Interrupt Priority Level - bit 4
ABSTIC.ILVL_3     3   Interrupt Priority Level - bit 3
ABSTIC.ILVL_2     2   Interrupt Priority Level - bit 2
ABSTIC.GLVL_1     1   Group Level - bit 1
ABSTIC.GLVL_0     0   Group Level - bit 0
XP2IC            0xF196   X-Bus Peripheral 2 IOM-2 IO Interrupt Controol Register
XP2IC.XP2IR       7   Interrupt Request Flag
XP2IC.XP2IE       6   Interrupt Enable Control Bit
XP2IC.ILVL_5      5   Interrupt Priority Level - bit 5
XP2IC.ILVL_4      4   Interrupt Priority Level - bit 4
XP2IC.ILVL_3      3   Interrupt Priority Level - bit 3
XP2IC.ILVL_2      2   Interrupt Priority Level - bit 2
XP2IC.GLVL_1      1   Group Level - bit 1
XP2IC.GLVL_0      0   Group Level - bit 0
RES6IC           0xF19A   reserved
S0TBIC           0xF19C   Serial Channel 0 Transmit Buffer IC Register
XP3IC            0xF19E   X-Bus Peripheral 3 PLL/RTC
EXICON           0xF1C0   External Interrupt Control Register
EXICON.EXI7ES_15  15  External Interrupt 15 Edge Selection Field - bit 15
EXICON.EXI7ES_14  14  External Interrupt 14 Edge Selection Field - bit 14
EXICON.EXI6ES_13  13  External Interrupt 13 Edge Selection Field - bit 13
EXICON.EXI6ES_12  12  External Interrupt 12 Edge Selection Field - bit 12
EXICON.EXI5ES_11  11  External Interrupt 11 Edge Selection Field - bit 11
EXICON.EXI5ES_10  10  External Interrupt 10 Edge Selection Field - bit 10
EXICON.EXI4ES_9   9   External Interrupt 9 Edge Selection Field - bit 9 
EXICON.EXI4ES_8   8   External Interrupt 8 Edge Selection Field - bit 8 
EXICON.EXI3ES_7   7   External Interrupt 7 Edge Selection Field - bit 7 
EXICON.EXI3ES_6   6   External Interrupt 6 Edge Selection Field - bit 6 
EXICON.EXI2ES_5   5   External Interrupt 5 Edge Selection Field - bit 5 
EXICON.EXI2ES_4   4   External Interrupt 4 Edge Selection Field - bit 4 
EXICON.EXI1ES_3   3   External Interrupt 3 Edge Selection Field - bit 3 
EXICON.EXI1ES_2   2   External Interrupt 2 Edge Selection Field - bit 2 
EXICON.EXI0ES_1   1   External Interrupt 1 Edge Selection Field - bit 1 
EXICON.EXI0ES_0   0   External Interrupt 0 Edge Selection Field - bit 0 
ODP2             0xF1C2   Port 2 Open Drain Control Register
ODP2.ODP2_7       7   Port 2 Open Drain control register bit 7
ODP2.ODP2_6       6   Port 2 Open Drain control register bit 6
ODP2.ODP2_5       5   Port 2 Open Drain control register bit 5
ODP2.ODP2_4       4   Port 2 Open Drain control register bit 4
ODP2.ODP2_3       3   Port 2 Open Drain control register bit 3
ODP2.ODP2_2       2   Port 2 Open Drain control register bit 2
ODP2.ODP2_1       1   Port 2 Open Drain control register bit 1
ODP2.ODP2_0       0   Port 2 Open Drain control register bit 0
ODP3             0xF1C6   Port 3 Open
ODP3.ODP3_15      15  Port 3 Open Drain control register bit 15
ODP3.ODP3_13      13  Port 3 Open Drain control register bit 13
ODP3.ODP3_11      11  Port 3 Open Drain control register bit 11
ODP3.ODP3_10      10  Port 3 Open Drain control register bit 10
ODP3.ODP3_9       9   Port 3 Open Drain control register bit 9 
ODP3.ODP3_8       8   Port 3 Open Drain control register bit 8 
ODP3.ODP3_6       6   Port 3 Open Drain control register bit 6 
ODP3.ODP3_5       5   Port 3 Open Drain control register bit 5 
ODP3.ODP3_3       3   Port 3 Open Drain control register bit 3 
RTCISNC          0xF1C8   RTC Interrupt Sub Node Control Register
RTCISNC.RTC3IR    9   RTC3 Interrupt Request Flag (bit protected)
RTCISNC.RTC3IE    8   RTC3 Interrupt Enable Control Bit
RTCISNC.RTC2IR    7   RTC2 Interrupt Request Flag (bit protected)
RTCISNC.RTC2IE    6   RTC2 Interrupt Enable Control Bit          
RTCISNC.RTC1IR    5   RTC1 Interrupt Request Flag (bit protected)
RTCISNC.RTC1IE    4   RTC1 Interrupt Enable Control Bit          
RTCISNC.RTC0IR    3   RTC0 Interrupt Request Flag (bit protected)
RTCISNC.RTC0IE    2   RTC0 Interrupt Enable Control Bit          
RTCISNC.T14IR     1   T14 Overflow Interrupt Request Flag (bit protected)
RTCISNC.T14IE     0   T14 Overflow Interrupt Enable Control Bit
ODP4             0xF1CA   Port 4 Open Drain Control Register
ODP4.ODP4_6       6   Port 4 Open Drain control register bit 6
ODP4.ODP4_5       5   Port 4 Open Drain control register bit 5
ODP4.ODP4_4       4   Port 4 Open Drain control register bit 4 
ODP4.ODP4_3       3   Port 4 Open Drain control register bit 3 
ODP4.ODP4_2       2   Port 4 Open Drain control register bit 2 
ODP4.ODP4_1       1   Port 4 Open Drain control register bit 1 
ODP4.ODP4_0       0   Port 4 Open Drain control register bit 0 
RTCCON           0xF1CC   RTC Control Register
RTCCON.ACCPOS     15  RTC register access possible
RTCCON.T14INC     3   Increment T14 Timer Value
RTCCON.T14DEC     2   Decrement T14 Timer Value
RTCCON.RTCPRE     1   RTC Input Source Prescaler enable
RTCCON.RTCR       0   RTC Run Bit
ODP6             0xF1CE   Port 6 Open Drain Control Register
ODP6.ODP6_7       7   Port 6 Open Drain control register bit 7
ODP6.ODP6_6       6   Port 6 Open Drain control register bit 6
ODP6.ODP6_5       5   Port 6 Open Drain control register bit 5
ODP6.ODP6_4       4   Port 6 Open Drain control register bit 
ODP6.ODP6_3       3   Port 6 Open Drain control register bit 3
ODP6.ODP6_2       2   Port 6 Open Drain control register bit 2
ODP6.ODP6_1       1   Port 6 Open Drain control register bit 1
ODP6.ODP6_0       0   Port 6 Open Drain control register bit 0
SYSCON2          0xF1D0   System Configuration Register 2/Clock Control
SYSCON2.CLKLOCK   15  Clock Signal Status Bit
SYSCON2.CLKREL_14 14  Reload Counter Value for Slowdown Divider - 14
SYSCON2.CLKREL_13 13  Reload Counter Value for Slowdown Divider - 13
SYSCON2.CLKREL_12 12  Reload Counter Value for Slowdown Divider - 12
SYSCON2.CLKREL_11 11  Reload Counter Value for Slowdown Divider - 11
SYSCON2.CLKREL_10 10  Reload Counter Value for Slowdown Divider - 10
SYSCON2.CLKCON_9  9   Clock State Control - bit 9
SYSCON2.CLKCON_8  8   Clock State Control - bit 8
SYSCON2.SCS       7   SDD Clock Source
SYSCON2.RCS       6   RTC Clock Source
SYSCON2.PDCON_5   5   Power Down Control - bit 5
SYSCON2.PDCON_4   4   Power Down Control - bit 4
ODP7             0xF1D2   Port 7 Open Drain Control Register
ODP7.ODP7_5       5   Port 6 Open Drain control register bit 5
ODP7.ODP7_4       4   Port 6 Open Drain control register bit 4
ODP7.ODP7_3       3   Port 6 Open Drain control register bit 3
ODP7.ODP7_2       2   Port 6 Open Drain control register bit 2
ODP7.ODP7_1       1   Port 6 Open Drain control register bit 1
ODP7.ODP7_0       0   Port 6 Open Drain control register bit 0
SYSCON3          0xF1D4   System Configuration Register 3/Periph. Managem.
SYSCON3.GRPDIS    15  Peripheral Group Disable Flag (PD-Bus and X-Bus Peripherals)
SYSCON3.PLLDIS    13  PLL Disable Flag
SYSCON3.PERDIS8   8   Peripheral Disable Flag 0 - 14 - bit 8
SYSCON3.PERDIS7   7   Peripheral Disable Flag 0 - 14 - bit 7
SYSCON3.PERDIS6   6   Peripheral Disable Flag 0 - 14 - bit 6
SYSCON3.PERDIS3   3   Peripheral Disable Flag 0 - 14 - bit 3
SYSCON3.PERDIS2   2   Peripheral Disable Flag 0 - 14 - bit 2
SYSCON3.PERDIS1   1   Peripheral Disable Flag 0 - 14 - bit 1
SYSCON3.PERDIS0   0   Peripheral Disable Flag 0 - 14 - bit 0
reserv_F1D6      0xF1D6   reserved - do not use
reserv_F1D8      0xF1D8   reserved - do not use
EXISEL           0xF1DA   External Interrupt Select Register
EXISEL.EXI6SS_13  13  Input from default pin. - bit 13
EXISEL.EXI6SS_12  12  Input from default pin. - bit 12
EXISEL.EXI5SS_11  11  Input from default pin. - bit 11
EXISEL.EXI5SS_10  10  Input from default pin. - bit 10
EXISEL.EXI4SS_9   9   Input from default pin. - bit 9 
EXISEL.EXI4SS_8   8   Input from default pin. - bit 8 
EXISEL.EXI3SS_7   7   Input from default pin. - bit 7 
EXISEL.EXI3SS_6   6   Input from default pin. - bit 6 
EXISEL.EXI2SS_5   5   Input from default pin. - bit 5 
EXISEL.EXI2SS_4   4   Input from default pin. - bit 4 
SYSCON1          0xF1DC   System Configuration Register 1/Sleep Mode
SYSCON1.SLEEPCON_1 1  SLEEP Mode Configuration - bit 1
SYSCON1.SLEEPCON_0 0  SLEEP Mode Configuration - bit 0
ISNC             0xF1DE   Interrupt Sub Node Control Register
ISNC.PLLIE        3   PLL Interrupt Enable Control Bit
ISNC.PLLIR        2   PLL Interrupt Request Flag
ISNC.RTCT14IE     1   T14 Overflow Interrupt Enable Control Bit
ISNC.RTCT14IR     0   T14 Overflow Interrupt Request Flag
DPP0             0xFE00   CPU Data Page Pointer 0 Register (10 bits)
DPP0.DPP0PN_9     9   Data Page Number of DPP0 - bit 9
DPP0.DPP0PN_8     8   Data Page Number of DPP0 - bit 8
DPP0.DPP0PN_7     7   Data Page Number of DPP0 - bit 7
DPP0.DPP0PN_6     6   Data Page Number of DPP0 - bit 6
DPP0.DPP0PN_5     5   Data Page Number of DPP0 - bit 5
DPP0.DPP0PN_4     4   Data Page Number of DPP0 - bit 4
DPP0.DPP0PN_3     3   Data Page Number of DPP0 - bit 3
DPP0.DPP0PN_2     2   Data Page Number of DPP0 - bit 2
DPP0.DPP0PN_1     1   Data Page Number of DPP0 - bit 1
DPP0.DPP0PN_0     0   Data Page Number of DPP0 - bit 0
DPP1             0xFE02   CPU Data Page Pointer 1 Register (10 bits)
DPP1.DPP1PN_9     9   Data Page Number of DPP1 - bit 9
DPP1.DPP1PN_8     8   Data Page Number of DPP1 - bit 8
DPP1.DPP1PN_7     7   Data Page Number of DPP1 - bit 7
DPP1.DPP1PN_6     6   Data Page Number of DPP1 - bit 6
DPP1.DPP1PN_5     5   Data Page Number of DPP1 - bit 5
DPP1.DPP1PN_4     4   Data Page Number of DPP1 - bit 4
DPP1.DPP1PN_3     3   Data Page Number of DPP1 - bit 3
DPP1.DPP1PN_2     2   Data Page Number of DPP1 - bit 2
DPP1.DPP1PN_1     1   Data Page Number of DPP1 - bit 1
DPP1.DPP1PN_0     0   Data Page Number of DPP1 - bit 0
DPP2             0xFE04   CPU Data Page Pointer 2 Register (10 bits)
DPP2.DPP2PN_9     9   Data Page Number of DPP2 - bit 9
DPP2.DPP2PN_8     8   Data Page Number of DPP2 - bit 8
DPP2.DPP2PN_7     7   Data Page Number of DPP2 - bit 7
DPP2.DPP2PN_6     6   Data Page Number of DPP2 - bit 6
DPP2.DPP2PN_5     5   Data Page Number of DPP2 - bit 5
DPP2.DPP2PN_4     4   Data Page Number of DPP2 - bit 4
DPP2.DPP2PN_3     3   Data Page Number of DPP2 - bit 3
DPP2.DPP2PN_2     2   Data Page Number of DPP2 - bit 2
DPP2.DPP2PN_1     1   Data Page Number of DPP2 - bit 1
DPP2.DPP2PN_0     0   Data Page Number of DPP2 - bit 0
DPP3             0xFE06   CPU Data Page Pointer 3 Register (10 bits)
DPP3.DPP3PN_9     9   Data Page Number of DPP3 - bit 9
DPP3.DPP3PN_8     8   Data Page Number of DPP3 - bit 8
DPP3.DPP3PN_7     7   Data Page Number of DPP3 - bit 7
DPP3.DPP3PN_6     6   Data Page Number of DPP3 - bit 6
DPP3.DPP3PN_5     5   Data Page Number of DPP3 - bit 5
DPP3.DPP3PN_4     4   Data Page Number of DPP3 - bit 4
DPP3.DPP3PN_3     3   Data Page Number of DPP3 - bit 3
DPP3.DPP3PN_2     2   Data Page Number of DPP3 - bit 2
DPP3.DPP3PN_1     1   Data Page Number of DPP3 - bit 1
DPP3.DPP3PN_0     0   Data Page Number of DPP3 - bit 0
CSP              0xFE08   CPU Code Segment Pointer Register (8 bits)
CSP.SEGNR_7       7   Segment Number - bit 7
CSP.SEGNR_6       6   Segment Number - bit 6
CSP.SEGNR_5       5   Segment Number - bit 5
CSP.SEGNR_4       4   Segment Number - bit 4
CSP.SEGNR_3       3   Segment Number - bit 3
CSP.SEGNR_2       2   Segment Number - bit 2
CSP.SEGNR_1       1   Segment Number - bit 1
CSP.SEGNR_0       0   Segment Number - bit 0
EMUCON           0xFE0A   Emulation Control Register2)
MDH              0xFE0C   CPU Multiply Divide Register - High Word
MDH.mdh_15        15
MDH.mdh_14        14
MDH.mdh_13        13
MDH.mdh_12        12
MDH.mdh_11        11
MDH.mdh_10        10
MDH.mdh_9         9 
MDH.mdh_8         8 
MDH.mdh_7         7 
MDH.mdh_6         6 
MDH.mdh_5         5 
MDH.mdh_4         4 
MDH.mdh_3         3 
MDH.mdh_2         2 
MDH.mdh_1         1 
MDH.mdh_0         0 
MDL              0xFE0E   CPU Multiply Divide Register - Low Word
MDL.MDL_15        15
MDL.MDL_14        14
MDL.MDL_13        13
MDL.MDL_12        12
MDL.MDL_11        11
MDL.MDL_10        10
MDL.MDL_9         9 
MDL.MDL_8         8 
MDL.MDL_7         7 
MDL.MDL_6         6 
MDL.MDL_5         5 
MDL.MDL_4         4 
MDL.MDL_3         3 
MDL.MDL_2         2 
MDL.MDL_1         1 
MDL.MDL_0         0 
CP               0xFE10   CPU Context Pointer Register
CP.cp_11          11  Modifiable portion of register CP - bit 11
CP.cp_10          10  Modifiable portion of register CP - bit 10
CP.cp_9           9   Modifiable portion of register CP - bit 9
CP.cp_8           8   Modifiable portion of register CP - bit 8
CP.cp_7           7   Modifiable portion of register CP - bit 7
CP.cp_6           6   Modifiable portion of register CP - bit 6
CP.cp_5           5   Modifiable portion of register CP - bit 5
CP.cp_4           4   Modifiable portion of register CP - bit 4
CP.cp_3           3   Modifiable portion of register CP - bit 3
CP.cp_2           2   Modifiable portion of register CP - bit 2
CP.cp_1           1   Modifiable portion of register CP - bit 1
SP               0xFE12   CPU System Stack Pointer Register
SP.sp_11          11  Modifiable portion of register SP - bit 11
SP.sp_10          10  Modifiable portion of register SP - bit 10
SP.sp_9           9   Modifiable portion of register SP - bit 9
SP.sp_8           8   Modifiable portion of register SP - bit 8
SP.sp_7           7   Modifiable portion of register SP - bit 7
SP.sp_6           6   Modifiable portion of register SP - bit 6
SP.sp_5           5   Modifiable portion of register SP - bit 5
SP.sp_4           4   Modifiable portion of register SP - bit 4
SP.sp_3           3   Modifiable portion of register SP - bit 3
SP.sp_2           2   Modifiable portion of register SP - bit 2
SP.sp_1           1   Modifiable portion of register SP - bit 1
STKOV            0xFE14   CPU Stack Overflow Pointer Register
STKOV.stkov_11    11  Modifiable portion of register STKOV - bit 11
STKOV.stkov_10    10  Modifiable portion of register STKOV - bit 10
STKOV.stkov_9     9   Modifiable portion of register STKOV - bit 9
STKOV.stkov_8     8   Modifiable portion of register STKOV - bit 8
STKOV.stkov_7     7   Modifiable portion of register STKOV - bit 7
STKOV.stkov_6     6   Modifiable portion of register STKOV - bit 6
STKOV.stkov_5     5   Modifiable portion of register STKOV - bit 5
STKOV.stkov_4     4   Modifiable portion of register STKOV - bit 4
STKOV.stkov_3     3   Modifiable portion of register STKOV - bit 3
STKOV.stkov_2     2   Modifiable portion of register STKOV - bit 2
STKOV.stkov_1     1   Modifiable portion of register STKOV - bit 1
STKUN            0xFE16   CPU Stack Underflow Pointer Register
STKUN.STKUN_11    11  Modifiable portion of register STKUN - bit 11
STKUN.STKUN_10    10  Modifiable portion of register STKUN - bit 10
STKUN.STKUN_9     9   Modifiable portion of register STKUN - bit 9
STKUN.STKUN_8     8   Modifiable portion of register STKUN - bit 8
STKUN.STKUN_7     7   Modifiable portion of register STKUN - bit 7
STKUN.STKUN_6     6   Modifiable portion of register STKUN - bit 6
STKUN.STKUN_5     5   Modifiable portion of register STKUN - bit 5
STKUN.STKUN_4     4   Modifiable portion of register STKUN - bit 4
STKUN.STKUN_3     3   Modifiable portion of register STKUN - bit 3
STKUN.STKUN_2     2   Modifiable portion of register STKUN - bit 2
STKUN.STKUN_1     1   Modifiable portion of register STKUN - bit 1
ADDRSEL1         0xFE18   Address Select Register 1
ADDRSEL1.RGSAD15  15  Range Start Address bit 15
ADDRSEL1.RGSAD14  14  Range Start Address bit 14
ADDRSEL1.RGSAD13  13  Range Start Address bit 13
ADDRSEL1.RGSAD12  12  Range Start Address bit 12
ADDRSEL1.RGSAD11  11  Range Start Address bit 11
ADDRSEL1.RGSAD10  10  Range Start Address bit 10
ADDRSEL1.RGSAD9   9   Range Start Address bit 9 
ADDRSEL1.RGSAD8   8   Range Start Address bit 8 
ADDRSEL1.RGSAD7   7   Range Start Address bit 7 
ADDRSEL1.RGSAD6   6   Range Start Address bit 6 
ADDRSEL1.RGSAD5   5   Range Start Address bit 5 
ADDRSEL1.RGSAD4   4   Range Start Address bit 4 
ADDRSEL1.RGSZ3    3   Range Size Selection bit 3
ADDRSEL1.RGSZ2    2   Range Size Selection bit 2
ADDRSEL1.RGSZ1    1   Range Size Selection bit 1
ADDRSEL1.RGSZ0    0   Range Size Selection bit 0
ADDRSEL2         0xFE1A   Address Select Register 2
ADDRSEL2.RGSAD15  15  Range Start Address bit 15
ADDRSEL2.RGSAD14  14  Range Start Address bit 14
ADDRSEL2.RGSAD13  13  Range Start Address bit 13
ADDRSEL2.RGSAD12  12  Range Start Address bit 12
ADDRSEL2.RGSAD11  11  Range Start Address bit 11
ADDRSEL2.RGSAD10  10  Range Start Address bit 10
ADDRSEL2.RGSAD9   9   Range Start Address bit 9 
ADDRSEL2.RGSAD8   8   Range Start Address bit 8 
ADDRSEL2.RGSAD7   7   Range Start Address bit 7 
ADDRSEL2.RGSAD6   6   Range Start Address bit 6 
ADDRSEL2.RGSAD5   5   Range Start Address bit 5 
ADDRSEL2.RGSAD4   4   Range Start Address bit 4 
ADDRSEL2.RGSZ3    3   Range Size Selection bit 3
ADDRSEL2.RGSZ2    2   Range Size Selection bit 2
ADDRSEL2.RGSZ1    1   Range Size Selection bit 1
ADDRSEL2.RGSZ0    0   Range Size Selection bit 0
ADDRSEL3         0xFE1C   Address Select Register 3
ADDRSEL3.RGSAD15  15  Range Start Address bit 15
ADDRSEL3.RGSAD14  14  Range Start Address bit 14
ADDRSEL3.RGSAD13  13  Range Start Address bit 13
ADDRSEL3.RGSAD12  12  Range Start Address bit 12
ADDRSEL3.RGSAD11  11  Range Start Address bit 11
ADDRSEL3.RGSAD10  10  Range Start Address bit 10
ADDRSEL3.RGSAD9   9   Range Start Address bit 9 
ADDRSEL3.RGSAD8   8   Range Start Address bit 8 
ADDRSEL3.RGSAD7   7   Range Start Address bit 7 
ADDRSEL3.RGSAD6   6   Range Start Address bit 6 
ADDRSEL3.RGSAD5   5   Range Start Address bit 5 
ADDRSEL3.RGSAD4   4   Range Start Address bit 4 
ADDRSEL3.RGSZ3    3   Range Size Selection bit 3
ADDRSEL3.RGSZ2    2   Range Size Selection bit 2
ADDRSEL3.RGSZ1    1   Range Size Selection bit 1
ADDRSEL3.RGSZ0    0   Range Size Selection bit 0
ADDRSEL4         0xFE1E   Address Select Register 4
ADDRSEL4.RGSAD15  15  Range Start Address bit 15
ADDRSEL4.RGSAD14  14  Range Start Address bit 14
ADDRSEL4.RGSAD13  13  Range Start Address bit 13
ADDRSEL4.RGSAD12  12  Range Start Address bit 12
ADDRSEL4.RGSAD11  11  Range Start Address bit 11
ADDRSEL4.RGSAD10  10  Range Start Address bit 10
ADDRSEL4.RGSAD9   9   Range Start Address bit 9 
ADDRSEL4.RGSAD8   8   Range Start Address bit 8 
ADDRSEL4.RGSAD7   7   Range Start Address bit 7 
ADDRSEL4.RGSAD6   6   Range Start Address bit 6 
ADDRSEL4.RGSAD5   5   Range Start Address bit 5 
ADDRSEL4.RGSAD4   4   Range Start Address bit 4 
ADDRSEL4.RGSZ3    3   Range Size Selection bit 3
ADDRSEL4.RGSZ2    2   Range Size Selection bit 2
ADDRSEL4.RGSZ1    1   Range Size Selection bit 1
ADDRSEL4.RGSZ0    0   Range Size Selection bit 0
ODP0H            0xFE22   Port 0 Open Drain Control Register High
ODP0H.ODP0H7      7   Port0H Open Drain control register bit 7
ODP0H.ODP0H6      6   Port0H Open Drain control register bit 6
ODP0H.ODP0H5      5   Port0H Open Drain control register bit 5
ODP0H.ODP0H4      4   Port0H Open Drain control register bit 4
ODP0H.ODP0H3      3   Port0H Open Drain control register bit 3
ODP0H.ODP0H2      2   Port0H Open Drain control register bit 2
ODP0H.ODP0H1      1   Port0H Open Drain control register bit 1
ODP0H.ODP0H0      0   Port0H Open Drain control register bit 0
ODP1L            0xFE24   Port 1 Open Drain Control Register Low
ODP1L.ODP1L7      7   Port1L Open Drain control register bit 7
ODP1L.ODP1L6      6   Port1L Open Drain control register bit 6
ODP1L.ODP1L5      5   Port1L Open Drain control register bit 5
ODP1L.ODP1L4      4   Port1L Open Drain control register bit 4
ODP1L.ODP1L3      3   Port1L Open Drain control register bit 3
ODP1L.ODP1L2      2   Port1L Open Drain control register bit 2
ODP1L.ODP1L1      1   Port1L Open Drain control register bit 1
ODP1L.ODP1L0      0   Port1L Open Drain control register bit 0
ODP1H            0xFE26   Port 1 Open Drain Control Register High
ODP1H.ODP1H7      7   Port1H Open Drain control register bit 7
ODP1H.ODP1H6      6   Port1H Open Drain control register bit 6
ODP1H.ODP1H5      5   Port1H Open Drain control register bit 5
ODP1H.ODP1H4      4   Port1H Open Drain control register bit 4
ODP1H.ODP1H3      3   Port1H Open Drain control register bit 3
ODP1H.ODP1H2      2   Port1H Open Drain control register bit 2
ODP1H.ODP1H1      1   Port1H Open Drain control register bit 1
ODP1H.ODP1H0      0   Port1H Open Drain control register bit 0
T2               0xFE40   GPT1 Timer 2 Register
T3               0xFE42   GPT1 Timer 3 Register
T4               0xFE44   GPT1 Timer 4 Register
T5               0xFE46   GPT2 Time
T6               0xFE48   GPT2 Timer 6 Register
CAPREL           0xFE4A   GPT1/2 Capture / Reload Register
GPTCLC           0xFE4C   GPT1/2 Clock Control Register
GPTCLC.EXDISR     3   External Disable Request
GPTCLC.SUSPEN     2   Peripheral Suspend Enable Bit for OCDS
GPTCLC.GPTDISS    1   GPT Disable Status Bit
GPTCLC.GPTDISR    0   GPT Disable Request Bit
P0LPUDSEL        0xFE60   Port 0 Low Pull-Up/Down Select Register
P0LPUDSEL.P0LPUDSEL7 7  Pulldown/Pullup Selection - bit 7
P0LPUDSEL.P0LPUDSEL6 6  Pulldown/Pullup Selection - bit 6
P0LPUDSEL.P0LPUDSEL5 5  Pulldown/Pullup Selection - bit 5
P0LPUDSEL.P0LPUDSEL4 4  Pulldown/Pullup Selection - bit 4
P0LPUDSEL.P0LPUDSEL3 3  Pulldown/Pullup Selection - bit 3
P0LPUDSEL.P0LPUDSEL2 2  Pulldown/Pullup Selection - bit 2
P0LPUDSEL.P0LPUDSEL1 1  Pulldown/Pullup Selection - bit 1
P0LPUDSEL.P0LPUDSEL0 0  Pulldown/Pullup Selection - bit 0
P0HPUDSEL        0xFE62   Port 0 High Pull-Up/Down Select Register
P0HPUDSEL.P0HPUDSEL7 7  Pulldown/Pullup Selection - bit 7
P0HPUDSEL.P0HPUDSEL6 6  Pulldown/Pullup Selection - bit 6
P0HPUDSEL.P0HPUDSEL5 5  Pulldown/Pullup Selection - bit 5
P0HPUDSEL.P0HPUDSEL4 4  Pulldown/Pullup Selection - bit 4
P0HPUDSEL.P0HPUDSEL3 3  Pulldown/Pullup Selection - bit 3
P0HPUDSEL.P0HPUDSEL2 2  Pulldown/Pullup Selection - bit 2
P0HPUDSEL.P0HPUDSEL1 1  Pulldown/Pullup Selection - bit 1
P0HPUDSEL.P0HPUDSEL0 0  Pulldown/Pullup Selection - bit 0
P0LPUDEN         0xFE64   Port 0 Low Pull Switch On/Off Register
P0LPUDEN.P0LPUDEN7 7 Pulldown/Pullup Enable - bit 7
P0LPUDEN.P0LPUDEN6 6 Pulldown/Pullup Enable - bit 6
P0LPUDEN.P0LPUDEN5 5 Pulldown/Pullup Enable - bit 5
P0LPUDEN.P0LPUDEN4 4 Pulldown/Pullup Enable - bit 4
P0LPUDEN.P0LPUDEN3 3 Pulldown/Pullup Enable - bit 3
P0LPUDEN.P0LPUDEN2 2 Pulldown/Pullup Enable - bit 2
P0LPUDEN.P0LPUDEN1 1 Pulldown/Pullup Enable - bit 1
P0LPUDEN.P0LPUDEN0 0 Pulldown/Pullup Enable - bit 0
P0HPUDEN         0xFE66   Port 0 High Pull Switch On/Off Register
P0HPUDEN.P0HPUDEN7 7 Pulldown/Pullup Enable - bit 7
P0HPUDEN.P0HPUDEN6 6 Pulldown/Pullup Enable - bit 6
P0HPUDEN.P0HPUDEN5 5 Pulldown/Pullup Enable - bit 5
P0HPUDEN.P0HPUDEN4 4 Pulldown/Pullup Enable - bit 4
P0HPUDEN.P0HPUDEN3 3 Pulldown/Pullup Enable - bit 3
P0HPUDEN.P0HPUDEN2 2 Pulldown/Pullup Enable - bit 2
P0HPUDEN.P0HPUDEN1 1 Pulldown/Pullup Enable - bit 1
P0HPUDEN.P0HPUDEN0 0 Pulldown/Pullup Enable - bit 0
P0LPHEN          0xFE68   Port 0 Low Pin Hold Enable Register
P0LPHEN.P0LPHEN7  7   Output Driver Enable in Power Down Mode - bit 7
P0LPHEN.P0LPHEN6  6   Output Driver Enable in Power Down Mode - bit 6
P0LPHEN.P0LPHEN5  5   Output Driver Enable in Power Down Mode - bit 5
P0LPHEN.P0LPHEN4  4   Output Driver Enable in Power Down Mode - bit 4
P0LPHEN.P0LPHEN3  3   Output Driver Enable in Power Down Mode - bit 3
P0LPHEN.P0LPHEN2  2   Output Driver Enable in Power Down Mode - bit 2
P0LPHEN.P0LPHEN1  1   Output Driver Enable in Power Down Mode - bit 1
P0LPHEN.P0LPHEN0  0   Output Driver Enable in Power Down Mode - bit 0
P0HPHEN          0xFE6A   Port 0 High Pin Hold Enable Register
P0HPHEN.P0HPHEN7  7   Output Driver Enable in Power Down Mode - bit 7
P0HPHEN.P0HPHEN6  6   Output Driver Enable in Power Down Mode - bit 6
P0HPHEN.P0HPHEN5  5   Output Driver Enable in Power Down Mode - bit 5
P0HPHEN.P0HPHEN4  4   Output Driver Enable in Power Down Mode - bit 4
P0HPHEN.P0HPHEN3  3   Output Driver Enable in Power Down Mode - bit 3
P0HPHEN.P0HPHEN2  2   Output Driver Enable in Power Down Mode - bit 2
P0HPHEN.P0HPHEN1  1   Output Driver Enable in Power Down Mode - bit 1
P0HPHEN.P0HPHEN0  0   Output Driver Enable in Power Down Mode - bit 0
P1LPUDSEL        0xFE6C   Port 1 Low Pull-Up/Down Select Register
P1LPUDSEL.P1LPUDSEL7 7  Pulldown/Pullup Selection - bit 7
P1LPUDSEL.P1LPUDSEL6 6  Pulldown/Pullup Selection - bit 6
P1LPUDSEL.P1LPUDSEL5 5  Pulldown/Pullup Selection - bit 5
P1LPUDSEL.P1LPUDSEL4 4  Pulldown/Pullup Selection - bit 4
P1LPUDSEL.P1LPUDSEL3 3  Pulldown/Pullup Selection - bit 3
P1LPUDSEL.P1LPUDSEL2 2  Pulldown/Pullup Selection - bit 2
P1LPUDSEL.P1LPUDSEL1 1  Pulldown/Pullup Selection - bit 1
P1LPUDSEL.P1LPUDSEL0 0  Pulldown/Pullup Selection - bit 0
P1HPUDSEL        0xFE6E   Port 1 High Pull-Up/Down Select Register
P1HPUDSEL.P1HPUDSEL7 7  Pulldown/Pullup Selection - bit 7
P1HPUDSEL.P1HPUDSEL6 6  Pulldown/Pullup Selection - bit 6
P1HPUDSEL.P1HPUDSEL5 5  Pulldown/Pullup Selection - bit 5
P1HPUDSEL.P1HPUDSEL4 4  Pulldown/Pullup Selection - bit 4
P1HPUDSEL.P1HPUDSEL3 3  Pulldown/Pullup Selection - bit 3
P1HPUDSEL.P1HPUDSEL2 2  Pulldown/Pullup Selection - bit 2
P1HPUDSEL.P1HPUDSEL1 1  Pulldown/Pullup Selection - bit 1
P1HPUDSEL.P1HPUDSEL0 0  Pulldown/Pullup Selection - bit 0
P1LPUDEN         0xFE70   Port 1 Low Pull Switch On/Off Register
P1LPUDEN.P1LPUDEN7 7 Pulldown/Pullup Enable - bit 7
P1LPUDEN.P1LPUDEN6 6 Pulldown/Pullup Enable - bit 6
P1LPUDEN.P1LPUDEN5 5 Pulldown/Pullup Enable - bit 5
P1LPUDEN.P1LPUDEN4 4 Pulldown/Pullup Enable - bit 4
P1LPUDEN.P1LPUDEN3 3 Pulldown/Pullup Enable - bit 3
P1LPUDEN.P1LPUDEN2 2 Pulldown/Pullup Enable - bit 2
P1LPUDEN.P1LPUDEN1 1 Pulldown/Pullup Enable - bit 1
P1LPUDEN.P1LPUDEN0 0 Pulldown/Pullup Enable - bit 0
P1HPUDEN         0xFE72   Port 1 High Pull Switch On/Off Register
P1HPUDEN.P1HPUDEN7 7 Pulldown/Pullup Enable - bit 7
P1HPUDEN.P1HPUDEN6 6 Pulldown/Pullup Enable - bit 6
P1HPUDEN.P1HPUDEN5 5 Pulldown/Pullup Enable - bit 5
P1HPUDEN.P1HPUDEN4 4 Pulldown/Pullup Enable - bit 4
P1HPUDEN.P1HPUDEN3 3 Pulldown/Pullup Enable - bit 3
P1HPUDEN.P1HPUDEN2 2 Pulldown/Pullup Enable - bit 2
P1HPUDEN.P1HPUDEN1 1 Pulldown/Pullup Enable - bit 1
P1HPUDEN.P1HPUDEN0 0 Pulldown/Pullup Enable - bit 0
P1LPHEN          0xFE74   Port 1 Low Pin Hold Enable Register
P1LPHEN.P1LPHEN7  7   Output Driver Enable in Power Down Mode - bit 7
P1LPHEN.P1LPHEN6  6   Output Driver Enable in Power Down Mode - bit 6
P1LPHEN.P1LPHEN5  5   Output Driver Enable in Power Down Mode - bit 5
P1LPHEN.P1LPHEN4  4   Output Driver Enable in Power Down Mode - bit 4
P1LPHEN.P1LPHEN3  3   Output Driver Enable in Power Down Mode - bit 3
P1LPHEN.P1LPHEN2  2   Output Driver Enable in Power Down Mode - bit 2
P1LPHEN.P1LPHEN1  1   Output Driver Enable in Power Down Mode - bit 1
P1LPHEN.P1LPHEN0  0   Output Driver Enable in Power Down Mode - bit 0
P1HPHEN          0xFE76   Port 1 High Pin Hold Enable Register
P1HPHEN.P1HPHEN7  7   Output Driver Enable in Power Down Mode - bit 7
P1HPHEN.P1HPHEN6  6   Output Driver Enable in Power Down Mode - bit 6
P1HPHEN.P1HPHEN5  5   Output Driver Enable in Power Down Mode - bit 5
P1HPHEN.P1HPHEN4  4   Output Driver Enable in Power Down Mode - bit 4
P1HPHEN.P1HPHEN3  3   Output Driver Enable in Power Down Mode - bit 3
P1HPHEN.P1HPHEN2  2   Output Driver Enable in Power Down Mode - bit 2
P1HPHEN.P1HPHEN1  1   Output Driver Enable in Power Down Mode - bit 1
P1HPHEN.P1HPHEN0  0   Output Driver Enable in Power Down Mode - bit 0
P2PUDSEL         0xFE78   Port 2 Pull-Up/Down Select Register
P2PUDSEL.P2PUDSEL7 7  Pulldown/Pullup Selection - bit 7
P2PUDSEL.P2PUDSEL6 6  Pulldown/Pullup Selection - bit 6
P2PUDSEL.P2PUDSEL5 5  Pulldown/Pullup Selection - bit 5
P2PUDSEL.P2PUDSEL4 4  Pulldown/Pullup Selection - bit 4
P2PUDSEL.P2PUDSEL3 3  Pulldown/Pullup Selection - bit 3
P2PUDSEL.P2PUDSEL2 2  Pulldown/Pullup Selection - bit 2
P2PUDSEL.P2PUDSEL1 1  Pulldown/Pullup Selection - bit 1
P2PUDSEL.P2PUDSEL0 0  Pulldown/Pullup Selection - bit 0
P2PUDEN          0xFE7A   Port 2 Pull Switch On/Off Register
P2PUDEN.P2PUDEN7  7   Pulldown/Pullup Enable - bit 7
P2PUDEN.P2PUDEN6  6   Pulldown/Pullup Enable - bit 6
P2PUDEN.P2PUDEN5  5   Pulldown/Pullup Enable - bit 5
P2PUDEN.P2PUDEN4  4   Pulldown/Pullup Enable - bit 4
P2PUDEN.P2PUDEN3  3   Pulldown/Pullup Enable - bit 3
P2PUDEN.P2PUDEN2  2   Pulldown/Pullup Enable - bit 2
P2PUDEN.P2PUDEN1  1   Pulldown/Pullup Enable - bit 1
P2PUDEN.P2PUDEN0  0   Pulldown/Pullup Enable - bit 0
P2PHEN           0xFE7C   Port 2 Pin Hold Enable Register
P2PHEN.P2PHEN7    7   Output Driver Enable in Power Down Mode - bit 7
P2PHEN.P2PHEN6    6   Output Driver Enable in Power Down Mode - bit 6
P2PHEN.P2PHEN5    5   Output Driver Enable in Power Down Mode - bit 5
P2PHEN.P2PHEN4    4   Output Driver Enable in Power Down Mode - bit 4
P2PHEN.P2PHEN3    3   Output Driver Enable in Power Down Mode - bit 3
P2PHEN.P2PHEN2    2   Output Driver Enable in Power Down Mode - bit 2
P2PHEN.P2PHEN1    1   Output Driver Enable in Power Down Mode - bit 1
P2PHEN.P2PHEN0    0   Output Driver Enable in Power Down Mode - bit 0
P3PUDSEL         0xFE7E   Port 3 Pull-Up/Down Select Register
P3PUDSEL.P3PUDSEL15 15  Pulldown/Pullup Selection - bit 15
P3PUDSEL.P3PUDSEL13 13  Pulldown/Pullup Selection - bit 13
P3PUDSEL.P3PUDSEL12 12  Pulldown/Pullup Selection - bit 12
P3PUDSEL.P3PUDSEL11 11  Pulldown/Pullup Selection - bit 11
P3PUDSEL.P3PUDSEL10 10  Pulldown/Pullup Selection - bit 10
P3PUDSEL.P3PUDSEL9  9   Pulldown/Pullup Selection - bit 9 
P3PUDSEL.P3PUDSEL8  8   Pulldown/Pullup Selection - bit 8 
P3PUDSEL.P3PUDSEL6  6   Pulldown/Pullup Selection - bit 6 
P3PUDSEL.P3PUDSEL5  5   Pulldown/Pullup Selection - bit 5 
P3PUDSEL.P3PUDSEL3  3   Pulldown/Pullup Selection - bit 3 
P3PUDEN          0xFE80   Port 3 Pull Switch On/Off Register
P3PUDEN.P3PUDEN15 15  Pulldown/Pullup Enable - bit 15
P3PUDEN.P3PUDEN13 13  Pulldown/Pullup Enable - bit 13
P3PUDEN.P3PUDEN12 12  Pulldown/Pullup Enable - bit 12
P3PUDEN.P3PUDEN11 11  Pulldown/Pullup Enable - bit 11
P3PUDEN.P3PUDEN10 10  Pulldown/Pullup Enable - bit 10
P3PUDEN.P3PUDEN9  9   Pulldown/Pullup Enable - bit 9
P3PUDEN.P3PUDEN8  8   Pulldown/Pullup Enable - bit 8
P3PUDEN.P3PUDEN6  6   Pulldown/Pullup Enable - bit 6
P3PUDEN.P3PUDEN5  5   Pulldown/Pullup Enable - bit 5
P3PUDEN.P3PUDEN3  3   Pulldown/Pullup Enable - bit 3
P3PHEN           0xFE82   Port 3 Pin Hold Enable Register
P3PHEN.P3PHEN15   15  Output Driver Enable in Power Down Mode - bit 15
P3PHEN.P3PHEN13   13  Output Driver Enable in Power Down Mode - bit 13
P3PHEN.P3PHEN12   12  Output Driver Enable in Power Down Mode - bit 12
P3PHEN.P3PHEN11   11  Output Driver Enable in Power Down Mode - bit 11
P3PHEN.P3PHEN10   10  Output Driver Enable in Power Down Mode - bit 10
P3PHEN.P3PHEN9    9   Output Driver Enable in Power Down Mode - bit 9 
P3PHEN.P3PHEN8    8   Output Driver Enable in Power Down Mode - bit 8 
P3PHEN.P3PHEN6    6   Output Driver Enable in Power Down Mode - bit 6 
P3PHEN.P3PHEN5    5   Output Driver Enable in Power Down Mode - bit 5 
P3PHEN.P3PHEN3    3   Output Driver Enable in Power Down Mode - bit 3 
P4PUDSEL         0xFE84   Port 4 Pull-Up/Down Select Register
P4PUDSEL.P4PUDSEL6 6  Pulldown/Pullup Selection - bit 6
P4PUDSEL.P4PUDSEL5 5  Pulldown/Pullup Selection - bit 5
P4PUDSEL.P4PUDSEL4 4  Pulldown/Pullup Selection - bit 4
P4PUDSEL.P4PUDSEL3 3  Pulldown/Pullup Selection - bit 3
P4PUDSEL.P4PUDSEL2 2  Pulldown/Pullup Selection - bit 2
P4PUDSEL.P4PUDSEL1 1  Pulldown/Pullup Selection - bit 1
P4PUDSEL.P4PUDSEL0 0  Pulldown/Pullup Selection - bit 0
P4PUDEN          0xFE86   Port 4 Pull Switch On/Off Register
P4PUDEN.P4PUDEN6  6   Pulldown/Pullup Enable - bit 6
P4PUDEN.P4PUDEN5  5   Pulldown/Pullup Enable - bit 5
P4PUDEN.P4PUDEN4  4   Pulldown/Pullup Enable - bit 4
P4PUDEN.P4PUDEN3  3   Pulldown/Pullup Enable - bit 3
P4PUDEN.P4PUDEN2  2   Pulldown/Pullup Enable - bit 2
P4PUDEN.P4PUDEN1  1   Pulldown/Pullup Enable - bit 1
P4PUDEN.P4PUDEN0  0   Pulldown/Pullup Enable - bit 0
P4PHEN           0xFE88   Port 4 Pin Hold Enable Register
P4PHEN.P4PHEN6    6   Output Driver Enable in Power Down Mode - bit 6
P4PHEN.P4PHEN5    5   Output Driver Enable in Power Down Mode - bit 5
P4PHEN.P4PHEN4    4   Output Driver Enable in Power Down Mode - bit 4
P4PHEN.P4PHEN3    3   Output Driver Enable in Power Down Mode - bit 3
P4PHEN.P4PHEN2    2   Output Driver Enable in Power Down Mode - bit 2
P4PHEN.P4PHEN1    1   Output Driver Enable in Power Down Mode - bit 1
P4PHEN.P4PHEN0    0   Output Driver Enable in Power Down Mode - bit 0
P6PUDSEL         0xFE90   Port 6 Pull-Up/Down Select Register
P6PUDSEL.P6PUDSEL7 7  Pulldown/Pullup Selection - bit 7
P6PUDSEL.P6PUDSEL6 6  Pulldown/Pullup Selection - bit 6
P6PUDSEL.P6PUDSEL5 5  Pulldown/Pullup Selection - bit 5
P6PUDSEL.P6PUDSEL4 4  Pulldown/Pullup Selection - bit 4
P6PUDSEL.P6PUDSEL3 3  Pulldown/Pullup Selection - bit 3
P6PUDSEL.P6PUDSEL2 2  Pulldown/Pullup Selection - bit 2
P6PUDSEL.P6PUDSEL1 1  Pulldown/Pullup Selection - bit 1
P6PUDSEL.P6PUDSEL0 0  Pulldown/Pullup Selection - bit 0
P6PUDEN          0xFE92   Port 6 Pull Switch On/Off Register
P6PUDEN.P6PUDEN7  7   Pulldown/Pullup Enable - bit 7
P6PUDEN.P6PUDEN6  6   Pulldown/Pullup Enable - bit 6
P6PUDEN.P6PUDEN5  5   Pulldown/Pullup Enable - bit 5
P6PUDEN.P6PUDEN4  4   Pulldown/Pullup Enable - bit 4
P6PUDEN.P6PUDEN3  3   Pulldown/Pullup Enable - bit 3
P6PUDEN.P6PUDEN2  2   Pulldown/Pullup Enable - bit 2
P6PUDEN.P6PUDEN1  1   Pulldown/Pullup Enable - bit 1
P6PUDEN.P6PUDEN0  0   Pulldown/Pullup Enable - bit 0
P6PHEN           0xFE94   Port 6 Pin Hold Enable Register
P6PHEN.P6PHEN7    7   Output Driver Enable in Power Down Mode - bit 7
P6PHEN.P6PHEN6    6   Output Driver Enable in Power Down Mode - bit 6
P6PHEN.P6PHEN5    5   Output Driver Enable in Power Down Mode - bit 5
P6PHEN.P6PHEN4    4   Output Driver Enable in Power Down Mode - bit 4
P6PHEN.P6PHEN3    3   Output Driver Enable in Power Down Mode - bit 3
P6PHEN.P6PHEN2    2   Output Driver Enable in Power Down Mode - bit 2
P6PHEN.P6PHEN1    1   Output Driver Enable in Power Down Mode - bit 1
P6PHEN.P6PHEN0    0   Output Driver Enable in Power Down Mode - bit 0
P7PUDSEL         0xFE96   Port 7 Pull-Up/Down Select Register
P7PUDSEL.P7PUDSEL5 5  Pulldown/Pullup Selection - bit 5
P7PUDSEL.P7PUDSEL4 4  Pulldown/Pullup Selection - bit 4
P7PUDSEL.P7PUDSEL3 3  Pulldown/Pullup Selection - bit 3
P7PUDSEL.P7PUDSEL2 2  Pulldown/Pullup Selection - bit 2
P7PUDSEL.P7PUDSEL1 1  Pulldown/Pullup Selection - bit 1
P7PUDSEL.P7PUDSEL0 0  Pulldown/Pullup Selection - bit 0
P7PUDEN          0xFE98   Port 7 Pull Switch On/Off Register
P7PUDEN.P7PUDEN5  5   Pulldown/Pullup Enable - bit 5
P7PUDEN.P7PUDEN4  4   Pulldown/Pullup Enable - bit 4
P7PUDEN.P7PUDEN3  3   Pulldown/Pullup Enable - bit 3
P7PUDEN.P7PUDEN2  2   Pulldown/Pullup Enable - bit 2
P7PUDEN.P7PUDEN1  1   Pulldown/Pullup Enable - bit 1
P7PUDEN.P7PUDEN0  0   Pulldown/Pullup Enable - bit 0
P7PHEN           0xFE9A   Port 7 Pin Hold Enable Register
P7PHEN.P7PHEN5    5   Output Driver Enable in Power Down Mode - bit 5
P7PHEN.P7PHEN4    4   Output Driver Enable in Power Down Mode - bit 4
P7PHEN.P7PHEN3    3   Output Driver Enable in Power Down Mode - bit 3
P7PHEN.P7PHEN2    2   Output Driver Enable in Power Down Mode - bit 2
P7PHEN.P7PHEN1    1   Output Driver Enable in Power Down Mode - bit 1
P7PHEN.P7PHEN0    0   Output Driver Enable in Power Down Mode - bit 0
S0PMW            0xFEAA   ASC IrDA PMW Control Regi
S0PMW.IRPW        8   IrDA Pulse Width Mode Control
S0PMW.PW_VALUE_7  7   IrDA Pulse Width Value - bit 7
S0PMW.PW_VALUE_6  6   IrDA Pulse Width Value - bit 6
S0PMW.PW_VALUE_5  5   IrDA Pulse Width Value - bit 5
S0PMW.PW_VALUE_4  4   IrDA Pulse Width Value - bit 4
S0PMW.PW_VALUE_3  3   IrDA Pulse Width Value - bit 3
S0PMW.PW_VALUE_2  2   IrDA Pulse Width Value - bit 2
S0PMW.PW_VALUE_1  1   IrDA Pulse Width Value - bit 1
S0PMW.PW_VALUE_0  0   IrDA Pulse Width Value - bit 0
WDT              0xFEAE   Watchdog Timer Register (RO)
S0TBUF           0xFEB0   Serial Channel 0 Transmit Buffer Register (WO)
S0TBUF.TD_VALUE_8 8   Transmit Data Register Value - bit 8
S0TBUF.TD_VALUE_7 7   Transmit Data Register Value - bit 7
S0TBUF.TD_VALUE_6 6   Transmit Data Register Value - bit 6
S0TBUF.TD_VALUE_5 5   Transmit Data Register Value - bit 5
S0TBUF.TD_VALUE_4 4   Transmit Data Register Value - bit 4
S0TBUF.TD_VALUE_3 3   Transmit Data Register Value - bit 3
S0TBUF.TD_VALUE_2 2   Transmit Data Register Value - bit 2
S0TBUF.TD_VALUE_1 1   Transmit Data Register Value - bit 1
S0TBUF.TD_VALUE_0 0   Transmit Data Register Value - bit 0
S0RBUF           0xFEB2   Serial Channel 0 Receive Buffer Register (RO)
S0RBUF.RD_VALUE_8 8   Receive Data Register Value - bit 8
S0RBUF.RD_VALUE_7 7   Receive Data Register Value - bit 7
S0RBUF.RD_VALUE_6 6   Receive Data Register Value - bit 6
S0RBUF.RD_VALUE_5 5   Receive Data Register Value - bit 5
S0RBUF.RD_VALUE_4 4   Receive Data Register Value - bit 4
S0RBUF.RD_VALUE_3 3   Receive Data Register Value - bit 3
S0RBUF.RD_VALUE_2 2   Receive Data Register Value - bit 2
S0RBUF.RD_VALUE_1 1   Receive Data Register Value - bit 1
S0RBUF.RD_VALUE_0 0   Receive Data Register Value - bit 0
S0BG             0xFEB4   Serial Chan
S0BG.BR_VALUE_12  12  Baudrate Timer/Reload Register Value - bit 12
S0BG.BR_VALUE_11  11  Baudrate Timer/Reload Register Value - bit 11
S0BG.BR_VALUE_10  10  Baudrate Timer/Reload Register Value - bit 10
S0BG.BR_VALUE_9   9   Baudrate Timer/Reload Register Value - bit 9 
S0BG.BR_VALUE_8   8   Baudrate Timer/Reload Register Value - bit 8 
S0BG.BR_VALUE_7   7   Baudrate Timer/Reload Register Value - bit 7 
S0BG.BR_VALUE_6   6   Baudrate Timer/Reload Register Value - bit 6 
S0BG.BR_VALUE_5   5   Baudrate Timer/Reload Register Value - bit 5 
S0BG.BR_VALUE_4   4   Baudrate Timer/Reload Register Value - bit 4 
S0BG.BR_VALUE_3   3   Baudrate Timer/Reload Register Value - bit 3 
S0BG.BR_VALUE_2   2   Baudrate Timer/Reload Register Value - bit 2 
S0BG.BR_VALUE_1   1   Baudrate Timer/Reload Register Value - bit 1 
S0BG.BR_VALUE_0   0   Baudrate Timer/Reload Register Value - bit 0 
S0FDV            0xFEB6   ASC Fracti
S0FDV.FD_VALUE_8  8   Fractional Divider Register Value - bit 8
S0FDV.FD_VALUE_7  7   Fractional Divider Register Value - bit 7
S0FDV.FD_VALUE_6  6   Fractional Divider Register Value - bit 6
S0FDV.FD_VALUE_5  5   Fractional Divider Register Value - bit 5
S0FDV.FD_VALUE_4  4   Fractional Divider Register Value - bit 4
S0FDV.FD_VALUE_3  3   Fractional Divider Register Value - bit 3
S0FDV.FD_VALUE_2  2   Fractional Divider Register Value - bit 2
S0FDV.FD_VALUE_1  1   Fractional Divider Register Value - bit 1
S0FDV.FD_VALUE_0  0   Fractional Divider Register Value - bit 0
PECC0            0xFEC0   PEC Channel 0 Control Register
PECC0.PT          15  Package Transfer
PECC0.CLT         12  Channel Link Toggle State
PECC0.CL          11  Channel Link Control
PECC0.INC_10      10  Increment Control - bit 10
PECC0.INC_9       9   Increment Control - bit 9 
PECC0.BWT         8   Byte/Word Transfer Selection
PECC0.COUNT_7     7   PEC Transfer Count - bit 7
PECC0.COUNT_6     6   PEC Transfer Count - bit 6
PECC0.COUNT_5     5   PEC Transfer Count - bit 5
PECC0.COUNT_4     4   PEC Transfer Count - bit 4
PECC0.COUNT_3     3   PEC Transfer Count - bit 3
PECC0.COUNT_2     2   PEC Transfer Count - bit 2
PECC0.COUNT_1     1   PEC Transfer Count - bit 1
PECC0.COUNT_0     0   PEC Transfer Count - bit 0
PECC1            0xFEC2   PEC Channel 1 Control Register
PECC1.PT          15  Package Transfer
PECC1.CLT         12  Channel Link Toggle State
PECC1.CL          11  Channel Link Control
PECC1.INC_10      10  Increment Control - bit 10
PECC1.INC_9       9   Increment Control - bit 9 
PECC1.BWT         8   Byte/Word Transfer Selection
PECC1.COUNT_7     7   PEC Transfer Count - bit 7
PECC1.COUNT_6     6   PEC Transfer Count - bit 6
PECC1.COUNT_5     5   PEC Transfer Count - bit 5
PECC1.COUNT_4     4   PEC Transfer Count - bit 4
PECC1.COUNT_3     3   PEC Transfer Count - bit 3
PECC1.COUNT_2     2   PEC Transfer Count - bit 2
PECC1.COUNT_1     1   PEC Transfer Count - bit 1
PECC1.COUNT_0     0   PEC Transfer Count - bit 0
PECC2            0xFEC4   PEC Channel 2 Control Register
PECC2.PT          15  Package Transfer
PECC2.CLT         12  Channel Link Toggle State
PECC2.CL          11  Channel Link Control
PECC2.INC_10      10  Increment Control - bit 10
PECC2.INC_9       9   Increment Control - bit 9 
PECC2.BWT         8   Byte/Word Transfer Selection
PECC2.COUNT_7     7   PEC Transfer Count - bit 7
PECC2.COUNT_6     6   PEC Transfer Count - bit 6
PECC2.COUNT_5     5   PEC Transfer Count - bit 5
PECC2.COUNT_4     4   PEC Transfer Count - bit 4
PECC2.COUNT_3     3   PEC Transfer Count - bit 3
PECC2.COUNT_2     2   PEC Transfer Count - bit 2
PECC2.COUNT_1     1   PEC Transfer Count - bit 1
PECC2.COUNT_0     0   PEC Transfer Count - bit 0
PECC3            0xFEC6   PEC Channel 3 Control Register
PECC3.PT          15  Package Transfer
PECC3.CLT         12  Channel Link Toggle State
PECC3.CL          11  Channel Link Control
PECC3.INC_10      10  Increment Control - bit 10
PECC3.INC_9       9   Increment Control - bit 9 
PECC3.BWT         8   Byte/Word Transfer Selection
PECC3.COUNT_7     7   PEC Transfer Count - bit 7
PECC3.COUNT_6     6   PEC Transfer Count - bit 6
PECC3.COUNT_5     5   PEC Transfer Count - bit 5
PECC3.COUNT_4     4   PEC Transfer Count - bit 4
PECC3.COUNT_3     3   PEC Transfer Count - bit 3
PECC3.COUNT_2     2   PEC Transfer Count - bit 2
PECC3.COUNT_1     1   PEC Transfer Count - bit 1
PECC3.COUNT_0     0   PEC Transfer Count - bit 0
PECC4            0xFEC8   PEC Channel 4 Control Register
PECC4.PT          15  Package Transfer
PECC4.CLT         12  Channel Link Toggle State
PECC4.CL          11  Channel Link Control
PECC4.INC_10      10  Increment Control - bit 10
PECC4.INC_9       9   Increment Control - bit 9 
PECC4.BWT         8   Byte/Word Transfer Selection
PECC4.COUNT_7     7   PEC Transfer Count - bit 7
PECC4.COUNT_6     6   PEC Transfer Count - bit 6
PECC4.COUNT_5     5   PEC Transfer Count - bit 5
PECC4.COUNT_4     4   PEC Transfer Count - bit 4
PECC4.COUNT_3     3   PEC Transfer Count - bit 3
PECC4.COUNT_2     2   PEC Transfer Count - bit 2
PECC4.COUNT_1     1   PEC Transfer Count - bit 1
PECC4.COUNT_0     0   PEC Transfer Count - bit 0
PECC5            0xFECA   PEC Channel 5 Control Register
PECC5.PT          15  Package Transfer
PECC5.CLT         12  Channel Link Toggle State
PECC5.CL          11  Channel Link Control
PECC5.INC_10      10  Increment Control - bit 10
PECC5.INC_9       9   Increment Control - bit 9 
PECC5.BWT         8   Byte/Word Transfer Selection
PECC5.COUNT_7     7   PEC Transfer Count - bit 7
PECC5.COUNT_6     6   PEC Transfer Count - bit 6
PECC5.COUNT_5     5   PEC Transfer Count - bit 5
PECC5.COUNT_4     4   PEC Transfer Count - bit 4
PECC5.COUNT_3     3   PEC Transfer Count - bit 3
PECC5.COUNT_2     2   PEC Transfer Count - bit 2
PECC5.COUNT_1     1   PEC Transfer Count - bit 1
PECC5.COUNT_0     0   PEC Transfer Count - bit 0
PECC6            0xFECC   PEC Channel 6 Control Register
PECC6.PT          15  Package Transfer
PECC6.CLT         12  Channel Link Toggle State
PECC6.CL          11  Channel Link Control
PECC6.INC_10      10  Increment Control - bit 10
PECC6.INC_9       9   Increment Control - bit 9 
PECC6.BWT         8   Byte/Word Transfer Selection
PECC6.COUNT_7     7   PEC Transfer Count - bit 7
PECC6.COUNT_6     6   PEC Transfer Count - bit 6
PECC6.COUNT_5     5   PEC Transfer Count - bit 5
PECC6.COUNT_4     4   PEC Transfer Count - bit 4
PECC6.COUNT_3     3   PEC Transfer Count - bit 3
PECC6.COUNT_2     2   PEC Transfer Count - bit 2
PECC6.COUNT_1     1   PEC Transfer Count - bit 1
PECC6.COUNT_0     0   PEC Transfer Count - bit 0
PECC7            0xFECE   PEC Channel 7 Control Register
PECC7.PT          15  Package Transfer
PECC7.CLT         12  Channel Link Toggle State
PECC7.CL          11  Channel Link Control
PECC7.INC_10      10  Increment Control - bit 10
PECC7.INC_9       9   Increment Control - bit 9 
PECC7.BWT         8   Byte/Word Transfer Selection
PECC7.COUNT_7     7   PEC Transfer Count - bit 7
PECC7.COUNT_6     6   PEC Transfer Count - bit 6
PECC7.COUNT_5     5   PEC Transfer Count - bit 5
PECC7.COUNT_4     4   PEC Transfer Count - bit 4
PECC7.COUNT_3     3   PEC Transfer Count - bit 3
PECC7.COUNT_2     2   PEC Transfer Count - bit 2
PECC7.COUNT_1     1   PEC Transfer Count - bit 1
PECC7.COUNT_0     0   PEC Transfer Count - bit 0
PECSN0           0xFED0   PEC Segment No Register
PECSN0.PECDSN_15  15  PEC Destination Segment Number - bit 15
PECSN0.PECDSN_14  14  PEC Destination Segment Number - bit 14
PECSN0.PECDSN_13  13  PEC Destination Segment Number - bit 13
PECSN0.PECDSN_12  12  PEC Destination Segment Number - bit 12
PECSN0.PECDSN_11  11  PEC Destination Segment Number - bit 11
PECSN0.PECDSN_10  10  PEC Destination Segment Number - bit 10
PECSN0.PECDSN_9   9   PEC Destination Segment Number - bit 9 
PECSN0.PECDSN_8   8   PEC Destination Segment Number - bit 8 
PECSN0.PECSSN_7   7   PEC Source Segment Number - bit 7
PECSN0.PECSSN_6   6   PEC Source Segment Number - bit 6
PECSN0.PECSSN_5   5   PEC Source Segment Number - bit 5
PECSN0.PECSSN_4   4   PEC Source Segment Number - bit 4
PECSN0.PECSSN_3   3   PEC Source Segment Number - bit 3
PECSN0.PECSSN_2   2   PEC Source Segment Number - bit 2
PECSN0.PECSSN_1   1   PEC Source Segment Number - bit 1
PECSN0.PECSSN_0   0   PEC Source Segment Number - bit 0
PECSN1           0xFED2   PEC Segment No Register
PECSN1.PECDSN_15  15  PEC Destination Segment Number - bit 15
PECSN1.PECDSN_14  14  PEC Destination Segment Number - bit 14
PECSN1.PECDSN_13  13  PEC Destination Segment Number - bit 13
PECSN1.PECDSN_12  12  PEC Destination Segment Number - bit 12
PECSN1.PECDSN_11  11  PEC Destination Segment Number - bit 11
PECSN1.PECDSN_10  10  PEC Destination Segment Number - bit 10
PECSN1.PECDSN_9   9   PEC Destination Segment Number - bit 9 
PECSN1.PECDSN_8   8   PEC Destination Segment Number - bit 8 
PECSN1.PECSSN_7   7   PEC Source Segment Number - bit 7
PECSN1.PECSSN_6   6   PEC Source Segment Number - bit 6
PECSN1.PECSSN_5   5   PEC Source Segment Number - bit 5
PECSN1.PECSSN_4   4   PEC Source Segment Number - bit 4
PECSN1.PECSSN_3   3   PEC Source Segment Number - bit 3
PECSN1.PECSSN_2   2   PEC Source Segment Number - bit 2
PECSN1.PECSSN_1   1   PEC Source Segment Number - bit 1
PECSN1.PECSSN_0   0   PEC Source Segment Number - bit 0
PECSN2           0xFED4   PEC Segment No Register
PECSN2.PECDSN_15  15  PEC Destination Segment Number - bit 15
PECSN2.PECDSN_14  14  PEC Destination Segment Number - bit 14
PECSN2.PECDSN_13  13  PEC Destination Segment Number - bit 13
PECSN2.PECDSN_12  12  PEC Destination Segment Number - bit 12
PECSN2.PECDSN_11  11  PEC Destination Segment Number - bit 11
PECSN2.PECDSN_10  10  PEC Destination Segment Number - bit 10
PECSN2.PECDSN_9   9   PEC Destination Segment Number - bit 9 
PECSN2.PECDSN_8   8   PEC Destination Segment Number - bit 8 
PECSN2.PECSSN_7   7   PEC Source Segment Number - bit 7
PECSN2.PECSSN_6   6   PEC Source Segment Number - bit 6
PECSN2.PECSSN_5   5   PEC Source Segment Number - bit 5
PECSN2.PECSSN_4   4   PEC Source Segment Number - bit 4
PECSN2.PECSSN_3   3   PEC Source Segment Number - bit 3
PECSN2.PECSSN_2   2   PEC Source Segment Number - bit 2
PECSN2.PECSSN_1   1   PEC Source Segment Number - bit 1
PECSN2.PECSSN_0   0   PEC Source Segment Number - bit 0
PECSN3           0xFED6   PEC Segment No Register
PECSN3.PECDSN_15  15  PEC Destination Segment Number - bit 15
PECSN3.PECDSN_14  14  PEC Destination Segment Number - bit 14
PECSN3.PECDSN_13  13  PEC Destination Segment Number - bit 13
PECSN3.PECDSN_12  12  PEC Destination Segment Number - bit 12
PECSN3.PECDSN_11  11  PEC Destination Segment Number - bit 11
PECSN3.PECDSN_10  10  PEC Destination Segment Number - bit 10
PECSN3.PECDSN_9   9   PEC Destination Segment Number - bit 9 
PECSN3.PECDSN_8   8   PEC Destination Segment Number - bit 8 
PECSN3.PECSSN_7   7   PEC Source Segment Number - bit 7
PECSN3.PECSSN_6   6   PEC Source Segment Number - bit 6
PECSN3.PECSSN_5   5   PEC Source Segment Number - bit 5
PECSN3.PECSSN_4   4   PEC Source Segment Number - bit 4
PECSN3.PECSSN_3   3   PEC Source Segment Number - bit 3
PECSN3.PECSSN_2   2   PEC Source Segment Number - bit 2
PECSN3.PECSSN_1   1   PEC Source Segment Number - bit 1
PECSN3.PECSSN_0   0   PEC Source Segment Number - bit 0
PECSN4           0xFED8   PEC Segment No Register
PECSN4.PECDSN_15  15  PEC Destination Segment Number - bit 15
PECSN4.PECDSN_14  14  PEC Destination Segment Number - bit 14
PECSN4.PECDSN_13  13  PEC Destination Segment Number - bit 13
PECSN4.PECDSN_12  12  PEC Destination Segment Number - bit 12
PECSN4.PECDSN_11  11  PEC Destination Segment Number - bit 11
PECSN4.PECDSN_10  10  PEC Destination Segment Number - bit 10
PECSN4.PECDSN_9   9   PEC Destination Segment Number - bit 9 
PECSN4.PECDSN_8   8   PEC Destination Segment Number - bit 8 
PECSN4.PECSSN_7   7   PEC Source Segment Number - bit 7
PECSN4.PECSSN_6   6   PEC Source Segment Number - bit 6
PECSN4.PECSSN_5   5   PEC Source Segment Number - bit 5
PECSN4.PECSSN_4   4   PEC Source Segment Number - bit 4
PECSN4.PECSSN_3   3   PEC Source Segment Number - bit 3
PECSN4.PECSSN_2   2   PEC Source Segment Number - bit 2
PECSN4.PECSSN_1   1   PEC Source Segment Number - bit 1
PECSN4.PECSSN_0   0   PEC Source Segment Number - bit 0
PECSN5           0xFEDA   PEC Segment No Register
PECSN5.PECDSN_15  15  PEC Destination Segment Number - bit 15
PECSN5.PECDSN_14  14  PEC Destination Segment Number - bit 14
PECSN5.PECDSN_13  13  PEC Destination Segment Number - bit 13
PECSN5.PECDSN_12  12  PEC Destination Segment Number - bit 12
PECSN5.PECDSN_11  11  PEC Destination Segment Number - bit 11
PECSN5.PECDSN_10  10  PEC Destination Segment Number - bit 10
PECSN5.PECDSN_9   9   PEC Destination Segment Number - bit 9 
PECSN5.PECDSN_8   8   PEC Destination Segment Number - bit 8 
PECSN5.PECSSN_7   7   PEC Source Segment Number - bit 7
PECSN5.PECSSN_6   6   PEC Source Segment Number - bit 6
PECSN5.PECSSN_5   5   PEC Source Segment Number - bit 5
PECSN5.PECSSN_4   4   PEC Source Segment Number - bit 4
PECSN5.PECSSN_3   3   PEC Source Segment Number - bit 3
PECSN5.PECSSN_2   2   PEC Source Segment Number - bit 2
PECSN5.PECSSN_1   1   PEC Source Segment Number - bit 1
PECSN5.PECSSN_0   0   PEC Source Segment Number - bit 0
PECSN6           0xFEDC   PEC Segment No Register
PECSN6.PECDSN_15  15  PEC Destination Segment Number - bit 15
PECSN6.PECDSN_14  14  PEC Destination Segment Number - bit 14
PECSN6.PECDSN_13  13  PEC Destination Segment Number - bit 13
PECSN6.PECDSN_12  12  PEC Destination Segment Number - bit 12
PECSN6.PECDSN_11  11  PEC Destination Segment Number - bit 11
PECSN6.PECDSN_10  10  PEC Destination Segment Number - bit 10
PECSN6.PECDSN_9   9   PEC Destination Segment Number - bit 9 
PECSN6.PECDSN_8   8   PEC Destination Segment Number - bit 8 
PECSN6.PECSSN_7   7   PEC Source Segment Number - bit 7
PECSN6.PECSSN_6   6   PEC Source Segment Number - bit 6
PECSN6.PECSSN_5   5   PEC Source Segment Number - bit 5
PECSN6.PECSSN_4   4   PEC Source Segment Number - bit 4
PECSN6.PECSSN_3   3   PEC Source Segment Number - bit 3
PECSN6.PECSSN_2   2   PEC Source Segment Number - bit 2
PECSN6.PECSSN_1   1   PEC Source Segment Number - bit 1
PECSN6.PECSSN_0   0   PEC Source Segment Number - bit 0
PECSN7           0xFEDE   PEC Segment No Register
PECSN7.PECDSN_15  15  PEC Destination Segment Number - bit 15
PECSN7.PECDSN_14  14  PEC Destination Segment Number - bit 14
PECSN7.PECDSN_13  13  PEC Destination Segment Number - bit 13
PECSN7.PECDSN_12  12  PEC Destination Segment Number - bit 12
PECSN7.PECDSN_11  11  PEC Destination Segment Number - bit 11
PECSN7.PECDSN_10  10  PEC Destination Segment Number - bit 10
PECSN7.PECDSN_9   9   PEC Destination Segment Number - bit 9 
PECSN7.PECDSN_8   8   PEC Destination Segment Number - bit 8 
PECSN7.PECSSN_7   7   PEC Source Segment Number - bit 7
PECSN7.PECSSN_6   6   PEC Source Segment Number - bit 6
PECSN7.PECSSN_5   5   PEC Source Segment Number - bit 5
PECSN7.PECSSN_4   4   PEC Source Segment Number - bit 4
PECSN7.PECSSN_3   3   PEC Source Segment Number - bit 3
PECSN7.PECSSN_2   2   PEC Source Segment Number - bit 2
PECSN7.PECSSN_1   1   PEC Source Segment Number - bit 1
PECSN7.PECSSN_0   0   PEC Source Segment Number - bit 0
PECXC0           0xFEF0   PEC Channel 0 Extended Control Register
PECXC0.COUNT2_15  15  Extended PEC Transfer Count - bit 15
PECXC0.COUNT2_14  14  Extended PEC Transfer Count - bit 14
PECXC0.COUNT2_13  13  Extended PEC Transfer Count - bit 13
PECXC0.COUNT2_12  12  Extended PEC Transfer Count - bit 12
PECXC0.COUNT2_11  11  Extended PEC Transfer Count - bit 11
PECXC0.COUNT2_10  10  Extended PEC Transfer Count - bit 10
PECXC0.COUNT2_9   9   Extended PEC Transfer Count - bit 9 
PECXC0.COUNT2_8   8   Extended PEC Transfer Count - bit 8 
PECXC0.COUNT2_7   7   Extended PEC Transfer Count - bit 7 
PECXC0.COUNT2_6   6   Extended PEC Transfer Count - bit 6 
PECXC0.COUNT2_5   5   Extended PEC Transfer Count - bit 5 
PECXC0.COUNT2_4   4   Extended PEC Transfer Count - bit 4 
PECXC0.COUNT2_3   3   Extended PEC Transfer Count - bit 3 
PECXC0.COUNT2_2   2   Extended PEC Transfer Count - bit 2 
PECXC0.COUNT2_1   1   Extended PEC Transfer Count - bit 1 
PECXC0.COUNT2_0   0   Extended PEC Transfer Count - bit 0 
PECXC2           0xFEF2   PEC Channel 2 Extended Control Register
PECXC2.COUNT2_15  15  Extended PEC Transfer Count - bit 15
PECXC2.COUNT2_14  14  Extended PEC Transfer Count - bit 14
PECXC2.COUNT2_13  13  Extended PEC Transfer Count - bit 13
PECXC2.COUNT2_12  12  Extended PEC Transfer Count - bit 12
PECXC2.COUNT2_11  11  Extended PEC Transfer Count - bit 11
PECXC2.COUNT2_10  10  Extended PEC Transfer Count - bit 10
PECXC2.COUNT2_9   9   Extended PEC Transfer Count - bit 9 
PECXC2.COUNT2_8   8   Extended PEC Transfer Count - bit 8 
PECXC2.COUNT2_7   7   Extended PEC Transfer Count - bit 7 
PECXC2.COUNT2_6   6   Extended PEC Transfer Count - bit 6 
PECXC2.COUNT2_5   5   Extended PEC Transfer Count - bit 5 
PECXC2.COUNT2_4   4   Extended PEC Transfer Count - bit 4 
PECXC2.COUNT2_3   3   Extended PEC Transfer Count - bit 3 
PECXC2.COUNT2_2   2   Extended PEC Transfer Count - bit 2 
PECXC2.COUNT2_1   1   Extended PEC Transfer Count - bit 1 
PECXC2.COUNT2_0   0   Extended PEC Transfer Count - bit 0 
ABS0CON          0xFEF8   ASC Autobaud Control Register
ABS0CON.RXINV     11  Receive Inverter Enable
ABS0CON.TXINV     10  Transmit Inverter Enable
ABS0CON.ABEM_9    9   Autobaud Echo Mode Enable - bit 9
ABS0CON.ABEM_8    8   Autobaud Echo Mode Enable - bit 8
ABS0CON.FCDETEN   4   First Character of Two-Byte Frame Detected Enable
ABS0CON.ABDETEN   3   Autobaud Detection Interrupt Enable
ABS0CON.ABSTEN    2   Start of Autobaud Detection Interrupt Enable
ABS0CON.AUREN     1   Automatic Autobaud Control of CON_REN
ABS0CON.ABEN      0   Autobaud Detection Enable
ABSTAT           0xFEFE   ASC Autobaud Status Register
ABSTAT.DETWAIT    4   Autobaud Detection is Waiting
ABSTAT.SCCDET     3   Second Character with Capital Letter Detected
ABSTAT.SCSDET     2   Second Character with Small Letter Detected
ABSTAT.FCCDET     1   First Character with Capital Letter Detected
ABSTAT.FCSDET     0   First Character with Small Letter Detected
P0L              0xFF00   Port 0 Low Register (Lower half)
P0L.P0L7          7   Port data register P0L bit 7
P0L.P0L6          6   Port data register P0L bit 6
P0L.P0L5          5   Port data register P0L bit 5
P0L.P0L4          4   Port data register P0L bit 4
P0L.P0L3          3   Port data register P0L bit 3
P0L.P0L2          2   Port data register P0L bit 2
P0L.P0L1          1   Port data register P0L bit 1
P0L.P0L0          0   Port data register P0L bit 0
P0H              0xFF02   Port 0 High Register (Upper half)
P0H.P0H7          7   Port data register P0H bit 7
P0H.P0H6          6   Port data register P0H bit 6
P0H.P0H5          5   Port data register P0H bit 5
P0H.P0H4          4   Port data register P0H bit 4
P0H.P0H3          3   Port data register P0H bit 3
P0H.P0H2          2   Port data register P0H bit 2
P0H.P0H1          1   Port data register P0H bit 1
P0H.P0H0          0   Port data register P0H bit 0
P1L              0xFF04   Port 1 Low Register (Lower half)
P1L.P1L7          7   Port data register P1L bit 7
P1L.P1L6          6   Port data register P1L bit 6
P1L.P1L5          5   Port data register P1L bit 5
P1L.P1L4          4   Port data register P1L bit 4
P1L.P1L3          3   Port data register P1L bit 3
P1L.P1L2          2   Port data register P1L bit 2
P1L.P1L1          1   Port data register P1L bit 1
P1L.P1L0          0   Port data register P1L bit 0
P1H              0xFF06   Port 1 High Register (Upper half)
P1H.P1H7          7   Port data register P1H bit 7
P1H.P1H6          6   Port data register P1H bit 6
P1H.P1H5          5   Port data register P1H bit 5
P1H.P1H4          4   Port data register P1H bit 4
P1H.P1H3          3   Port data register P1H bit 3
P1H.P1H2          2   Port data register P1H bit 2
P1H.P1H1          1   Port data register P1H bit 1
P1H.P1H0          0   Port data register P1H bit 0
BUSCON0          0xFF0C   Bus Configuration Register 0
BUSCON0.CSWEN0    15  Write Chip Select Enable
BUSCON0.CSREN0    14  Read Chip Select Enable
BUSCON0.RDYEN0    12  READY Input Enable
BUSCON0.BUSACT0   10  Bus Active Control
BUSCON0.ALECTL0   9   ALE Lengthening Control
BUSCON0.EWEN0     8   Early Write Enable
BUSCON0.BTYP_7    7   External Bus Configuration - bit 7
BUSCON0.BTYP_6    6   External Bus Configuration - bit 6
BUSCON0.MTTC0     5   Memory Tristate Time Control
BUSCON0.RWDC0     4   Read/Write Delay Control for BUSCON
BUSCON0.MCTC_3    3   Memory Cycle Time Control - bit 3
BUSCON0.MCTC_2    2   Memory Cycle Time Control - bit 2
BUSCON0.MCTC_1    1   Memory Cycle Time Control - bit 1
BUSCON0.MCTC_0    0   Memory Cycle Time Control - bit 0
MDC              0xFF0E   CPU Multiply Divide Control Register
MDC.MDRIU         4   Multiply/Divide Register In Use
PSW              0xFF10   CPU Program Status Word
PSW.ILVL_15       15  Interrupt and EBC Control Field - bit 15
PSW.ILVL_14       14  Interrupt and EBC Control Field - bit 14
PSW.ILVL_13       13  Interrupt and EBC Control Field - bit 13
PSW.ILVL_12       12  Interrupt and EBC Control Field - bit 12
PSW.IEN           11  Interrupt and EBC Control Field
PSW.HLDEN         10  Interrupt and EBC Control Field
PSW.USR0          6   User General Purpose Flag
PSW.MULIP         5   Multiplication/Division In Progress
PSW.E             4   End of Table Flag
PSW.Z             3   Zero F lag
PSW.V             2   Overflow Result
PSW.C             1   Carry Flag
PSW.N             0   Negative Result
SYSCON           0xFF12   CPU System Configuration Register
SYSCON.STKSZ_15   15  System Stack Size - bit 15
SYSCON.STKSZ_14   14  System Stack Size - bit 14
SYSCON.STKSZ_13   13  System Stack Size - bit 13
SYSCON.ROMS1      12  Internal ROM Mapping
SYSCON.SGTDIS     11  Segmentation Disable/Enable Control (Cleared after reset)
SYSCON.ROMEN      10  Internal ROM Enable (Set according to pin EA during reset)
SYSCON.BYTDIS     9   Disable/Enable Control for Pin BHE (Set according to data bus width)
SYSCON.CLKEN      8   System Clock Output Enable (CLKOUT, cleared after reset)
SYSCON.WRCFG      7   Write Configuration Control (Set according to pin P0H.0 during reset)
SYSCON.CSCFG      6   Chip Select Configuration Control (Cleared after reset)
SYSCON.OSCENBL    4   Oscillator Watchdog Enable Bit
SYSCON.XPEN       2   Peripheral Enable Bit
SYSCON.VISIBLE    1   Visible Mode Control
SYSCON.XPER_SHARE 0   XBUS Peripheral Share Mode Control
BUSCON1          0xFF14   Bus Configuration Register 1
BUSCON1.CSWEN1    15  Write Chip Select Enable
BUSCON1.CSREN1    14  Read Chip Select Enable
BUSCON1.RDYEN1    12  READY Input Enable
BUSCON1.BUSACT1   10  Bus Active Control
BUSCON1.ALECTL1   9   ALE Lengthening Control
BUSCON1.EWEN1     8   Early Write Enable
BUSCON1.BTYP_7    7   External Bus Configuration - bit 7
BUSCON1.BTYP_6    6   External Bus Configuration - bit 6
BUSCON1.MTTC1     5   Memory Tristate Time Control
BUSCON1.RWDC1     4   Read/Write Delay Control for BUSCON
BUSCON1.MCTC_3    3   Memory Cycle Time Control - bit 3
BUSCON1.MCTC_2    2   Memory Cycle Time Control - bit 2
BUSCON1.MCTC_1    1   Memory Cycle Time Control - bit 1
BUSCON1.MCTC_0    0   Memory Cycle Time Control - bit 0
BUSCON2          0xFF16   Bus Configuration Register 2
BUSCON2.CSWEN2    15  Write Chip Select Enable
BUSCON2.CSREN2    14  Read Chip Select Enable
BUSCON2.RDYEN2    12  READY Input Enable
BUSCON2.BUSACT2   10  Bus Active Control
BUSCON2.ALECTL2   9   ALE Lengthening Control
BUSCON2.EWEN2     8   Early Write Enable
BUSCON2.BTYP_7    7   External Bus Configuration - bit 7
BUSCON2.BTYP_6    6   External Bus Configuration - bit 6
BUSCON2.MTTC2     5   Memory Tristate Time Control
BUSCON2.RWDC2     4   Read/Write Delay Control for BUSCON
BUSCON2.MCTC_3    3   Memory Cycle Time Control - bit 3
BUSCON2.MCTC_2    2   Memory Cycle Time Control - bit 2
BUSCON2.MCTC_1    1   Memory Cycle Time Control - bit 1
BUSCON2.MCTC_0    0   Memory Cycle Time Control - bit 0
BUSCON3          0xFF18   Bus Configuration Register 3
BUSCON3.CSWEN3    15  Write Chip Select Enable
BUSCON3.CSREN3    14  Read Chip Select Enable
BUSCON3.RDYEN3    12  READY Input Enable
BUSCON3.BUSACT3   10  Bus Active Control
BUSCON3.ALECTL3   9   ALE Lengthening Control
BUSCON3.EWEN3     8   Early Write Enable
BUSCON3.BTYP_7    7   External Bus Configuration - bit 7
BUSCON3.BTYP_6    6   External Bus Configuration - bit 6
BUSCON3.MTTC3     5   Memory Tristate Time Control
BUSCON3.RWDC3     4   Read/Write Delay Control for BUSCON
BUSCON3.MCTC_3    3   Memory Cycle Time Control - bit 3
BUSCON3.MCTC_2    2   Memory Cycle Time Control - bit 2
BUSCON3.MCTC_1    1   Memory Cycle Time Control - bit 1
BUSCON3.MCTC_0    0   Memory Cycle Time Control - bit 0
BUSCON4          0xFF1A   Bus Configuration Register 4
BUSCON4.CSWEN4    15  Write Chip Select Enable
BUSCON4.CSREN4    14  Read Chip Select Enable
BUSCON4.RDYEN4    12  READY Input Enable
BUSCON4.BUSACT4   10  Bus Active Control
BUSCON4.ALECTL4   9   ALE Lengthening Control
BUSCON4.EWEN4     8   Early Write Enable
BUSCON4.BTYP_7    7   External Bus Configuration - bit 7
BUSCON4.BTYP_6    6   External Bus Configuration - bit 6
BUSCON4.MTTC4     5   Memory Tristate Time Control
BUSCON4.RWDC4     4   Read/Write Delay Control for BUSCON
BUSCON4.MCTC_3    3   Memory Cycle Time Control - bit 3
BUSCON4.MCTC_2    2   Memory Cycle Time Control - bit 2
BUSCON4.MCTC_1    1   Memory Cycle Time Control - bit 1
BUSCON4.MCTC_0    0   Memory Cycle Time Control - bit 0
ZEROS            0xFF1C   Constant Value 0sRegister'
ONES             0xFF1E   Constant Value 1sRegister'
T2CON            0xFF40   GPT1 Timer 2 Control Register
T2CON.T2IREN      15  Timer 2 Interrupt Enable
T2CON.T2RDIR      14  Timer 2 Rotation Direction
T2CON.T2CHDIR     13  Timer 2 Count Direction Change
T2CON.T2EDGE      12  Timer 2 Edge Detection
T2CON.T2RC        9   Timer 2 Remote Control
T2CON.T2UDE       8   Timer 2 External Up/Down Enable
T2CON.T2UD        7   Timer 2 Up / Down Control
T2CON.T2R         6   Timer 2 Run Bit
T2CON.T2M_5       5   Timer 2 Mode Control - bit 5
T2CON.T2M_4       4   Timer 2 Mode Control - bit 4
T2CON.T2M_3       3   Timer 2 Mode Control - bit 3
T2CON.T2I_2       2   Timer 2 Input Selection - bit 2
T2CON.T2I_1       1   Timer 2 Input Selection - bit 1
T2CON.T2I_0       0   Timer 2 Input Selection - bit 0
T3CON            0xFF42   GPT1 Timer 3 Control Register
T3CON.T3IREN      15  Timer 3 Interrupt Enable
T3CON.T3RDIR      14  Timer 3 Rotation Direction
T3CON.T3CHDIR     13  Timer 3 Count Direction Change
T3CON.T3EDGE      12  Timer 3 Edge Detection
T3CON.FM1         11  Fast Mode for Timer Block 1
T3CON.T3OTL       10  Timer 3 Output Toggle Latch
T3CON.T3OE        9   Alternate Output Function Enable
T3CON.T3UDE       8   Timer 3 External Up/Down Enable
T3CON.T3UD        7   Timer 3 Up / Down Control
T3CON.T3R         6   Timer 3 Run Bit
T3CON.T3M_5       5   Timer 3 Mode Control - bit 5
T3CON.T3M_4       4   Timer 3 Mode Control - bit 4
T3CON.T3M_3       3   Timer 3 Mode Control - bit 3
T3CON.T3I_2       2   Timer 3 Input Selection - bit 2
T3CON.T3I_1       1   Timer 3 Input Selection - bit 1
T3CON.T3I_0       0   Timer 3 Input Selection - bit 0
T4CON            0xFF44   GPT1 Timer 4 Control Register
T4CON.T4IREN      15  Timer 4 Interrupt Enable
T4CON.T4RDIR      14  Timer 4 Rotation Direction
T4CON.T4CHDIR     13  Timer 4 Count Direction Change
T4CON.T4EDGE      12  Timer 4 Edge Detection
T4CON.T4RC        9   Timer 4 Remote Control
T4CON.T4UD        7   Timer 4 Up / Down Control
T4CON.T4R         6   Timer 4 Run Bit
T4CON.T4M_5       5   Timer 4 Mode Control - bit 5
T4CON.T4M_4       4   Timer 4 Mode Control - bit 4
T4CON.T4M_3       3   Timer 4 Mode Control - bit 3
T4CON.T4I_2       2   Timer 4 Input Selection - bit 2
T4CON.T4I_1       1   Timer 4 Input Selection - bit 1
T4CON.T4I_0       0   Timer 4 Input Selection - bit 0
T5CON            0xFF46   GPT2 Timer 5 Control Register
T5CON.T5SC        15  Timer 5 Capture Mode Enable
T5CON.T5CLR       14  Timer 5 Clear Bit
T5CON.CI_13       13  Register CAPREL Capture Trigger Selection - bit 13
T5CON.CI_12       12  Register CAPREL Capture Trigger Selection - bit 12
T5CON.CC          11  Capture Correction
T5CON.T5RC        9   Timer 4 Remote Control
T5CON.T5UD        7   Timer 4 Up / Down Control
T5CON.T5R         6   Timer 4 Run Bit
T5CON.T5M_5       5   Timer 4 Mode Control - bit 5
T5CON.T5M_4       4   Timer 4 Mode Control - bit 4
T5CON.T5M_3       3   Timer 4 Mode Control - bit 3
T5CON.T5I_2       2   Timer 4 Input Selection - bit 2
T5CON.T5I_1       1   Timer 4 Input Selection - bit 1
T5CON.T5I_0       0   Timer 4 Input Selection - bit 0
T6CON            0xFF48   GPT2 Timer 6 Control Register
T6CON.T6SR        15  Timer 6 Reload Mode Enable
T6CON.T6CLR       14  Timer 6 Clear Bit
T6CON.FM2         11  Fast Mode for Timer Block 2
T6CON.T6OTL       10  Timer 6 Output Toggle Latch
T6CON.T6UD        7   Timer 6 Up / Down Control
T6CON.T6R         6   Timer 6 Run Bit
T6CON.T6M_5       5   Timer 6 Mode Control - bit 5
T6CON.T6M_4       4   Timer 6 Mode Control - bit 4
T6CON.T6M_3       3   Timer 6 Mode Control - bit 3
T6CON.T6I_2       2   Timer 6 Input Selection - bit 2
T6CON.T6I_1       1   Timer 6 Input Selection - bit 1
T6CON.T6I_0       0   Timer 6 Input Selection - bit 0
T2IC             0xFF60   GPT1 Timer 2 Interrupt Control Register
T2IC.T2IR         7   Interrupt Request Flag
T2IC.T2IE         6   Interrupt Enable Control Bit (individually enables/disables a specific source)
T2IC.ILVL_5       5   Interrupt Priority Level - bit 5
T2IC.ILVL_4       4   Interrupt Priority Level - bit 4
T2IC.ILVL_3       3   Interrupt Priority Level - bit 3
T2IC.ILVL_2       2   Interrupt Priority Level - bit 2
T2IC.GLVL_1       1   Group Level - bit 1
T2IC.GLVL_0       0   Group Level - bit 0
T3IC             0xFF62   GPT1 Timer 3 Interrupt Control Register
T3IC.T3IR         7   Interrupt Request Flag
T3IC.T3IE         6   Interrupt Enable Control Bit (individually enables/disables a specific source)
T3IC.ILVL_5       5   Interrupt Priority Level - bit 5
T3IC.ILVL_4       4   Interrupt Priority Level - bit 4
T3IC.ILVL_3       3   Interrupt Priority Level - bit 3
T3IC.ILVL_2       2   Interrupt Priority Level - bit 2
T3IC.GLVL_1       1   Group Level - bit 1
T3IC.GLVL_0       0   Group Level - bit 0
T4IC             0xFF64   GPT1 Timer 4 Interrupt Control Register
T4IC.T4IR         7   Interrupt Request Flag
T4IC.T4IE         6   Interrupt Enable Control Bit (individually enables/disables a specific source)
T4IC.ILVL_5       5   Interrupt Priority Level - bit 5
T4IC.ILVL_4       4   Interrupt Priority Level - bit 4
T4IC.ILVL_3       3   Interrupt Priority Level - bit 3
T4IC.ILVL_2       2   Interrupt Priority Level - bit 2
T4IC.GLVL_1       1   Group Level - bit 1
T4IC.GLVL_0       0   Group Level - bit 0
T5IC             0xFF66   GPT2 Timer 5 Interrupt Control Register
T5IC.T5IR         7   Interrupt Request Flag
T5IC.T5IE         6   Interrupt Enable Control Bit (individually enables/disables a specific source)
T5IC.ILVL_5       5   Interrupt Priority Level - bit 5
T5IC.ILVL_4       4   Interrupt Priority Level - bit 4
T5IC.ILVL_3       3   Interrupt Priority Level - bit 3
T5IC.ILVL_2       2   Interrupt Priority Level - bit 2
T5IC.GLVL_1       1   Group Level - bit 1
T5IC.GLVL_0       0   Group Level - bit 0
T6IC             0xFF68   GPT2 Timer 6 Interrupt Control Register
T6IC.T2IR         7   Interrupt Request Flag
T6IC.T2IE         6   Interrupt Enable Control Bit (individually enables/disables a specific source)
T6IC.ILVL_5       5   Interrupt Priority Level - bit 5
T6IC.ILVL_4       4   Interrupt Priority Level - bit 4
T6IC.ILVL_3       3   Interrupt Priority Level - bit 3
T6IC.ILVL_2       2   Interrupt Priority Level - bit 2
T6IC.GLVL_1       1   Group Level - bit 1
T6IC.GLVL_0       0   Group Level - bit 0
CRIC             0xFF6A   GPT2 CAPREL Interrupt Control Register
CRIC.CRIR         7   Interrupt Request Flag
CRIC.CRIE         6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CRIC.ILVL_5       5   Interrupt Priority Level - bit 5
CRIC.ILVL_4       4   Interrupt Priority Level - bit 4
CRIC.ILVL_3       3   Interrupt Priority Level - bit 3
CRIC.ILVL_2       2   Interrupt Priority Level - bit 2
CRIC.GLVL_1       1   Group Level - bit 1
CRIC.GLVL_0       0   Group Level - bit 0
S0TIC            0xFF6C   Serial Channel 0 Transmit Interrupt Control Register
S0TIC.S0TIR       7   Interrupt Request Flag
S0TIC.S0TIE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
S0TIC.ILVL_5      5   Interrupt Priority Level - bit 5
S0TIC.ILVL_4      4   Interrupt Priority Level - bit 4
S0TIC.ILVL_3      3   Interrupt Priority Level - bit 3
S0TIC.ILVL_2      2   Interrupt Priority Level - bit 2
S0TIC.GLVL_1      1   Group Level - bit 1
S0TIC.GLVL_0      0   Group Level - bit 0
S0RIC            0xFF6E   Serial Channel 0 Receive Interrupt Control Register
S0RIC.S0RIR       7   Interrupt Request Flag
S0RIC.S0RIE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
S0RIC.ILVL_5      5   Interrupt Priority Level - bit 5
S0RIC.ILVL_4      4   Interrupt Priority Level - bit 4
S0RIC.ILVL_3      3   Interrupt Priority Level - bit 3
S0RIC.ILVL_2      2   Interrupt Priority Level - bit 2
S0RIC.GLVL_1      1   Group Level - bit 1
S0RIC.GLVL_0      0   Group Level - bit 0
S0EIC            0xFF70   Serial Channel 0 Error Interrupt Control Register
S0EIC.S0EIR       7   Interrupt Request Flag
S0EIC.S0EIE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
S0EIC.ILVL_5      5   Interrupt Priority Level - bit 5
S0EIC.ILVL_4      4   Interrupt Priority Level - bit 4
S0EIC.ILVL_3      3   Interrupt Priority Level - bit 3
S0EIC.ILVL_2      2   Interrupt Priority Level - bit 2
S0EIC.GLVL_1      1   Group Level - bit 1
S0EIC.GLVL_0      0   Group Level - bit 0
SSCTIC           0xFF72   SSC Transmit Interrupt Control Register
SSCTIC.SSCTIR     7   Interrupt Request Flag
SSCTIC.SSCTIE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
SSCTIC.ILVL_5     5   Interrupt Priority Level - bit 5
SSCTIC.ILVL_4     4   Interrupt Priority Level - bit 4
SSCTIC.ILVL_3     3   Interrupt Priority Level - bit 3
SSCTIC.ILVL_2     2   Interrupt Priority Level - bit 2
SSCTIC.GLVL_1     1   Group Level - bit 1
SSCTIC.GLVL_0     0   Group Level - bit 0
SSCRIC           0xFF74   SSC Receive Interrupt Control Register
SSCRIC.SSCRIR     7   Interrupt Request Flag
SSCRIC.SSCRIE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
SSCRIC.ILVL_5     5   Interrupt Priority Level - bit 5
SSCRIC.ILVL_4     4   Interrupt Priority Level - bit 4
SSCRIC.ILVL_3     3   Interrupt Priority Level - bit 3
SSCRIC.ILVL_2     2   Interrupt Priority Level - bit 2
SSCRIC.GLVL_1     1   Group Level - bit 1
SSCRIC.GLVL_0     0   Group Level - bit 0
SSCEIC           0xFF76   SSC Error Interrupt Control Register
SSCEIC.SSCEIR     7   Interrupt Request Flag
SSCEIC.SSCEIE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
SSCEIC.ILVL_5     5   Interrupt Priority Level - bit 5
SSCEIC.ILVL_4     4   Interrupt Priority Level - bit 4
SSCEIC.ILVL_3     3   Interrupt Priority Level - bit 3
SSCEIC.ILVL_2     2   Interrupt Priority Level - bit 2
SSCEIC.GLVL_1     1   Group Level - bit 1
SSCEIC.GLVL_0     0   Group Level - bit 0
URD3IC           0xFF78   UDC RX Done3  Interrupt Control Register
URD3IC.URD3IR     7   Interrupt Request Flag
URD3IC.URD3IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
URD3IC.ILVL_5     5   Interrupt Priority Level - bit 5
URD3IC.ILVL_4     4   Interrupt Priority Level - bit 4
URD3IC.ILVL_3     3   Interrupt Priority Level - bit 3
URD3IC.ILVL_2     2   Interrupt Priority Level - bit 2
URD3IC.GLVL_1     1   Group Level - bit 1
URD3IC.GLVL_0     0   Group Level - bit 0
URD4IC           0xFF7A   UDC RX Done4  Interrupt Control Register
URD4IC.URD4IR     7   Interrupt Request Flag
URD4IC.URD4IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
URD4IC.ILVL_5     5   Interrupt Priority Level - bit 5
URD4IC.ILVL_4     4   Interrupt Priority Level - bit 4
URD4IC.ILVL_3     3   Interrupt Priority Level - bit 3
URD4IC.ILVL_2     2   Interrupt Priority Level - bit 2
URD4IC.GLVL_1     1   Group Level - bit 1
URD4IC.GLVL_0     0   Group Level - bit 0
URD5IC           0xFF7C   UDC RX Done5  Interrupt Control Register
URD5IC.URD5IR     7   Interrupt Request Flag
URD5IC.URD5IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
URD5IC.ILVL_5     5   Interrupt Priority Level - bit 5
URD5IC.ILVL_4     4   Interrupt Priority Level - bit 4
URD5IC.ILVL_3     3   Interrupt Priority Level - bit 3
URD5IC.ILVL_2     2   Interrupt Priority Level - bit 2
URD5IC.GLVL_1     1   Group Level - bit 1
URD5IC.GLVL_0     0   Group Level - bit 0
URD6IC           0xFF7E   UDC RX Done6  Interrupt Control Register
URD6IC.URD6IR     7   Interrupt Request Flag
URD6IC.URD6IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
URD6IC.ILVL_5     5   Interrupt Priority Level - bit 5
URD6IC.ILVL_4     4   Interrupt Priority Level - bit 4
URD6IC.ILVL_3     3   Interrupt Priority Level - bit 3
URD6IC.ILVL_2     2   Interrupt Priority Level - bit 2
URD6IC.GLVL_1     1   Group Level - bit 1
URD6IC.GLVL_0     0   Group Level - bit 0
URD7IC           0xFF80   UDC RX Done7  Interrupt Control Register
URD7IC.URD7IR     7   Interrupt Request Flag
URD7IC.URD7IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
URD7IC.ILVL_5     5   Interrupt Priority Level - bit 5
URD7IC.ILVL_4     4   Interrupt Priority Level - bit 4
URD7IC.ILVL_3     3   Interrupt Priority Level - bit 3
URD7IC.ILVL_2     2   Interrupt Priority Level - bit 2
URD7IC.GLVL_1     1   Group Level - bit 1
URD7IC.GLVL_0     0   Group Level - bit 0
UTD0IC           0xFF82   UDC TX Done0  Interrupt Control Register
UTD0IC.UTD0IR     7   Interrupt Request Flag
UTD0IC.UTD0IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
UTD0IC.ILVL_5     5   Interrupt Priority Level - bit 5
UTD0IC.ILVL_4     4   Interrupt Priority Level - bit 4
UTD0IC.ILVL_3     3   Interrupt Priority Level - bit 3
UTD0IC.ILVL_2     2   Interrupt Priority Level - bit 2
UTD0IC.GLVL_1     1   Group Level - bit 1
UTD0IC.GLVL_0     0   Group Level - bit 0
UTD1IC           0xFF84   UDC TX Done1  Interrupt Control Register
UTD1IC.UTD1IR     7   Interrupt Request Flag
UTD1IC.UTD1IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
UTD1IC.ILVL_5     5   Interrupt Priority Level - bit 5
UTD1IC.ILVL_4     4   Interrupt Priority Level - bit 4
UTD1IC.ILVL_3     3   Interrupt Priority Level - bit 3
UTD1IC.ILVL_2     2   Interrupt Priority Level - bit 2
UTD1IC.GLVL_1     1   Group Level - bit 1
UTD1IC.GLVL_0     0   Group Level - bit 0
UTD2IC           0xFF86   UDC TX Done2  Interrupt Control Register
UTD2IC.UTD2IR     7   Interrupt Request Flag
UTD2IC.UTD2IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
UTD2IC.ILVL_5     5   Interrupt Priority Level - bit 5
UTD2IC.ILVL_4     4   Interrupt Priority Level - bit 4
UTD2IC.ILVL_3     3   Interrupt Priority Level - bit 3
UTD2IC.ILVL_2     2   Interrupt Priority Level - bit 2
UTD2IC.GLVL_1     1   Group Level - bit 1
UTD2IC.GLVL_0     0   Group Level - bit 0
FEI0IC           0xFF88   Fast External Interrupt 0 Control Register
FEI0IC.FEI0IR     7   Interrupt Request Flag
FEI0IC.FEI0IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
FEI0IC.ILVL_5     5   Interrupt Priority Level - bit 5
FEI0IC.ILVL_4     4   Interrupt Priority Level - bit 4
FEI0IC.ILVL_3     3   Interrupt Priority Level - bit 3
FEI0IC.ILVL_2     2   Interrupt Priority Level - bit 2
FEI0IC.GLVL_1     1   Group Level - bit 1
FEI0IC.GLVL_0     0   Group Level - bit 0
FEI1IC           0xFF8A   Fast External Interrupt 1 Control Register
FEI1IC.FEI1IR     7   Interrupt Request Flag
FEI1IC.FEI1IE     6   Interrupt Enable Control Bit
FEI1IC.ILVL_5     5   Interrupt Priority Level - bit 5
FEI1IC.ILVL_4     4   Interrupt Priority Level - bit 4
FEI1IC.ILVL_3     3   Interrupt Priority Level - bit 3
FEI1IC.ILVL_2     2   Interrupt Priority Level - bit 2
FEI1IC.GLVL_1     1   Group Level - bit 1
FEI1IC.GLVL_0     0   Group Level - bit 0
FEI2IC           0xFF8C   Fast External Interrupt 2 Control Register
FEI2IC.FEI2IR     7   Interrupt Request Flag
FEI2IC.FEI2IE     6   Interrupt Enable Control Bit
FEI2IC.ILVL_5     5   Interrupt Priority Level - bit 5
FEI2IC.ILVL_4     4   Interrupt Priority Level - bit 4
FEI2IC.ILVL_3     3   Interrupt Priority Level - bit 3
FEI2IC.ILVL_2     2   Interrupt Priority Level - bit 2
FEI2IC.GLVL_1     1   Group Level - bit 1
FEI2IC.GLVL_0     0   Group Level - bit 0
FEI3IC           0xFF8E   Fast External Interrupt 3 Control Register
FEI3IC.FEI3IR     7   Interrupt Request Flag
FEI3IC.FEI3IE     6   Interrupt Enable Control Bit
FEI3IC.ILVL_5     5   Interrupt Priority Level - bit 5
FEI3IC.ILVL_4     4   Interrupt Priority Level - bit 4
FEI3IC.ILVL_3     3   Interrupt Priority Level - bit 3
FEI3IC.ILVL_2     2   Interrupt Priority Level - bit 2
FEI3IC.GLVL_1     1   Group Level - bit 1
FEI3IC.GLVL_0     0   Group Level - bit 0
FEI4IC           0xFF90   Fast External Interrupt 4 Control Register
FEI4IC.FEI4IR     7   Interrupt Request Flag
FEI4IC.FEI4IE     6   Interrupt Enable Control Bit
FEI4IC.ILVL_5     5   Interrupt Priority Level - bit 5
FEI4IC.ILVL_4     4   Interrupt Priority Level - bit 4
FEI4IC.ILVL_3     3   Interrupt Priority Level - bit 3
FEI4IC.ILVL_2     2   Interrupt Priority Level - bit 2
FEI4IC.GLVL_1     1   Group Level - bit 1
FEI4IC.GLVL_0     0   Group Level - bit 0
FEI5IC           0xFF92   Fast External Interrupt 5 Control Register
FEI5IC.FEI5IR     7   Interrupt Request Flag
FEI5IC.FEI5IE     6   Interrupt Enable Control Bit
FEI5IC.ILVL_5     5   Interrupt Priority Level - bit 5
FEI5IC.ILVL_4     4   Interrupt Priority Level - bit 4
FEI5IC.ILVL_3     3   Interrupt Priority Level - bit 3
FEI5IC.ILVL_2     2   Interrupt Priority Level - bit 2
FEI5IC.GLVL_1     1   Group Level - bit 1
FEI5IC.GLVL_0     0   Group Level - bit 0
FEI6IC           0xFF94   Fast External Interrupt 6 Control Register
FEI6IC.FEI6IR     7   Interrupt Request Flag
FEI6IC.FEI6IE     6   Interrupt Enable Control Bit
FEI6IC.ILVL_5     5   Interrupt Priority Level - bit 5
FEI6IC.ILVL_4     4   Interrupt Priority Level - bit 4
FEI6IC.ILVL_3     3   Interrupt Priority Level - bit 3
FEI6IC.ILVL_2     2   Interrupt Priority Level - bit 2
FEI6IC.GLVL_1     1   Group Level - bit 1
FEI6IC.GLVL_0     0   Group Level - bit 0
FEI7IC           0xFF96   Fast External Interrupt 7 Control Register
FEI7IC.FEI7IR     7   Interrupt Request Flag
FEI7IC.FEI7IE     6   Interrupt Enable Control Bit
FEI7IC.ILVL_5     5   Interrupt Priority Level - bit 5
FEI7IC.ILVL_4     4   Interrupt Priority Level - bit 4
FEI7IC.ILVL_3     3   Interrupt Priority Level - bit 3
FEI7IC.ILVL_2     2   Interrupt Priority Level - bit 2
FEI7IC.GLVL_1     1   Group Level - bit 1
FEI7IC.GLVL_0     0   Group Level - bit 0
RES4IC           0xFF98   reserved
IOMIOIC          0xFF9A   IOM-2 IO Interrupt Control Register
IOMIOIC.IOMIOIR   7   Interrupt Request Flag           
IOMIOIC.IOMIOIE   6   Interrupt Enable Control Bit     
IOMIOIC.ILVL_5    5   Interrupt Priority Level - bit 5 
IOMIOIC.ILVL_4    4   Interrupt Priority Level - bit 4 
IOMIOIC.ILVL_3    3   Interrupt Priority Level - bit 3 
IOMIOIC.ILVL_2    2   Interrupt Priority Level - bit 2 
IOMIOIC.GLVL_1    1   Group Level - bit 1              
IOMIOIC.GLVL_0    0   Group Level - bit 0              
URD2IC           0xFF9C   UDC RX Done2  Interrupt Control Register
URD2IC.URD2IR     7   Interrupt Request Flag          
URD2IC.URD2IE     6   Interrupt Enable Control Bit    
URD2IC.ILVL_5     5   Interrupt Priority Level - bit 5
URD2IC.ILVL_4     4   Interrupt Priority Level - bit 4
URD2IC.ILVL_3     3   Interrupt Priority Level - bit 3
URD2IC.ILVL_2     2   Interrupt Priority Level - bit 2
URD2IC.GLVL_1     1   Group Level - bit 1             
URD2IC.GLVL_0     0   Group Level - bit 0             
URD1IC           0xFF9E   UDC RX Done1  Interrupt Control Register
URD1IC.URD1IR     7   Interrupt Request Flag          
URD1IC.URD1IE     6   Interrupt Enable Control Bit    
URD1IC.ILVL_5     5   Interrupt Priority Level - bit 5
URD1IC.ILVL_4     4   Interrupt Priority Level - bit 4
URD1IC.ILVL_3     3   Interrupt Priority Level - bit 3
URD1IC.ILVL_2     2   Interrupt Priority Level - bit 2
URD1IC.GLVL_1     1   Group Level - bit 1             
URD1IC.GLVL_0     0   Group Level - bit 0             
CLISNC           0xFFA8   The channel link interrupt subnode register
CLISNC.C6IR       13  Channel Service Request Flag
CLISNC.C6IE       12  Channel Link Interrupt Enable Bit
CLISNC.C4IR       9   Channel Service Request Flag
CLISNC.C4IE       8   Channel Link Interrupt Enable Bit
CLISNC.C2IR       5   Channel Service Request Flag
CLISNC.C2IE       4   Channel Link Interrupt Enable Bit
CLISNC.C0IR       1   Channel Service Request Flag
CLISNC.C0IE       0   Channel Link Interrupt Enable Bit
FOCON            0xFFAA   Frequency Output Control Register
FOCON.FOEN        15  Frequency Output Enable
FOCON.FOSS        14  Frequency Output Signal Select
FOCON.FORV_13     13  Frequency Output Reload Value - bit 13
FOCON.FORV_12     12  Frequency Output Reload Value - bit 12
FOCON.FORV_11     11  Frequency Output Reload Value - bit 11
FOCON.FORV_10     10  Frequency Output Reload Value - bit 10
FOCON.FORV_9      9   Frequency Output Reload Value - bit 9 
FOCON.FORV_8      8   Frequency Output Reload Value - bit 8 
FOCON.FOTL        6   Frequency Output Toggle Latch
FOCON.FOCNT_5     5   Frequency Output Counter - bit 5
FOCON.FOCNT_4     4   Frequency Output Counter - bit 4
FOCON.FOCNT_3     3   Frequency Output Counter - bit 3
FOCON.FOCNT_2     2   Frequency Output Counter - bit 2
FOCON.FOCNT_1     1   Frequency Output Counter - bit 1
FOCON.FOCNT_0     0   Frequency Output Counter - bit 0
TFR              0xFFAC   Trap Flag Register
TFR.NMI           15  Non Maskable Interrupt Flag
TFR.STKOF         14  Stack Overflow Flag
TFR.STKUF         13  Stack Underflow Flag
TFR.UNDOPC        7   Undefined Opcode Flag
TFR.PRTFLT        3   Protection Fault Flag
TFR.ILLOPA        2   Illegal Word Operand Access Flag
TFR.ILLINA        1   Illegal Instruction Access Flag
TFR.ILLBUS        0   Illegal External Bus Access Flag
WDTCON           0xFFAE   Watchdog Timer Control Register
WDTCON.WDTREL_15  15  Watchdog Timer Reload Value - bit 15
WDTCON.WDTREL_14  14  Watchdog Timer Reload Value - bit 14
WDTCON.WDTREL_13  13  Watchdog Timer Reload Value - bit 13
WDTCON.WDTREL_12  12  Watchdog Timer Reload Value - bit 12
WDTCON.WDTREL_11  11  Watchdog Timer Reload Value - bit 11
WDTCON.WDTREL_10  10  Watchdog Timer Reload Value - bit 10
WDTCON.WDTREL_9   9   Watchdog Timer Reload Value - bit 9 
WDTCON.WDTREL_8   8   Watchdog Timer Reload Value - bit 8 
WDTCON.LHWR       4   Long Hardware Reset Indication Flag
WDTCON.SHWR       3   Short Hardware Reset Indication Flag
WDTCON.SWR        2   Software Reset Indication Flag
WDTCON.WDTR       1   Watchdog Timer Reset Indication Flag
WDTCON.WDTIN      0   Watchdog Timer Input Frequency Select
S0CON            0xFFB0   Serial Channel 0 Control Register
S0CON.R         15  Baudrate Generator Run Bit
S0CON.LB        14  LoopBack Mode Enable Bit
S0CON.BRS       13  Baudrate Selection Bit
S0CON.ODD       12  Parity Selection Bit
S0CON.FDE       11  Fractional Divider Enable
S0CON.OE        10  Overrun Error Flag
S0CON.FE        9   Framing Error Flag
S0CON.PE        8   Parity Error Flag
S0CON.OEN       7   Overrun Check Enable Bit
S0CON.FEN       6   Framing Check Enable Bit
S0CON.PEN_RXDI  5   Parity Check Enable / IrDA Input Inverter Enable
S0CON.REN       4   Receiver Enable Bit
S0CON.STP       3   Number of Stop Bits Selection
S0CON.M_2       2   ASC0 Mode Control - bit 2
S0CON.M_1       1   ASC0 Mode Control - bit 1
S0CON.M_0       0   ASC0 Mode Control - bit 0
SSCCON           0xFFB2   SSC Control Register
S0CLC            0xFFBA   ASC Clock Control Register
S0CLC.EXDISR      3   External Disable Request
S0CLC.SUSPEN      2   Peripheral Suspend Enable Bit for OCDS
S0CLC.S0DISS      1   ASC Disable Status Bit
S0CLC.S0DISR      0   ASC Disable Request Bit
P2               0xFFC0   Port 2 Register
P2.P2_7           7   Port data register P2 bit 7 
P2.P2_6           6   Port data register P2 bit 6 
P2.P2_5           5   Port data register P2 bit 5 
P2.P2_4           4   Port data register P2 bit 4 
P2.P2_3           3   Port data register P2 bit 3 
P2.P2_2           2   Port data register P2 bit 2 
P2.P2_1           1   Port data register P2 bit 1 
P2.P2_0           0   Port data register P2 bit 0 
DP2              0xFFC2   Port 2 Direction Control Register
DP2.DP2_7         7   Port direction register DP2 bit 7
DP2.DP2_6         6   Port direction register DP2 bit 6
DP2.DP2_5         5   Port direction register DP2 bit 5
DP2.DP2_4         4   Port direction register DP2 bit 4
DP2.DP2_3         3   Port direction register DP2 bit 3
DP2.DP2_2         2   Port direction register DP2 bit 2
DP2.DP2_1         1   Port direction register DP2 bit 1
DP2.DP2_0         0   Port direction register DP2 bit 0
P3               0xFFC4   Port 3 Register
P3.P3_15          15  Port data register P3 bit 15
P3.P3_13          13  Port data register P3 bit 13
P3.P3_12          12  Port data register P3 bit 12
P3.P3_11          11  Port data register P3 bit 11
P3.P3_10          10  Port data register P3 bit 10
P3.P3_9           9   Port data register P3 bit 9 
P3.P3_8           8   Port data register P3 bit 8 
P3.P3_6           6   Port data register P3 bit 6 
P3.P3_5           5   Port data register P3 bit 5 
P3.P3_3           3   Port data register P3 bit 3 
DP3              0xFFC6   Port 3 Direction Control Register
DP3.DP3_15        15  Port direction register DP3 bit 15
DP3.DP3_13        13  Port direction register DP3 bit 13
DP3.DP3_12        12  Port direction register DP3 bit 12
DP3.DP3_11        11  Port direction register DP3 bit 11
DP3.DP3_10        10  Port direction register DP3 bit 10
DP3.DP3_9         9   Port direction register DP3 bit 9 
DP3.DP3_8         8   Port direction register DP3 bit 8 
DP3.DP3_6         6   Port direction register DP3 bit 6 
DP3.DP3_5         5   Port direction register DP3 bit 5 
DP3.DP3_3         3   Port direction register DP3 bit 3 
P4               0xFFC8   Port 4 Register (8 bits)
P4.P4_6           6   Port data register P4 bit 6
P4.P4_5           5   Port data register P4 bit 5
P4.P4_4           4   Port data register P4 bit 4 
P4.P4_3           3   Port data register P4 bit 3 
P4.P4_2           2   Port data register P4 bit 2 
P4.P4_1           1   Port data register P4 bit 1 
P4.P4_0           0   Port data register P4 bit 0 
DP4              0xFFCA   Port 4 Direction Control Register
DP4.DP4_6         6   Port direction register DP4 bit 6
DP4.DP4_5         5   Port direction register DP4 bit 5
DP4.DP4_4         4   Port direction register DP4 bit 4 
DP4.DP4_3         3   Port direction register DP4 bit 3 
DP4.DP4_2         2   Port direction register DP4 bit 2 
DP4.DP4_1         1   Port direction register DP4 bit 1 
DP4.DP4_0         0   Port direction register DP4 bit 0 
P6               0xFFCC   Port 6 Register (8 bits)
P6.P6_7           7   Port data register P6 bit 7 
P6.P6_6           6   Port data register P6 bit 6 
P6.P6_5           5   Port data register P6 bit 5 
P6.P6_4           4   Port data register P6 bit 4
P6.P6_3           3   Port data register P6 bit 3 
P6.P6_2           2   Port data register P6 bit 2 
P6.P6_1           1   Port data register P6 bit 1 
P6.P6_0           0   Port data register P6 bit 0 
DP6              0xFFCE   Port 6 Direction Control Register
DP6.DP6_7         7   Port direction register DP6 bit 7 
DP6.DP6_6         6   Port direction register DP6 bit 6 
DP6.DP6_5         5   Port direction register DP6 bit 5 
DP6.DP6_4         4   Port direction register DP6 bit 4
DP6.DP6_3         3   Port direction register DP6 bit 3 
DP6.DP6_2         2   Port direction register DP6 bit 2 
DP6.DP6_1         1   Port direction register DP6 bit 1 
DP6.DP6_0         0   Port direction register DP6 bit 0 
P7               0xFFD0   Port 7 Register (8 bits)
P7.P7_5           5   Port data register P7 bit 5 
P7.P7_4           4   Port data register P7 bit 4 
P7.P7_3           3   Port data register P7 bit 3 
P7.P7_2           2   Port data register P7 bit 2 
P7.P7_1           1   Port data register P7 bit 1 
P7.P7_0           0   Port data register P7 bit 0 
DP7              0xFFD2   Port 7 Direction Control Register
DP7.DP7_5         5   Port direction register DP7 bit 5
DP7.DP7_4         4   Port direction register DP7 bit 4
DP7.DP7_3         3   Port direction register DP7 bit 3
DP7.DP7_2         2   Port direction register DP7 bit 2
DP7.DP7_1         1   Port direction register DP7 bit 1
DP7.DP7_0         0   Port direction register DP7 bit 0


.C165_UTAH
; http://www.infineon.com/cgi/ecrm.dll/ecrm/scripts/public_download.jsp?oid=18320&parent_oid=13746


; MEMORY MAP
area DATA INT_PROG_MEM   0x0000:0x8000   Internal Program Memory Area
area BSS  RESERVED       0x8000:0xA000   Reserved for XFLASH
area BSS  RESERVED       0xA000:0xE000   Reserved for XRAM
area BSS  RESERVED       0xE000:0xE800   Reserved for Compatible XRAM
area BSS  RESERVED       0xE800:0xED00   Reserved for XPERs
area DATA EPEC           0xED00:0xED6E   EPEC Registers
area BSS  RESERVED       0xED6E:0xEE00                 
area DATA USBD           0xEE00:0xEE72   USBD Registers
area BSS  RESERVED       0xEE72:0xEF00   Reserved for XPERs
area DATA IOM-2          0xEF00:0xF000   IOM-2 Registers
area DATA E_SFR          0xF000:0xF200   ESFR Area
area DATA IRAM           0xF200:0xFE00   IRAM Area
area DATA SFR            0xFE00:0x10000  SFR Area 


; Interrupt and reset vector assignments
entry RESET     0x0000   RESET
entry NMITRAP   0x0008   NMITRAP Non-Maskable Interrupt (Class A Hardware Traps)
entry STOTRAP   0x0010   STOTRAP Stack Overflow (Class A Hardware Traps)
entry STUTRAP   0x0018   STUTRAP Stack Underflow (Class A Hardware Traps)
entry DEBTRAP   0x0020   Debug Trap
entry BTRAP     0x0028   BTRAP Class B Hardware Traps
entry URD3IE    0x0040   UDC RX Done3
entry URD4IE    0x0044   UDC RX Done4
entry URD5IE    0x0048   UDC RX Done5
entry URD6IE    0x004C   UDC RX Done6
entry URD7IE    0x0050   UDC RX Done7
entry UTD0IE    0x0054   UDC TX Done0
entry UTD1IE    0x0058   UDC TX Done1
entry UTD2IE    0x005C   UDC TX Done2
entry EX0IE     0x0060   Fast ext. Interrupt
entry EX1IE     0x0064   Fast ext. Interrupt
entry EX2IE     0x0068   Fast ext. Interrupt
entry EX3IE     0x006C   Fast ext. Interrupt
entry EX4IE     0x0070   Fast ext. Interrupt
entry EX5IE     0x0074   Fast ext. Interrupt
entry EX6IE     0x0078   Fast ext. Interrupt
entry EX7IE     0x007C   Fast ext. Interrupt
entry URD2IE    0x0080   UDC RX Done2
entry URD1IE    0x0084   UDC RX Done1
entry T2IE      0x0088   GPT Timer 2
entry T3IE      0x008C   GPT Timer 3
entry T4IE      0x0090   GPT Timer 4
entry T5IE      0x0094   GPT Timer 5
entry T6IE      0x0098   GPT Timer 6
entry CRIE      0x009C   GPT CAPREL Register
entry IOMIOIE   0x00A4   IOM-2 I/O
entry S0TIE     0x00A8   ASC Transmit
entry S0RIE     0x00AC   ASC Receive
entry S0EIE     0x00B0   ASC Error
entry SSCTIE    0x00B4   SSC Transmit
entry SSCRIE    0x00B8   SSC Receive
entry SSCEIE    0x00BC   SSC Error
entry UTD3IE    0x00C0   UDC TX Done3
entry UTD4IE    0x00C4   UDC TX Done4
entry UTD5IE    0x00C8   UDC TX Done5
entry UTD6IE    0x00CC   UDC TX Done6
entry UTD7IE    0x00D0   UDC TX Done7
entry URXRIE    0x00D4   UDC RXRR
entry UTXRIE    0x00D8   UDC TXWR
entry UCFGVIE   0x00DC   UDC Config Val
entry USOFIE    0x00E0   UDC Start of Frame
entry USSOIE    0x00E4   UDC Suspend off
entry USSIE     0x00E8   UDC Suspend
entry ULCDIE    0x00EC   UDC Load Config Done
entry USETIE    0x00F0   UDC SETUP
entry URD0IE    0x00F4   UDC RX Done0
entry EPECIE    0x00F8   EPEC
entry IOMC0TIE  0x00FC   IOM-2 Channel0 TX
entry UTXRIE    0x0100   UDC TXWR
entry EPECIE    0x0104   EPEC
entry IOMIOIE   0x0108   IOM-2 IO
entry XP3IE     0x010C   Internal PLL Lock / RTC
entry ABENDIE   0x0114   ASC Autobaud End
entry ABSTIE    0x0118   ASC Autobaud Start
entry S0TBIE    0x011C   ASC Transmit Buffer
entry IOMC0RIE  0x0120   IOM-2 Channel0 RX
entry IOMC1TIE  0x0124   IOM-2 Channel1 TX
entry IOMC1RIE  0x0128   IOM-2 Channel1 RX
entry CLISNIE   0x0130   CLISN Interrupt


; INPUT/OUTPUT PORTS

; EPEC Registers
EPECCLC                    0xED00   EPEC Clock Control Register
EPECCLC.EPECEX_DIS          3   EPEC Controller Clock Disable
EPECCLC.EPECGPSEN           2   EPEC Controller Clock OCDS Disable
EPECCLC.EPECDIS             1   EPEC Controller Clock Status
EPECCLC.EPECDISR            0   EPEC Controller Clock Disable
EPECID                     0xED08   EPEC Identification Register
EPECID.ID_15                15  EPEC Identification Register - bit 15
EPECID.ID_14                14  EPEC Identification Register - bit 14
EPECID.ID_13                13  EPEC Identification Register - bit 13
EPECID.ID_12                12  EPEC Identification Register - bit 12
EPECID.ID_11                11  EPEC Identification Register - bit 11
EPECID.ID_10                10  EPEC Identification Register - bit 10
EPECID.ID_9                 9   EPEC Identification Register - bit 9 
EPECID.ID_8                 8   EPEC Identification Register - bit 8 
EPECID.ID_7                 7   EPEC Identification Register - bit 7 
EPECID.ID_6                 6   EPEC Identification Register - bit 6 
EPECID.ID_5                 5   EPEC Identification Register - bit 5 
EPECID.ID_4                 4   EPEC Identification Register - bit 4 
EPECID.ID_3                 3   EPEC Identification Register - bit 3 
EPECID.ID_2                 2   EPEC Identification Register - bit 2 
EPECID.ID_1                 1   EPEC Identification Register - bit 1 
EPECID.ID_0                 0   EPEC Identification Register - bit 0 
EPEC_SPTR_IN_R00           0xED10   16 LSBs of USB endpoint#0 source pointer IN
EPEC_SPTR_IN_R01           0xED12   8 MSBs of USB endpoint#0 source pointer IN
EPEC_SPTR_OUT_R00          0xED14   16 LSBs of USB endpoint#0 source pointer OUT
EPEC_SPTR_OUT_R01          0xED16   8 MSBs of USB endpoint#0 source pointer OUT
EPEC_SPTR_REG10            0xED18   16 LSBs of USB endpoint#1 source pointer
EPEC_SPTR_REG10.SPTR1_15    15  16 LSBs of USB endpoint#1 source pointer - bit 15
EPEC_SPTR_REG10.SPTR1_14    14  16 LSBs of USB endpoint#1 source pointer - bit 14
EPEC_SPTR_REG10.SPTR1_13    13  16 LSBs of USB endpoint#1 source pointer - bit 13
EPEC_SPTR_REG10.SPTR1_12    12  16 LSBs of USB endpoint#1 source pointer - bit 12
EPEC_SPTR_REG10.SPTR1_11    11  16 LSBs of USB endpoint#1 source pointer - bit 11
EPEC_SPTR_REG10.SPTR1_10    10  16 LSBs of USB endpoint#1 source pointer - bit 10
EPEC_SPTR_REG10.SPTR1_9     9   16 LSBs of USB endpoint#1 source pointer - bit 9 
EPEC_SPTR_REG10.SPTR1_8     8   16 LSBs of USB endpoint#1 source pointer - bit 8 
EPEC_SPTR_REG10.SPTR1_7     7   16 LSBs of USB endpoint#1 source pointer - bit 7 
EPEC_SPTR_REG10.SPTR1_6     6   16 LSBs of USB endpoint#1 source pointer - bit 6 
EPEC_SPTR_REG10.SPTR1_5     5   16 LSBs of USB endpoint#1 source pointer - bit 5 
EPEC_SPTR_REG10.SPTR1_4     4   16 LSBs of USB endpoint#1 source pointer - bit 4 
EPEC_SPTR_REG10.SPTR1_3     3   16 LSBs of USB endpoint#1 source pointer - bit 3 
EPEC_SPTR_REG10.SPTR1_2     2   16 LSBs of USB endpoint#1 source pointer - bit 2 
EPEC_SPTR_REG10.SPTR1_1     1   16 LSBs of USB endpoint#1 source pointer - bit 1 
EPEC_SPTR_REG10.SPTR1_0     0   16 LSBs of USB endpoint#1 source pointer - bit 0 
EPEC_SPTR_REG11            0xED1A   8 MSBs of USB endpoint#1 source pointer
EPEC_SPTR_REG11.SPTR1_7     7   8 MSBs of USB endpoint#1 source pointer - bit 7
EPEC_SPTR_REG11.SPTR1_6     6   8 MSBs of USB endpoint#1 source pointer - bit 6
EPEC_SPTR_REG11.SPTR1_5     5   8 MSBs of USB endpoint#1 source pointer - bit 5
EPEC_SPTR_REG11.SPTR1_4     4   8 MSBs of USB endpoint#1 source pointer - bit 4
EPEC_SPTR_REG11.SPTR1_3     3   8 MSBs of USB endpoint#1 source pointer - bit 3
EPEC_SPTR_REG11.SPTR1_2     2   8 MSBs of USB endpoint#1 source pointer - bit 2
EPEC_SPTR_REG11.SPTR1_1     1   8 MSBs of USB endpoint#1 source pointer - bit 1
EPEC_SPTR_REG11.SPTR1_0     0   8 MSBs of USB endpoint#1 source pointer - bit 0
EPEC_SPTR_REG20            0xED1C   16 LSBs of USB endpoint#2 source pointer
EPEC_SPTR_REG20.SPTR2_15    15  16 LSBs of USB endpoint#2 source pointer - bit 15
EPEC_SPTR_REG20.SPTR2_14    14  16 LSBs of USB endpoint#2 source pointer - bit 14
EPEC_SPTR_REG20.SPTR2_13    13  16 LSBs of USB endpoint#2 source pointer - bit 13
EPEC_SPTR_REG20.SPTR2_12    12  16 LSBs of USB endpoint#2 source pointer - bit 12
EPEC_SPTR_REG20.SPTR2_11    11  16 LSBs of USB endpoint#2 source pointer - bit 11
EPEC_SPTR_REG20.SPTR2_10    10  16 LSBs of USB endpoint#2 source pointer - bit 10
EPEC_SPTR_REG20.SPTR2_9     9   16 LSBs of USB endpoint#2 source pointer - bit 9 
EPEC_SPTR_REG20.SPTR2_8     8   16 LSBs of USB endpoint#2 source pointer - bit 8 
EPEC_SPTR_REG20.SPTR2_7     7   16 LSBs of USB endpoint#2 source pointer - bit 7 
EPEC_SPTR_REG20.SPTR2_6     6   16 LSBs of USB endpoint#2 source pointer - bit 6 
EPEC_SPTR_REG20.SPTR2_5     5   16 LSBs of USB endpoint#2 source pointer - bit 5 
EPEC_SPTR_REG20.SPTR2_4     4   16 LSBs of USB endpoint#2 source pointer - bit 4 
EPEC_SPTR_REG20.SPTR2_3     3   16 LSBs of USB endpoint#2 source pointer - bit 3 
EPEC_SPTR_REG20.SPTR2_2     2   16 LSBs of USB endpoint#2 source pointer - bit 2 
EPEC_SPTR_REG20.SPTR2_1     1   16 LSBs of USB endpoint#2 source pointer - bit 1 
EPEC_SPTR_REG20.SPTR2_0     0   16 LSBs of USB endpoint#2 source pointer - bit 0 
EPEC_SPTR_REG21            0xED1E   8 MSBs of USB endpoint#2 source pointer
EPEC_SPTR_REG21.SPTR2_7     7   8 MSBs of USB endpoint#2 source pointer - bit 7
EPEC_SPTR_REG21.SPTR2_6     6   8 MSBs of USB endpoint#2 source pointer - bit 6
EPEC_SPTR_REG21.SPTR2_5     5   8 MSBs of USB endpoint#2 source pointer - bit 5
EPEC_SPTR_REG21.SPTR2_4     4   8 MSBs of USB endpoint#2 source pointer - bit 4
EPEC_SPTR_REG21.SPTR2_3     3   8 MSBs of USB endpoint#2 source pointer - bit 3
EPEC_SPTR_REG21.SPTR2_2     2   8 MSBs of USB endpoint#2 source pointer - bit 2
EPEC_SPTR_REG21.SPTR2_1     1   8 MSBs of USB endpoint#2 source pointer - bit 1
EPEC_SPTR_REG21.SPTR2_0     0   8 MSBs of USB endpoint#2 source pointer - bit 0
EPEC_SPTR_REG30            0xED20   16 LSBs of USB endpoint#3 source pointer
EPEC_SPTR_REG30.SPTR3_15    15  16 LSBs of USB endpoint#3 source pointer - bit 15
EPEC_SPTR_REG30.SPTR3_14    14  16 LSBs of USB endpoint#3 source pointer - bit 14
EPEC_SPTR_REG30.SPTR3_13    13  16 LSBs of USB endpoint#3 source pointer - bit 13
EPEC_SPTR_REG30.SPTR3_12    12  16 LSBs of USB endpoint#3 source pointer - bit 12
EPEC_SPTR_REG30.SPTR3_11    11  16 LSBs of USB endpoint#3 source pointer - bit 11
EPEC_SPTR_REG30.SPTR3_10    10  16 LSBs of USB endpoint#3 source pointer - bit 10
EPEC_SPTR_REG30.SPTR3_9     9   16 LSBs of USB endpoint#3 source pointer - bit 9 
EPEC_SPTR_REG30.SPTR3_8     8   16 LSBs of USB endpoint#3 source pointer - bit 8 
EPEC_SPTR_REG30.SPTR3_7     7   16 LSBs of USB endpoint#3 source pointer - bit 7 
EPEC_SPTR_REG30.SPTR3_6     6   16 LSBs of USB endpoint#3 source pointer - bit 6 
EPEC_SPTR_REG30.SPTR3_5     5   16 LSBs of USB endpoint#3 source pointer - bit 5 
EPEC_SPTR_REG30.SPTR3_4     4   16 LSBs of USB endpoint#3 source pointer - bit 4 
EPEC_SPTR_REG30.SPTR3_3     3   16 LSBs of USB endpoint#3 source pointer - bit 3 
EPEC_SPTR_REG30.SPTR3_2     2   16 LSBs of USB endpoint#3 source pointer - bit 2 
EPEC_SPTR_REG30.SPTR3_1     1   16 LSBs of USB endpoint#3 source pointer - bit 1 
EPEC_SPTR_REG30.SPTR3_0     0   16 LSBs of USB endpoint#3 source pointer - bit 0 
EPEC_SPTR_REG31            0xED22   8 MSBs of USB endpoint#3 source pointer
EPEC_SPTR_REG31.SPTR3_7     7   8 MSBs of USB endpoint#3 source pointer - bit 7
EPEC_SPTR_REG31.SPTR3_6     6   8 MSBs of USB endpoint#3 source pointer - bit 6
EPEC_SPTR_REG31.SPTR3_5     5   8 MSBs of USB endpoint#3 source pointer - bit 5
EPEC_SPTR_REG31.SPTR3_4     4   8 MSBs of USB endpoint#3 source pointer - bit 4
EPEC_SPTR_REG31.SPTR3_3     3   8 MSBs of USB endpoint#3 source pointer - bit 3
EPEC_SPTR_REG31.SPTR3_2     2   8 MSBs of USB endpoint#3 source pointer - bit 2
EPEC_SPTR_REG31.SPTR3_1     1   8 MSBs of USB endpoint#3 source pointer - bit 1
EPEC_SPTR_REG31.SPTR3_0     0   8 MSBs of USB endpoint#3 source pointer - bit 0
EPEC_SPTR_REG40            0xED24   16 LSBs of USB endpoint#4 source pointer
EPEC_SPTR_REG40.SPTR4_15    15  16 LSBs of USB endpoint#4 source pointer - bit 15
EPEC_SPTR_REG40.SPTR4_14    14  16 LSBs of USB endpoint#4 source pointer - bit 14
EPEC_SPTR_REG40.SPTR4_13    13  16 LSBs of USB endpoint#4 source pointer - bit 13
EPEC_SPTR_REG40.SPTR4_12    12  16 LSBs of USB endpoint#4 source pointer - bit 12
EPEC_SPTR_REG40.SPTR4_11    11  16 LSBs of USB endpoint#4 source pointer - bit 11
EPEC_SPTR_REG40.SPTR4_10    10  16 LSBs of USB endpoint#4 source pointer - bit 10
EPEC_SPTR_REG40.SPTR4_9     9   16 LSBs of USB endpoint#4 source pointer - bit 9 
EPEC_SPTR_REG40.SPTR4_8     8   16 LSBs of USB endpoint#4 source pointer - bit 8 
EPEC_SPTR_REG40.SPTR4_7     7   16 LSBs of USB endpoint#4 source pointer - bit 7 
EPEC_SPTR_REG40.SPTR4_6     6   16 LSBs of USB endpoint#4 source pointer - bit 6 
EPEC_SPTR_REG40.SPTR4_5     5   16 LSBs of USB endpoint#4 source pointer - bit 5 
EPEC_SPTR_REG40.SPTR4_4     4   16 LSBs of USB endpoint#4 source pointer - bit 4 
EPEC_SPTR_REG40.SPTR4_3     3   16 LSBs of USB endpoint#4 source pointer - bit 3 
EPEC_SPTR_REG40.SPTR4_2     2   16 LSBs of USB endpoint#4 source pointer - bit 2 
EPEC_SPTR_REG40.SPTR4_1     1   16 LSBs of USB endpoint#4 source pointer - bit 1 
EPEC_SPTR_REG40.SPTR4_0     0   16 LSBs of USB endpoint#4 source pointer - bit 0 
EPEC_SPTR_REG41            0xED26   8 MSBs of USB endpoint#4 source pointer
EPEC_SPTR_REG41.SPTR4_7     7   8 MSBs of USB endpoint#4 source pointer - bit 7
EPEC_SPTR_REG41.SPTR4_6     6   8 MSBs of USB endpoint#4 source pointer - bit 6
EPEC_SPTR_REG41.SPTR4_5     5   8 MSBs of USB endpoint#4 source pointer - bit 5
EPEC_SPTR_REG41.SPTR4_4     4   8 MSBs of USB endpoint#4 source pointer - bit 4
EPEC_SPTR_REG41.SPTR4_3     3   8 MSBs of USB endpoint#4 source pointer - bit 3
EPEC_SPTR_REG41.SPTR4_2     2   8 MSBs of USB endpoint#4 source pointer - bit 2
EPEC_SPTR_REG41.SPTR4_1     1   8 MSBs of USB endpoint#4 source pointer - bit 1
EPEC_SPTR_REG41.SPTR4_0     0   8 MSBs of USB endpoint#4 source pointer - bit 0
EPEC_SPTR_REG50            0xED28   16 LSBs of USB endpoint#5 source pointer
EPEC_SPTR_REG50.SPTR5_15    15  16 LSBs of USB endpoint#5 source pointer - bit 15
EPEC_SPTR_REG50.SPTR5_14    14  16 LSBs of USB endpoint#5 source pointer - bit 14
EPEC_SPTR_REG50.SPTR5_13    13  16 LSBs of USB endpoint#5 source pointer - bit 13
EPEC_SPTR_REG50.SPTR5_12    12  16 LSBs of USB endpoint#5 source pointer - bit 12
EPEC_SPTR_REG50.SPTR5_11    11  16 LSBs of USB endpoint#5 source pointer - bit 11
EPEC_SPTR_REG50.SPTR5_10    10  16 LSBs of USB endpoint#5 source pointer - bit 10
EPEC_SPTR_REG50.SPTR5_9     9   16 LSBs of USB endpoint#5 source pointer - bit 9 
EPEC_SPTR_REG50.SPTR5_8     8   16 LSBs of USB endpoint#5 source pointer - bit 8 
EPEC_SPTR_REG50.SPTR5_7     7   16 LSBs of USB endpoint#5 source pointer - bit 7 
EPEC_SPTR_REG50.SPTR5_6     6   16 LSBs of USB endpoint#5 source pointer - bit 6 
EPEC_SPTR_REG50.SPTR5_5     5   16 LSBs of USB endpoint#5 source pointer - bit 5 
EPEC_SPTR_REG50.SPTR5_4     4   16 LSBs of USB endpoint#5 source pointer - bit 4 
EPEC_SPTR_REG50.SPTR5_3     3   16 LSBs of USB endpoint#5 source pointer - bit 3 
EPEC_SPTR_REG50.SPTR5_2     2   16 LSBs of USB endpoint#5 source pointer - bit 2 
EPEC_SPTR_REG50.SPTR5_1     1   16 LSBs of USB endpoint#5 source pointer - bit 1 
EPEC_SPTR_REG50.SPTR5_0     0   16 LSBs of USB endpoint#5 source pointer - bit 0 
EPEC_SPTR_REG51            0xED2A   8 MSBs of USB endpoint#5 source pointer
EPEC_SPTR_REG51.SPTR5_7     7   8 MSBs of USB endpoint#5 source pointer - bit 7
EPEC_SPTR_REG51.SPTR5_6     6   8 MSBs of USB endpoint#5 source pointer - bit 6
EPEC_SPTR_REG51.SPTR5_5     5   8 MSBs of USB endpoint#5 source pointer - bit 5
EPEC_SPTR_REG51.SPTR5_4     4   8 MSBs of USB endpoint#5 source pointer - bit 4
EPEC_SPTR_REG51.SPTR5_3     3   8 MSBs of USB endpoint#5 source pointer - bit 3
EPEC_SPTR_REG51.SPTR5_2     2   8 MSBs of USB endpoint#5 source pointer - bit 2
EPEC_SPTR_REG51.SPTR5_1     1   8 MSBs of USB endpoint#5 source pointer - bit 1
EPEC_SPTR_REG51.SPTR5_0     0   8 MSBs of USB endpoint#5 source pointer - bit 0
EPEC_SPTR_REG60            0xED2C   16 LSBs of USB endpoint#6 source pointer
EPEC_SPTR_REG60.SPTR6_15    15  16 LSBs of USB endpoint#6 source pointer - bit 15
EPEC_SPTR_REG60.SPTR6_14    14  16 LSBs of USB endpoint#6 source pointer - bit 14
EPEC_SPTR_REG60.SPTR6_13    13  16 LSBs of USB endpoint#6 source pointer - bit 13
EPEC_SPTR_REG60.SPTR6_12    12  16 LSBs of USB endpoint#6 source pointer - bit 12
EPEC_SPTR_REG60.SPTR6_11    11  16 LSBs of USB endpoint#6 source pointer - bit 11
EPEC_SPTR_REG60.SPTR6_10    10  16 LSBs of USB endpoint#6 source pointer - bit 10
EPEC_SPTR_REG60.SPTR6_9     9   16 LSBs of USB endpoint#6 source pointer - bit 9 
EPEC_SPTR_REG60.SPTR6_8     8   16 LSBs of USB endpoint#6 source pointer - bit 8 
EPEC_SPTR_REG60.SPTR6_7     7   16 LSBs of USB endpoint#6 source pointer - bit 7 
EPEC_SPTR_REG60.SPTR6_6     6   16 LSBs of USB endpoint#6 source pointer - bit 6 
EPEC_SPTR_REG60.SPTR6_5     5   16 LSBs of USB endpoint#6 source pointer - bit 5 
EPEC_SPTR_REG60.SPTR6_4     4   16 LSBs of USB endpoint#6 source pointer - bit 4 
EPEC_SPTR_REG60.SPTR6_3     3   16 LSBs of USB endpoint#6 source pointer - bit 3 
EPEC_SPTR_REG60.SPTR6_2     2   16 LSBs of USB endpoint#6 source pointer - bit 2 
EPEC_SPTR_REG60.SPTR6_1     1   16 LSBs of USB endpoint#6 source pointer - bit 1 
EPEC_SPTR_REG60.SPTR6_0     0   16 LSBs of USB endpoint#6 source pointer - bit 0 
EPEC_SPTR_REG61            0xED2E   8 MSBs of USB endpoint#6 source pointer
EPEC_SPTR_REG61.SPTR6_7     7   8 MSBs of USB endpoint#6 source pointer - bit 7
EPEC_SPTR_REG61.SPTR6_6     6   8 MSBs of USB endpoint#6 source pointer - bit 6
EPEC_SPTR_REG61.SPTR6_5     5   8 MSBs of USB endpoint#6 source pointer - bit 5
EPEC_SPTR_REG61.SPTR6_4     4   8 MSBs of USB endpoint#6 source pointer - bit 4
EPEC_SPTR_REG61.SPTR6_3     3   8 MSBs of USB endpoint#6 source pointer - bit 3
EPEC_SPTR_REG61.SPTR6_2     2   8 MSBs of USB endpoint#6 source pointer - bit 2
EPEC_SPTR_REG61.SPTR6_1     1   8 MSBs of USB endpoint#6 source pointer - bit 1
EPEC_SPTR_REG61.SPTR6_0     0   8 MSBs of USB endpoint#6 source pointer - bit 0
EPEC_SPTR_REG70            0xED30   16 LSBs of USB endpoint#7 source pointer
EPEC_SPTR_REG70.SPTR7_15    15  16 LSBs of USB endpoint#7 source pointer - bit 15
EPEC_SPTR_REG70.SPTR7_14    14  16 LSBs of USB endpoint#7 source pointer - bit 14
EPEC_SPTR_REG70.SPTR7_13    13  16 LSBs of USB endpoint#7 source pointer - bit 13
EPEC_SPTR_REG70.SPTR7_12    12  16 LSBs of USB endpoint#7 source pointer - bit 12
EPEC_SPTR_REG70.SPTR7_11    11  16 LSBs of USB endpoint#7 source pointer - bit 11
EPEC_SPTR_REG70.SPTR7_10    10  16 LSBs of USB endpoint#7 source pointer - bit 10
EPEC_SPTR_REG70.SPTR7_9     9   16 LSBs of USB endpoint#7 source pointer - bit 9 
EPEC_SPTR_REG70.SPTR7_8     8   16 LSBs of USB endpoint#7 source pointer - bit 8 
EPEC_SPTR_REG70.SPTR7_7     7   16 LSBs of USB endpoint#7 source pointer - bit 7 
EPEC_SPTR_REG70.SPTR7_6     6   16 LSBs of USB endpoint#7 source pointer - bit 6 
EPEC_SPTR_REG70.SPTR7_5     5   16 LSBs of USB endpoint#7 source pointer - bit 5 
EPEC_SPTR_REG70.SPTR7_4     4   16 LSBs of USB endpoint#7 source pointer - bit 4 
EPEC_SPTR_REG70.SPTR7_3     3   16 LSBs of USB endpoint#7 source pointer - bit 3 
EPEC_SPTR_REG70.SPTR7_2     2   16 LSBs of USB endpoint#7 source pointer - bit 2 
EPEC_SPTR_REG70.SPTR7_1     1   16 LSBs of USB endpoint#7 source pointer - bit 1 
EPEC_SPTR_REG70.SPTR7_0     0   16 LSBs of USB endpoint#7 source pointer - bit 0 
EPEC_SPTR_REG71            0xED32   8 MSBs of USB endpoint#7 source pointer
EPEC_SPTR_REG71.SPTR7_7     7   8 MSBs of USB endpoint#7 source pointer - bit 7
EPEC_SPTR_REG71.SPTR7_6     6   8 MSBs of USB endpoint#7 source pointer - bit 6
EPEC_SPTR_REG71.SPTR7_5     5   8 MSBs of USB endpoint#7 source pointer - bit 5
EPEC_SPTR_REG71.SPTR7_4     4   8 MSBs of USB endpoint#7 source pointer - bit 4
EPEC_SPTR_REG71.SPTR7_3     3   8 MSBs of USB endpoint#7 source pointer - bit 3
EPEC_SPTR_REG71.SPTR7_2     2   8 MSBs of USB endpoint#7 source pointer - bit 2
EPEC_SPTR_REG71.SPTR7_1     1   8 MSBs of USB endpoint#7 source pointer - bit 1
EPEC_SPTR_REG71.SPTR7_0     0   8 MSBs of USB endpoint#7 source pointer - bit 0
EPEC_DPTR_IN_R00           0xED34   16 LSBs of USB endpoint#0 destination pointer IN
EPEC_DPTR_IN_R01           0xED36   8 MSBs of USB endpoint#0 destination pointer IN
EPEC_DPTR_OUT_R00          0xED38   16 LSBs of USB endpoint#0 destination pointer OUT
EPEC_DPTR_OUT_R01          0xED3A   8 MSBs of USB endpoint#0 destination pointer OUT
EPEC_DPTR_REG10            0xED3C   16 LSBs of USB endpoint#1 destination pointer
EPEC_DPTR_REG10.DPTR1_15    15  16 LSBs of USB endpoint#1 destination pointer - bit 15
EPEC_DPTR_REG10.DPTR1_14    14  16 LSBs of USB endpoint#1 destination pointer - bit 14
EPEC_DPTR_REG10.DPTR1_13    13  16 LSBs of USB endpoint#1 destination pointer - bit 13
EPEC_DPTR_REG10.DPTR1_12    12  16 LSBs of USB endpoint#1 destination pointer - bit 12
EPEC_DPTR_REG10.DPTR1_11    11  16 LSBs of USB endpoint#1 destination pointer - bit 11
EPEC_DPTR_REG10.DPTR1_10    10  16 LSBs of USB endpoint#1 destination pointer - bit 10
EPEC_DPTR_REG10.DPTR1_9     9   16 LSBs of USB endpoint#1 destination pointer - bit 9 
EPEC_DPTR_REG10.DPTR1_8     8   16 LSBs of USB endpoint#1 destination pointer - bit 8 
EPEC_DPTR_REG10.DPTR1_7     7   16 LSBs of USB endpoint#1 destination pointer - bit 7 
EPEC_DPTR_REG10.DPTR1_6     6   16 LSBs of USB endpoint#1 destination pointer - bit 6 
EPEC_DPTR_REG10.DPTR1_5     5   16 LSBs of USB endpoint#1 destination pointer - bit 5 
EPEC_DPTR_REG10.DPTR1_4     4   16 LSBs of USB endpoint#1 destination pointer - bit 4 
EPEC_DPTR_REG10.DPTR1_3     3   16 LSBs of USB endpoint#1 destination pointer - bit 3 
EPEC_DPTR_REG10.DPTR1_2     2   16 LSBs of USB endpoint#1 destination pointer - bit 2 
EPEC_DPTR_REG10.DPTR1_1     1   16 LSBs of USB endpoint#1 destination pointer - bit 1 
EPEC_DPTR_REG10.DPTR1_0     0   16 LSBs of USB endpoint#1 destination pointer - bit 0 
EPEC_DPTR_REG11            0xED3E   8 MSBs of USB endpoint#1 destination pointer
EPEC_DPTR_REG11.DPTR1_7     7   8 MSBs of USB endpoint#1 source pointer - bit 7
EPEC_DPTR_REG11.DPTR1_6     6   8 MSBs of USB endpoint#1 source pointer - bit 6
EPEC_DPTR_REG11.DPTR1_5     5   8 MSBs of USB endpoint#1 source pointer - bit 5
EPEC_DPTR_REG11.DPTR1_4     4   8 MSBs of USB endpoint#1 source pointer - bit 4
EPEC_DPTR_REG11.DPTR1_3     3   8 MSBs of USB endpoint#1 source pointer - bit 3
EPEC_DPTR_REG11.DPTR1_2     2   8 MSBs of USB endpoint#1 source pointer - bit 2
EPEC_DPTR_REG11.DPTR1_1     1   8 MSBs of USB endpoint#1 source pointer - bit 1
EPEC_DPTR_REG11.DPTR1_0     0   8 MSBs of USB endpoint#1 source pointer - bit 0
EPEC_DPTR_REG20            0xED40   16 LSBs of USB endpoint#2 destination pointer
EPEC_DPTR_REG20.DPTR2_15    15  16 LSBs of USB endpoint#2 destination pointer - bit 15
EPEC_DPTR_REG20.DPTR2_14    14  16 LSBs of USB endpoint#2 destination pointer - bit 14
EPEC_DPTR_REG20.DPTR2_13    13  16 LSBs of USB endpoint#2 destination pointer - bit 13
EPEC_DPTR_REG20.DPTR2_12    12  16 LSBs of USB endpoint#2 destination pointer - bit 12
EPEC_DPTR_REG20.DPTR2_11    11  16 LSBs of USB endpoint#2 destination pointer - bit 11
EPEC_DPTR_REG20.DPTR2_10    10  16 LSBs of USB endpoint#2 destination pointer - bit 10
EPEC_DPTR_REG20.DPTR2_9     9   16 LSBs of USB endpoint#2 destination pointer - bit 9 
EPEC_DPTR_REG20.DPTR2_8     8   16 LSBs of USB endpoint#2 destination pointer - bit 8 
EPEC_DPTR_REG20.DPTR2_7     7   16 LSBs of USB endpoint#2 destination pointer - bit 7 
EPEC_DPTR_REG20.DPTR2_6     6   16 LSBs of USB endpoint#2 destination pointer - bit 6 
EPEC_DPTR_REG20.DPTR2_5     5   16 LSBs of USB endpoint#2 destination pointer - bit 5 
EPEC_DPTR_REG20.DPTR2_4     4   16 LSBs of USB endpoint#2 destination pointer - bit 4 
EPEC_DPTR_REG20.DPTR2_3     3   16 LSBs of USB endpoint#2 destination pointer - bit 3 
EPEC_DPTR_REG20.DPTR2_2     2   16 LSBs of USB endpoint#2 destination pointer - bit 2 
EPEC_DPTR_REG20.DPTR2_1     1   16 LSBs of USB endpoint#2 destination pointer - bit 1 
EPEC_DPTR_REG20.DPTR2_0     0   16 LSBs of USB endpoint#2 destination pointer - bit 0 
EPEC_DPTR_REG21            0xED42   8 MSBs of USB endpoint#2 destination pointer
EPEC_DPTR_REG21.DPTR2_7     7   8 MSBs of USB endpoint#2 source pointer - bit 7
EPEC_DPTR_REG21.DPTR2_6     6   8 MSBs of USB endpoint#2 source pointer - bit 6
EPEC_DPTR_REG21.DPTR2_5     5   8 MSBs of USB endpoint#2 source pointer - bit 5
EPEC_DPTR_REG21.DPTR2_4     4   8 MSBs of USB endpoint#2 source pointer - bit 4
EPEC_DPTR_REG21.DPTR2_3     3   8 MSBs of USB endpoint#2 source pointer - bit 3
EPEC_DPTR_REG21.DPTR2_2     2   8 MSBs of USB endpoint#2 source pointer - bit 2
EPEC_DPTR_REG21.DPTR2_1     1   8 MSBs of USB endpoint#2 source pointer - bit 1
EPEC_DPTR_REG21.DPTR2_0     0   8 MSBs of USB endpoint#2 source pointer - bit 0
EPEC_DPTR_REG30            0xED44   16 LSBs of USB endpoint#3 destination pointer
EPEC_DPTR_REG30.DPTR3_15    15  16 LSBs of USB endpoint#3 destination pointer - bit 15
EPEC_DPTR_REG30.DPTR3_14    14  16 LSBs of USB endpoint#3 destination pointer - bit 14
EPEC_DPTR_REG30.DPTR3_13    13  16 LSBs of USB endpoint#3 destination pointer - bit 13
EPEC_DPTR_REG30.DPTR3_12    12  16 LSBs of USB endpoint#3 destination pointer - bit 12
EPEC_DPTR_REG30.DPTR3_11    11  16 LSBs of USB endpoint#3 destination pointer - bit 11
EPEC_DPTR_REG30.DPTR3_10    10  16 LSBs of USB endpoint#3 destination pointer - bit 10
EPEC_DPTR_REG30.DPTR3_9     9   16 LSBs of USB endpoint#3 destination pointer - bit 9 
EPEC_DPTR_REG30.DPTR3_8     8   16 LSBs of USB endpoint#3 destination pointer - bit 8 
EPEC_DPTR_REG30.DPTR3_7     7   16 LSBs of USB endpoint#3 destination pointer - bit 7 
EPEC_DPTR_REG30.DPTR3_6     6   16 LSBs of USB endpoint#3 destination pointer - bit 6 
EPEC_DPTR_REG30.DPTR3_5     5   16 LSBs of USB endpoint#3 destination pointer - bit 5 
EPEC_DPTR_REG30.DPTR3_4     4   16 LSBs of USB endpoint#3 destination pointer - bit 4 
EPEC_DPTR_REG30.DPTR3_3     3   16 LSBs of USB endpoint#3 destination pointer - bit 3 
EPEC_DPTR_REG30.DPTR3_2     2   16 LSBs of USB endpoint#3 destination pointer - bit 2 
EPEC_DPTR_REG30.DPTR3_1     1   16 LSBs of USB endpoint#3 destination pointer - bit 1 
EPEC_DPTR_REG30.DPTR3_0     0   16 LSBs of USB endpoint#3 destination pointer - bit 0 
EPEC_DPTR_REG31            0xED46   8 MSBs of USB endpoint#3 destination pointer
EPEC_DPTR_REG31.DPTR3_7     7   8 MSBs of USB endpoint#3 source pointer - bit 7
EPEC_DPTR_REG31.DPTR3_6     6   8 MSBs of USB endpoint#3 source pointer - bit 6
EPEC_DPTR_REG31.DPTR3_5     5   8 MSBs of USB endpoint#3 source pointer - bit 5
EPEC_DPTR_REG31.DPTR3_4     4   8 MSBs of USB endpoint#3 source pointer - bit 4
EPEC_DPTR_REG31.DPTR3_3     3   8 MSBs of USB endpoint#3 source pointer - bit 3
EPEC_DPTR_REG31.DPTR3_2     2   8 MSBs of USB endpoint#3 source pointer - bit 2
EPEC_DPTR_REG31.DPTR3_1     1   8 MSBs of USB endpoint#3 source pointer - bit 1
EPEC_DPTR_REG31.DPTR3_0     0   8 MSBs of USB endpoint#3 source pointer - bit 0
EPEC_DPTR_REG40            0xED48   16 LSBs of USB endpoint#4 destination pointer
EPEC_DPTR_REG40.DPTR4_15    15  16 LSBs of USB endpoint#4 destination pointer - bit 15
EPEC_DPTR_REG40.DPTR4_14    14  16 LSBs of USB endpoint#4 destination pointer - bit 14
EPEC_DPTR_REG40.DPTR4_13    13  16 LSBs of USB endpoint#4 destination pointer - bit 13
EPEC_DPTR_REG40.DPTR4_12    12  16 LSBs of USB endpoint#4 destination pointer - bit 12
EPEC_DPTR_REG40.DPTR4_11    11  16 LSBs of USB endpoint#4 destination pointer - bit 11
EPEC_DPTR_REG40.DPTR4_10    10  16 LSBs of USB endpoint#4 destination pointer - bit 10
EPEC_DPTR_REG40.DPTR4_9     9   16 LSBs of USB endpoint#4 destination pointer - bit 9 
EPEC_DPTR_REG40.DPTR4_8     8   16 LSBs of USB endpoint#4 destination pointer - bit 8 
EPEC_DPTR_REG40.DPTR4_7     7   16 LSBs of USB endpoint#4 destination pointer - bit 7 
EPEC_DPTR_REG40.DPTR4_6     6   16 LSBs of USB endpoint#4 destination pointer - bit 6 
EPEC_DPTR_REG40.DPTR4_5     5   16 LSBs of USB endpoint#4 destination pointer - bit 5 
EPEC_DPTR_REG40.DPTR4_4     4   16 LSBs of USB endpoint#4 destination pointer - bit 4 
EPEC_DPTR_REG40.DPTR4_3     3   16 LSBs of USB endpoint#4 destination pointer - bit 3 
EPEC_DPTR_REG40.DPTR4_2     2   16 LSBs of USB endpoint#4 destination pointer - bit 2 
EPEC_DPTR_REG40.DPTR4_1     1   16 LSBs of USB endpoint#4 destination pointer - bit 1 
EPEC_DPTR_REG40.DPTR4_0     0   16 LSBs of USB endpoint#4 destination pointer - bit 0 
EPEC_DPTR_REG41            0xED4A   8 MSBs of USB endpoint#4 destination pointer
EPEC_DPTR_REG41.DPTR4_7     7   8 MSBs of USB endpoint#4 source pointer - bit 7
EPEC_DPTR_REG41.DPTR4_6     6   8 MSBs of USB endpoint#4 source pointer - bit 6
EPEC_DPTR_REG41.DPTR4_5     5   8 MSBs of USB endpoint#4 source pointer - bit 5
EPEC_DPTR_REG41.DPTR4_4     4   8 MSBs of USB endpoint#4 source pointer - bit 4
EPEC_DPTR_REG41.DPTR4_3     3   8 MSBs of USB endpoint#4 source pointer - bit 3
EPEC_DPTR_REG41.DPTR4_2     2   8 MSBs of USB endpoint#4 source pointer - bit 2
EPEC_DPTR_REG41.DPTR4_1     1   8 MSBs of USB endpoint#4 source pointer - bit 1
EPEC_DPTR_REG41.DPTR4_0     0   8 MSBs of USB endpoint#4 source pointer - bit 0
EPEC_DPTR_REG50            0xED4C   16 LSBs of USB endpoint#5 destination pointer
EPEC_DPTR_REG50.DPTR5_15    15  16 LSBs of USB endpoint#5 destination pointer - bit 15
EPEC_DPTR_REG50.DPTR5_14    14  16 LSBs of USB endpoint#5 destination pointer - bit 14
EPEC_DPTR_REG50.DPTR5_13    13  16 LSBs of USB endpoint#5 destination pointer - bit 13
EPEC_DPTR_REG50.DPTR5_12    12  16 LSBs of USB endpoint#5 destination pointer - bit 12
EPEC_DPTR_REG50.DPTR5_11    11  16 LSBs of USB endpoint#5 destination pointer - bit 11
EPEC_DPTR_REG50.DPTR5_10    10  16 LSBs of USB endpoint#5 destination pointer - bit 10
EPEC_DPTR_REG50.DPTR5_9     9   16 LSBs of USB endpoint#5 destination pointer - bit 9 
EPEC_DPTR_REG50.DPTR5_8     8   16 LSBs of USB endpoint#5 destination pointer - bit 8 
EPEC_DPTR_REG50.DPTR5_7     7   16 LSBs of USB endpoint#5 destination pointer - bit 7 
EPEC_DPTR_REG50.DPTR5_6     6   16 LSBs of USB endpoint#5 destination pointer - bit 6 
EPEC_DPTR_REG50.DPTR5_5     5   16 LSBs of USB endpoint#5 destination pointer - bit 5 
EPEC_DPTR_REG50.DPTR5_4     4   16 LSBs of USB endpoint#5 destination pointer - bit 4 
EPEC_DPTR_REG50.DPTR5_3     3   16 LSBs of USB endpoint#5 destination pointer - bit 3 
EPEC_DPTR_REG50.DPTR5_2     2   16 LSBs of USB endpoint#5 destination pointer - bit 2 
EPEC_DPTR_REG50.DPTR5_1     1   16 LSBs of USB endpoint#5 destination pointer - bit 1 
EPEC_DPTR_REG50.DPTR5_0     0   16 LSBs of USB endpoint#5 destination pointer - bit 0 
EPEC_DPTR_REG51            0xED4E   8 MSBs of USB endpoint#5 destination pointer
EPEC_DPTR_REG51.DPTR5_7     7   8 MSBs of USB endpoint#5 source pointer - bit 7
EPEC_DPTR_REG51.DPTR5_6     6   8 MSBs of USB endpoint#5 source pointer - bit 6
EPEC_DPTR_REG51.DPTR5_5     5   8 MSBs of USB endpoint#5 source pointer - bit 5
EPEC_DPTR_REG51.DPTR5_4     4   8 MSBs of USB endpoint#5 source pointer - bit 4
EPEC_DPTR_REG51.DPTR5_3     3   8 MSBs of USB endpoint#5 source pointer - bit 3
EPEC_DPTR_REG51.DPTR5_2     2   8 MSBs of USB endpoint#5 source pointer - bit 2
EPEC_DPTR_REG51.DPTR5_1     1   8 MSBs of USB endpoint#5 source pointer - bit 1
EPEC_DPTR_REG51.DPTR5_0     0   8 MSBs of USB endpoint#5 source pointer - bit 0
EPEC_DPTR_REG60            0xED50   16 LSBs of USB endpoint#6 destination pointer
EPEC_DPTR_REG60.DPTR6_15    15  16 LSBs of USB endpoint#6 destination pointer - bit 15
EPEC_DPTR_REG60.DPTR6_14    14  16 LSBs of USB endpoint#6 destination pointer - bit 14
EPEC_DPTR_REG60.DPTR6_13    13  16 LSBs of USB endpoint#6 destination pointer - bit 13
EPEC_DPTR_REG60.DPTR6_12    12  16 LSBs of USB endpoint#6 destination pointer - bit 12
EPEC_DPTR_REG60.DPTR6_11    11  16 LSBs of USB endpoint#6 destination pointer - bit 11
EPEC_DPTR_REG60.DPTR6_10    10  16 LSBs of USB endpoint#6 destination pointer - bit 10
EPEC_DPTR_REG60.DPTR6_9     9   16 LSBs of USB endpoint#6 destination pointer - bit 9 
EPEC_DPTR_REG60.DPTR6_8     8   16 LSBs of USB endpoint#6 destination pointer - bit 8 
EPEC_DPTR_REG60.DPTR6_7     7   16 LSBs of USB endpoint#6 destination pointer - bit 7 
EPEC_DPTR_REG60.DPTR6_6     6   16 LSBs of USB endpoint#6 destination pointer - bit 6 
EPEC_DPTR_REG60.DPTR6_5     5   16 LSBs of USB endpoint#6 destination pointer - bit 5 
EPEC_DPTR_REG60.DPTR6_4     4   16 LSBs of USB endpoint#6 destination pointer - bit 4 
EPEC_DPTR_REG60.DPTR6_3     3   16 LSBs of USB endpoint#6 destination pointer - bit 3 
EPEC_DPTR_REG60.DPTR6_2     2   16 LSBs of USB endpoint#6 destination pointer - bit 2 
EPEC_DPTR_REG60.DPTR6_1     1   16 LSBs of USB endpoint#6 destination pointer - bit 1 
EPEC_DPTR_REG60.DPTR6_0     0   16 LSBs of USB endpoint#6 destination pointer - bit 0 
EPEC_DPTR_REG61            0xED52   8 MSBs of USB endpoint#6 destination pointer
EPEC_DPTR_REG61.DPTR6_7     7   8 MSBs of USB endpoint#6 source pointer - bit 7
EPEC_DPTR_REG61.DPTR6_6     6   8 MSBs of USB endpoint#6 source pointer - bit 6
EPEC_DPTR_REG61.DPTR6_5     5   8 MSBs of USB endpoint#6 source pointer - bit 5
EPEC_DPTR_REG61.DPTR6_4     4   8 MSBs of USB endpoint#6 source pointer - bit 4
EPEC_DPTR_REG61.DPTR6_3     3   8 MSBs of USB endpoint#6 source pointer - bit 3
EPEC_DPTR_REG61.DPTR6_2     2   8 MSBs of USB endpoint#6 source pointer - bit 2
EPEC_DPTR_REG61.DPTR6_1     1   8 MSBs of USB endpoint#6 source pointer - bit 1
EPEC_DPTR_REG61.DPTR6_0     0   8 MSBs of USB endpoint#6 source pointer - bit 0
EPEC_DPTR_REG70            0xED54   16 LSBs of USB endpoint#7 destination pointer
EPEC_DPTR_REG70.DPTR7_15    15  16 LSBs of USB endpoint#7 destination pointer - bit 15
EPEC_DPTR_REG70.DPTR7_14    14  16 LSBs of USB endpoint#7 destination pointer - bit 14
EPEC_DPTR_REG70.DPTR7_13    13  16 LSBs of USB endpoint#7 destination pointer - bit 13
EPEC_DPTR_REG70.DPTR7_12    12  16 LSBs of USB endpoint#7 destination pointer - bit 12
EPEC_DPTR_REG70.DPTR7_11    11  16 LSBs of USB endpoint#7 destination pointer - bit 11
EPEC_DPTR_REG70.DPTR7_10    10  16 LSBs of USB endpoint#7 destination pointer - bit 10
EPEC_DPTR_REG70.DPTR7_9     9   16 LSBs of USB endpoint#7 destination pointer - bit 9 
EPEC_DPTR_REG70.DPTR7_8     8   16 LSBs of USB endpoint#7 destination pointer - bit 8 
EPEC_DPTR_REG70.DPTR7_7     7   16 LSBs of USB endpoint#7 destination pointer - bit 7 
EPEC_DPTR_REG70.DPTR7_6     6   16 LSBs of USB endpoint#7 destination pointer - bit 6 
EPEC_DPTR_REG70.DPTR7_5     5   16 LSBs of USB endpoint#7 destination pointer - bit 5 
EPEC_DPTR_REG70.DPTR7_4     4   16 LSBs of USB endpoint#7 destination pointer - bit 4 
EPEC_DPTR_REG70.DPTR7_3     3   16 LSBs of USB endpoint#7 destination pointer - bit 3 
EPEC_DPTR_REG70.DPTR7_2     2   16 LSBs of USB endpoint#7 destination pointer - bit 2 
EPEC_DPTR_REG70.DPTR7_1     1   16 LSBs of USB endpoint#7 destination pointer - bit 1 
EPEC_DPTR_REG70.DPTR7_0     0   16 LSBs of USB endpoint#7 destination pointer - bit 0 
EPEC_DPTR_REG71            0xED56   8 MSBs of USB endpoint#7 destination pointer
EPEC_DPTR_REG71.DPTR7_7     7   8 MSBs of USB endpoint#7 source pointer - bit 7
EPEC_DPTR_REG71.DPTR7_6     6   8 MSBs of USB endpoint#7 source pointer - bit 6
EPEC_DPTR_REG71.DPTR7_5     5   8 MSBs of USB endpoint#7 source pointer - bit 5
EPEC_DPTR_REG71.DPTR7_4     4   8 MSBs of USB endpoint#7 source pointer - bit 4
EPEC_DPTR_REG71.DPTR7_3     3   8 MSBs of USB endpoint#7 source pointer - bit 3
EPEC_DPTR_REG71.DPTR7_2     2   8 MSBs of USB endpoint#7 source pointer - bit 2
EPEC_DPTR_REG71.DPTR7_1     1   8 MSBs of USB endpoint#7 source pointer - bit 1
EPEC_DPTR_REG71.DPTR7_0     0   8 MSBs of USB endpoint#7 source pointer - bit 0
EPEC_CTRL_IN_R0            0xED58   Control and Status register for USB endpoint#0 IN
EPEC_CTRL_OUT_R0           0xED5A   Control and Status register for USB endpoint#0 OUT
EPEC_CTRL_REG1             0xED5C   Control and Status register for USB endpoint#1
EPEC_CTRL_REG1.TXR_ENA1     15  Transfer / Receive Enable control bit, set by SW and cleared by EPEC after transfer complete
EPEC_CTRL_REG1.EXT_SRC      14  External Source
EPEC_CTRL_REG1.REQ_SRC_13   13  EPEC request sourceRX/TX Fifo - bit
EPEC_CTRL_REG1.REQ_SRC_12   12  EPEC request sourceRX/TX Fifo - bit 12
EPEC_CTRL_REG1.CNT_UP_DN    11  Byte Counter direction select
EPEC_CTRL_REG1.CLR          10  Clear EPEC channel
EPEC_CTRL_REG1.BYTE_CNT_9   9   Number of bytes to be transmitted - bit 9
EPEC_CTRL_REG1.BYTE_CNT_8   8   Number of bytes to be transmitted - bit 8
EPEC_CTRL_REG1.BYTE_CNT_7   7   Number of bytes to be transmitted - bit 7
EPEC_CTRL_REG1.BYTE_CNT_6   6   Number of bytes to be transmitted - bit 6
EPEC_CTRL_REG1.BYTE_CNT_5   5   Number of bytes to be transmitted - bit 5
EPEC_CTRL_REG1.BYTE_CNT_4   4   Number of bytes to be transmitted - bit 4
EPEC_CTRL_REG1.BYTE_CNT_3   3   Number of bytes to be transmitted - bit 3
EPEC_CTRL_REG1.BYTE_CNT_2   2   Number of bytes to be transmitted - bit 2
EPEC_CTRL_REG1.BYTE_CNT_1   1   Number of bytes to be transmitted - bit 1
EPEC_CTRL_REG1.BYTE_CNT_0   0   Number of bytes to be transmitted - bit 0
EPEC_CTRL_REG2             0xED5E   Control and Status register for USB endpoint#2
EPEC_CTRL_REG2.TXR_ENA2     15  Transfer / Receive Enable control bit, set by SW and cleared by EPEC after transfer complete
EPEC_CTRL_REG2.EXT_SRC      14  External Source
EPEC_CTRL_REG2.REQ_SRC_13   13  EPEC request sourceRX/TX Fifo - bit
EPEC_CTRL_REG2.REQ_SRC_12   12  EPEC request sourceRX/TX Fifo - bit 12
EPEC_CTRL_REG2.CNT_UP_DN    11  Byte Counter direction select
EPEC_CTRL_REG2.CLR          10  Clear EPEC channel
EPEC_CTRL_REG2.BYTE_CNT_9   9   Number of bytes to be transmitted - bit 9
EPEC_CTRL_REG2.BYTE_CNT_8   8   Number of bytes to be transmitted - bit 8
EPEC_CTRL_REG2.BYTE_CNT_7   7   Number of bytes to be transmitted - bit 7
EPEC_CTRL_REG2.BYTE_CNT_6   6   Number of bytes to be transmitted - bit 6
EPEC_CTRL_REG2.BYTE_CNT_5   5   Number of bytes to be transmitted - bit 5
EPEC_CTRL_REG2.BYTE_CNT_4   4   Number of bytes to be transmitted - bit 4
EPEC_CTRL_REG2.BYTE_CNT_3   3   Number of bytes to be transmitted - bit 3
EPEC_CTRL_REG2.BYTE_CNT_2   2   Number of bytes to be transmitted - bit 2
EPEC_CTRL_REG2.BYTE_CNT_1   1   Number of bytes to be transmitted - bit 1
EPEC_CTRL_REG2.BYTE_CNT_0   0   Number of bytes to be transmitted - bit 0
EPEC_CTRL_REG3             0xED60   Control and Status register for USB endpoint#3
EPEC_CTRL_REG3.TXR_ENA3     15  Transfer / Receive Enable control bit, set by SW and cleared by EPEC after transfer complete
EPEC_CTRL_REG3.EXT_SRC      14  External Source
EPEC_CTRL_REG3.REQ_SRC_13   13  EPEC request sourceRX/TX Fifo - bit
EPEC_CTRL_REG3.REQ_SRC_12   12  EPEC request sourceRX/TX Fifo - bit 12
EPEC_CTRL_REG3.CNT_UP_DN    11  Byte Counter direction select
EPEC_CTRL_REG3.CLR          10  Clear EPEC channel
EPEC_CTRL_REG3.BYTE_CNT_9   9   Number of bytes to be transmitted - bit 9
EPEC_CTRL_REG3.BYTE_CNT_8   8   Number of bytes to be transmitted - bit 8
EPEC_CTRL_REG3.BYTE_CNT_7   7   Number of bytes to be transmitted - bit 7
EPEC_CTRL_REG3.BYTE_CNT_6   6   Number of bytes to be transmitted - bit 6
EPEC_CTRL_REG3.BYTE_CNT_5   5   Number of bytes to be transmitted - bit 5
EPEC_CTRL_REG3.BYTE_CNT_4   4   Number of bytes to be transmitted - bit 4
EPEC_CTRL_REG3.BYTE_CNT_3   3   Number of bytes to be transmitted - bit 3
EPEC_CTRL_REG3.BYTE_CNT_2   2   Number of bytes to be transmitted - bit 2
EPEC_CTRL_REG3.BYTE_CNT_1   1   Number of bytes to be transmitted - bit 1
EPEC_CTRL_REG3.BYTE_CNT_0   0   Number of bytes to be transmitted - bit 0
EPEC_CTRL_REG4             0xED62   Control and Status register for USB endpoint#4
EPEC_CTRL_REG4.TXR_ENA3     15  Transfer / Receive Enable control bit, set by SW and cleared by EPEC after transfer complete
EPEC_CTRL_REG4.EXT_SRC      14  External Source
EPEC_CTRL_REG4.REQ_SRC_13   13  EPEC request sourceRX/TX Fifo - bit
EPEC_CTRL_REG4.REQ_SRC_12   12  EPEC request sourceRX/TX Fifo - bit 12
EPEC_CTRL_REG4.CNT_UP_DN    11  Byte Counter direction select
EPEC_CTRL_REG4.CLR          10  Clear EPEC channel
EPEC_CTRL_REG4.BYTE_CNT_9   9   Number of bytes to be transmitted - bit 9
EPEC_CTRL_REG4.BYTE_CNT_8   8   Number of bytes to be transmitted - bit 8
EPEC_CTRL_REG4.BYTE_CNT_7   7   Number of bytes to be transmitted - bit 7
EPEC_CTRL_REG4.BYTE_CNT_6   6   Number of bytes to be transmitted - bit 6
EPEC_CTRL_REG4.BYTE_CNT_5   5   Number of bytes to be transmitted - bit 5
EPEC_CTRL_REG4.BYTE_CNT_4   4   Number of bytes to be transmitted - bit 4
EPEC_CTRL_REG4.BYTE_CNT_3   3   Number of bytes to be transmitted - bit 3
EPEC_CTRL_REG4.BYTE_CNT_2   2   Number of bytes to be transmitted - bit 2
EPEC_CTRL_REG4.BYTE_CNT_1   1   Number of bytes to be transmitted - bit 1
EPEC_CTRL_REG4.BYTE_CNT_0   0   Number of bytes to be transmitted - bit 0
EPEC_CTRL_REG5             0xED64   Control and Status register for USB endpoint#5
EPEC_CTRL_REG5.TXR_ENA5     15  Transfer / Receive Enable control bit, set by SW and cleared by EPEC after transfer complete
EPEC_CTRL_REG5.EXT_SRC      14  External Source
EPEC_CTRL_REG5.REQ_SRC_13   13  EPEC request sourceRX/TX Fifo - bit
EPEC_CTRL_REG5.REQ_SRC_12   12  EPEC request sourceRX/TX Fifo - bit 12
EPEC_CTRL_REG5.CNT_UP_DN    11  Byte Counter direction select
EPEC_CTRL_REG5.CLR          10  Clear EPEC channel
EPEC_CTRL_REG5.BYTE_CNT_9   9   Number of bytes to be transmitted - bit 9
EPEC_CTRL_REG5.BYTE_CNT_8   8   Number of bytes to be transmitted - bit 8
EPEC_CTRL_REG5.BYTE_CNT_7   7   Number of bytes to be transmitted - bit 7
EPEC_CTRL_REG5.BYTE_CNT_6   6   Number of bytes to be transmitted - bit 6
EPEC_CTRL_REG5.BYTE_CNT_5   5   Number of bytes to be transmitted - bit 5
EPEC_CTRL_REG5.BYTE_CNT_4   4   Number of bytes to be transmitted - bit 4
EPEC_CTRL_REG5.BYTE_CNT_3   3   Number of bytes to be transmitted - bit 3
EPEC_CTRL_REG5.BYTE_CNT_2   2   Number of bytes to be transmitted - bit 2
EPEC_CTRL_REG5.BYTE_CNT_1   1   Number of bytes to be transmitted - bit 1
EPEC_CTRL_REG5.BYTE_CNT_0   0   Number of bytes to be transmitted - bit 0
EPEC_CTRL_REG6             0xED66   Control and Status register for USB endpoint#6
EPEC_CTRL_REG6.TXR_ENA6     15  Transfer / Receive Enable control bit, set by SW and cleared by EPEC after transfer complete
EPEC_CTRL_REG6.EXT_SRC      14  External Source
EPEC_CTRL_REG6.REQ_SRC_13   13  EPEC request sourceRX/TX Fifo - bit
EPEC_CTRL_REG6.REQ_SRC_12   12  EPEC request sourceRX/TX Fifo - bit 12
EPEC_CTRL_REG6.CNT_UP_DN    11  Byte Counter direction select
EPEC_CTRL_REG6.CLR          10  Clear EPEC channel
EPEC_CTRL_REG6.BYTE_CNT_9   9   Number of bytes to be transmitted - bit 9
EPEC_CTRL_REG6.BYTE_CNT_8   8   Number of bytes to be transmitted - bit 8
EPEC_CTRL_REG6.BYTE_CNT_7   7   Number of bytes to be transmitted - bit 7
EPEC_CTRL_REG6.BYTE_CNT_6   6   Number of bytes to be transmitted - bit 6
EPEC_CTRL_REG6.BYTE_CNT_5   5   Number of bytes to be transmitted - bit 5
EPEC_CTRL_REG6.BYTE_CNT_4   4   Number of bytes to be transmitted - bit 4
EPEC_CTRL_REG6.BYTE_CNT_3   3   Number of bytes to be transmitted - bit 3
EPEC_CTRL_REG6.BYTE_CNT_2   2   Number of bytes to be transmitted - bit 2
EPEC_CTRL_REG6.BYTE_CNT_1   1   Number of bytes to be transmitted - bit 1
EPEC_CTRL_REG6.BYTE_CNT_0   0   Number of bytes to be transmitted - bit 0
EPEC_CTRL_REG7             0xED68   Control and Status register for USB endpoint#7
EPEC_CTRL_REG7.TXR_ENA7     15  Transfer / Receive Enable control bit, set by SW and cleared by EPEC after transfer complete
EPEC_CTRL_REG7.EXT_SRC      14  External Source
EPEC_CTRL_REG7.REQ_SRC_13   13  EPEC request sourceRX/TX Fifo - bit
EPEC_CTRL_REG7.REQ_SRC_12   12  EPEC request sourceRX/TX Fifo - bit 12
EPEC_CTRL_REG7.CNT_UP_DN    11  Byte Counter direction select
EPEC_CTRL_REG7.CLR          10  Clear EPEC channel
EPEC_CTRL_REG7.BYTE_CNT_9   9   Number of bytes to be transmitted - bit 9
EPEC_CTRL_REG7.BYTE_CNT_8   8   Number of bytes to be transmitted - bit 8
EPEC_CTRL_REG7.BYTE_CNT_7   7   Number of bytes to be transmitted - bit 7
EPEC_CTRL_REG7.BYTE_CNT_6   6   Number of bytes to be transmitted - bit 6
EPEC_CTRL_REG7.BYTE_CNT_5   5   Number of bytes to be transmitted - bit 5
EPEC_CTRL_REG7.BYTE_CNT_4   4   Number of bytes to be transmitted - bit 4
EPEC_CTRL_REG7.BYTE_CNT_3   3   Number of bytes to be transmitted - bit 3
EPEC_CTRL_REG7.BYTE_CNT_2   2   Number of bytes to be transmitted - bit 2
EPEC_CTRL_REG7.BYTE_CNT_1   1   Number of bytes to be transmitted - bit 1
EPEC_CTRL_REG7.BYTE_CNT_0   0   Number of bytes to be transmitted - bit 0
EPEC_INT_REG               0xED6A   EPEC Interrupt
EPEC_INT_REG.RxTxSTART_15   15  Rx / Tx Start - bit 15
EPEC_INT_REG.RxTxSTART_14   14  Rx / Tx Start - bit 14
EPEC_INT_REG.RxTxSTART_13   13  Rx / Tx Start - bit 13
EPEC_INT_REG.RxTxSTART_12   12  Rx / Tx Start - bit 12
EPEC_INT_REG.RxTxSTART_11   11  Rx / Tx Start - bit 11
EPEC_INT_REG.RxTxSTART_10   10  Rx / Tx Start - bit 10
EPEC_INT_REG.RxTxSTART_9    9   Rx / Tx Start - bit 9 
EPEC_INT_REG.RxTxSTART_8    8   Rx / Tx Start - bit 8 
EPEC_INT_REG.TXDONE_INT7    7   TX packet transfer completed by EPEC - bit 7
EPEC_INT_REG.TXDONE_INT6    6   TX packet transfer completed by EPEC - bit 6
EPEC_INT_REG.TXDONE_INT5    5   TX packet transfer completed by EPEC - bit 5
EPEC_INT_REG.TXDONE_INT4    4   TX packet transfer completed by EPEC - bit 4
EPEC_INT_REG.TXDONE_INT3    3   TX packet transfer completed by EPEC - bit 3
EPEC_INT_REG.TXDONE_INT2    2   TX packet transfer completed by EPEC - bit 2
EPEC_INT_REG.TXDONE_INT1    1   TX packet transfer completed by EPEC - bit 1
EPEC_INT_REG.TXDONE_INT0    0   TX packet transfer completed by EPEC - bit 0
EPEC_INTMSK_REG            0xED6C   EPEC Interrupt Mask Register
EPEC_INTMSK_REG.RxTxSTARTMSK_15 15  Rx / Tx Start Mask - bit 15
EPEC_INTMSK_REG.RxTxSTARTMSK_14 14  Rx / Tx Start Mask - bit 14
EPEC_INTMSK_REG.RxTxSTARTMSK_13 13  Rx / Tx Start Mask - bit 13
EPEC_INTMSK_REG.RxTxSTARTMSK_12 12  Rx / Tx Start Mask - bit 12
EPEC_INTMSK_REG.RxTxSTARTMSK_11 11  Rx / Tx Start Mask - bit 11
EPEC_INTMSK_REG.RxTxSTARTMSK_10 10  Rx / Tx Start Mask - bit 10
EPEC_INTMSK_REG.RxTxSTARTMSK_9  9   Rx / Tx Start Mask - bit 9 
EPEC_INTMSK_REG.RxTxSTARTMSK_8  8   Rx / Tx Start Mask - bit 8 
EPEC_INTMSK_REG.TXDONE_INTMSK7  7   Mask interrupt TX packet transfer completed by EPEC - bit 7
EPEC_INTMSK_REG.TXDONE_INTMSK6  6   Mask interrupt TX packet transfer completed by EPEC - bit 6
EPEC_INTMSK_REG.TXDONE_INTMSK5  5   Mask interrupt TX packet transfer completed by EPEC - bit 5
EPEC_INTMSK_REG.TXDONE_INTMSK4  4   Mask interrupt TX packet transfer completed by EPEC - bit 4
EPEC_INTMSK_REG.TXDONE_INTMSK3  3   Mask interrupt TX packet transfer completed by EPEC - bit 3
EPEC_INTMSK_REG.TXDONE_INTMSK2  2   Mask interrupt TX packet transfer completed by EPEC - bit 2
EPEC_INTMSK_REG.TXDONE_INTMSK1  1   Mask interrupt TX packet transfer completed by EPEC - bit 1
EPEC_INTMSK_REG.TXDONE_INTMSK0  0   Mask interrupt TX packet transfer completed by EPEC - bit 0


; USBD Register Set
USBCLC                     0xEE00   USB clock control register
USBCLC.USBEX_DIS            3   USB Controller Clock Disable
USBCLC.USBGPSEN             2   USB Controller Clock OCDS Disable
USBCLC.USBDIS               1   USB Controller Clock Status
USBCLC.USBDISR              0   USB Controller Clock Disable
USBD_ID                    0xEE08   USB peripheral identification register, set to ZERO in the current version.
USBD_CMD_REG               0xEE10   Command register
USBD_CMD_REG.Autoflush_Enable           15
USBD_CMD_REG.Flush_TX_Channel_Select_14 14
USBD_CMD_REG.Flush_TX_Channel_Select_13 13
USBD_CMD_REG.Flush_TX_Channel_Select_12 12
USBD_CMD_REG.Flush_TX _Channel          11
USBD_CMD_REG.UDC_Suspend                10
USBD_CMD_REG.DEV_Resume                 9
USBD_CMD_REG.USB_TXProtect              8
USBD_CMD_REG.STALL_EP_7                 7
USBD_CMD_REG.STALL_EP_6                 6
USBD_CMD_REG.STALL_EP_5                 5
USBD_CMD_REG.STALL_EP_4                 4
USBD_CMD_REG.STALL_EP_3                 3
USBD_CMD_REG.STALL_EP_2                 2
USBD_CMD_REG.STALL_EP_1                 1
USBD_CMD_REG.STALL_EP_0                 0
USBD_STATUS_REG0           0xEE12   USB endpoint FIFO status
USBD_STATUS_REG0.RX_EMPTY_15 15
USBD_STATUS_REG0.RX_EMPTY_14 14
USBD_STATUS_REG0.RX_EMPTY_13 13
USBD_STATUS_REG0.RX_EMPTY_12 12
USBD_STATUS_REG0.RX_EMPTY_11 11
USBD_STATUS_REG0.RX_EMPTY_10 10
USBD_STATUS_REG0.RX_EMPTY_9  9 
USBD_STATUS_REG0.RX_EMPTY_8  8 
USBD_STATUS_REG0.TX_FULL_7   7 
USBD_STATUS_REG0.TX_FULL_6   6 
USBD_STATUS_REG0.TX_FULL_5   5 
USBD_STATUS_REG0.TX_FULL_4   4 
USBD_STATUS_REG0.TX_FULL_3   3 
USBD_STATUS_REG0.TX_FULL_2   2 
USBD_STATUS_REG0.TX_FULL_1   1 
USBD_STATUS_REG0.TX_FULL_0   0 
USBD_STATUS_REG1           0xEE14   USB endpoint FIFO handshake control
USBD_STATUS_REG1.RX_XFR_ACK_15 15
USBD_STATUS_REG1.RX_XFR_ACK_14 14
USBD_STATUS_REG1.RX_XFR_ACK_13 13
USBD_STATUS_REG1.RX_XFR_ACK_12 12
USBD_STATUS_REG1.RX_XFR_ACK_11 11
USBD_STATUS_REG1.RX_XFR_ACK_10 10
USBD_STATUS_REG1.RX_XFR_ACK_9  9 
USBD_STATUS_REG1.RX_XFR_ACK_8  8 
USBD_STATUS_REG1.TX_XFR_ACK_7  7 
USBD_STATUS_REG1.TX_XFR_ACK_6  6 
USBD_STATUS_REG1.TX_XFR_ACK_5  5 
USBD_STATUS_REG1.TX_XFR_ACK_4  4 
USBD_STATUS_REG1.TX_XFR_ACK_3  3 
USBD_STATUS_REG1.TX_XFR_ACK_2  2 
USBD_STATUS_REG1.TX_XFR_ACK_1  1 
USBD_STATUS_REG1.TX_XFR_ACK_0  0 
USBD_STATUS_REG2           0xEE16   USB Device Remote Wake-Up Feature Status
USBD_STATUS_REG2.DEV_REM_WAKEUP_FEAT 0
reserv_EE18                0xEE18   RESERVED
reserv_EE1A                0xEE1A   RESERVED
reserv_EE1C                0xEE1C   RESERVED
reserv_EE1E                0xEE1E   RESERVED
reserv_EE20                0xEE20   RESERVED
reserv_EE22                0xEE22   RESERVED
USBD_TIME_REG              0xEE24   USB timestamp info: Frame number of the transmitted frame
USBD_TIME_REG.FRAME_NUMBER_10 10
USBD_TIME_REG.FRAME_NUMBER_9  9 
USBD_TIME_REG.FRAME_NUMBER_8  8 
USBD_TIME_REG.FRAME_NUMBER_7  7 
USBD_TIME_REG.FRAME_NUMBER_6  6 
USBD_TIME_REG.FRAME_NUMBER_5  5 
USBD_TIME_REG.FRAME_NUMBER_4  4 
USBD_TIME_REG.FRAME_NUMBER_3  3 
USBD_TIME_REG.FRAME_NUMBER_2  2 
USBD_TIME_REG.FRAME_NUMBER_1  1 
USBD_TIME_REG.FRAME_NUMBER_0  0 
USBD_SETUP_REG01           0xEE26   USB setup bytes (1:0)
USBD_SETUP_REG01.Setup_Byte1_15 15
USBD_SETUP_REG01.Setup_Byte1_14 14
USBD_SETUP_REG01.Setup_Byte1_13 13
USBD_SETUP_REG01.Setup_Byte1_12 12
USBD_SETUP_REG01.Setup_Byte1_11 11
USBD_SETUP_REG01.Setup_Byte1_10 10
USBD_SETUP_REG01.Setup_Byte1_9  9 
USBD_SETUP_REG01.Setup_Byte1_8  8 
USBD_SETUP_REG01.Setup_Byte0_7  7 
USBD_SETUP_REG01.Setup_Byte0_6  6 
USBD_SETUP_REG01.Setup_Byte0_5  5 
USBD_SETUP_REG01.Setup_Byte0_4  4 
USBD_SETUP_REG01.Setup_Byte0_3  3 
USBD_SETUP_REG01.Setup_Byte0_2  2 
USBD_SETUP_REG01.Setup_Byte0_1  1 
USBD_SETUP_REG01.Setup_Byte0_0  0 
USBD_SETUP_REG23           0xEE28   USB setup bytes (3:2)
USBD_SETUP_REG23.Setup_Byte3_15 15
USBD_SETUP_REG23.Setup_Byte3_14 14
USBD_SETUP_REG23.Setup_Byte3_13 13
USBD_SETUP_REG23.Setup_Byte3_12 12
USBD_SETUP_REG23.Setup_Byte3_11 11
USBD_SETUP_REG23.Setup_Byte3_10 10
USBD_SETUP_REG23.Setup_Byte3_9  9 
USBD_SETUP_REG23.Setup_Byte3_8  8 
USBD_SETUP_REG23.Setup_Byte2_7  7 
USBD_SETUP_REG23.Setup_Byte2_6  6 
USBD_SETUP_REG23.Setup_Byte2_5  5 
USBD_SETUP_REG23.Setup_Byte2_4  4 
USBD_SETUP_REG23.Setup_Byte2_3  3 
USBD_SETUP_REG23.Setup_Byte2_2  2 
USBD_SETUP_REG23.Setup_Byte2_1  1 
USBD_SETUP_REG23.Setup_Byte2_0  0 
USBD_SETUP_REG45           0xEE2A   USB setup bytes (5:4)
USBD_SETUP_REG45.Setup_Byte5_15 15
USBD_SETUP_REG45.Setup_Byte5_14 14
USBD_SETUP_REG45.Setup_Byte5_13 13
USBD_SETUP_REG45.Setup_Byte5_12 12
USBD_SETUP_REG45.Setup_Byte5_11 11
USBD_SETUP_REG45.Setup_Byte5_10 10
USBD_SETUP_REG45.Setup_Byte5_9  9 
USBD_SETUP_REG45.Setup_Byte5_8  8 
USBD_SETUP_REG45.Setup_Byte4_7  7 
USBD_SETUP_REG45.Setup_Byte4_6  6 
USBD_SETUP_REG45.Setup_Byte4_5  5 
USBD_SETUP_REG45.Setup_Byte4_4  4 
USBD_SETUP_REG45.Setup_Byte4_3  3 
USBD_SETUP_REG45.Setup_Byte4_2  2 
USBD_SETUP_REG45.Setup_Byte4_1  1 
USBD_SETUP_REG45.Setup_Byte4_0  0 
USBD_SETUP_REG67           0xEE2C   USB setup bytes (7:6)
USBD_SETUP_REG67.Setup_Byte7_15 15
USBD_SETUP_REG67.Setup_Byte7_14 14
USBD_SETUP_REG67.Setup_Byte7_13 13
USBD_SETUP_REG67.Setup_Byte7_12 12
USBD_SETUP_REG67.Setup_Byte7_11 11
USBD_SETUP_REG67.Setup_Byte7_10 10
USBD_SETUP_REG67.Setup_Byte7_9  9 
USBD_SETUP_REG67.Setup_Byte7_8  8 
USBD_SETUP_REG67.Setup_Byte6_7  7 
USBD_SETUP_REG67.Setup_Byte6_6  6 
USBD_SETUP_REG67.Setup_Byte6_5  5 
USBD_SETUP_REG67.Setup_Byte6_4  4 
USBD_SETUP_REG67.Setup_Byte6_3  3 
USBD_SETUP_REG67.Setup_Byte6_2  2 
USBD_SETUP_REG67.Setup_Byte6_1  1 
USBD_SETUP_REG67.Setup_Byte6_0  0 
USBD_TXWR0                 0xEE2E   USB Transmit FIFO data register
USBD_TXWR0.TXWR0_15         15  16-bit word for Transmit FIFO endpoint#0 - bit 15
USBD_TXWR0.TXWR0_14         14  16-bit word for Transmit FIFO endpoint#0 - bit 14
USBD_TXWR0.TXWR0_13         13  16-bit word for Transmit FIFO endpoint#0 - bit 13
USBD_TXWR0.TXWR0_12         12  16-bit word for Transmit FIFO endpoint#0 - bit 12
USBD_TXWR0.TXWR0_11         11  16-bit word for Transmit FIFO endpoint#0 - bit 11
USBD_TXWR0.TXWR0_10         10  16-bit word for Transmit FIFO endpoint#0 - bit 10
USBD_TXWR0.TXWR0_9          9   16-bit word for Transmit FIFO endpoint#0 - bit 9 
USBD_TXWR0.TXWR0_8          8   16-bit word for Transmit FIFO endpoint#0 - bit 8 
USBD_TXWR0.TXWR0_7          7   16-bit word for Transmit FIFO endpoint#0 - bit 7 
USBD_TXWR0.TXWR0_6          6   16-bit word for Transmit FIFO endpoint#0 - bit 6 
USBD_TXWR0.TXWR0_5          5   16-bit word for Transmit FIFO endpoint#0 - bit 5 
USBD_TXWR0.TXWR0_4          4   16-bit word for Transmit FIFO endpoint#0 - bit 4 
USBD_TXWR0.TXWR0_3          3   16-bit word for Transmit FIFO endpoint#0 - bit 3 
USBD_TXWR0.TXWR0_2          2   16-bit word for Transmit FIFO endpoint#0 - bit 2 
USBD_TXWR0.TXWR0_1          1   16-bit word for Transmit FIFO endpoint#0 - bit 1 
USBD_TXWR0.TXWR0_0          0   16-bit word for Transmit FIFO endpoint#0 - bit 0 
USBD_TXEOD0                0xEE30   EPEC/SW End-of-packet indication for USBD.
USBD_TXEOD0.TXEOD           0
USBD_RXRR0                 0xEE32   USB Receive FIFO data register
USBD_RXRR0.RXRR0_15         15  16-bit word for Receive FIFO endpoint#0 - bit 15
USBD_RXRR0.RXRR0_14         14  16-bit word for Receive FIFO endpoint#0 - bit 14
USBD_RXRR0.RXRR0_13         13  16-bit word for Receive FIFO endpoint#0 - bit 13
USBD_RXRR0.RXRR0_12         12  16-bit word for Receive FIFO endpoint#0 - bit 12
USBD_RXRR0.RXRR0_11         11  16-bit word for Receive FIFO endpoint#0 - bit 11
USBD_RXRR0.RXRR0_10         10  16-bit word for Receive FIFO endpoint#0 - bit 10
USBD_RXRR0.RXRR0_9          9   16-bit word for Receive FIFO endpoint#0 - bit 9 
USBD_RXRR0.RXRR0_8          8   16-bit word for Receive FIFO endpoint#0 - bit 8 
USBD_RXRR0.RXRR0_7          7   16-bit word for Receive FIFO endpoint#0 - bit 7 
USBD_RXRR0.RXRR0_6          6   16-bit word for Receive FIFO endpoint#0 - bit 6 
USBD_RXRR0.RXRR0_5          5   16-bit word for Receive FIFO endpoint#0 - bit 5 
USBD_RXRR0.RXRR0_4          4   16-bit word for Receive FIFO endpoint#0 - bit 4 
USBD_RXRR0.RXRR0_3          3   16-bit word for Receive FIFO endpoint#0 - bit 3 
USBD_RXRR0.RXRR0_2          2   16-bit word for Receive FIFO endpoint#0 - bit 2 
USBD_RXRR0.RXRR0_1          1   16-bit word for Receive FIFO endpoint#0 - bit 1 
USBD_RXRR0.RXRR0_0          0   16-bit word for Receive FIFO endpoint#0 - bit 0 
USBD_RX_BYTECNT0           0xEE34   USB receive packet length in bytes
USBD_RX_BYTECNT0.RX_STATUS  15  packet status indication
USBD_RX_BYTECNT0.RX_BYTECNT_9 9 10-bit byte counter for received packet in endpoint#0 - bit 9
USBD_RX_BYTECNT0.RX_BYTECNT_8 8 10-bit byte counter for received packet in endpoint#0 - bit 8
USBD_RX_BYTECNT0.RX_BYTECNT_7 7 10-bit byte counter for received packet in endpoint#0 - bit 7
USBD_RX_BYTECNT0.RX_BYTECNT_6 6 10-bit byte counter for received packet in endpoint#0 - bit 6
USBD_RX_BYTECNT0.RX_BYTECNT_5 5 10-bit byte counter for received packet in endpoint#0 - bit 5
USBD_RX_BYTECNT0.RX_BYTECNT_4 4 10-bit byte counter for received packet in endpoint#0 - bit 4
USBD_RX_BYTECNT0.RX_BYTECNT_3 3 10-bit byte counter for received packet in endpoint#0 - bit 3
USBD_RX_BYTECNT0.RX_BYTECNT_2 2 10-bit byte counter for received packet in endpoint#0 - bit 2
USBD_RX_BYTECNT0.RX_BYTECNT_1 1 10-bit byte counter for received packet in endpoint#0 - bit 1
USBD_RX_BYTECNT0.RX_BYTECNT_0 0 10-bit byte counter for received packet in endpoint#0 - bit 0
USBD_TXWR1                 0xEE36   USB Transmit FIFO data register
USBD_TXWR1.TXWR1_15         15  16-bit word for Transmit FIFO endpoint#1 - bit 15
USBD_TXWR1.TXWR1_14         14  16-bit word for Transmit FIFO endpoint#1 - bit 14
USBD_TXWR1.TXWR1_13         13  16-bit word for Transmit FIFO endpoint#1 - bit 13
USBD_TXWR1.TXWR1_12         12  16-bit word for Transmit FIFO endpoint#1 - bit 12
USBD_TXWR1.TXWR1_11         11  16-bit word for Transmit FIFO endpoint#1 - bit 11
USBD_TXWR1.TXWR1_10         10  16-bit word for Transmit FIFO endpoint#1 - bit 10
USBD_TXWR1.TXWR1_9          9   16-bit word for Transmit FIFO endpoint#1 - bit 9 
USBD_TXWR1.TXWR1_8          8   16-bit word for Transmit FIFO endpoint#1 - bit 8 
USBD_TXWR1.TXWR1_7          7   16-bit word for Transmit FIFO endpoint#1 - bit 7 
USBD_TXWR1.TXWR1_6          6   16-bit word for Transmit FIFO endpoint#1 - bit 6 
USBD_TXWR1.TXWR1_5          5   16-bit word for Transmit FIFO endpoint#1 - bit 5 
USBD_TXWR1.TXWR1_4          4   16-bit word for Transmit FIFO endpoint#1 - bit 4 
USBD_TXWR1.TXWR1_3          3   16-bit word for Transmit FIFO endpoint#1 - bit 3 
USBD_TXWR1.TXWR1_2          2   16-bit word for Transmit FIFO endpoint#1 - bit 2 
USBD_TXWR1.TXWR1_1          1   16-bit word for Transmit FIFO endpoint#1 - bit 1 
USBD_TXWR1.TXWR1_0          0   16-bit word for Transmit FIFO endpoint#1 - bit 0 
USBD_TXEOD1                0xEE38   EPEC/SW End-of-packet indication for USBD.
USBD_TXEOD1.TXEOD           0
USBD_RXRR1                 0xEE3A   USB Receive FIFO data register
USBD_RXRR1.RXRR1_15         15  16-bit word for Receive FIFO endpoint#1 - bit 15
USBD_RXRR1.RXRR1_14         14  16-bit word for Receive FIFO endpoint#1 - bit 14
USBD_RXRR1.RXRR1_13         13  16-bit word for Receive FIFO endpoint#1 - bit 13
USBD_RXRR1.RXRR1_12         12  16-bit word for Receive FIFO endpoint#1 - bit 12
USBD_RXRR1.RXRR1_11         11  16-bit word for Receive FIFO endpoint#1 - bit 11
USBD_RXRR1.RXRR1_10         10  16-bit word for Receive FIFO endpoint#1 - bit 10
USBD_RXRR1.RXRR1_9          9   16-bit word for Receive FIFO endpoint#1 - bit 9 
USBD_RXRR1.RXRR1_8          8   16-bit word for Receive FIFO endpoint#1 - bit 8 
USBD_RXRR1.RXRR1_7          7   16-bit word for Receive FIFO endpoint#1 - bit 7 
USBD_RXRR1.RXRR1_6          6   16-bit word for Receive FIFO endpoint#1 - bit 6 
USBD_RXRR1.RXRR1_5          5   16-bit word for Receive FIFO endpoint#1 - bit 5 
USBD_RXRR1.RXRR1_4          4   16-bit word for Receive FIFO endpoint#1 - bit 4 
USBD_RXRR1.RXRR1_3          3   16-bit word for Receive FIFO endpoint#1 - bit 3 
USBD_RXRR1.RXRR1_2          2   16-bit word for Receive FIFO endpoint#1 - bit 2 
USBD_RXRR1.RXRR1_1          1   16-bit word for Receive FIFO endpoint#1 - bit 1 
USBD_RXRR1.RXRR1_0          0   16-bit word for Receive FIFO endpoint#1 - bit 0 
USBD_RX_BYTECNT1           0xEE3C   USB receive packet length in bytes
USBD_RX_BYTECNT1.RX_STATUS  15  packet status indication
USBD_RX_BYTECNT1.RX_BYTECNT_9 9 10-bit byte counter for received packet in endpoint#1 - bit 9
USBD_RX_BYTECNT1.RX_BYTECNT_8 8 10-bit byte counter for received packet in endpoint#1 - bit 8
USBD_RX_BYTECNT1.RX_BYTECNT_7 7 10-bit byte counter for received packet in endpoint#1 - bit 7
USBD_RX_BYTECNT1.RX_BYTECNT_6 6 10-bit byte counter for received packet in endpoint#1 - bit 6
USBD_RX_BYTECNT1.RX_BYTECNT_5 5 10-bit byte counter for received packet in endpoint#1 - bit 5
USBD_RX_BYTECNT1.RX_BYTECNT_4 4 10-bit byte counter for received packet in endpoint#1 - bit 4
USBD_RX_BYTECNT1.RX_BYTECNT_3 3 10-bit byte counter for received packet in endpoint#1 - bit 3
USBD_RX_BYTECNT1.RX_BYTECNT_2 2 10-bit byte counter for received packet in endpoint#1 - bit 2
USBD_RX_BYTECNT1.RX_BYTECNT_1 1 10-bit byte counter for received packet in endpoint#1 - bit 1
USBD_RX_BYTECNT1.RX_BYTECNT_0 0 10-bit byte counter for received packet in endpoint#1 - bit 0
USBD_TXWR2                 0xEE3E   USB Transmit FIFO data register
USBD_TXWR2.TXWR2_15         15  16-bit word for Transmit FIFO endpoint#2 - bit 15
USBD_TXWR2.TXWR2_14         14  16-bit word for Transmit FIFO endpoint#2 - bit 14
USBD_TXWR2.TXWR2_13         13  16-bit word for Transmit FIFO endpoint#2 - bit 13
USBD_TXWR2.TXWR2_12         12  16-bit word for Transmit FIFO endpoint#2 - bit 12
USBD_TXWR2.TXWR2_11         11  16-bit word for Transmit FIFO endpoint#2 - bit 11
USBD_TXWR2.TXWR2_10         10  16-bit word for Transmit FIFO endpoint#2 - bit 10
USBD_TXWR2.TXWR2_9          9   16-bit word for Transmit FIFO endpoint#2 - bit 9 
USBD_TXWR2.TXWR2_8          8   16-bit word for Transmit FIFO endpoint#2 - bit 8 
USBD_TXWR2.TXWR2_7          7   16-bit word for Transmit FIFO endpoint#2 - bit 7 
USBD_TXWR2.TXWR2_6          6   16-bit word for Transmit FIFO endpoint#2 - bit 6 
USBD_TXWR2.TXWR2_5          5   16-bit word for Transmit FIFO endpoint#2 - bit 5 
USBD_TXWR2.TXWR2_4          4   16-bit word for Transmit FIFO endpoint#2 - bit 4 
USBD_TXWR2.TXWR2_3          3   16-bit word for Transmit FIFO endpoint#2 - bit 3 
USBD_TXWR2.TXWR2_2          2   16-bit word for Transmit FIFO endpoint#2 - bit 2 
USBD_TXWR2.TXWR2_1          1   16-bit word for Transmit FIFO endpoint#2 - bit 1 
USBD_TXWR2.TXWR2_0          0   16-bit word for Transmit FIFO endpoint#2 - bit 0 
USBD_TXEOD2                0xEE40   EPEC/SW End-of-packet indication for USBD.
USBD_TXEOD2.TXEOD           0
USBD_RXRR2                 0xEE42   USB Receive FIFO data register
USBD_RXRR2.RXRR2_15         15  16-bit word for Receive FIFO endpoint#2 - bit 15
USBD_RXRR2.RXRR2_14         14  16-bit word for Receive FIFO endpoint#2 - bit 14
USBD_RXRR2.RXRR2_13         13  16-bit word for Receive FIFO endpoint#2 - bit 13
USBD_RXRR2.RXRR2_12         12  16-bit word for Receive FIFO endpoint#2 - bit 12
USBD_RXRR2.RXRR2_11         11  16-bit word for Receive FIFO endpoint#2 - bit 11
USBD_RXRR2.RXRR2_10         10  16-bit word for Receive FIFO endpoint#2 - bit 10
USBD_RXRR2.RXRR2_9          9   16-bit word for Receive FIFO endpoint#2 - bit 9 
USBD_RXRR2.RXRR2_8          8   16-bit word for Receive FIFO endpoint#2 - bit 8 
USBD_RXRR2.RXRR2_7          7   16-bit word for Receive FIFO endpoint#2 - bit 7 
USBD_RXRR2.RXRR2_6          6   16-bit word for Receive FIFO endpoint#2 - bit 6 
USBD_RXRR2.RXRR2_5          5   16-bit word for Receive FIFO endpoint#2 - bit 5 
USBD_RXRR2.RXRR2_4          4   16-bit word for Receive FIFO endpoint#2 - bit 4 
USBD_RXRR2.RXRR2_3          3   16-bit word for Receive FIFO endpoint#2 - bit 3 
USBD_RXRR2.RXRR2_2          2   16-bit word for Receive FIFO endpoint#2 - bit 2 
USBD_RXRR2.RXRR2_1          1   16-bit word for Receive FIFO endpoint#2 - bit 1 
USBD_RXRR2.RXRR2_0          0   16-bit word for Receive FIFO endpoint#2 - bit 0 
USBD_RX_BYTECNT2           0xEE44   USB receive packet length in bytes
USBD_RX_BYTECNT2.RX_STATUS  15  packet status indication
USBD_RX_BYTECNT2.RX_BYTECNT_9 9 10-bit byte counter for received packet in endpoint#2 - bit 9
USBD_RX_BYTECNT2.RX_BYTECNT_8 8 10-bit byte counter for received packet in endpoint#2 - bit 8
USBD_RX_BYTECNT2.RX_BYTECNT_7 7 10-bit byte counter for received packet in endpoint#2 - bit 7
USBD_RX_BYTECNT2.RX_BYTECNT_6 6 10-bit byte counter for received packet in endpoint#2 - bit 6
USBD_RX_BYTECNT2.RX_BYTECNT_5 5 10-bit byte counter for received packet in endpoint#2 - bit 5
USBD_RX_BYTECNT2.RX_BYTECNT_4 4 10-bit byte counter for received packet in endpoint#2 - bit 4
USBD_RX_BYTECNT2.RX_BYTECNT_3 3 10-bit byte counter for received packet in endpoint#2 - bit 3
USBD_RX_BYTECNT2.RX_BYTECNT_2 2 10-bit byte counter for received packet in endpoint#2 - bit 2
USBD_RX_BYTECNT2.RX_BYTECNT_1 1 10-bit byte counter for received packet in endpoint#2 - bit 1
USBD_RX_BYTECNT2.RX_BYTECNT_0 0 10-bit byte counter for received packet in endpoint#2 - bit 0
USBD_TXWR3                 0xEE46   USB Transmit FIFO data register
USBD_TXWR3.TXWR3_15         15  16-bit word for Transmit FIFO endpoint#3 - bit 15
USBD_TXWR3.TXWR3_14         14  16-bit word for Transmit FIFO endpoint#3 - bit 14
USBD_TXWR3.TXWR3_13         13  16-bit word for Transmit FIFO endpoint#3 - bit 13
USBD_TXWR3.TXWR3_12         12  16-bit word for Transmit FIFO endpoint#3 - bit 12
USBD_TXWR3.TXWR3_11         11  16-bit word for Transmit FIFO endpoint#3 - bit 11
USBD_TXWR3.TXWR3_10         10  16-bit word for Transmit FIFO endpoint#3 - bit 10
USBD_TXWR3.TXWR3_9          9   16-bit word for Transmit FIFO endpoint#3 - bit 9 
USBD_TXWR3.TXWR3_8          8   16-bit word for Transmit FIFO endpoint#3 - bit 8 
USBD_TXWR3.TXWR3_7          7   16-bit word for Transmit FIFO endpoint#3 - bit 7 
USBD_TXWR3.TXWR3_6          6   16-bit word for Transmit FIFO endpoint#3 - bit 6 
USBD_TXWR3.TXWR3_5          5   16-bit word for Transmit FIFO endpoint#3 - bit 5 
USBD_TXWR3.TXWR3_4          4   16-bit word for Transmit FIFO endpoint#3 - bit 4 
USBD_TXWR3.TXWR3_3          3   16-bit word for Transmit FIFO endpoint#3 - bit 3 
USBD_TXWR3.TXWR3_2          2   16-bit word for Transmit FIFO endpoint#3 - bit 2 
USBD_TXWR3.TXWR3_1          1   16-bit word for Transmit FIFO endpoint#3 - bit 1 
USBD_TXWR3.TXWR3_0          0   16-bit word for Transmit FIFO endpoint#3 - bit 0 
USBD_TXEOD3                0xEE48   EPEC/SW End-of-packet indication for USBD.
USBD_TXEOD3.TXEOD           0
USBD_RXRR3                 0xEE4A   USB Receive FIFO data register
USBD_RXRR3.RXRR3_15         15  16-bit word for Receive FIFO endpoint#3 - bit 15
USBD_RXRR3.RXRR3_14         14  16-bit word for Receive FIFO endpoint#3 - bit 14
USBD_RXRR3.RXRR3_13         13  16-bit word for Receive FIFO endpoint#3 - bit 13
USBD_RXRR3.RXRR3_12         12  16-bit word for Receive FIFO endpoint#3 - bit 12
USBD_RXRR3.RXRR3_11         11  16-bit word for Receive FIFO endpoint#3 - bit 11
USBD_RXRR3.RXRR3_10         10  16-bit word for Receive FIFO endpoint#3 - bit 10
USBD_RXRR3.RXRR3_9          9   16-bit word for Receive FIFO endpoint#3 - bit 9 
USBD_RXRR3.RXRR3_8          8   16-bit word for Receive FIFO endpoint#3 - bit 8 
USBD_RXRR3.RXRR3_7          7   16-bit word for Receive FIFO endpoint#3 - bit 7 
USBD_RXRR3.RXRR3_6          6   16-bit word for Receive FIFO endpoint#3 - bit 6 
USBD_RXRR3.RXRR3_5          5   16-bit word for Receive FIFO endpoint#3 - bit 5 
USBD_RXRR3.RXRR3_4          4   16-bit word for Receive FIFO endpoint#3 - bit 4 
USBD_RXRR3.RXRR3_3          3   16-bit word for Receive FIFO endpoint#3 - bit 3 
USBD_RXRR3.RXRR3_2          2   16-bit word for Receive FIFO endpoint#3 - bit 2 
USBD_RXRR3.RXRR3_1          1   16-bit word for Receive FIFO endpoint#3 - bit 1 
USBD_RXRR3.RXRR3_0          0   16-bit word for Receive FIFO endpoint#3 - bit 0 
USBD_RX_BYTECNT3           0xEE4C   USB receive packet length in bytes
USBD_RX_BYTECNT3.RX_STATUS  15  packet status indication
USBD_RX_BYTECNT3.RX_BYTECNT_9 9 10-bit byte counter for received packet in endpoint#3 - bit 9
USBD_RX_BYTECNT3.RX_BYTECNT_8 8 10-bit byte counter for received packet in endpoint#3 - bit 8
USBD_RX_BYTECNT3.RX_BYTECNT_7 7 10-bit byte counter for received packet in endpoint#3 - bit 7
USBD_RX_BYTECNT3.RX_BYTECNT_6 6 10-bit byte counter for received packet in endpoint#3 - bit 6
USBD_RX_BYTECNT3.RX_BYTECNT_5 5 10-bit byte counter for received packet in endpoint#3 - bit 5
USBD_RX_BYTECNT3.RX_BYTECNT_4 4 10-bit byte counter for received packet in endpoint#3 - bit 4
USBD_RX_BYTECNT3.RX_BYTECNT_3 3 10-bit byte counter for received packet in endpoint#3 - bit 3
USBD_RX_BYTECNT3.RX_BYTECNT_2 2 10-bit byte counter for received packet in endpoint#3 - bit 2
USBD_RX_BYTECNT3.RX_BYTECNT_1 1 10-bit byte counter for received packet in endpoint#3 - bit 1
USBD_RX_BYTECNT3.RX_BYTECNT_0 0 10-bit byte counter for received packet in endpoint#3 - bit 0
USBD_TXWR4                 0xEE4E   USB Transmit FIFO data register
USBD_TXWR4.TXWR4_15         15  16-bit word for Transmit FIFO endpoint#4 - bit 15
USBD_TXWR4.TXWR4_14         14  16-bit word for Transmit FIFO endpoint#4 - bit 14
USBD_TXWR4.TXWR4_13         13  16-bit word for Transmit FIFO endpoint#4 - bit 13
USBD_TXWR4.TXWR4_12         12  16-bit word for Transmit FIFO endpoint#4 - bit 12
USBD_TXWR4.TXWR4_11         11  16-bit word for Transmit FIFO endpoint#4 - bit 11
USBD_TXWR4.TXWR4_10         10  16-bit word for Transmit FIFO endpoint#4 - bit 10
USBD_TXWR4.TXWR4_9          9   16-bit word for Transmit FIFO endpoint#4 - bit 9 
USBD_TXWR4.TXWR4_8          8   16-bit word for Transmit FIFO endpoint#4 - bit 8 
USBD_TXWR4.TXWR4_7          7   16-bit word for Transmit FIFO endpoint#4 - bit 7 
USBD_TXWR4.TXWR4_6          6   16-bit word for Transmit FIFO endpoint#4 - bit 6 
USBD_TXWR4.TXWR4_5          5   16-bit word for Transmit FIFO endpoint#4 - bit 5 
USBD_TXWR4.TXWR4_4          4   16-bit word for Transmit FIFO endpoint#4 - bit 4 
USBD_TXWR4.TXWR4_3          3   16-bit word for Transmit FIFO endpoint#4 - bit 3 
USBD_TXWR4.TXWR4_2          2   16-bit word for Transmit FIFO endpoint#4 - bit 2 
USBD_TXWR4.TXWR4_1          1   16-bit word for Transmit FIFO endpoint#4 - bit 1 
USBD_TXWR4.TXWR4_0          0   16-bit word for Transmit FIFO endpoint#4 - bit 0 
USBD_TXEOD4                0xEE50   EPEC/SW End-of-packet indication for USBD.
USBD_TXEOD4.TXEOD           0
USBD_RXRR4                 0xEE52   USB Receive FIFO data register
USBD_RXRR4.RXRR4_15         15  16-bit word for Receive FIFO endpoint#4 - bit 15
USBD_RXRR4.RXRR4_14         14  16-bit word for Receive FIFO endpoint#4 - bit 14
USBD_RXRR4.RXRR4_13         13  16-bit word for Receive FIFO endpoint#4 - bit 13
USBD_RXRR4.RXRR4_12         12  16-bit word for Receive FIFO endpoint#4 - bit 12
USBD_RXRR4.RXRR4_11         11  16-bit word for Receive FIFO endpoint#4 - bit 11
USBD_RXRR4.RXRR4_10         10  16-bit word for Receive FIFO endpoint#4 - bit 10
USBD_RXRR4.RXRR4_9          9   16-bit word for Receive FIFO endpoint#4 - bit 9 
USBD_RXRR4.RXRR4_8          8   16-bit word for Receive FIFO endpoint#4 - bit 8 
USBD_RXRR4.RXRR4_7          7   16-bit word for Receive FIFO endpoint#4 - bit 7 
USBD_RXRR4.RXRR4_6          6   16-bit word for Receive FIFO endpoint#4 - bit 6 
USBD_RXRR4.RXRR4_5          5   16-bit word for Receive FIFO endpoint#4 - bit 5 
USBD_RXRR4.RXRR4_4          4   16-bit word for Receive FIFO endpoint#4 - bit 4 
USBD_RXRR4.RXRR4_3          3   16-bit word for Receive FIFO endpoint#4 - bit 3 
USBD_RXRR4.RXRR4_2          2   16-bit word for Receive FIFO endpoint#4 - bit 2 
USBD_RXRR4.RXRR4_1          1   16-bit word for Receive FIFO endpoint#4 - bit 1 
USBD_RXRR4.RXRR4_0          0   16-bit word for Receive FIFO endpoint#4 - bit 0 
USBD_RX_BYTECNT4           0xEE54   USB receive packet length in bytes
USBD_RX_BYTECNT4.RX_STATUS  15  packet status indication
USBD_RX_BYTECNT4.RX_BYTECNT_9 9 10-bit byte counter for received packet in endpoint#4 - bit 9
USBD_RX_BYTECNT4.RX_BYTECNT_8 8 10-bit byte counter for received packet in endpoint#4 - bit 8
USBD_RX_BYTECNT4.RX_BYTECNT_7 7 10-bit byte counter for received packet in endpoint#4 - bit 7
USBD_RX_BYTECNT4.RX_BYTECNT_6 6 10-bit byte counter for received packet in endpoint#4 - bit 6
USBD_RX_BYTECNT4.RX_BYTECNT_5 5 10-bit byte counter for received packet in endpoint#4 - bit 5
USBD_RX_BYTECNT4.RX_BYTECNT_4 4 10-bit byte counter for received packet in endpoint#4 - bit 4
USBD_RX_BYTECNT4.RX_BYTECNT_3 3 10-bit byte counter for received packet in endpoint#4 - bit 3
USBD_RX_BYTECNT4.RX_BYTECNT_2 2 10-bit byte counter for received packet in endpoint#4 - bit 2
USBD_RX_BYTECNT4.RX_BYTECNT_1 1 10-bit byte counter for received packet in endpoint#4 - bit 1
USBD_RX_BYTECNT4.RX_BYTECNT_0 0 10-bit byte counter for received packet in endpoint#4 - bit 0
USBD_TXWR5                 0xEE56   USB Transmit FIFO data register
USBD_TXWR5.TXWR5_15         15  16-bit word for Transmit FIFO endpoint#5 - bit 15
USBD_TXWR5.TXWR5_14         14  16-bit word for Transmit FIFO endpoint#5 - bit 14
USBD_TXWR5.TXWR5_13         13  16-bit word for Transmit FIFO endpoint#5 - bit 13
USBD_TXWR5.TXWR5_12         12  16-bit word for Transmit FIFO endpoint#5 - bit 12
USBD_TXWR5.TXWR5_11         11  16-bit word for Transmit FIFO endpoint#5 - bit 11
USBD_TXWR5.TXWR5_10         10  16-bit word for Transmit FIFO endpoint#5 - bit 10
USBD_TXWR5.TXWR5_9          9   16-bit word for Transmit FIFO endpoint#5 - bit 9 
USBD_TXWR5.TXWR5_8          8   16-bit word for Transmit FIFO endpoint#5 - bit 8 
USBD_TXWR5.TXWR5_7          7   16-bit word for Transmit FIFO endpoint#5 - bit 7 
USBD_TXWR5.TXWR5_6          6   16-bit word for Transmit FIFO endpoint#5 - bit 6 
USBD_TXWR5.TXWR5_5          5   16-bit word for Transmit FIFO endpoint#5 - bit 5 
USBD_TXWR5.TXWR5_4          4   16-bit word for Transmit FIFO endpoint#5 - bit 4 
USBD_TXWR5.TXWR5_3          3   16-bit word for Transmit FIFO endpoint#5 - bit 3 
USBD_TXWR5.TXWR5_2          2   16-bit word for Transmit FIFO endpoint#5 - bit 2 
USBD_TXWR5.TXWR5_1          1   16-bit word for Transmit FIFO endpoint#5 - bit 1 
USBD_TXWR5.TXWR5_0          0   16-bit word for Transmit FIFO endpoint#5 - bit 0 
USBD_TXEOD5                0xEE58   EPEC/SW End-of-packet indication for USBD.
USBD_TXEOD5.TXEOD           0
USBD_RXRR5                 0xEE5A   USB Receive FIFO data register
USBD_RXRR5.RXRR5_15         15  16-bit word for Receive FIFO endpoint#5 - bit 15
USBD_RXRR5.RXRR5_14         14  16-bit word for Receive FIFO endpoint#5 - bit 14
USBD_RXRR5.RXRR5_13         13  16-bit word for Receive FIFO endpoint#5 - bit 13
USBD_RXRR5.RXRR5_12         12  16-bit word for Receive FIFO endpoint#5 - bit 12
USBD_RXRR5.RXRR5_11         11  16-bit word for Receive FIFO endpoint#5 - bit 11
USBD_RXRR5.RXRR5_10         10  16-bit word for Receive FIFO endpoint#5 - bit 10
USBD_RXRR5.RXRR5_9          9   16-bit word for Receive FIFO endpoint#5 - bit 9 
USBD_RXRR5.RXRR5_8          8   16-bit word for Receive FIFO endpoint#5 - bit 8 
USBD_RXRR5.RXRR5_7          7   16-bit word for Receive FIFO endpoint#5 - bit 7 
USBD_RXRR5.RXRR5_6          6   16-bit word for Receive FIFO endpoint#5 - bit 6 
USBD_RXRR5.RXRR5_5          5   16-bit word for Receive FIFO endpoint#5 - bit 5 
USBD_RXRR5.RXRR5_4          4   16-bit word for Receive FIFO endpoint#5 - bit 4 
USBD_RXRR5.RXRR5_3          3   16-bit word for Receive FIFO endpoint#5 - bit 3 
USBD_RXRR5.RXRR5_2          2   16-bit word for Receive FIFO endpoint#5 - bit 2 
USBD_RXRR5.RXRR5_1          1   16-bit word for Receive FIFO endpoint#5 - bit 1 
USBD_RXRR5.RXRR5_0          0   16-bit word for Receive FIFO endpoint#5 - bit 0 
USBD_RX_BYTECNT5           0xEE5C   USB receive packet length in bytes
USBD_RX_BYTECNT5.RX_STATUS  15  packet status indication
USBD_RX_BYTECNT5.RX_BYTECNT_9 9 10-bit byte counter for received packet in endpoint#5 - bit 9
USBD_RX_BYTECNT5.RX_BYTECNT_8 8 10-bit byte counter for received packet in endpoint#5 - bit 8
USBD_RX_BYTECNT5.RX_BYTECNT_7 7 10-bit byte counter for received packet in endpoint#5 - bit 7
USBD_RX_BYTECNT5.RX_BYTECNT_6 6 10-bit byte counter for received packet in endpoint#5 - bit 6
USBD_RX_BYTECNT5.RX_BYTECNT_5 5 10-bit byte counter for received packet in endpoint#5 - bit 5
USBD_RX_BYTECNT5.RX_BYTECNT_4 4 10-bit byte counter for received packet in endpoint#5 - bit 4
USBD_RX_BYTECNT5.RX_BYTECNT_3 3 10-bit byte counter for received packet in endpoint#5 - bit 3
USBD_RX_BYTECNT5.RX_BYTECNT_2 2 10-bit byte counter for received packet in endpoint#5 - bit 2
USBD_RX_BYTECNT5.RX_BYTECNT_1 1 10-bit byte counter for received packet in endpoint#5 - bit 1
USBD_RX_BYTECNT5.RX_BYTECNT_0 0 10-bit byte counter for received packet in endpoint#5 - bit 0
USBD_TXWR6                 0xEE5E   USB Transmit FIFO data register
USBD_TXWR6.TXWR6_15         15  16-bit word for Transmit FIFO endpoint#6 - bit 15
USBD_TXWR6.TXWR6_14         14  16-bit word for Transmit FIFO endpoint#6 - bit 14
USBD_TXWR6.TXWR6_13         13  16-bit word for Transmit FIFO endpoint#6 - bit 13
USBD_TXWR6.TXWR6_12         12  16-bit word for Transmit FIFO endpoint#6 - bit 12
USBD_TXWR6.TXWR6_11         11  16-bit word for Transmit FIFO endpoint#6 - bit 11
USBD_TXWR6.TXWR6_10         10  16-bit word for Transmit FIFO endpoint#6 - bit 10
USBD_TXWR6.TXWR6_9          9   16-bit word for Transmit FIFO endpoint#6 - bit 9 
USBD_TXWR6.TXWR6_8          8   16-bit word for Transmit FIFO endpoint#6 - bit 8 
USBD_TXWR6.TXWR6_7          7   16-bit word for Transmit FIFO endpoint#6 - bit 7 
USBD_TXWR6.TXWR6_6          6   16-bit word for Transmit FIFO endpoint#6 - bit 6 
USBD_TXWR6.TXWR6_5          5   16-bit word for Transmit FIFO endpoint#6 - bit 5 
USBD_TXWR6.TXWR6_4          4   16-bit word for Transmit FIFO endpoint#6 - bit 4 
USBD_TXWR6.TXWR6_3          3   16-bit word for Transmit FIFO endpoint#6 - bit 3 
USBD_TXWR6.TXWR6_2          2   16-bit word for Transmit FIFO endpoint#6 - bit 2 
USBD_TXWR6.TXWR6_1          1   16-bit word for Transmit FIFO endpoint#6 - bit 1 
USBD_TXWR6.TXWR6_0          0   16-bit word for Transmit FIFO endpoint#6 - bit 0 
USBD_TXEOD6                0xEE60   EPEC/SW End-of-packet indication for USBD.
USBD_TXEOD6.TXEOD           0
USBD_RXRR6                 0xEE62   USB Receive FIFO data register
USBD_RXRR6.RXRR6_15         15  16-bit word for Receive FIFO endpoint#6 - bit 15
USBD_RXRR6.RXRR6_14         14  16-bit word for Receive FIFO endpoint#6 - bit 14
USBD_RXRR6.RXRR6_13         13  16-bit word for Receive FIFO endpoint#6 - bit 13
USBD_RXRR6.RXRR6_12         12  16-bit word for Receive FIFO endpoint#6 - bit 12
USBD_RXRR6.RXRR6_11         11  16-bit word for Receive FIFO endpoint#6 - bit 11
USBD_RXRR6.RXRR6_10         10  16-bit word for Receive FIFO endpoint#6 - bit 10
USBD_RXRR6.RXRR6_9          9   16-bit word for Receive FIFO endpoint#6 - bit 9 
USBD_RXRR6.RXRR6_8          8   16-bit word for Receive FIFO endpoint#6 - bit 8 
USBD_RXRR6.RXRR6_7          7   16-bit word for Receive FIFO endpoint#6 - bit 7 
USBD_RXRR6.RXRR6_6          6   16-bit word for Receive FIFO endpoint#6 - bit 6 
USBD_RXRR6.RXRR6_5          5   16-bit word for Receive FIFO endpoint#6 - bit 5 
USBD_RXRR6.RXRR6_4          4   16-bit word for Receive FIFO endpoint#6 - bit 4 
USBD_RXRR6.RXRR6_3          3   16-bit word for Receive FIFO endpoint#6 - bit 3 
USBD_RXRR6.RXRR6_2          2   16-bit word for Receive FIFO endpoint#6 - bit 2 
USBD_RXRR6.RXRR6_1          1   16-bit word for Receive FIFO endpoint#6 - bit 1 
USBD_RXRR6.RXRR6_0          0   16-bit word for Receive FIFO endpoint#6 - bit 0 
USBD_RX_BYTECNT6           0xEE64   USB receive packet length in bytes
USBD_RX_BYTECNT6.RX_STATUS  15  packet status indication
USBD_RX_BYTECNT6.RX_BYTECNT_9 9 10-bit byte counter for received packet in endpoint#6 - bit 9
USBD_RX_BYTECNT6.RX_BYTECNT_8 8 10-bit byte counter for received packet in endpoint#6 - bit 8
USBD_RX_BYTECNT6.RX_BYTECNT_7 7 10-bit byte counter for received packet in endpoint#6 - bit 7
USBD_RX_BYTECNT6.RX_BYTECNT_6 6 10-bit byte counter for received packet in endpoint#6 - bit 6
USBD_RX_BYTECNT6.RX_BYTECNT_5 5 10-bit byte counter for received packet in endpoint#6 - bit 5
USBD_RX_BYTECNT6.RX_BYTECNT_4 4 10-bit byte counter for received packet in endpoint#6 - bit 4
USBD_RX_BYTECNT6.RX_BYTECNT_3 3 10-bit byte counter for received packet in endpoint#6 - bit 3
USBD_RX_BYTECNT6.RX_BYTECNT_2 2 10-bit byte counter for received packet in endpoint#6 - bit 2
USBD_RX_BYTECNT6.RX_BYTECNT_1 1 10-bit byte counter for received packet in endpoint#6 - bit 1
USBD_RX_BYTECNT6.RX_BYTECNT_0 0 10-bit byte counter for received packet in endpoint#6 - bit 0
USBD_TXWR7                 0xEE66   USB Transmit FIFO data register
USBD_TXWR7.TXWR7_15         15  16-bit word for Transmit FIFO endpoint#7 - bit 15
USBD_TXWR7.TXWR7_14         14  16-bit word for Transmit FIFO endpoint#7 - bit 14
USBD_TXWR7.TXWR7_13         13  16-bit word for Transmit FIFO endpoint#7 - bit 13
USBD_TXWR7.TXWR7_12         12  16-bit word for Transmit FIFO endpoint#7 - bit 12
USBD_TXWR7.TXWR7_11         11  16-bit word for Transmit FIFO endpoint#7 - bit 11
USBD_TXWR7.TXWR7_10         10  16-bit word for Transmit FIFO endpoint#7 - bit 10
USBD_TXWR7.TXWR7_9          9   16-bit word for Transmit FIFO endpoint#7 - bit 9 
USBD_TXWR7.TXWR7_8          8   16-bit word for Transmit FIFO endpoint#7 - bit 8 
USBD_TXWR7.TXWR7_7          7   16-bit word for Transmit FIFO endpoint#7 - bit 7 
USBD_TXWR7.TXWR7_6          6   16-bit word for Transmit FIFO endpoint#7 - bit 6 
USBD_TXWR7.TXWR7_5          5   16-bit word for Transmit FIFO endpoint#7 - bit 5 
USBD_TXWR7.TXWR7_4          4   16-bit word for Transmit FIFO endpoint#7 - bit 4 
USBD_TXWR7.TXWR7_3          3   16-bit word for Transmit FIFO endpoint#7 - bit 3 
USBD_TXWR7.TXWR7_2          2   16-bit word for Transmit FIFO endpoint#7 - bit 2 
USBD_TXWR7.TXWR7_1          1   16-bit word for Transmit FIFO endpoint#7 - bit 1 
USBD_TXWR7.TXWR7_0          0   16-bit word for Transmit FIFO endpoint#7 - bit 0 
USBD_TXEOD7                0xEE68   EPEC/SW End-of-packet indication for USBD.
USBD_TXEOD7.TXEOD           0
USBD_RXRR7                 0xEE6A   USB Receive FIFO data register
USBD_RXRR7.RXRR7_15         15  16-bit word for Receive FIFO endpoint#7 - bit 15
USBD_RXRR7.RXRR7_14         14  16-bit word for Receive FIFO endpoint#7 - bit 14
USBD_RXRR7.RXRR7_13         13  16-bit word for Receive FIFO endpoint#7 - bit 13
USBD_RXRR7.RXRR7_12         12  16-bit word for Receive FIFO endpoint#7 - bit 12
USBD_RXRR7.RXRR7_11         11  16-bit word for Receive FIFO endpoint#7 - bit 11
USBD_RXRR7.RXRR7_10         10  16-bit word for Receive FIFO endpoint#7 - bit 10
USBD_RXRR7.RXRR7_9          9   16-bit word for Receive FIFO endpoint#7 - bit 9 
USBD_RXRR7.RXRR7_8          8   16-bit word for Receive FIFO endpoint#7 - bit 8 
USBD_RXRR7.RXRR7_7          7   16-bit word for Receive FIFO endpoint#7 - bit 7 
USBD_RXRR7.RXRR7_6          6   16-bit word for Receive FIFO endpoint#7 - bit 6 
USBD_RXRR7.RXRR7_5          5   16-bit word for Receive FIFO endpoint#7 - bit 5 
USBD_RXRR7.RXRR7_4          4   16-bit word for Receive FIFO endpoint#7 - bit 4 
USBD_RXRR7.RXRR7_3          3   16-bit word for Receive FIFO endpoint#7 - bit 3 
USBD_RXRR7.RXRR7_2          2   16-bit word for Receive FIFO endpoint#7 - bit 2 
USBD_RXRR7.RXRR7_1          1   16-bit word for Receive FIFO endpoint#7 - bit 1 
USBD_RXRR7.RXRR7_0          0   16-bit word for Receive FIFO endpoint#7 - bit 0 
USBD_RX_BYTECNT7           0xEE6C   USB receive packet length in bytes
USBD_RX_BYTECNT7.RX_STATUS  15  packet status indication
USBD_RX_BYTECNT7.RX_BYTECNT_9 9 10-bit byte counter for received packet in endpoint#7 - bit 9
USBD_RX_BYTECNT7.RX_BYTECNT_8 8 10-bit byte counter for received packet in endpoint#7 - bit 8
USBD_RX_BYTECNT7.RX_BYTECNT_7 7 10-bit byte counter for received packet in endpoint#7 - bit 7
USBD_RX_BYTECNT7.RX_BYTECNT_6 6 10-bit byte counter for received packet in endpoint#7 - bit 6
USBD_RX_BYTECNT7.RX_BYTECNT_5 5 10-bit byte counter for received packet in endpoint#7 - bit 5
USBD_RX_BYTECNT7.RX_BYTECNT_4 4 10-bit byte counter for received packet in endpoint#7 - bit 4
USBD_RX_BYTECNT7.RX_BYTECNT_3 3 10-bit byte counter for received packet in endpoint#7 - bit 3
USBD_RX_BYTECNT7.RX_BYTECNT_2 2 10-bit byte counter for received packet in endpoint#7 - bit 2
USBD_RX_BYTECNT7.RX_BYTECNT_1 1 10-bit byte counter for received packet in endpoint#7 - bit 1
USBD_RX_BYTECNT7.RX_BYTECNT_0 0 10-bit byte counter for received packet in endpoint#7 - bit 0
USBD_CFGVAL                0xEE6E   Current Configuration & Alternate Setting selected by Host
USBD_CFGVAL.AS_IF3_9        9   Alternate Setting selected for Interface  - bit 9
USBD_CFGVAL.AS_IF3_8        8   Alternate Setting selected for Interface  - bit 8
USBD_CFGVAL.AS_IF2_7        7   Alternate Setting selected for Interface  - bit 7
USBD_CFGVAL.AS_IF2_6        6   Alternate Setting selected for Interface  - bit 6
USBD_CFGVAL.AS_IF1_5        5   Alternate Setting selected for Interface  - bit 5
USBD_CFGVAL.AS_IF1_4        4   Alternate Setting selected for Interface  - bit 4
USBD_CFGVAL.AS_IF0_3        3   Alternate Setting selected for Interface  - bit 3
USBD_CFGVAL.AS_IF0_2        2   Alternate Setting selected for Interface  - bit 2
USBD_CFGVAL.CFG_1           1   Configuration selected by host - bit 1
USBD_CFGVAL.CFG_0           0   Configuration selected by host - bit 0
USBC_CMD_RESET             0xEE70   USB Block Reset
USBC_CMD_RESET.USBC_RST     0   Resets the USB block including the transmit and receive logic

; IOM-2 Registers
IOMCLC                 0xEF00   IOM-2 Clock Control Register
IOMCLC.IOMEX_DIS        3   IOM-2 Controller Clock Disable
IOMCLC.IOMGPSEN         2   IOM-2 Controller Clock OCDS Disable
IOMCLC.IOMDIS           1   IOM-2 Controller Clock Status
IOMCLC.IOMDISR          0   IOM-2 Controller Clock Disable
reserv_EF02            0xEF02   RESERVED
reserv_EF04            0xEF04   RESERVED
reserv_EF06            0xEF06   RESERVED
IOMID                  0xEF08   IOM-2 Identification Register
IOMID.ID_15             15  IOM-2 Identification Register - bit 15
IOMID.ID_14             14  IOM-2 Identification Register - bit 14
IOMID.ID_13             13  IOM-2 Identification Register - bit 13
IOMID.ID_12             12  IOM-2 Identification Register - bit 12
IOMID.ID_11             11  IOM-2 Identification Register - bit 11
IOMID.ID_10             10  IOM-2 Identification Register - bit 10
IOMID.ID_9              9   IOM-2 Identification Register - bit 9 
IOMID.ID_8              8   IOM-2 Identification Register - bit 8 
IOMID.ID_7              7   IOM-2 Identification Register - bit 7 
IOMID.ID_6              6   IOM-2 Identification Register - bit 6 
IOMID.ID_5              5   IOM-2 Identification Register - bit 5 
IOMID.ID_4              4   IOM-2 Identification Register - bit 4 
IOMID.ID_3              3   IOM-2 Identification Register - bit 3 
IOMID.ID_2              2   IOM-2 Identification Register - bit 2 
IOMID.ID_1              1   IOM-2 Identification Register - bit 1 
IOMID.ID_0              0   IOM-2 Identification Register - bit 0 
reserv_EF0A            0xEF0A   RESERVED
reserv_EF0C            0xEF0C   RESERVED
reserv_EF0E            0xEF0E   RESERVED
CDA_10                 0xEF10   Controller Data Access Register 10
CDA_10.CDA_10_7         7    H Data register which can be accessed from the CPU - bit 7
CDA_10.CDA_10_6         6    H Data register which can be accessed from the CPU - bit 6
CDA_10.CDA_10_5         5    H Data register which can be accessed from the CPU - bit 5
CDA_10.CDA_10_4         4    H Data register which can be accessed from the CPU - bit 4
CDA_10.CDA_10_3         3    H Data register which can be accessed from the CPU - bit 3
CDA_10.CDA_10_2         2    H Data register which can be accessed from the CPU - bit 2
CDA_10.CDA_10_1         1    H Data register which can be accessed from the CPU - bit 1
CDA_10.CDA_10_0         0    H Data register which can be accessed from the CPU - bit 0
CDA_11                 0xEF12   Controller Data Access Register 11
CDA_11.CDA_11_7         7    H Data register which can be accessed from the CPU - bit 7
CDA_11.CDA_11_6         6    H Data register which can be accessed from the CPU - bit 6
CDA_11.CDA_11_5         5    H Data register which can be accessed from the CPU - bit 5
CDA_11.CDA_11_4         4    H Data register which can be accessed from the CPU - bit 4
CDA_11.CDA_11_3         3    H Data register which can be accessed from the CPU - bit 3
CDA_11.CDA_11_2         2    H Data register which can be accessed from the CPU - bit 2
CDA_11.CDA_11_1         1    H Data register which can be accessed from the CPU - bit 1
CDA_11.CDA_11_0         0    H Data register which can be accessed from the CPU - bit 0
CDA_20                 0xEF14   Controller Data Access Register 21
CDA_20.CDA_20_7         7    H Data register which can be accessed from the CPU - bit 7
CDA_20.CDA_20_6         6    H Data register which can be accessed from the CPU - bit 6
CDA_20.CDA_20_5         5    H Data register which can be accessed from the CPU - bit 5
CDA_20.CDA_20_4         4    H Data register which can be accessed from the CPU - bit 4
CDA_20.CDA_20_3         3    H Data register which can be accessed from the CPU - bit 3
CDA_20.CDA_20_2         2    H Data register which can be accessed from the CPU - bit 2
CDA_20.CDA_20_1         1    H Data register which can be accessed from the CPU - bit 1
CDA_20.CDA_20_0         0    H Data register which can be accessed from the CPU - bit 0
CDA_21                 0xEF16   Controller Data Access Register 22
CDA_21.CDA_21_7         7    H Data register which can be accessed from the CPU - bit 7
CDA_21.CDA_21_6         6    H Data register which can be accessed from the CPU - bit 6
CDA_21.CDA_21_5         5    H Data register which can be accessed from the CPU - bit 5
CDA_21.CDA_21_4         4    H Data register which can be accessed from the CPU - bit 4
CDA_21.CDA_21_3         3    H Data register which can be accessed from the CPU - bit 3
CDA_21.CDA_21_2         2    H Data register which can be accessed from the CPU - bit 2
CDA_21.CDA_21_1         1    H Data register which can be accessed from the CPU - bit 1
CDA_21.CDA_21_0         0    H Data register which can be accessed from the CPU - bit 0
CDA_TSDP10             0xEF18   Time Slot and Data Port Selection for CDA 10
CDA_TSDP10.DPS          15  Data Port Selection
CDA_TSDP10.TSS_4        4   Time Slot Selection - bit 4
CDA_TSDP10.TSS_3        3   Time Slot Selection - bit 3
CDA_TSDP10.TSS_2        2   Time Slot Selection - bit 2
CDA_TSDP10.TSS_1        1   Time Slot Selection - bit 1
CDA_TSDP10.TSS_0        0   Time Slot Selection - bit 0
CDA_TSDP11             0xEF1A   Time Slot and Data Port Selection for CDA 11
CDA_TSDP11.DPS          15  Data Port Selection
CDA_TSDP11.TSS_4        4   Time Slot Selection - bit 4
CDA_TSDP11.TSS_3        3   Time Slot Selection - bit 3
CDA_TSDP11.TSS_2        2   Time Slot Selection - bit 2
CDA_TSDP11.TSS_1        1   Time Slot Selection - bit 1
CDA_TSDP11.TSS_0        0   Time Slot Selection - bit 0
CDA_TSDP20             0xEF1C   Time Slot and Data Port Selection for CDA 20
CDA_TSDP20.DPS          15  Data Port Selection
CDA_TSDP20.TSS_4        4   Time Slot Selection - bit 4
CDA_TSDP20.TSS_3        3   Time Slot Selection - bit 3
CDA_TSDP20.TSS_2        2   Time Slot Selection - bit 2
CDA_TSDP20.TSS_1        1   Time Slot Selection - bit 1
CDA_TSDP20.TSS_0        0   Time Slot Selection - bit 0
CDA_TSDP21             0xEF1E   Time Slot and Data Port Selection for CDA 21
CDA_TSDP21.DPS          15  Data Port Selection
CDA_TSDP21.TSS_4        4   Time Slot Selection - bit 4
CDA_TSDP21.TSS_3        3   Time Slot Selection - bit 3
CDA_TSDP21.TSS_2        2   Time Slot Selection - bit 2
CDA_TSDP21.TSS_1        1   Time Slot Selection - bit 1
CDA_TSDP21.TSS_0        0   Time Slot Selection - bit 0
B1_TSDP                0xEF20   Time Slot and Data Port Selection for B1
B1_TSDP.DPS             15  Data Port Selection
B1_TSDP.TSS_4           4   Time Slot Selection - bit 4
B1_TSDP.TSS_3           3   Time Slot Selection - bit 3
B1_TSDP.TSS_2           2   Time Slot Selection - bit 2
B1_TSDP.TSS_1           1   Time Slot Selection - bit 1
B1_TSDP.TSS_0           0   Time Slot Selection - bit 0
B2_TSDP                0xEF22   Time Slot and Data Port Selection for B2
B2_TSDP.DPS             15  Data Port Selection
B2_TSDP.TSS_4           4   Time Slot Selection - bit 4
B2_TSDP.TSS_3           3   Time Slot Selection - bit 3
B2_TSDP.TSS_2           2   Time Slot Selection - bit 2
B2_TSDP.TSS_1           1   Time Slot Selection - bit 1
B2_TSDP.TSS_0           0   Time Slot Selection - bit 0
D1_TSDP                0xEF24   Time Slot and Data Port Selection for D1
D1_TSDP.DPS             15  Data Port Selection        
D1_TSDP.TSS_4           4   Time Slot Selection - bit 4
D1_TSDP.TSS_3           3   Time Slot Selection - bit 3
D1_TSDP.TSS_2           2   Time Slot Selection - bit 2
D1_TSDP.TSS_1           1   Time Slot Selection - bit 1
D1_TSDP.TSS_0           0   Time Slot Selection - bit 0
D2_TSDP                0xEF26   Time Slot and Data Port Selection for D2
D2_TSDP.DPS             15  Data Port Selection        
D2_TSDP.TSS_4           4   Time Slot Selection - bit 4
D2_TSDP.TSS_3           3   Time Slot Selection - bit 3
D2_TSDP.TSS_2           2   Time Slot Selection - bit 2
D2_TSDP.TSS_1           1   Time Slot Selection - bit 1
D2_TSDP.TSS_0           0   Time Slot Selection - bit 0
reserv_EF28            0xEF28   RESERVED
reserv_EF2A            0xEF2A   RESERVED
reserv_EF2C            0xEF2C   RESERVED
reserv_EF2E            0xEF2E   RESERVED
ISTA                   0xEF30   Interrupt Status Register
ISTA.RPF3               15  Receive Pool Full for HDLC channel 3
ISTA.RPF2               14  Receive Pool Full for HDLC channel 2
ISTA.RPF1               13  Receive Pool Full for HDLC channel 1
ISTA.RPF0               12  Receive Pool Full for HDLC channel 0
ISTA.XPR3               11  Transmit Pool Ready for HDLC channel 3
ISTA.XPR2               10  Transmit Pool Ready for HDLC channel 2
ISTA.XPR1               9   Transmit Pool Ready for HDLC channel 1
ISTA.XPR0               8   Transmit Pool Ready for HDLC channel 0
ISTA.DCSI               7   Clock STATUS Interrupt
ISTA.ST                 6   Synchronous Transfer
ISTA.CIC                5   Channel Change
ISTA.MOS                4   Monitor Status
ISTA.HDLC3              3   HDLC Channel Interrupts - bit 3
ISTA.HDLC2              2   HDLC Channel Interrupts - bit 2
ISTA.HDLC1              1   HDLC Channel Interrupts - bit 1
ISTA.HDLC0              0   HDLC Channel Interrupts - bit 0
MASK                   0xEF32   Interrupt Mask Register
MASK.RPF3               15  Receive Pool Full for HDLC channel 3
MASK.RPF2               14  Receive Pool Full for HDLC channel 2
MASK.RPF1               13  Receive Pool Full for HDLC channel 1
MASK.RPF0               12  Receive Pool Full for HDLC channel 0
MASK.XPR3               11  Transmit Pool Ready for HDLC channel 3
MASK.XPR2               10  Transmit Pool Ready for HDLC channel 2
MASK.XPR1               9   Transmit Pool Ready for HDLC channel 1
MASK.XPR0               8   Transmit Pool Ready for HDLC channel 0
MASK.DCSI               7   Clock STATUS Interrupt
MASK.ST                 6   Synchronous Transfer
MASK.CIC                5   Channel Change
MASK.MOS                4   Monitor Status
MASK.HDLC3              3   HDLC Channel Interrupts - bit 3
MASK.HDLC2              2   HDLC Channel Interrupts - bit 2
MASK.HDLC1              1   HDLC Channel Interrupts - bit 1
MASK.HDLC0              0   HDLC Channel Interrupts - bit 0
CDA1_CR                0xEF34   Control Register for CDA Channel 1
CDA1_CR.EN_I1           4   Enable Input CDA11
CDA1_CR.EN_I0           3   Enable Input CDA10
CDA1_CR.EN_O1           2   Enable Output CDA11
CDA1_CR.EN_O0           1   Enable Output CDA10
CDA1_CR.SWAP            0   Swap Inputs
CDA2_CR                0xEF36   Control Register for CDA Channel 2
CDA2_CR.EN_I1           4   Enable Input CDA21
CDA2_CR.EN_I0           3   Enable Input CDA20
CDA2_CR.EN_O1           2   Enable Output CDA21
CDA2_CR.EN_O0           1   Enable Output CDA20
CDA2_CR.SWAP            0   Swap Inputs
CIC_CR                 0xEF38   Control Register for Control/Indication Channel
CIC_CR.DPS_CI1          15  Data Port Selection CI1 Data
CIC_CR.EN_CI1           14  Enable CI1 Data
CIC_CR.DPS_CI0          7   Data Port Selection CI0 Data
CIC_CR.EN_CI0           6   Enable CI0 Data
MON_CR                 0xEF3A   Control Register for Monitor Channel
MON_CR.EN_MON           15  Enable Output
MON_CR.DPS              7   Data Port Selection
MON_CR.MCS_2            2   Monitor Channel Selection - bit 2
MON_CR.MCS_1            1   Monitor Channel Selection - bit 1
MON_CR.MCS_0            0   Monitor Channel Selection - bit 0
IOM_CR                 0xEF3C   Control Register for IOM Interface
IOM_CR.SPU              3   Software Power UP
IOM_CR.DIS_OD           2   Open_Drain
IOM_CR.CLKM             1   Clock Mode
IOM_CR.DIS_IOM          0   Disable IOM
reserv_EF3E            0xEF3E   RESERVED
STI                    0xEF40   Synchronous Transfer Interrupt
STI.STOV21              7   Synchronous Transfer Overflow Interrupt
STI.STOV20              6   Synchronous Transfer Overflow Interrupt
STI.STOV11              5   Synchronous Transfer Overflow Interrupt
STI.STOV10              4   Synchronous Transfer Overflow Interrupt
STI.STI21               3   Synchronous Transfer Interrupt
STI.STI20               2   Synchronous Transfer Interrupt
STI.STI11               1   Synchronous Transfer Interrupt
STI.STI10               0   Synchronous Transfer Interrupt
MSTI                   0xEF42   Mask Synchronous Transfer Interrupt
MSTI.STOV21             7   Synchronous Transfer Overflow for STI 21
MSTI.STOV20             6   Synchronous Transfer Overflow for STI 20
MSTI.STOV11             5   Synchronous Transfer Overflow for STI 11
MSTI.STOV10             4   Synchronous Transfer Overflow for STI 10
MSTI.STI21              3   Synchronous Transfer Interrupt 21
MSTI.STI20              2   Synchronous Transfer Interrupt 20
MSTI.STI11              1   Synchronous Transfer Interrupt 11
MSTI.STI10              0   Synchronous Transfer Interrupt 10
ASTI                   0xEF44   Acknowledge Synchronous Transfer Interrupt
ASTI.ACK21              3   Acknowledge Synchronous Transfer Interrupt
ASTI.ACK20              2   Acknowledge Synchronous Transfer Interrupt
ASTI.ACK11              1   Acknowledge Synchronous Transfer Interrupt
ASTI.ACK10              0   Acknowledge Synchronous Transfer Interrupt
reserv_EF46            0xEF46   RESERVED
reserv_EF48            0xEF48   RESERVED
reserv_EF4A            0xEF4A   RESERVED
reserv_EF4C            0xEF4C   RESERVED
reserv_EF4E            0xEF4E   RESERVED
MOR                    0xEF50   Monitor Receive Channel
MOR.MOR_7               7   MONITOR Data Received - bit 7
MOR.MOR_6               6   MONITOR Data Received - bit 6
MOR.MOR_5               5   MONITOR Data Received - bit 5
MOR.MOR_4               4   MONITOR Data Received - bit 4
MOR.MOR_3               3   MONITOR Data Received - bit 3
MOR.MOR_2               2   MONITOR Data Received - bit 2
MOR.MOR_1               1   MONITOR Data Received - bit 1
MOR.MOR_0               0   MONITOR Data Received - bit 0
MOX                    0xEF52   Monitor Transmit Channel
MOX.MOX_7               7   MONITOR Data Transmitted - bit 7
MOX.MOX_6               6   MONITOR Data Transmitted - bit 6
MOX.MOX_5               5   MONITOR Data Transmitted - bit 5
MOX.MOX_4               4   MONITOR Data Transmitted - bit 4
MOX.MOX_3               3   MONITOR Data Transmitted - bit 3
MOX.MOX_2               2   MONITOR Data Transmitted - bit 2
MOX.MOX_1               1   MONITOR Data Transmitted - bit 1
MOX.MOX_0               0   MONITOR Data Transmitted - bit 0
MOCR                   0xEF54   Monitor Control Register
MOCR.MRE                3   MONITOR Receive Interrupt Enable
MOCR.MRC                2   MR Bit Control
MOCR.MIE                1   MONITOR Interrupt Enable
MOCR.MXC                0   MX Bit Control
MSTA                   0xEF56   Monitor Status Register
MSTA.MAC                15  MONITOR Transmit Channel Active
MOSR                   0xEF58   Monitor Interrupt Status Register
MOSR.MDR                3   MONITOR channel Data Received
MOSR.MER                2   MONITOR channel End of Reception
MOSR.MDA                1   MONITOR Channel Data Acknowledge
MOSR.MAB                0   MONITOR Channel Data Abort
MCDA                   0xEF5A   MCDA - Monitoring CDA Bits
MCDA.MCDA21_7           7    Monitoring CDA21 Bit
MCDA.MCDA21_6           6    Monitoring CDA21 Bit
MCDA.MCDA20_5           5    Monitoring CDA20 Bit
MCDA.MCDA20_4           4    Monitoring CDA20 Bit
MCDA.MCDA11_3           3    Monitoring CDA11 Bit
MCDA.MCDA11_2           2    Monitoring CDA11 Bit
MCDA.MCDA10_1           1    Monitoring CDA10 Bit
MCDA.MCDA10_0           0    Monitoring CDA10 Bit
reserv_EF5C            0xEF5C   RESERVED
reserv_EF5E            0xEF5E   RESERVED
CIC0_D                 0xEF60   Command/Indication Channel 0 Data
CIC0_D.CODR0_11         11  C/I Code 0 Receive - bit 11
CIC0_D.CODR0_10         10  C/I Code 0 Receive - bit 10
CIC0_D.CODR0_9          9   C/I Code 0 Receive - bit 9 
CIC0_D.CODR0_8          8   C/I Code 0 Receive - bit 8 
CIC0_D.CODX0_3          3   C/I-Code 0 Transmit - bit 3
CIC0_D.CODX0_2          2   C/I-Code 0 Transmit - bit 2
CIC0_D.CODX0_1          1   C/I-Code 0 Transmit - bit 1
CIC0_D.CODX0_0          0   C/I-Code 0 Transmit - bit 0
CIC1_D                 0xEF62   Command/Indication Channel 1 Data
CIC1_D.CODR1_13         13  C/I-Code 1 Receive - bit 13
CIC1_D.CODR1_12         12  C/I-Code 1 Receive - bit 12
CIC1_D.CODR1_11         11  C/I-Code 1 Receive - bit 11
CIC1_D.CODR1_10         10  C/I-Code 1 Receive - bit 10
CIC1_D.CODR1_9          9   C/I-Code 1 Receive - bit 9 
CIC1_D.CODR1_8          8   C/I-Code 1 Receive - bit 8 
CIC1_D.CODX1_5          5   C/I-Code 1 Transmit - bit 5
CIC1_D.CODX1_4          4   C/I-Code 1 Transmit - bit 4
CIC1_D.CODX1_3          3   C/I-Code 1 Transmit - bit 3
CIC1_D.CODX1_2          2   C/I-Code 1 Transmit - bit 2
CIC1_D.CODX1_1          1   C/I-Code 1 Transmit - bit 1
CIC1_D.CODX1_0          0   C/I-Code 1 Transmit - bit 0
CIC_CMD                0xEF64   Command/Indication Channel Command Register
CIC_CMD.EXCERPT_10      10  Digital Interface Modes - bit 10
CIC_CMD.EXCERPT_9       9   Digital Interface Modes - bit 9 
CIC_CMD.EXCERPT_8       8   Digital Interface Modes - bit 8 
CIC_CMD.TIC_DIS         6   TIC Bus Disable
CIC_CMD.CI1E            5   C/I-channel 1 interrupt enable
CIC_CMD.CICW            4   W 1 C/I-Channel Width
CIC_CMD.BAC             3   W 0 Bus Access Control
CIC_CMD.TBA_2           2   TIC Bus Addres - bit 2
CIC_CMD.TBA_1           1   TIC Bus Addres - bit 1
CIC_CMD.TBA_0           0   TIC Bus Addres - bit 0
CIC_ST                 0xEF66   Command/Indication Channel Status Register
CIC_ST.CIC0             15  C/I Code 0 Change
CIC_ST.CIC1             14  C/I Code 1 Change
CIC_ST.S_G              13  Stop/Go Bit Monitoring
CIC_ST.BAS              12  Bus Access Status
CIC_ST.DCOD             7   DCL Clock Off Detection
DCSI                   0xEF68   DCL Clock Supervision Interval
DCSI.DCSI_VAL_10        10  DCL Clock Supervision Interval Value - bit 10
DCSI.DCSI_VAL_9         9   DCL Clock Supervision Interval Value - bit 9 
DCSI.DCSI_VAL_8         8   DCL Clock Supervision Interval Value - bit 8 
DCSI.DCSI_VAL_7         7   DCL Clock Supervision Interval Value - bit 7 
DCSI.DCSI_VAL_6         6   DCL Clock Supervision Interval Value - bit 6 
DCSI.DCSI_VAL_5         5   DCL Clock Supervision Interval Value - bit 5 
DCSI.DCSI_VAL_4         4   DCL Clock Supervision Interval Value - bit 4 
DCSI.DCSI_VAL_3         3   DCL Clock Supervision Interval Value - bit 3 
DCSI.DCSI_VAL_2         2   DCL Clock Supervision Interval Value - bit 2 
DCSI.DCSI_VAL_1         1   DCL Clock Supervision Interval Value - bit 1 
DCSI.DCSI_VAL_0         0   DCL Clock Supervision Interval Value - bit 0 
reserv_EF6A            0xEF6A   RESERVED
reserv_EF6C            0xEF6C   RESERVED
reserv_EF6E            0xEF6E   RESERVED
reserv_EF70            0xEF70   RESERVED
reserv_EF72            0xEF72   RESERVED
reserv_EF74            0xEF74   RESERVED
reserv_EF76            0xEF76   RESERVED
reserv_EF78            0xEF78   RESERVED
reserv_EF7A            0xEF7A   RESERVED
reserv_EF7C            0xEF7C   RESERVED
reserv_EF7E            0xEF7E   RESERVED
RFIFO_0                0xEF80   Receive FIFO (HDLC-Channel 0)
RFIFO_0.DATA_15         15
RFIFO_0.DATA_14         14
RFIFO_0.DATA_13         13
RFIFO_0.DATA_12         12
RFIFO_0.DATA_11         11
RFIFO_0.DATA_10         10
RFIFO_0.DATA_9          9 
RFIFO_0.DATA_8          8 
RFIFO_0.DATA_7          7 
RFIFO_0.DATA_6          6 
RFIFO_0.DATA_5          5 
RFIFO_0.DATA_4          4 
RFIFO_0.DATA_3          3 
RFIFO_0.DATA_2          2 
RFIFO_0.DATA_1          1 
RFIFO_0.DATA_0          0 
TFIFO_0                0xEF82   Transmit FIFO (HDLC-Channel 0)
TFIFO_0.DATA_15         15
TFIFO_0.DATA_14         14
TFIFO_0.DATA_13         13
TFIFO_0.DATA_12         12
TFIFO_0.DATA_11         11
TFIFO_0.DATA_10         10
TFIFO_0.DATA_9          9 
TFIFO_0.DATA_8          8 
TFIFO_0.DATA_7          7 
TFIFO_0.DATA_6          6 
TFIFO_0.DATA_5          5 
TFIFO_0.DATA_4          4 
TFIFO_0.DATA_3          3 
TFIFO_0.DATA_2          2 
TFIFO_0.DATA_1          1 
TFIFO_0.DATA_0          0 
ISTAH_0                0xEF84   Interrupt Status Register (HDLC-Channel 0)
ISTAH_0.RME             15  Receive Message End
ISTAH_0.RPF             14  Receive Pool Full
ISTAH_0.RFO             13  Receive Frame Overflow
ISTAH_0.FFO             12  Following Frame Overflow
ISTAH_0.XPR             7   Transmit Pool Ready
ISTAH_0.XMR             6   Transmit Message Repeat
ISTAH_0.XDU             5   Transmit Data Underrun
ISTAH_0.XDOV            4   Transmit Data Overflow
MASKH_0                0xEF86   Interrupt Mask Register (HDLC-Channel 0)
MASKH_0.RME             15
MASKH_0.RPF             14
MASKH_0.RFO             13
MASKH_0.FFO             12
MASKH_0.XPR             7
MASKH_0.XMR             6
MASKH_0.XDU             5
MASKH_0.XDOV            4
STAR_0                 0xEF88   Status Register (HDLC-Channel 0)
STAR_0.VFR              15  Valid Frame
STAR_0.RDO              14  Receive Data Overflow
STAR_0.CRC              13  CRC Check
STAR_0.RAB              12  Receive Message Aborted
STAR_0.SA1              11  SAPI Address Identification
STAR_0.SA0              10  SAPI Address Identification
STAR_0.C_R              9   Command/Response
STAR_0.TA               8   TEI Address Identification
STAR_0.RACI             7   Receiver Active Indication
CMDR_0                 0xEF8A   Command Register (HDLC-Channel 0)
CMDR_0.RRES             15  Receiver Reset
CMDR_0.XRES             7   Transmitter Reset
CMDR_0.XME              6   Transmit Message End
CMDR_0.XTF              5   Transmit Transparent Frame
IOMSEL_0               0xEF8C   IOM-2 Channel Selection (HDLC-Channel 0)
IOMSEL_0.EN_D2          3   Select second 2-bit IOM-2 Channel (D2)
IOMSEL_0.EN_D1          2   Select first 2-bit IOM-2 Channel (D1)
IOMSEL_0.EN_B2          1   Select second 8-bit IOM-2 Channel (B2)
IOMSEL_0.EN_B1          0   Select first 8-bit IOM-2 Channel (B1)
MODEH_0                0xEF8E   Mode Register (HDLC-Channel 0)
MODEH_0.RPE             15  Receive PEC Enable
MODEH_0.XPE             14  Transmit PEC Enable
MODEH_0.SRA             12  Store Receive Address
MODEH_0.XCRC            11  Transmit CRC
MODEH_0.RCRC            10  Receive CRC
MODEH_0.ITF             8   Interframe Time Fill
MODEH_0.MDS_7           7   0 Mode Select - bit 7
MODEH_0.MDS_6           6   0 Mode Select - bit 6
MODEH_0.MDS_5           5   0 Mode Select - bit 5
MODEH_0.RAC             3   Receiver Active
SAP1_0                 0xEF90   SAPI1 Register (HDLC-Channel 0)
SAP1_0.SAPI1_7          7   SAPI1 value - bit 7
SAP1_0.SAPI1_6          6   SAPI1 value - bit 6
SAP1_0.SAPI1_5          5   SAPI1 value - bit 5
SAP1_0.SAPI1_4          4   SAPI1 value - bit 4
SAP1_0.SAPI1_3          3   SAPI1 value - bit 3
SAP1_0.SAPI1_2          2   SAPI1 value - bit 2
SAP1_0.MHA              0   Mask High Address
SAP2_0                 0xEF92   SAPI2 Register (HDLC-Channel 0)
SAP2_0.SAPI2_7          7   SAPI2 value - bit 7
SAP2_0.SAPI2_6          6   SAPI2 value - bit 6
SAP2_0.SAPI2_5          5   SAPI2 value - bit 5
SAP2_0.SAPI2_4          4   SAPI2 value - bit 4
SAP2_0.SAPI2_3          3   SAPI2 value - bit 3
SAP2_0.SAPI2_2          2   SAPI2 value - bit 2
SAP2_0.MLA              0   Mask Low Address
RBC_0                  0xEF94   Receive Frame Byte Count (HDLC-Channel 0)
RBC_0.OV                12  Overflow
RBC_0.RBC_11            11
RBC_0.RBC_10            10
RBC_0.RBC_9             9 
RBC_0.RBC_8             8 
RBC_0.RBC_7             7 
RBC_0.RBC_6             6 
RBC_0.RBC_5             5 
RBC_0.RBC_4             4 
RBC_0.RBC_3             3 
RBC_0.RBC_2             2 
RBC_0.RBC_1             1 
RBC_0.RBC_0             0 
TEI1_0                 0xEF96   TEI1 Register (HDLC-Channel 0)
TEI1_0.TEI1_7           7   Terminal Endpoint Identifier - bit 7
TEI1_0.TEI1_6           6   Terminal Endpoint Identifier - bit 6
TEI1_0.TEI1_5           5   Terminal Endpoint Identifier - bit 5
TEI1_0.TEI1_4           4   Terminal Endpoint Identifier - bit 4
TEI1_0.TEI1_3           3   Terminal Endpoint Identifier - bit 3
TEI1_0.TEI1_2           2   Terminal Endpoint Identifier - bit 2
TEI1_0.TEI1_1           1   Terminal Endpoint Identifier - bit 1
TEI1_0.EA               0   Address field Extension bit
TEI2_0                 0xEF98   TEI2 Register (HDLC-Channel 0)
TEI2_0.TEI1_7           7   Terminal Endpoint Identifier - bit 7
TEI2_0.TEI1_6           6   Terminal Endpoint Identifier - bit 6
TEI2_0.TEI1_5           5   Terminal Endpoint Identifier - bit 5
TEI2_0.TEI1_4           4   Terminal Endpoint Identifier - bit 4
TEI2_0.TEI1_3           3   Terminal Endpoint Identifier - bit 3
TEI2_0.TEI1_2           2   Terminal Endpoint Identifier - bit 2
TEI2_0.TEI1_1           1   Terminal Endpoint Identifier - bit 1
TEI2_0.EA               0   Address field Extension bit
LOOP_0                 0xEF9A   Looping Register (HDLC-Channel 0)
LOOP_0.ELP              2   External Loop
LOOP_0.FAST             1   Fast Looping
LOOP_0.TLP              0   Transmit Loop
reserv_EF9C            0xEF9C   RESERVED
reserv_EF9E            0xEF9E   RESERVED
RFIFO_1                0xEFA0   Receive FIFO (HDLC-Channel 1)
RFIFO_1.DATA_15         15
RFIFO_1.DATA_14         14
RFIFO_1.DATA_13         13
RFIFO_1.DATA_12         12
RFIFO_1.DATA_11         11
RFIFO_1.DATA_10         10
RFIFO_1.DATA_9          9 
RFIFO_1.DATA_8          8 
RFIFO_1.DATA_7          7 
RFIFO_1.DATA_6          6 
RFIFO_1.DATA_5          5 
RFIFO_1.DATA_4          4 
RFIFO_1.DATA_3          3 
RFIFO_1.DATA_2          2 
RFIFO_1.DATA_1          1 
RFIFO_1.DATA_0          0 
TFIFO_1                0xEFA2   Transmit FIFO (HDLC-Channel 1)
TFIFO_1.DATA_15         15
TFIFO_1.DATA_14         14
TFIFO_1.DATA_13         13
TFIFO_1.DATA_12         12
TFIFO_1.DATA_11         11
TFIFO_1.DATA_10         10
TFIFO_1.DATA_9          9 
TFIFO_1.DATA_8          8 
TFIFO_1.DATA_7          7 
TFIFO_1.DATA_6          6 
TFIFO_1.DATA_5          5 
TFIFO_1.DATA_4          4 
TFIFO_1.DATA_3          3 
TFIFO_1.DATA_2          2 
TFIFO_1.DATA_1          1 
TFIFO_1.DATA_0          0 
ISTAH_1                0xEFA4   Interrupt Status Register (HDLC-Channel 1)
ISTAH_1.RME             15  Receive Message End
ISTAH_1.RPF             14  Receive Pool Full
ISTAH_1.RFO             13  Receive Frame Overflow
ISTAH_1.FFO             12  Following Frame Overflow
ISTAH_1.XPR             7   Transmit Pool Ready
ISTAH_1.XMR             6   Transmit Message Repeat
ISTAH_1.XDU             5   Transmit Data Underrun
ISTAH_1.XDOV            4   Transmit Data Overflow
MASKH_1                0xEFA6   Interrupt Mask Register (HDLC-Channel 1)
MASKH_1.RME             15
MASKH_1.RPF             14
MASKH_1.RFO             13
MASKH_1.FFO             12
MASKH_1.XPR             7
MASKH_1.XMR             6
MASKH_1.XDU             5
MASKH_1.XDOV            4
STAR_1                 0xEFA8   Status Register (HDLC-Channel 1)
STAR_1.VFR              15  Valid Frame
STAR_1.RDO              14  Receive Data Overflow
STAR_1.CRC              13  CRC Check
STAR_1.RAB              12  Receive Message Aborted
STAR_1.SA1              11  SAPI Address Identification
STAR_1.SA0              10  SAPI Address Identification
STAR_1.C_R              9   Command/Response
STAR_1.TA               8   TEI Address Identification
STAR_1.RACI             7   Receiver Active Indication
CMDR_1                 0xEFAA   Command Register (HDLC-Channel 1)
CMDR_1.RRES             15  Receiver Reset
CMDR_1.XRES             7   Transmitter Reset
CMDR_1.XME              6   Transmit Message End
CMDR_1.XTF              5   Transmit Transparent Frame
IOMSEL_1               0xEFAC   IOM-2 Channel Selection (HDLC-Channel 1)
IOMSEL_1.EN_D2          3   Select second 2-bit IOM-2 Channel (D2)
IOMSEL_1.EN_D1          2   Select first 2-bit IOM-2 Channel (D1)
IOMSEL_1.EN_B2          1   Select second 8-bit IOM-2 Channel (B2)
IOMSEL_1.EN_B1          0   Select first 8-bit IOM-2 Channel (B1)
MODEH_1                0xEFAE   Mode Register (HDLC-Channel 1)
MODEH_1.RPE             15  Receive PEC Enable
MODEH_1.XPE             14  Transmit PEC Enable
MODEH_1.SRA             12  Store Receive Address
MODEH_1.XCRC            11  Transmit CRC
MODEH_1.RCRC            10  Receive CRC
MODEH_1.ITF             8   Interframe Time Fill
MODEH_1.MDS_7           7   0 Mode Select - bit 7
MODEH_1.MDS_6           6   0 Mode Select - bit 6
MODEH_1.MDS_5           5   0 Mode Select - bit 5
MODEH_1.RAC             3   Receiver Active
SAP1_1                 0xEFB0   SAPI1 Register (HDLC-Channel 1)
SAP1_1.SAPI1_7          7   SAPI1 value - bit 7
SAP1_1.SAPI1_6          6   SAPI1 value - bit 6
SAP1_1.SAPI1_5          5   SAPI1 value - bit 5
SAP1_1.SAPI1_4          4   SAPI1 value - bit 4
SAP1_1.SAPI1_3          3   SAPI1 value - bit 3
SAP1_1.SAPI1_2          2   SAPI1 value - bit 2
SAP1_1.MHA              0   Mask High Address
SAP2_1                 0xEFB2   SAPI2 Register (HDLC-Channel 1)
SAP2_1.SAPI2_7          7   SAPI2 value - bit 7
SAP2_1.SAPI2_6          6   SAPI2 value - bit 6
SAP2_1.SAPI2_5          5   SAPI2 value - bit 5
SAP2_1.SAPI2_4          4   SAPI2 value - bit 4
SAP2_1.SAPI2_3          3   SAPI2 value - bit 3
SAP2_1.SAPI2_2          2   SAPI2 value - bit 2
SAP2_1.MLA              0   Mask Low Address
RBC_1                  0xEFB4   Receive Frame Byte Count (HDLC-Channel 1)
RBC_1.OV                12  Overflow
RBC_1.RBC_11            11
RBC_1.RBC_10            10
RBC_1.RBC_9             9 
RBC_1.RBC_8             8 
RBC_1.RBC_7             7 
RBC_1.RBC_6             6 
RBC_1.RBC_5             5 
RBC_1.RBC_4             4 
RBC_1.RBC_3             3 
RBC_1.RBC_2             2 
RBC_1.RBC_1             1 
RBC_1.RBC_0             0 
TEI1_1                 0xEFB6   TEI1 Register (HDLC-Channel 1)
TEI1_1.TEI1_7           7   Terminal Endpoint Identifier - bit 7
TEI1_1.TEI1_6           6   Terminal Endpoint Identifier - bit 6
TEI1_1.TEI1_5           5   Terminal Endpoint Identifier - bit 5
TEI1_1.TEI1_4           4   Terminal Endpoint Identifier - bit 4
TEI1_1.TEI1_3           3   Terminal Endpoint Identifier - bit 3
TEI1_1.TEI1_2           2   Terminal Endpoint Identifier - bit 2
TEI1_1.TEI1_1           1   Terminal Endpoint Identifier - bit 1
TEI1_1.EA               0   Address field Extension bit
TEI2_1                 0xEFB8   TEI2 Register (HDLC-Channel 1)
TEI2_1.TEI1_7           7   Terminal Endpoint Identifier - bit 7
TEI2_1.TEI1_6           6   Terminal Endpoint Identifier - bit 6
TEI2_1.TEI1_5           5   Terminal Endpoint Identifier - bit 5
TEI2_1.TEI1_4           4   Terminal Endpoint Identifier - bit 4
TEI2_1.TEI1_3           3   Terminal Endpoint Identifier - bit 3
TEI2_1.TEI1_2           2   Terminal Endpoint Identifier - bit 2
TEI2_1.TEI1_1           1   Terminal Endpoint Identifier - bit 1
TEI2_1.EA               0   Address field Extension bit
LOOP_1                 0xEFBA   Looping Register (HDLC-Channel 1)
LOOP_1.ELP              2   External Loop
LOOP_1.FAST             1   Fast Looping
LOOP_1.TLP              0   Transmit Loop
reserv_EFBC            0xEFBC   RESERVED
reserv_EFBE            0xEFBE   RESERVED
RFIFO_2                0xEFC0   Receive FIFO (HDLC-Channel 2)
RFIFO_2.DATA_15         15
RFIFO_2.DATA_14         14
RFIFO_2.DATA_13         13
RFIFO_2.DATA_12         12
RFIFO_2.DATA_11         11
RFIFO_2.DATA_10         10
RFIFO_2.DATA_9          9 
RFIFO_2.DATA_8          8 
RFIFO_2.DATA_7          7 
RFIFO_2.DATA_6          6 
RFIFO_2.DATA_5          5 
RFIFO_2.DATA_4          4 
RFIFO_2.DATA_3          3 
RFIFO_2.DATA_2          2 
RFIFO_2.DATA_1          1 
RFIFO_2.DATA_0          0 
TFIFO_2                0xEFC2   Transmit FIFO (HDLC-Channel 2)
TFIFO_2.DATA_15         15
TFIFO_2.DATA_14         14
TFIFO_2.DATA_13         13
TFIFO_2.DATA_12         12
TFIFO_2.DATA_11         11
TFIFO_2.DATA_10         10
TFIFO_2.DATA_9          9 
TFIFO_2.DATA_8          8 
TFIFO_2.DATA_7          7 
TFIFO_2.DATA_6          6 
TFIFO_2.DATA_5          5 
TFIFO_2.DATA_4          4 
TFIFO_2.DATA_3          3 
TFIFO_2.DATA_2          2 
TFIFO_2.DATA_1          1 
TFIFO_2.DATA_0          0 
ISTAH_2                0xEFC4   Interrupt Status Register (HDLC-Channel 2)
ISTAH_2.RME             15  Receive Message End
ISTAH_2.RPF             14  Receive Pool Full
ISTAH_2.RFO             13  Receive Frame Overflow
ISTAH_2.FFO             12  Following Frame Overflow
ISTAH_2.XPR             7   Transmit Pool Ready
ISTAH_2.XMR             6   Transmit Message Repeat
ISTAH_2.XDU             5   Transmit Data Underrun
ISTAH_2.XDOV            4   Transmit Data Overflow
MASKH_2                0xEFC6   Interrupt Mask Register (HDLC-Channel 2)
MASKH_2.RME             15
MASKH_2.RPF             14
MASKH_2.RFO             13
MASKH_2.FFO             12
MASKH_2.XPR             7
MASKH_2.XMR             6
MASKH_2.XDU             5
MASKH_2.XDOV            4
STAR_2                 0xEFC8   Status Register (HDLC-Channel 2)
STAR_2.VFR              15  Valid Frame
STAR_2.RDO              14  Receive Data Overflow
STAR_2.CRC              13  CRC Check
STAR_2.RAB              12  Receive Message Aborted
STAR_2.SA1              11  SAPI Address Identification
STAR_2.SA0              10  SAPI Address Identification
STAR_2.C_R              9   Command/Response
STAR_2.TA               8   TEI Address Identification
STAR_2.RACI             7   Receiver Active Indication
CMDR_2                 0xEFCA   Comm ERer (HDLC-Channel 2)
CMDR_2.RRES             15  Receiver Reset
CMDR_2.XRES             7   Transmitter Reset
CMDR_2.XME              6   Transmit Message End
CMDR_2.XTF              5   Transmit Transparent Frame
IOMSEL_2               0xEFCC   IOM-2 Channel Selection (HDLC-Channel 2)
IOMSEL_2.EN_D2          3   Select second 2-bit IOM-2 Channel (D2)
IOMSEL_2.EN_D1          2   Select first 2-bit IOM-2 Channel (D1)
IOMSEL_2.EN_B2          1   Select second 8-bit IOM-2 Channel (B2)
IOMSEL_2.EN_B1          0   Select first 8-bit IOM-2 Channel (B1)
MODEH_2                0xEFCE   Mode Register (HDLC-Channel 2)
MODEH_2.RPE             15  Receive PEC Enable
MODEH_2.XPE             14  Transmit PEC Enable
MODEH_2.SRA             12  Store Receive Address
MODEH_2.XCRC            11  Transmit CRC
MODEH_2.RCRC            10  Receive CRC
MODEH_2.ITF             8   Interframe Time Fill
MODEH_2.MDS_7           7   0 Mode Select - bit 7
MODEH_2.MDS_6           6   0 Mode Select - bit 6
MODEH_2.MDS_5           5   0 Mode Select - bit 5
MODEH_2.RAC             3   Receiver Active
SAP1_2                 0xEFD0   SAPI1 Register (HDLC-Channel 2)
SAP1_2.SAPI1_7          7   SAPI1 value - bit 7
SAP1_2.SAPI1_6          6   SAPI1 value - bit 6
SAP1_2.SAPI1_5          5   SAPI1 value - bit 5
SAP1_2.SAPI1_4          4   SAPI1 value - bit 4
SAP1_2.SAPI1_3          3   SAPI1 value - bit 3
SAP1_2.SAPI1_2          2   SAPI1 value - bit 2
SAP1_2.MHA              0   Mask High Address
SAP2_2                 0xEFD2   SAPI2 Register (HDLC-Channel 2)
SAP2_2.SAPI2_7          7   SAPI2 value - bit 7
SAP2_2.SAPI2_6          6   SAPI2 value - bit 6
SAP2_2.SAPI2_5          5   SAPI2 value - bit 5
SAP2_2.SAPI2_4          4   SAPI2 value - bit 4
SAP2_2.SAPI2_3          3   SAPI2 value - bit 3
SAP2_2.SAPI2_2          2   SAPI2 value - bit 2
SAP2_2.MLA              0   Mask Low Address
RBC_2                  0xEFD4   Receive Frame Byte Count (HDLC-Channel 2)
RBC_2.OV                12  Overflow
RBC_2.RBC_11            11
RBC_2.RBC_10            10
RBC_2.RBC_9             9 
RBC_2.RBC_8             8 
RBC_2.RBC_7             7 
RBC_2.RBC_6             6 
RBC_2.RBC_5             5 
RBC_2.RBC_4             4 
RBC_2.RBC_3             3 
RBC_2.RBC_2             2 
RBC_2.RBC_1             1 
RBC_2.RBC_0             0 
TEI1_2                 0xEFD6   TEI1 Register (HDLC-Channel 2)
TEI1_2.TEI1_7           7   Terminal Endpoint Identifier - bit 7
TEI1_2.TEI1_6           6   Terminal Endpoint Identifier - bit 6
TEI1_2.TEI1_5           5   Terminal Endpoint Identifier - bit 5
TEI1_2.TEI1_4           4   Terminal Endpoint Identifier - bit 4
TEI1_2.TEI1_3           3   Terminal Endpoint Identifier - bit 3
TEI1_2.TEI1_2           2   Terminal Endpoint Identifier - bit 2
TEI1_2.TEI1_1           1   Terminal Endpoint Identifier - bit 1
TEI1_2.EA               0   Address field Extension bit
TEI2_2                 0xEFD8   TEI2 Register (HDLC-Channel 2)
TEI2_2.TEI1_7           7   Terminal Endpoint Identifier - bit 7
TEI2_2.TEI1_6           6   Terminal Endpoint Identifier - bit 6
TEI2_2.TEI1_5           5   Terminal Endpoint Identifier - bit 5
TEI2_2.TEI1_4           4   Terminal Endpoint Identifier - bit 4
TEI2_2.TEI1_3           3   Terminal Endpoint Identifier - bit 3
TEI2_2.TEI1_2           2   Terminal Endpoint Identifier - bit 2
TEI2_2.TEI1_1           1   Terminal Endpoint Identifier - bit 1
TEI2_2.EA               0   Address field Extension bit
LOOP_2                 0xEFDA   Looping Register (HDLC-Channel 2)
LOOP_2.ELP              2   External Loop
LOOP_2.FAST             1   Fast Looping
LOOP_2.TLP              0   Transmit Loop
reserv_EFDC            0xEFDC   RESERVED
reserv_EFDE            0xEFDE   RESERVED
RFIFO_3                0xEFE0   Receive FIFO (HDLC-Channel 3)
RFIFO_3.DATA_15         15
RFIFO_3.DATA_14         14
RFIFO_3.DATA_13         13
RFIFO_3.DATA_12         12
RFIFO_3.DATA_11         11
RFIFO_3.DATA_10         10
RFIFO_3.DATA_9          9 
RFIFO_3.DATA_8          8 
RFIFO_3.DATA_7          7 
RFIFO_3.DATA_6          6 
RFIFO_3.DATA_5          5 
RFIFO_3.DATA_4          4 
RFIFO_3.DATA_3          3 
RFIFO_3.DATA_2          2 
RFIFO_3.DATA_1          1 
RFIFO_3.DATA_0          0 
TFIFO_3                0xEFE2   Transmit FIFO (HDLC-Channel 3)
TFIFO_3.DATA_15         15
TFIFO_3.DATA_14         14
TFIFO_3.DATA_13         13
TFIFO_3.DATA_12         12
TFIFO_3.DATA_11         11
TFIFO_3.DATA_10         10
TFIFO_3.DATA_9          9 
TFIFO_3.DATA_8          8 
TFIFO_3.DATA_7          7 
TFIFO_3.DATA_6          6 
TFIFO_3.DATA_5          5 
TFIFO_3.DATA_4          4 
TFIFO_3.DATA_3          3 
TFIFO_3.DATA_2          2 
TFIFO_3.DATA_1          1 
TFIFO_3.DATA_0          0 
ISTAH_3                0xEFE4   Interrupt Status Register (HDLC-Channel 3)
ISTAH_3.RME             15  Receive Message End
ISTAH_3.RPF             14  Receive Pool Full
ISTAH_3.RFO             13  Receive Frame Overflow
ISTAH_3.FFO             12  Following Frame Overflow
ISTAH_3.XPR             7   Transmit Pool Ready
ISTAH_3.XMR             6   Transmit Message Repeat
ISTAH_3.XDU             5   Transmit Data Underrun
ISTAH_3.XDOV            4   Transmit Data Overflow
MASKH_3                0xEFE6   Interrupt Mask Register (HDLC-Channel 3)
MASKH_3.RME             15
MASKH_3.RPF             14
MASKH_3.RFO             13
MASKH_3.FFO             12
MASKH_3.XPR             7
MASKH_3.XMR             6
MASKH_3.XDU             5
MASKH_3.XDOV            4
STAR_3                 0xEFE8   Status Register (HDLC-Channel 3)
STAR_3.VFR              15  Valid Frame
STAR_3.RDO              14  Receive Data Overflow
STAR_3.CRC              13  CRC Check
STAR_3.RAB              12  Receive Message Aborted
STAR_3.SA1              11  SAPI Address Identification
STAR_3.SA0              10  SAPI Address Identification
STAR_3.C_R              9   Command/Response
STAR_3.TA               8   TEI Address Identification
STAR_3.RACI             7   Receiver Active Indication
CMDR_3                 0xEFEA   Command Register (HDLC-Channel 3)
CMDR_3.RRES             15  Receiver Reset
CMDR_3.XRES             7   Transmitter Reset
CMDR_3.XME              6   Transmit Message End
CMDR_3.XTF              5   Transmit Transparent Frame
IOMSEL_3               0xEFEC   IOM-2 Channel Selection (HDLC-Channel 3)
IOMSEL_3.EN_D2          3   Select second 2-bit IOM-2 Channel (D2)
IOMSEL_3.EN_D1          2   Select first 2-bit IOM-2 Channel (D1)
IOMSEL_3.EN_B2          1   Select second 8-bit IOM-2 Channel (B2)
IOMSEL_3.EN_B1          0   Select first 8-bit IOM-2 Channel (B1)
MODEH_3                0xEFEE   Mode Register (HDLC-Channel 3)
MODEH_3.RPE             15  Receive PEC Enable
MODEH_3.XPE             14  Transmit PEC Enable
MODEH_3.SRA             12  Store Receive Address
MODEH_3.XCRC            11  Transmit CRC
MODEH_3.RCRC            10  Receive CRC
MODEH_3.ITF             8   Interframe Time Fill
MODEH_3.MDS_7           7   0 Mode Select - bit 7
MODEH_3.MDS_6           6   0 Mode Select - bit 6
MODEH_3.MDS_5           5   0 Mode Select - bit 5
MODEH_3.RAC             3   Receiver Active
SAP1_3                 0xEFF0   SAPI1 Register (HDLC-Channel 3)
SAP1_3.SAPI1_7          7   SAPI1 value - bit 7
SAP1_3.SAPI1_6          6   SAPI1 value - bit 6
SAP1_3.SAPI1_5          5   SAPI1 value - bit 5
SAP1_3.SAPI1_4          4   SAPI1 value - bit 4
SAP1_3.SAPI1_3          3   SAPI1 value - bit 3
SAP1_3.SAPI1_2          2   SAPI1 value - bit 2
SAP1_3.MHA              0   Mask High Address
SAP2_3                 0xEFF2   SAPI2 Register (HDLC-Channel 3)
SAP2_3.SAPI2_7          7   SAPI2 value - bit 7
SAP2_3.SAPI2_6          6   SAPI2 value - bit 6
SAP2_3.SAPI2_5          5   SAPI2 value - bit 5
SAP2_3.SAPI2_4          4   SAPI2 value - bit 4
SAP2_3.SAPI2_3          3   SAPI2 value - bit 3
SAP2_3.SAPI2_2          2   SAPI2 value - bit 2
SAP2_3.MLA              0   Mask Low Address
RBC_3                  0xEFF4   Receive Frame Byte Count (HDLC-Channel 3)
RBC_3.OV                12  Overflow
RBC_3.RBC_11            11
RBC_3.RBC_10            10
RBC_3.RBC_9             9 
RBC_3.RBC_8             8 
RBC_3.RBC_7             7 
RBC_3.RBC_6             6 
RBC_3.RBC_5             5 
RBC_3.RBC_4             4 
RBC_3.RBC_3             3 
RBC_3.RBC_2             2 
RBC_3.RBC_1             1 
RBC_3.RBC_0             0 
TEI1_3                 0xEFF6   TEI1 Register (HDLC-Channel 3)
TEI1_3.TEI1_7           7   Terminal Endpoint Identifier - bit 7
TEI1_3.TEI1_6           6   Terminal Endpoint Identifier - bit 6
TEI1_3.TEI1_5           5   Terminal Endpoint Identifier - bit 5
TEI1_3.TEI1_4           4   Terminal Endpoint Identifier - bit 4
TEI1_3.TEI1_3           3   Terminal Endpoint Identifier - bit 3
TEI1_3.TEI1_2           2   Terminal Endpoint Identifier - bit 2
TEI1_3.TEI1_1           1   Terminal Endpoint Identifier - bit 1
TEI1_3.EA               0   Address field Extension bit
TEI2_3                 0xEFF8   TEI2 Register (HDLC-Channel 3)
TEI2_3.TEI1_7           7   Terminal Endpoint Identifier - bit 7
TEI2_3.TEI1_6           6   Terminal Endpoint Identifier - bit 6
TEI2_3.TEI1_5           5   Terminal Endpoint Identifier - bit 5
TEI2_3.TEI1_4           4   Terminal Endpoint Identifier - bit 4
TEI2_3.TEI1_3           3   Terminal Endpoint Identifier - bit 3
TEI2_3.TEI1_2           2   Terminal Endpoint Identifier - bit 2
TEI2_3.TEI1_1           1   Terminal Endpoint Identifier - bit 1
TEI2_3.EA               0   Address field Extension bit
LOOP_3                 0xEFFA   Looping Register (HDLC-Channel 3)
LOOP_3.ELP              2   External Loop
LOOP_3.FAST             1   Fast Looping
LOOP_3.TLP              0   Transmit Loop
reserv_EFFC            0xEFFC   RESERVED
reserv_EFFE            0xEFFE   RESERVED

; E_SFR and SFR Registers
XADRS1           0xF014   XBUS Address Select Register 1
XADRS1.RGSAD15    15  Range Start Address bit 15
XADRS1.RGSAD14    14  Range Start Address bit 14
XADRS1.RGSAD13    13  Range Start Address bit 13
XADRS1.RGSAD12    12  Range Start Address bit 12
XADRS1.RGSAD11    11  Range Start Address bit 11
XADRS1.RGSAD10    10  Range Start Address bit 10
XADRS1.RGSAD9     9   Range Start Address bit 9
XADRS1.RGSAD8     8   Range Start Address bit 8
XADRS1.RGSAD7     7   Range Start Address bit 7
XADRS1.RGSAD6     6   Range Start Address bit 6
XADRS1.RGSAD5     5   Range Start Address bit 5
XADRS1.RGSAD4     4   Range Start Address bit 4
XADRS1.RGSZ3      3   Range Size Selection bit 3
XADRS1.RGSZ2      2   Range Size Selection bit 2
XADRS1.RGSZ1      1   Range Size Selection bit 1
XADRS1.RGSZ0      0   Range Size Selection bit 0
XADRS2           0xF016   XBUS Address Select Register 2
XADRS2.RGSAD15    15  Range Start Address bit 15
XADRS2.RGSAD14    14  Range Start Address bit 14
XADRS2.RGSAD13    13  Range Start Address bit 13
XADRS2.RGSAD12    12  Range Start Address bit 12
XADRS2.RGSAD11    11  Range Start Address bit 11
XADRS2.RGSAD10    10  Range Start Address bit 10
XADRS2.RGSAD9     9   Range Start Address bit 9
XADRS2.RGSAD8     8   Range Start Address bit 8
XADRS2.RGSAD7     7   Range Start Address bit 7
XADRS2.RGSAD6     6   Range Start Address bit 6
XADRS2.RGSAD5     5   Range Start Address bit 5
XADRS2.RGSAD4     4   Range Start Address bit 4
XADRS2.RGSZ3      3   Range Size Selection bit 3
XADRS2.RGSZ2      2   Range Size Selection bit 2
XADRS2.RGSZ1      1   Range Size Selection bit 1
XADRS2.RGSZ0      0   Range Size Selection bit 0
XADRS3           0xF018   XBUS Address Select Register 3
XADRS3.RGSAD15    15  Range Start Address bit 15
XADRS3.RGSAD14    14  Range Start Address bit 14
XADRS3.RGSAD13    13  Range Start Address bit 13
XADRS3.RGSAD12    12  Range Start Address bit 12
XADRS3.RGSAD11    11  Range Start Address bit 11
XADRS3.RGSAD10    10  Range Start Address bit 10
XADRS3.RGSAD9     9   Range Start Address bit 9
XADRS3.RGSAD8     8   Range Start Address bit 8
XADRS3.RGSAD7     7   Range Start Address bit 7
XADRS3.RGSAD6     6   Range Start Address bit 6
XADRS3.RGSAD5     5   Range Start Address bit 5
XADRS3.RGSAD4     4   Range Start Address bit 4
XADRS3.RGSZ3      3   Range Size Selection bit 3
XADRS3.RGSZ2      2   Range Size Selection bit 2
XADRS3.RGSZ1      1   Range Size Selection bit 1
XADRS3.RGSZ0      0   Range Size Selection bit 0
XADRS4           0xF01A   XBUS Address Select Register 4
XADRS4.RGSAD15    15  Range Start Address bit 15
XADRS4.RGSAD14    14  Range Start Address bit 14
XADRS4.RGSAD13    13  Range Start Address bit 13
XADRS4.RGSAD12    12  Range Start Address bit 12
XADRS4.RGSAD11    11  Range Start Address bit 11
XADRS4.RGSAD10    10  Range Start Address bit 10
XADRS4.RGSAD9     9   Range Start Address bit 9
XADRS4.RGSAD8     8   Range Start Address bit 8
XADRS4.RGSAD7     7   Range Start Address bit 7
XADRS4.RGSAD6     6   Range Start Address bit 6
XADRS4.RGSAD5     5   Range Start Address bit 5
XADRS4.RGSAD4     4   Range Start Address bit 4
XADRS4.RGSZ3      3   Range Size Selection bit 3
XADRS4.RGSZ2      2   Range Size Selection bit 2
XADRS4.RGSZ1      1   Range Size Selection bit 1
XADRS4.RGSZ0      0   Range Size Selection bit 0
XADRS5           0xF01C   XBUS Address Select Register 5
XADRS5.RGSAD15    15  Range Start Address bit 15
XADRS5.RGSAD14    14  Range Start Address bit 14
XADRS5.RGSAD13    13  Range Start Address bit 13
XADRS5.RGSAD12    12  Range Start Address bit 12
XADRS5.RGSAD11    11  Range Start Address bit 11
XADRS5.RGSAD10    10  Range Start Address bit 10
XADRS5.RGSAD9     9   Range Start Address bit 9
XADRS5.RGSAD8     8   Range Start Address bit 8
XADRS5.RGSAD7     7   Range Start Address bit 7
XADRS5.RGSAD6     6   Range Start Address bit 6
XADRS5.RGSAD5     5   Range Start Address bit 5
XADRS5.RGSAD4     4   Range Start Address bit 4
XADRS5.RGSZ3      3   Range Size Selection bit 3
XADRS5.RGSZ2      2   Range Size Selection bit 2
XADRS5.RGSZ1      1   Range Size Selection bit 1
XADRS5.RGSZ0      0   Range Size Selection bit 0
XADRS6           0xF01E   XBUS Address Select Register 6
XADRS6.RGSAD15    15  Range Start Address bit 15
XADRS6.RGSAD14    14  Range Start Address bit 14
XADRS6.RGSAD13    13  Range Start Address bit 13
XADRS6.RGSAD12    12  Range Start Address bit 12
XADRS6.RGSAD11    11  Range Start Address bit 11
XADRS6.RGSAD10    10  Range Start Address bit 10
XADRS6.RGSAD9     9   Range Start Address bit 9
XADRS6.RGSAD8     8   Range Start Address bit 8
XADRS6.RGSAD7     7   Range Start Address bit 7
XADRS6.RGSAD6     6   Range Start Address bit 6
XADRS6.RGSAD5     5   Range Start Address bit 5
XADRS6.RGSAD4     4   Range Start Address bit 4
XADRS6.RGSZ3      3   Range Size Selection bit 3
XADRS6.RGSZ2      2   Range Size Selection bit 2
XADRS6.RGSZ1      1   Range Size Selection bit 1
XADRS6.RGSZ0      0   Range Size Selection bit 0
XPERCON          0xF024   XBUS Peripheral Control Register
XPERCON.XPER7     7
XPERCON.XPER6     6
XPERCON.XPER5     5
IDMEM2           0xF076   Identifier
IDPROG           0xF078   Identifier
IDPROG.PROGVPP_15 15  Programming VPP Voltage - bit 15
IDPROG.PROGVPP_14 14  Programming VPP Voltage - bit 14
IDPROG.PROGVPP_13 13  Programming VPP Voltage - bit 13
IDPROG.PROGVPP_12 12  Programming VPP Voltage - bit 12
IDPROG.PROGVPP_11 11  Programming VPP Voltage - bit 11
IDPROG.PROGVPP_10 10  Programming VPP Voltage - bit 10
IDPROG.PROGVPP_9  9   Programming VPP Voltage - bit 9 
IDPROG.PROGVPP_8  8   Programming VPP Voltage - bit 8 
IDPROG.PROGVDD_7  7   Programming VDD Voltage - bit 7 
IDPROG.PROGVDD_6  6   Programming VDD Voltage - bit 6 
IDPROG.PROGVDD_5  5   Programming VDD Voltage - bit 5 
IDPROG.PROGVDD_4  4   Programming VDD Voltage - bit 4 
IDPROG.PROGVDD_3  3   Programming VDD Voltage - bit 3 
IDPROG.PROGVDD_2  2   Programming VDD Voltage - bit 2 
IDPROG.PROGVDD_1  1   Programming VDD Voltage - bit 1 
IDPROG.PROGVDD_0  0   Programming VDD Voltage - bit 0 
IDMEM            0xF07A   Identifier
IDMEM.Type_15     15  Type of on-chip Program Memory - bit 15
IDMEM.Type_14     14  Type of on-chip Program Memory - bit 14
IDMEM.Type_13     13  Type of on-chip Program Memory - bit 13
IDMEM.Type_12     12  Type of on-chip Program Memory - bit 12
IDMEM.Size_11     11  Size of on-chip Program Memory - bit 11
IDMEM.Size_10     10  Size of on-chip Program Memory - bit 10
IDMEM.Size_9      9   Size of on-chip Program Memory - bit 9 
IDMEM.Size_8      8   Size of on-chip Program Memory - bit 8 
IDMEM.Size_7      7   Size of on-chip Program Memory - bit 7 
IDMEM.Size_6      6   Size of on-chip Program Memory - bit 6 
IDMEM.Size_5      5   Size of on-chip Program Memory - bit 5 
IDMEM.Size_4      4   Size of on-chip Program Memory - bit 4 
IDMEM.Size_3      3   Size of on-chip Program Memory - bit 3 
IDMEM.Size_2      2   Size of on-chip Program Memory - bit 2 
IDMEM.Size_1      1   Size of on-chip Program Memory - bit 1 
IDMEM.Size_0      0   Size of on-chip Program Memory - bit 0 
IDCHIP           0xF07C   Identifier
IDCHIP.CHIPID_15  15  Device Identification - bit 15
IDCHIP.CHIPID_14  14  Device Identification - bit 14
IDCHIP.CHIPID_13  13  Device Identification - bit 13
IDCHIP.CHIPID_12  12  Device Identification - bit 12
IDCHIP.CHIPID_11  11  Device Identification - bit 11
IDCHIP.CHIPID_10  10  Device Identification - bit 10
IDCHIP.CHIPID_9   9   Device Identification - bit 9
IDCHIP.CHIPID_8   8   Device Identification - bit 8
IDCHIP.Revision_7 7   Device Revision Code - bit 7
IDCHIP.Revision_6 6   Device Revision Code - bit 6
IDCHIP.Revision_5 5   Device Revision Code - bit 5
IDCHIP.Revision_4 4   Device Revision Code - bit 4
IDCHIP.Revision_3 3   Device Revision Code - bit 3
IDCHIP.Revision_2 2   Device Revision Code - bit 2
IDCHIP.Revision_1 1   Device Revision Code - bit 1
IDCHIP.Revision_0 0   Device Revision Code - bit 0
IDMANUF          0xF07E   Identifier
IDMANUF.MANUF_15  15  Manufacturer - bit 15
IDMANUF.MANUF_14  14  Manufacturer - bit 14
IDMANUF.MANUF_13  13  Manufacturer - bit 13
IDMANUF.MANUF_12  12  Manufacturer - bit 12
IDMANUF.MANUF_11  11  Manufacturer - bit 11
IDMANUF.MANUF_10  10  Manufacturer - bit 10
IDMANUF.MANUF_9   9   Manufacturer - bit 9 
IDMANUF.MANUF_8   8   Manufacturer - bit 8 
IDMANUF.MANUF_7   7   Manufacturer - bit 7 
IDMANUF.MANUF_6   6   Manufacturer - bit 6 
IDMANUF.MANUF_5   5   Manufacturer - bit 5 
IDMANUF.DEPT_4    4   Department - bit 4 
IDMANUF.DEPT_3    3   Department - bit 3 
IDMANUF.DEPT_2    2   Department - bit 2 
IDMANUF.DEPT_1    1   Department - bit 1 
IDMANUF.DEPT_0    0   Department - bit 0 
SSCTB            0xF0B0   SSC Transmit Buffer (WO)
SSCRB            0xF0B2   SSC Receive Buffer (RO)
SSCBR            0xF0B4   SSC Baudrate Register
SSCCLC           0xF0B6   SSC Clock Control Register
SSCCLC.EXDISR     3   External Disable Request
SSCCLC.SUSPEN     2   Peripheral Suspend Enable Bit for OCDS
SSCCLC.SSCDISS    1   SSC Disable Status Bit
SSCCLC.SSCDISR    0   SSC Disable Request Bit
SCUSLC           0xF0C0   Security Level Control Register
SCUSLC.COMMAND_15 15
SCUSLC.COMMAND_14 14
SCUSLC.COMMAND_13 13
SCUSLC.COMMAND_12 12
SCUSLC.COMMAND_11 11
SCUSLC.COMMAND_10 10
SCUSLC.COMMAND_9  9 
SCUSLC.COMMAND_8  8 
SCUSLC.COMMAND_7  7 
SCUSLC.COMMAND_6  6 
SCUSLC.COMMAND_5  5 
SCUSLC.COMMAND_4  4 
SCUSLC.COMMAND_3  3 
SCUSLC.COMMAND_2  2 
SCUSLC.COMMAND_1  1 
SCUSLC.COMMAND_0  0 
SCUSLS           0xF0C2   Security Level Status Register
SCUSLS.STATE_15   15  Actual State - bit 15
SCUSLS.STATE_14   14  Actual State - bit 14
SCUSLS.STATE_13   13  Actual State - bit 13
SCUSLS.SL_12      12  Security Level - bit 12
SCUSLS.SL_11      11  Security Level - bit 11
SCUSLS.PASSWORD_7 7   Current Password - bit 7
SCUSLS.PASSWORD_6 6   Current Password - bit 6
SCUSLS.PASSWORD_5 5   Current Password - bit 5
SCUSLS.PASSWORD_4 4   Current Password - bit 4
SCUSLS.PASSWORD_3 3   Current Password - bit 3
SCUSLS.PASSWORD_2 2   Current Password - bit 2
SCUSLS.PASSWORD_1 1   Current Password - bit 1
SCUSLS.PASSWORD_0 0   Current Password - bit 0
RTCCLC           0xF0C8   RTC Clock Control Register
RTCCLC.EXDISR     3   External Disable Request
RTCCLC.SUSPEN     2   Peripheral Suspend Enable Bit for OCDS
RTCCLC.RTCDISS    1   RTC Disable Status Bit
RTCCLC.RTCDISR    0   RTC Disable Request Bit
RTCRELL          0xF0CC   RTC Timer Reload Register Low
RTCRELH          0xF0CE   RTC Timer Reload Register High
T14REL           0xF0D0   Timer 14 Reload Register
T14              0xF0D2   Timer 14 Register
RTCL             0xF0D4   RTC Timer Register Low
RTCH             0xF0D6   RTC Timer Register High
DTIDR            0xF0D8   Task ID register1)
DP0L             0xF100   P0L Direction Control Register
DP0L.DP0L7        7   Port direction register DP0L bit 7
DP0L.DP0L6        6   Port direction register DP0L bit 6
DP0L.DP0L5        5   Port direction register DP0L bit 5
DP0L.DP0L4        4   Port direction register DP0L bit 4
DP0L.DP0L3        3   Port direction register DP0L bit 3
DP0L.DP0L2        2   Port direction register DP0L bit 2
DP0L.DP0L1        1   Port direction register DP0L bit 1
DP0L.DP0L0        0   Port direction register DP0L bit 0
DP0H             0xF102   P0H Direction Control Register
DP0H.DP0H7        7   Port direction register DP0H bit 7
DP0H.DP0H6        6   Port direction register DP0H bit 6
DP0H.DP0H5        5   Port direction register DP0H bit 5
DP0H.DP0H4        4   Port direction register DP0H bit 4
DP0H.DP0H3        3   Port direction register DP0H bit 3
DP0H.DP0H2        2   Port direction register DP0H bit 2
DP0H.DP0H1        1   Port direction register DP0H bit 1
DP0H.DP0H0        0   Port direction register DP0H bit 0
DP1L             0xF104   P1L Direction Control Register
DP1L.DP1L7        7   Port direction register DP1L bit 7
DP1L.DP1L6        6   Port direction register DP1L bit 6
DP1L.DP1L5        5   Port direction register DP1L bit 5
DP1L.DP1L4        4   Port direction register DP1L bit 4
DP1L.DP1L3        3   Port direction register DP1L bit 3
DP1L.DP1L2        2   Port direction register DP1L bit 2
DP1L.DP1L1        1   Port direction register DP1L bit 1
DP1L.DP1L0        0   Port direction register DP1L bit 0
DP1H             0xF106   P1H Direction Control Register
DP1H.DP1H7        7   Port direction register DP1H bit 7
DP1H.DP1H6        6   Port direction register DP1H bit 6
DP1H.DP1H5        5   Port direction register DP1H bit 5
DP1H.DP1H4        4   Port direction register DP1H bit 4
DP1H.DP1H3        3   Port direction register DP1H bit 3
DP1H.DP1H2        2   Port direction register DP1H bit 2
DP1H.DP1H1        1   Port direction register DP1H bit 1
DP1H.DP1H0        0   Port direction register DP1L bit 0
RP0H             0xF108   System Startup Configuration
RP0H.CLKCFG_7     7   Clock Generation Mode Configuration - bit 7
RP0H.CLKCFG_6     6   Clock Generation Mode Configuration - bit 6
RP0H.CLKCFG_5     5   Clock Generation Mode Configuration - bit 5
RP0H.SALSEL_4     4   Segment Address Line Selection - bit 4
RP0H.SALSEL_3     3   Segment Address Line Selection - bit 3
RP0H.CSSEL_2      2   Chip Select Line Selection - bit 2
RP0H.CSSEL_1      1   Chip Select Line Selection - bit 1
RP0H.WRC          0   Write Configuration
XBCON1           0xF114   XBUS Control register 1: IOM-2 module
XBCON1.RDYEN1     12  READY Enable
XBCON1.BSWC1      11  BUSCON Switch Control
XBCON1.BUSACT1    10  Bus Active Control
XBCON1.ALECTL1    9   ALE Lengthening Control Bit
XBCON1.EWEN1      8   Early Write Enable
XBCON1.BTYP1_7    7   Bus Type Selection - bit 7
XBCON1.BTYP1_6    6   Bus Type Selection - bit 6
XBCON1.MTTC1      5   Memory Tri-state Time Control
XBCON1.RWDC1      4   READ/WRITE Delay Control
XBCON1.MCTC1_3    3   Memory Cycle Time Control - bit 3
XBCON1.MCTC1_2    2   Memory Cycle Time Control - bit 2
XBCON1.MCTC1_1    1   Memory Cycle Time Control - bit 1
XBCON1.MCTC1_0    0   Memory Cycle Time Control - bit 0
XBCON2           0xF116   XBUS Control register 2: reserved
XBCON2.RDYEN2     12  READY Enable
XBCON2.BSWC2      11  BUSCON Switch Control
XBCON2.BUSACT2    10  Bus Active Control
XBCON2.ALECTL2    9   ALE Lengthening Control Bit
XBCON2.EWEN2      8   Early Write Enable
XBCON2.BTYP2_7    7   Bus Type Selection - bit 7
XBCON2.BTYP2_6    6   Bus Type Selection - bit 6
XBCON2.MTTC2      5   Memory Tri-state Time Control
XBCON2.RWDC2      4   READ/WRITE Delay Control
XBCON2.MCTC2_3    3   Memory Cycle Time Control - bit 3
XBCON2.MCTC2_2    2   Memory Cycle Time Control - bit 2
XBCON2.MCTC2_1    1   Memory Cycle Time Control - bit 1
XBCON2.MCTC2_0    0   Memory Cycle Time Control - bit 0
XBCON3           0xF118   XBUS Control register 3: reserved
XBCON3.RDYEN3     12  READY Enable
XBCON3.BSWC3      11  BUSCON Switch Control
XBCON3.BUSACT3    10  Bus Active Control
XBCON3.ALECTL3    9   ALE Lengthening Control Bit
XBCON3.EWEN3      8   Early Write Enable
XBCON3.BTYP3_7    7   Bus Type Selection - bit 7
XBCON3.BTYP3_6    6   Bus Type Selection - bit 6
XBCON3.MTTC3      5   Memory Tri-state Time Control
XBCON3.RWDC3      4   READ/WRITE Delay Control
XBCON3.MCTC3_3    3   Memory Cycle Time Control - bit 3
XBCON3.MCTC3_2    2   Memory Cycle Time Control - bit 2
XBCON3.MCTC3_1    1   Memory Cycle Time Control - bit 1
XBCON3.MCTC3_0    0   Memory Cycle Time Control - bit 0
XBCON4           0xF11A   XBUS Control register 3: reserved
XBCON5           0xF11C   XBUS Control register 5: reserved
XBCON6           0xF11E   XBUS Control register 6: reserved
UTD3IC           0xF160   UDC TX Done3  Interrupt Control Register
UTD3IC.UTD3IR     7   Interrupt Request Flag
UTD3IC.UTD3IE     6   Interrupt Enable Control Bit
UTD3IC.ILVL_5     5   Interrupt Priority Level - bit 5
UTD3IC.ILVL_4     4   Interrupt Priority Level - bit 4
UTD3IC.ILVL_3     3   Interrupt Priority Level - bit 3
UTD3IC.ILVL_2     2   Interrupt Priority Level - bit 2
UTD3IC.GLVL_1     1   Group Level - bit 1
UTD3IC.GLVL_0     0   Group Level - bit 0
UTD4IC           0xF162   UDC TX Done4  Interrupt Control Register
UTD4IC.UTD4IR     7   Interrupt Request Flag
UTD4IC.UTD4IE     6   Interrupt Enable Control Bit
UTD4IC.ILVL_5     5   Interrupt Priority Level - bit 5
UTD4IC.ILVL_4     4   Interrupt Priority Level - bit 4
UTD4IC.ILVL_3     3   Interrupt Priority Level - bit 3
UTD4IC.ILVL_2     2   Interrupt Priority Level - bit 2
UTD4IC.GLVL_1     1   Group Level - bit 1
UTD4IC.GLVL_0     0   Group Level - bit 0
UTD5IC           0xF164   UDC TX Done5  Interrupt Control Register
UTD5IC.UTD5IR     7   Interrupt Request Flag
UTD5IC.UTD5IE     6   Interrupt Enable Control Bit
UTD5IC.ILVL_5     5   Interrupt Priority Level - bit 5
UTD5IC.ILVL_4     4   Interrupt Priority Level - bit 4
UTD5IC.ILVL_3     3   Interrupt Priority Level - bit 3
UTD5IC.ILVL_2     2   Interrupt Priority Level - bit 2
UTD5IC.GLVL_1     1   Group Level - bit 1
UTD5IC.GLVL_0     0   Group Level - bit 0
UTD6IC           0xF166   UDC TX Done6  Interrupt Control Register
UTD6IC.UTD6IR     7   Interrupt Request Flag
UTD6IC.UTD6IE     6   Interrupt Enable Control Bit
UTD6IC.ILVL_5     5   Interrupt Priority Level - bit 5
UTD6IC.ILVL_4     4   Interrupt Priority Level - bit 4
UTD6IC.ILVL_3     3   Interrupt Priority Level - bit 3
UTD6IC.ILVL_2     2   Interrupt Priority Level - bit 2
UTD6IC.GLVL_1     1   Group Level - bit 1
UTD6IC.GLVL_0     0   Group Level - bit 0
UTD7IC           0xF168   UDC TX Done7  Interrupt Control Register
UTD7IC.UTD7IR     7   Interrupt Request Flag
UTD7IC.UTD7IE     6   Interrupt Enable Control Bit
UTD7IC.ILVL_5     5   Interrupt Priority Level - bit 5
UTD7IC.ILVL_4     4   Interrupt Priority Level - bit 4
UTD7IC.ILVL_3     3   Interrupt Priority Level - bit 3
UTD7IC.ILVL_2     2   Interrupt Priority Level - bit 2
UTD7IC.GLVL_1     1   Group Level - bit 1
UTD7IC.GLVL_0     0   Group Level - bit 0
URXRIC           0xF16A   UDC RXRR  Interrupt Control Register
URXRIC.URXRIR     7   Interrupt Request Flag          
URXRIC.URXRIE     6   Interrupt Enable Control Bit    
URXRIC.ILVL_5     5   Interrupt Priority Level - bit 5
URXRIC.ILVL_4     4   Interrupt Priority Level - bit 4
URXRIC.ILVL_3     3   Interrupt Priority Level - bit 3
URXRIC.ILVL_2     2   Interrupt Priority Level - bit 2
URXRIC.GLVL_1     1   Group Level - bit 1             
URXRIC.GLVL_0     0   Group Level - bit 0             
UTXRIC           0xF16C   UDC TXWR  Interrupt Control Register
UTXRIC.UTXRIR     7   Interrupt Request Flag          
UTXRIC.UTXRIE     6   Interrupt Enable Control Bit    
UTXRIC.ILVL_5     5   Interrupt Priority Level - bit 5
UTXRIC.ILVL_4     4   Interrupt Priority Level - bit 4
UTXRIC.ILVL_3     3   Interrupt Priority Level - bit 3
UTXRIC.ILVL_2     2   Interrupt Priority Level - bit 2
UTXRIC.GLVL_1     1   Group Level - bit 1             
UTXRIC.GLVL_0     0   Group Level - bit 0
UCFGVIC          0xF16E   UDC Config Val Interrupt Control Register
UCFGVIC.UCFGVIR   7   Interrupt Request Flag          
UCFGVIC.UCFGVIE   6   Interrupt Enable Control Bit    
UCFGVIC.ILVL_5    5   Interrupt Priority Level - bit 5
UCFGVIC.ILVL_4    4   Interrupt Priority Level - bit 4
UCFGVIC.ILVL_3    3   Interrupt Priority Level - bit 3
UCFGVIC.ILVL_2    2   Interrupt Priority Level - bit 2
UCFGVIC.GLVL_1    1   Group Level - bit 1             
UCFGVIC.GLVL_0    0   Group Level - bit 0
USOFIC           0xF170   UDC Start of Frame Interrupt Control Register
USOFIC.USOFIR     7   Interrupt Request Flag          
USOFIC.USOFIE     6   Interrupt Enable Control Bit    
USOFIC.ILVL_5     5   Interrupt Priority Level - bit 5
USOFIC.ILVL_4     4   Interrupt Priority Level - bit 4
USOFIC.ILVL_3     3   Interrupt Priority Level - bit 3
USOFIC.ILVL_2     2   Interrupt Priority Level - bit 2
USOFIC.GLVL_1     1   Group Level - bit 1             
USOFIC.GLVL_0     0   Group Level - bit 0
USSOIC           0xF172   UDC Suspend  off Interrupt Control Register
USSOIC.USSOIR     7   Interrupt Request Flag          
USSOIC.USSOIE     6   Interrupt Enable Control Bit    
USSOIC.ILVL_5     5   Interrupt Priority Level - bit 5
USSOIC.ILVL_4     4   Interrupt Priority Level - bit 4
USSOIC.ILVL_3     3   Interrupt Priority Level - bit 3
USSOIC.ILVL_2     2   Interrupt Priority Level - bit 2
USSOIC.GLVL_1     1   Group Level - bit 1             
USSOIC.GLVL_0     0   Group Level - bit 0
USSIC            0xF174   UDC Suspend  Interrupt Control Register
USSIC.USSIR       7   Interrupt Request Flag
USSIC.USSIE       6   Interrupt Enable Control Bit
USSIC.ILVL_5      5   Interrupt Priority Level - bit 5
USSIC.ILVL_4      4   Interrupt Priority Level - bit 4
USSIC.ILVL_3      3   Interrupt Priority Level - bit 3
USSIC.ILVL_2      2   Interrupt Priority Level - bit 2
USSIC.GLVL_1      1   Group Level - bit 1
USSIC.GLVL_0      0   Group Level - bit 0
ULCDIC           0xF176   UDC Load Config Done  Interrupt Control Register
ULCDIC.ULCDIR     7   Interrupt Request Flag          
ULCDIC.ULCDIE     6   Interrupt Enable Control Bit    
ULCDIC.ILVL_5     5   Interrupt Priority Level - bit 5
ULCDIC.ILVL_4     4   Interrupt Priority Level - bit 4
ULCDIC.ILVL_3     3   Interrupt Priority Level - bit 3
ULCDIC.ILVL_2     2   Interrupt Priority Level - bit 2
ULCDIC.GLVL_1     1   Group Level - bit 1             
ULCDIC.GLVL_0     0   Group Level - bit 0
USETIC           0xF178   UDC SETUP Interrupt Control Register
USETIC.USETIR     7   Interrupt Request Flag          
USETIC.USETIE     6   Interrupt Enable Control Bit    
USETIC.ILVL_5     5   Interrupt Priority Level - bit 5
USETIC.ILVL_4     4   Interrupt Priority Level - bit 4
USETIC.ILVL_3     3   Interrupt Priority Level - bit 3
USETIC.ILVL_2     2   Interrupt Priority Level - bit 2
USETIC.GLVL_1     1   Group Level - bit 1             
USETIC.GLVL_0     0   Group Level - bit 0
URD0IC           0xF17A   UDC RX Done0  Interrupt Control Register
URD0IC.URD0IR     7   Interrupt Request Flag          
URD0IC.URD0IE     6   Interrupt Enable Control Bit    
URD0IC.ILVL_5     5   Interrupt Priority Level - bit 5
URD0IC.ILVL_4     4   Interrupt Priority Level - bit 4
URD0IC.ILVL_3     3   Interrupt Priority Level - bit 3
URD0IC.ILVL_2     2   Interrupt Priority Level - bit 2
URD0IC.GLVL_1     1   Group Level - bit 1             
URD0IC.GLVL_0     0   Group Level - bit 0
EPECIC           0xF17C   EPEC Interrupt
IOMC0TIC         0xF17E   IOM-2 Channel0 TX Interrupt Control Register
IOMC0TIC.IOMC0TIR 7   Interrupt Request Flag          
IOMC0TIC.IOMC0TIE 6   Interrupt Enable Control Bit    
IOMC0TIC.ILVL_5   5   Interrupt Priority Level - bit 5
IOMC0TIC.ILVL_4   4   Interrupt Priority Level - bit 4
IOMC0TIC.ILVL_3   3   Interrupt Priority Level - bit 3
IOMC0TIC.ILVL_2   2   Interrupt Priority Level - bit 2
IOMC0TIC.GLVL_1   1   Group Level - bit 1             
IOMC0TIC.GLVL_0   0   Group Level - bit 0             
PECCLIC          0xF180   PEC Channel Link Interrupt Control Register
PECCLIC.PECCLIR   7   Interrupt Request Flag          
PECCLIC.PECCLIE   6   Interrupt Enable Control Bit    
PECCLIC.ILVL_5    5   Interrupt Priority Level - bit 5
PECCLIC.ILVL_4    4   Interrupt Priority Level - bit 4
PECCLIC.ILVL_3    3   Interrupt Priority Level - bit 3
PECCLIC.ILVL_2    2   Interrupt Priority Level - bit 2
PECCLIC.GLVL_1    1   Group Level - bit 1             
PECCLIC.GLVL_0    0   Group Level - bit 0
IOMC0RIC         0xF182   IOM-2 Channel0 RX Interrupt Control Register
IOMC0RIC.IOMC0RIR 7   Interrupt Request Flag          
IOMC0RIC.IOMC0RIE 6   Interrupt Enable Control Bit    
IOMC0RIC.ILVL_5   5   Interrupt Priority Level - bit 5
IOMC0RIC.ILVL_4   4   Interrupt Priority Level - bit 4
IOMC0RIC.ILVL_3   3   Interrupt Priority Level - bit 3
IOMC0RIC.ILVL_2   2   Interrupt Priority Level - bit 2
IOMC0RIC.GLVL_1   1   Group Level - bit 1             
IOMC0RIC.GLVL_0   0   Group Level - bit 0             
RTC_INTIC        0xF184   RTC_INT Sub Node Interrupt Register
RTC_INTIC.RTC_INTIR 7 Interrupt Request Flag          
RTC_INTIC.RTC_INTIE 6 Interrupt Enable Control Bit    
RTC_INTIC.ILVL_5  5   Interrupt Priority Level - bit 5
RTC_INTIC.ILVL_4  4   Interrupt Priority Level - bit 4
RTC_INTIC.ILVL_3  3   Interrupt Priority Level - bit 3
RTC_INTIC.ILVL_2  2   Interrupt Priority Level - bit 2
RTC_INTIC.GLVL_1  1   Group Level - bit 1
RTC_INTIC.GLVL_0  0   Group Level - bit 0
XP0IC            0xF186   X-Bus Peripheral 0 UDC TXWR Interrupt Control Register
XP0IC.XP0IR       7   Interrupt Request Flag
XP0IC.XP0IE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
XP0IC.ILVL_5      5   Interrupt Priority Level - bit 5
XP0IC.ILVL_4      4   Interrupt Priority Level - bit 4
XP0IC.ILVL_3      3   Interrupt Priority Level - bit 3
XP0IC.ILVL_2      2   Interrupt Priority Level - bit 2
XP0IC.GLVL_1      1   Group Level - bit 1
XP0IC.GLVL_0      0   Group Level - bit 0
IOMC1TIC         0xF18A   IOM-2 Channel1 TX Interrupt Control Register
IOMC1TIC.IOMC1TIR 7   Interrupt Request Flag
IOMC1TIC.IOMC1TIE 6   Interrupt Enable Control Bit
IOMC1TIC.ILVL_5   5   Interrupt Priority Level - bit 5
IOMC1TIC.ILVL_4   4   Interrupt Priority Level - bit 4
IOMC1TIC.ILVL_3   3   Interrupt Priority Level - bit 3
IOMC1TIC.ILVL_2   2   Interrupt Priority Level - bit 2
IOMC1TIC.GLVL_1   1   Group Level - bit 1
IOMC1TIC.GLVL_0   0   Group Level - bit 0
ABENDIC          0xF18C   ASC Autobaud End Interrupt Control Register
ABENDIC.ABENDIR   7   Interrupt Request Flag
ABENDIC.ABENDIE   6   Interrupt Enable Control Bit (individually enables/disables a specific source)
ABENDIC.ILVL_5    5   Interrupt Priority Level - bit 5
ABENDIC.ILVL_4    4   Interrupt Priority Level - bit 4
ABENDIC.ILVL_3    3   Interrupt Priority Level - bit 3
ABENDIC.ILVL_2    2   Interrupt Priority Level - bit 2
ABENDIC.GLVL_1    1   Group Level - bit 1
ABENDIC.GLVL_0    0   Group Level - bit 0
XP1IC            0xF18E   X-Bus Peripheral 1 Register
IOMC1RIC         0xF192   IOM-2 Channel1 RX Interrupt Control Register
IOMC1RIC.IOMC1RIR 7   Interrupt Request Flag          
IOMC1RIC.IOMC1RIE 6   Interrupt Enable Control Bit    
IOMC1RIC.ILVL_5   5   Interrupt Priority Level - bit 5
IOMC1RIC.ILVL_4   4   Interrupt Priority Level - bit 4
IOMC1RIC.ILVL_3   3   Interrupt Priority Level - bit 3
IOMC1RIC.ILVL_2   2   Interrupt Priority Level - bit 2
IOMC1RIC.GLVL_1   1   Group Level - bit 1             
IOMC1RIC.GLVL_0   0   Group Level - bit 0             
ABSTIC           0xF194   ASC Autobaud Start Interrupt Control Register
ABSTIC.ABSTIR     7   Interrupt Request Flag
ABSTIC.ABSTIE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
ABSTIC.ILVL_5     5   Interrupt Priority Level - bit 5
ABSTIC.ILVL_4     4   Interrupt Priority Level - bit 4
ABSTIC.ILVL_3     3   Interrupt Priority Level - bit 3
ABSTIC.ILVL_2     2   Interrupt Priority Level - bit 2
ABSTIC.GLVL_1     1   Group Level - bit 1
ABSTIC.GLVL_0     0   Group Level - bit 0
XP2IC            0xF196   X-Bus Peripheral 2 IOM-2 IO Interrupt Controol Register
XP2IC.XP2IR       7   Interrupt Request Flag
XP2IC.XP2IE       6   Interrupt Enable Control Bit
XP2IC.ILVL_5      5   Interrupt Priority Level - bit 5
XP2IC.ILVL_4      4   Interrupt Priority Level - bit 4
XP2IC.ILVL_3      3   Interrupt Priority Level - bit 3
XP2IC.ILVL_2      2   Interrupt Priority Level - bit 2
XP2IC.GLVL_1      1   Group Level - bit 1
XP2IC.GLVL_0      0   Group Level - bit 0
RES6IC           0xF19A   reserved
S0TBIC           0xF19C   Serial Channel 0 Transmit Buffer IC Register
XP3IC            0xF19E   X-Bus Peripheral 3 PLL/RTC
EXICON           0xF1C0   External Interrupt Control Register
EXICON.EXI7ES_15  15  External Interrupt 15 Edge Selection Field - bit 15
EXICON.EXI7ES_14  14  External Interrupt 14 Edge Selection Field - bit 14
EXICON.EXI6ES_13  13  External Interrupt 13 Edge Selection Field - bit 13
EXICON.EXI6ES_12  12  External Interrupt 12 Edge Selection Field - bit 12
EXICON.EXI5ES_11  11  External Interrupt 11 Edge Selection Field - bit 11
EXICON.EXI5ES_10  10  External Interrupt 10 Edge Selection Field - bit 10
EXICON.EXI4ES_9   9   External Interrupt 9 Edge Selection Field - bit 9 
EXICON.EXI4ES_8   8   External Interrupt 8 Edge Selection Field - bit 8 
EXICON.EXI3ES_7   7   External Interrupt 7 Edge Selection Field - bit 7 
EXICON.EXI3ES_6   6   External Interrupt 6 Edge Selection Field - bit 6 
EXICON.EXI2ES_5   5   External Interrupt 5 Edge Selection Field - bit 5 
EXICON.EXI2ES_4   4   External Interrupt 4 Edge Selection Field - bit 4 
EXICON.EXI1ES_3   3   External Interrupt 3 Edge Selection Field - bit 3 
EXICON.EXI1ES_2   2   External Interrupt 2 Edge Selection Field - bit 2 
EXICON.EXI0ES_1   1   External Interrupt 1 Edge Selection Field - bit 1 
EXICON.EXI0ES_0   0   External Interrupt 0 Edge Selection Field - bit 0 
ODP2             0xF1C2   Port 2 Open Drain Control Register
ODP2.ODP2_7       7   Port 2 Open Drain control register bit 7
ODP2.ODP2_6       6   Port 2 Open Drain control register bit 6
ODP2.ODP2_5       5   Port 2 Open Drain control register bit 5
ODP2.ODP2_4       4   Port 2 Open Drain control register bit 4
ODP2.ODP2_3       3   Port 2 Open Drain control register bit 3
ODP2.ODP2_2       2   Port 2 Open Drain control register bit 2
ODP2.ODP2_1       1   Port 2 Open Drain control register bit 1
ODP2.ODP2_0       0   Port 2 Open Drain control register bit 0
ODP3             0xF1C6   Port 3 Open
ODP3.ODP3_15      15  Port 3 Open Drain control register bit 15
ODP3.ODP3_13      13  Port 3 Open Drain control register bit 13
ODP3.ODP3_11      11  Port 3 Open Drain control register bit 11
ODP3.ODP3_10      10  Port 3 Open Drain control register bit 10
ODP3.ODP3_9       9   Port 3 Open Drain control register bit 9 
ODP3.ODP3_8       8   Port 3 Open Drain control register bit 8 
ODP3.ODP3_6       6   Port 3 Open Drain control register bit 6 
ODP3.ODP3_5       5   Port 3 Open Drain control register bit 5 
ODP3.ODP3_3       3   Port 3 Open Drain control register bit 3 
RTCISNC          0xF1C8   RTC Interrupt Sub Node Control Register
RTCISNC.RTC3IR    9   RTC3 Interrupt Request Flag (bit protected)
RTCISNC.RTC3IE    8   RTC3 Interrupt Enable Control Bit
RTCISNC.RTC2IR    7   RTC2 Interrupt Request Flag (bit protected)
RTCISNC.RTC2IE    6   RTC2 Interrupt Enable Control Bit          
RTCISNC.RTC1IR    5   RTC1 Interrupt Request Flag (bit protected)
RTCISNC.RTC1IE    4   RTC1 Interrupt Enable Control Bit          
RTCISNC.RTC0IR    3   RTC0 Interrupt Request Flag (bit protected)
RTCISNC.RTC0IE    2   RTC0 Interrupt Enable Control Bit          
RTCISNC.T14IR     1   T14 Overflow Interrupt Request Flag (bit protected)
RTCISNC.T14IE     0   T14 Overflow Interrupt Enable Control Bit
ODP4             0xF1CA   Port 4 Open Drain Control Register
ODP4.ODP4_6       6   Port 4 Open Drain control register bit 6
ODP4.ODP4_5       5   Port 4 Open Drain control register bit 5
ODP4.ODP4_4       4   Port 4 Open Drain control register bit 4 
ODP4.ODP4_3       3   Port 4 Open Drain control register bit 3 
ODP4.ODP4_2       2   Port 4 Open Drain control register bit 2 
ODP4.ODP4_1       1   Port 4 Open Drain control register bit 1 
ODP4.ODP4_0       0   Port 4 Open Drain control register bit 0 
RTCCON           0xF1CC   RTC Control Register
RTCCON.ACCPOS     15  RTC register access possible
RTCCON.T14INC     3   Increment T14 Timer Value
RTCCON.T14DEC     2   Decrement T14 Timer Value
RTCCON.RTCPRE     1   RTC Input Source Prescaler enable
RTCCON.RTCR       0   RTC Run Bit
ODP6             0xF1CE   Port 6 Open Drain Control Register
ODP6.ODP6_7       7   Port 6 Open Drain control register bit 7
ODP6.ODP6_6       6   Port 6 Open Drain control register bit 6
ODP6.ODP6_5       5   Port 6 Open Drain control register bit 5
ODP6.ODP6_4       4   Port 6 Open Drain control register bit 
ODP6.ODP6_3       3   Port 6 Open Drain control register bit 3
ODP6.ODP6_2       2   Port 6 Open Drain control register bit 2
ODP6.ODP6_1       1   Port 6 Open Drain control register bit 1
ODP6.ODP6_0       0   Port 6 Open Drain control register bit 0
SYSCON2          0xF1D0   System Configuration Register 2/Clock Control
SYSCON2.CLKLOCK   15  Clock Signal Status Bit
SYSCON2.CLKREL_14 14  Reload Counter Value for Slowdown Divider - 14
SYSCON2.CLKREL_13 13  Reload Counter Value for Slowdown Divider - 13
SYSCON2.CLKREL_12 12  Reload Counter Value for Slowdown Divider - 12
SYSCON2.CLKREL_11 11  Reload Counter Value for Slowdown Divider - 11
SYSCON2.CLKREL_10 10  Reload Counter Value for Slowdown Divider - 10
SYSCON2.CLKCON_9  9   Clock State Control - bit 9
SYSCON2.CLKCON_8  8   Clock State Control - bit 8
SYSCON2.SCS       7   SDD Clock Source
SYSCON2.RCS       6   RTC Clock Source
SYSCON2.PDCON_5   5   Power Down Control - bit 5
SYSCON2.PDCON_4   4   Power Down Control - bit 4
ODP7             0xF1D2   Port 7 Open Drain Control Register
ODP7.ODP7_5       5   Port 6 Open Drain control register bit 5
ODP7.ODP7_4       4   Port 6 Open Drain control register bit 4
ODP7.ODP7_3       3   Port 6 Open Drain control register bit 3
ODP7.ODP7_2       2   Port 6 Open Drain control register bit 2
ODP7.ODP7_1       1   Port 6 Open Drain control register bit 1
ODP7.ODP7_0       0   Port 6 Open Drain control register bit 0
SYSCON3          0xF1D4   System Configuration Register 3/Periph. Managem.
SYSCON3.GRPDIS    15  Peripheral Group Disable Flag (PD-Bus and X-Bus Peripherals)
SYSCON3.PLLDIS    13  PLL Disable Flag
SYSCON3.USBTDIS_12 12 USB Transceiver Disable Flag ONLY IF BIT XPERCON.6 = '1'  - bit 12
SYSCON3.USBTDIS_11 11 USB Transceiver Disable Flag ONLY IF BIT XPERCON.6 = '1'  - bit 11
SYSCON3.PERDIS8   8   Peripheral Disable Flag 0 - 14 - bit 8
SYSCON3.PERDIS7   7   Peripheral Disable Flag 0 - 14 - bit 7
SYSCON3.PERDIS6   6   Peripheral Disable Flag 0 - 14 - bit 6
SYSCON3.PERDIS3   3   Peripheral Disable Flag 0 - 14 - bit 3
SYSCON3.PERDIS2   2   Peripheral Disable Flag 0 - 14 - bit 2
SYSCON3.PERDIS1   1   Peripheral Disable Flag 0 - 14 - bit 1
SYSCON3.PERDIS0   0   Peripheral Disable Flag 0 - 14 - bit 0
reserv_F1D6      0xF1D6   reserved - do not use
reserv_F1D8      0xF1D8   reserved - do not use
EXISEL           0xF1DA   External Interrupt Select Register
EXISEL.EXI6SS_13  13  Input from default pin. - bit 13
EXISEL.EXI6SS_12  12  Input from default pin. - bit 12
EXISEL.EXI5SS_11  11  Input from default pin. - bit 11
EXISEL.EXI5SS_10  10  Input from default pin. - bit 10
EXISEL.EXI4SS_9   9   Input from default pin. - bit 9 
EXISEL.EXI4SS_8   8   Input from default pin. - bit 8 
EXISEL.EXI3SS_7   7   Input from default pin. - bit 7 
EXISEL.EXI3SS_6   6   Input from default pin. - bit 6 
EXISEL.EXI2SS_5   5   Input from default pin. - bit 5 
EXISEL.EXI2SS_4   4   Input from default pin. - bit 4 
SYSCON1          0xF1DC   System Configuration Register 1/Sleep Mode
SYSCON1.SLEEPCON_1 1  SLEEP Mode Configuration - bit 1
SYSCON1.SLEEPCON_0 0  SLEEP Mode Configuration - bit 0
ISNC             0xF1DE   Interrupt Sub Node Control Register
ISNC.PLLIE        3   PLL Interrupt Enable Control Bit
ISNC.PLLIR        2   PLL Interrupt Request Flag
ISNC.RTCT14IE     1   T14 Overflow Interrupt Enable Control Bit
ISNC.RTCT14IR     0   T14 Overflow Interrupt Request Flag
DPP0             0xFE00   CPU Data Page Pointer 0 Register (10 bits)
DPP0.DPP0PN_9     9   Data Page Number of DPP0 - bit 9
DPP0.DPP0PN_8     8   Data Page Number of DPP0 - bit 8
DPP0.DPP0PN_7     7   Data Page Number of DPP0 - bit 7
DPP0.DPP0PN_6     6   Data Page Number of DPP0 - bit 6
DPP0.DPP0PN_5     5   Data Page Number of DPP0 - bit 5
DPP0.DPP0PN_4     4   Data Page Number of DPP0 - bit 4
DPP0.DPP0PN_3     3   Data Page Number of DPP0 - bit 3
DPP0.DPP0PN_2     2   Data Page Number of DPP0 - bit 2
DPP0.DPP0PN_1     1   Data Page Number of DPP0 - bit 1
DPP0.DPP0PN_0     0   Data Page Number of DPP0 - bit 0
DPP1             0xFE02   CPU Data Page Pointer 1 Register (10 bits)
DPP1.DPP1PN_9     9   Data Page Number of DPP1 - bit 9
DPP1.DPP1PN_8     8   Data Page Number of DPP1 - bit 8
DPP1.DPP1PN_7     7   Data Page Number of DPP1 - bit 7
DPP1.DPP1PN_6     6   Data Page Number of DPP1 - bit 6
DPP1.DPP1PN_5     5   Data Page Number of DPP1 - bit 5
DPP1.DPP1PN_4     4   Data Page Number of DPP1 - bit 4
DPP1.DPP1PN_3     3   Data Page Number of DPP1 - bit 3
DPP1.DPP1PN_2     2   Data Page Number of DPP1 - bit 2
DPP1.DPP1PN_1     1   Data Page Number of DPP1 - bit 1
DPP1.DPP1PN_0     0   Data Page Number of DPP1 - bit 0
DPP2             0xFE04   CPU Data Page Pointer 2 Register (10 bits)
DPP2.DPP2PN_9     9   Data Page Number of DPP2 - bit 9
DPP2.DPP2PN_8     8   Data Page Number of DPP2 - bit 8
DPP2.DPP2PN_7     7   Data Page Number of DPP2 - bit 7
DPP2.DPP2PN_6     6   Data Page Number of DPP2 - bit 6
DPP2.DPP2PN_5     5   Data Page Number of DPP2 - bit 5
DPP2.DPP2PN_4     4   Data Page Number of DPP2 - bit 4
DPP2.DPP2PN_3     3   Data Page Number of DPP2 - bit 3
DPP2.DPP2PN_2     2   Data Page Number of DPP2 - bit 2
DPP2.DPP2PN_1     1   Data Page Number of DPP2 - bit 1
DPP2.DPP2PN_0     0   Data Page Number of DPP2 - bit 0
DPP3             0xFE06   CPU Data Page Pointer 3 Register (10 bits)
DPP3.DPP3PN_9     9   Data Page Number of DPP3 - bit 9
DPP3.DPP3PN_8     8   Data Page Number of DPP3 - bit 8
DPP3.DPP3PN_7     7   Data Page Number of DPP3 - bit 7
DPP3.DPP3PN_6     6   Data Page Number of DPP3 - bit 6
DPP3.DPP3PN_5     5   Data Page Number of DPP3 - bit 5
DPP3.DPP3PN_4     4   Data Page Number of DPP3 - bit 4
DPP3.DPP3PN_3     3   Data Page Number of DPP3 - bit 3
DPP3.DPP3PN_2     2   Data Page Number of DPP3 - bit 2
DPP3.DPP3PN_1     1   Data Page Number of DPP3 - bit 1
DPP3.DPP3PN_0     0   Data Page Number of DPP3 - bit 0
CSP              0xFE08   CPU Code Segment Pointer Register (8 bits)
CSP.SEGNR_7       7   Segment Number - bit 7
CSP.SEGNR_6       6   Segment Number - bit 6
CSP.SEGNR_5       5   Segment Number - bit 5
CSP.SEGNR_4       4   Segment Number - bit 4
CSP.SEGNR_3       3   Segment Number - bit 3
CSP.SEGNR_2       2   Segment Number - bit 2
CSP.SEGNR_1       1   Segment Number - bit 1
CSP.SEGNR_0       0   Segment Number - bit 0
EMUCON           0xFE0A   Emulation Control Register2)
MDH              0xFE0C   CPU Multiply Divide Register - High Word
MDH.mdh_15        15
MDH.mdh_14        14
MDH.mdh_13        13
MDH.mdh_12        12
MDH.mdh_11        11
MDH.mdh_10        10
MDH.mdh_9         9 
MDH.mdh_8         8 
MDH.mdh_7         7 
MDH.mdh_6         6 
MDH.mdh_5         5 
MDH.mdh_4         4 
MDH.mdh_3         3 
MDH.mdh_2         2 
MDH.mdh_1         1 
MDH.mdh_0         0 
MDL              0xFE0E   CPU Multiply Divide Register - Low Word
MDL.MDL_15        15
MDL.MDL_14        14
MDL.MDL_13        13
MDL.MDL_12        12
MDL.MDL_11        11
MDL.MDL_10        10
MDL.MDL_9         9 
MDL.MDL_8         8 
MDL.MDL_7         7 
MDL.MDL_6         6 
MDL.MDL_5         5 
MDL.MDL_4         4 
MDL.MDL_3         3 
MDL.MDL_2         2 
MDL.MDL_1         1 
MDL.MDL_0         0 
CP               0xFE10   CPU Context Pointer Register
CP.cp_11          11  Modifiable portion of register CP - bit 11
CP.cp_10          10  Modifiable portion of register CP - bit 10
CP.cp_9           9   Modifiable portion of register CP - bit 9
CP.cp_8           8   Modifiable portion of register CP - bit 8
CP.cp_7           7   Modifiable portion of register CP - bit 7
CP.cp_6           6   Modifiable portion of register CP - bit 6
CP.cp_5           5   Modifiable portion of register CP - bit 5
CP.cp_4           4   Modifiable portion of register CP - bit 4
CP.cp_3           3   Modifiable portion of register CP - bit 3
CP.cp_2           2   Modifiable portion of register CP - bit 2
CP.cp_1           1   Modifiable portion of register CP - bit 1
SP               0xFE12   CPU System Stack Pointer Register
SP.sp_11          11  Modifiable portion of register SP - bit 11
SP.sp_10          10  Modifiable portion of register SP - bit 10
SP.sp_9           9   Modifiable portion of register SP - bit 9
SP.sp_8           8   Modifiable portion of register SP - bit 8
SP.sp_7           7   Modifiable portion of register SP - bit 7
SP.sp_6           6   Modifiable portion of register SP - bit 6
SP.sp_5           5   Modifiable portion of register SP - bit 5
SP.sp_4           4   Modifiable portion of register SP - bit 4
SP.sp_3           3   Modifiable portion of register SP - bit 3
SP.sp_2           2   Modifiable portion of register SP - bit 2
SP.sp_1           1   Modifiable portion of register SP - bit 1
STKOV            0xFE14   CPU Stack Overflow Pointer Register
STKOV.stkov_11    11  Modifiable portion of register STKOV - bit 11
STKOV.stkov_10    10  Modifiable portion of register STKOV - bit 10
STKOV.stkov_9     9   Modifiable portion of register STKOV - bit 9
STKOV.stkov_8     8   Modifiable portion of register STKOV - bit 8
STKOV.stkov_7     7   Modifiable portion of register STKOV - bit 7
STKOV.stkov_6     6   Modifiable portion of register STKOV - bit 6
STKOV.stkov_5     5   Modifiable portion of register STKOV - bit 5
STKOV.stkov_4     4   Modifiable portion of register STKOV - bit 4
STKOV.stkov_3     3   Modifiable portion of register STKOV - bit 3
STKOV.stkov_2     2   Modifiable portion of register STKOV - bit 2
STKOV.stkov_1     1   Modifiable portion of register STKOV - bit 1
STKUN            0xFE16   CPU Stack Underflow Pointer Register
STKUN.STKUN_11    11  Modifiable portion of register STKUN - bit 11
STKUN.STKUN_10    10  Modifiable portion of register STKUN - bit 10
STKUN.STKUN_9     9   Modifiable portion of register STKUN - bit 9
STKUN.STKUN_8     8   Modifiable portion of register STKUN - bit 8
STKUN.STKUN_7     7   Modifiable portion of register STKUN - bit 7
STKUN.STKUN_6     6   Modifiable portion of register STKUN - bit 6
STKUN.STKUN_5     5   Modifiable portion of register STKUN - bit 5
STKUN.STKUN_4     4   Modifiable portion of register STKUN - bit 4
STKUN.STKUN_3     3   Modifiable portion of register STKUN - bit 3
STKUN.STKUN_2     2   Modifiable portion of register STKUN - bit 2
STKUN.STKUN_1     1   Modifiable portion of register STKUN - bit 1
ADDRSEL1         0xFE18   Address Select Register 1
ADDRSEL1.RGSAD15  15  Range Start Address bit 15
ADDRSEL1.RGSAD14  14  Range Start Address bit 14
ADDRSEL1.RGSAD13  13  Range Start Address bit 13
ADDRSEL1.RGSAD12  12  Range Start Address bit 12
ADDRSEL1.RGSAD11  11  Range Start Address bit 11
ADDRSEL1.RGSAD10  10  Range Start Address bit 10
ADDRSEL1.RGSAD9   9   Range Start Address bit 9 
ADDRSEL1.RGSAD8   8   Range Start Address bit 8 
ADDRSEL1.RGSAD7   7   Range Start Address bit 7 
ADDRSEL1.RGSAD6   6   Range Start Address bit 6 
ADDRSEL1.RGSAD5   5   Range Start Address bit 5 
ADDRSEL1.RGSAD4   4   Range Start Address bit 4 
ADDRSEL1.RGSZ3    3   Range Size Selection bit 3
ADDRSEL1.RGSZ2    2   Range Size Selection bit 2
ADDRSEL1.RGSZ1    1   Range Size Selection bit 1
ADDRSEL1.RGSZ0    0   Range Size Selection bit 0
ADDRSEL2         0xFE1A   Address Select Register 2
ADDRSEL2.RGSAD15  15  Range Start Address bit 15
ADDRSEL2.RGSAD14  14  Range Start Address bit 14
ADDRSEL2.RGSAD13  13  Range Start Address bit 13
ADDRSEL2.RGSAD12  12  Range Start Address bit 12
ADDRSEL2.RGSAD11  11  Range Start Address bit 11
ADDRSEL2.RGSAD10  10  Range Start Address bit 10
ADDRSEL2.RGSAD9   9   Range Start Address bit 9 
ADDRSEL2.RGSAD8   8   Range Start Address bit 8 
ADDRSEL2.RGSAD7   7   Range Start Address bit 7 
ADDRSEL2.RGSAD6   6   Range Start Address bit 6 
ADDRSEL2.RGSAD5   5   Range Start Address bit 5 
ADDRSEL2.RGSAD4   4   Range Start Address bit 4 
ADDRSEL2.RGSZ3    3   Range Size Selection bit 3
ADDRSEL2.RGSZ2    2   Range Size Selection bit 2
ADDRSEL2.RGSZ1    1   Range Size Selection bit 1
ADDRSEL2.RGSZ0    0   Range Size Selection bit 0
ADDRSEL3         0xFE1C   Address Select Register 3
ADDRSEL3.RGSAD15  15  Range Start Address bit 15
ADDRSEL3.RGSAD14  14  Range Start Address bit 14
ADDRSEL3.RGSAD13  13  Range Start Address bit 13
ADDRSEL3.RGSAD12  12  Range Start Address bit 12
ADDRSEL3.RGSAD11  11  Range Start Address bit 11
ADDRSEL3.RGSAD10  10  Range Start Address bit 10
ADDRSEL3.RGSAD9   9   Range Start Address bit 9 
ADDRSEL3.RGSAD8   8   Range Start Address bit 8 
ADDRSEL3.RGSAD7   7   Range Start Address bit 7 
ADDRSEL3.RGSAD6   6   Range Start Address bit 6 
ADDRSEL3.RGSAD5   5   Range Start Address bit 5 
ADDRSEL3.RGSAD4   4   Range Start Address bit 4 
ADDRSEL3.RGSZ3    3   Range Size Selection bit 3
ADDRSEL3.RGSZ2    2   Range Size Selection bit 2
ADDRSEL3.RGSZ1    1   Range Size Selection bit 1
ADDRSEL3.RGSZ0    0   Range Size Selection bit 0
ADDRSEL4         0xFE1E   Address Select Register 4
ADDRSEL4.RGSAD15  15  Range Start Address bit 15
ADDRSEL4.RGSAD14  14  Range Start Address bit 14
ADDRSEL4.RGSAD13  13  Range Start Address bit 13
ADDRSEL4.RGSAD12  12  Range Start Address bit 12
ADDRSEL4.RGSAD11  11  Range Start Address bit 11
ADDRSEL4.RGSAD10  10  Range Start Address bit 10
ADDRSEL4.RGSAD9   9   Range Start Address bit 9 
ADDRSEL4.RGSAD8   8   Range Start Address bit 8 
ADDRSEL4.RGSAD7   7   Range Start Address bit 7 
ADDRSEL4.RGSAD6   6   Range Start Address bit 6 
ADDRSEL4.RGSAD5   5   Range Start Address bit 5 
ADDRSEL4.RGSAD4   4   Range Start Address bit 4 
ADDRSEL4.RGSZ3    3   Range Size Selection bit 3
ADDRSEL4.RGSZ2    2   Range Size Selection bit 2
ADDRSEL4.RGSZ1    1   Range Size Selection bit 1
ADDRSEL4.RGSZ0    0   Range Size Selection bit 0
ODP0H            0xFE22   Port 0 Open Drain Control Register High
ODP0H.ODP0H7      7   Port0H Open Drain control register bit 7
ODP0H.ODP0H6      6   Port0H Open Drain control register bit 6
ODP0H.ODP0H5      5   Port0H Open Drain control register bit 5
ODP0H.ODP0H4      4   Port0H Open Drain control register bit 4
ODP0H.ODP0H3      3   Port0H Open Drain control register bit 3
ODP0H.ODP0H2      2   Port0H Open Drain control register bit 2
ODP0H.ODP0H1      1   Port0H Open Drain control register bit 1
ODP0H.ODP0H0      0   Port0H Open Drain control register bit 0
ODP1L            0xFE24   Port 1 Open Drain Control Register Low
ODP1L.ODP1L7      7   Port1L Open Drain control register bit 7
ODP1L.ODP1L6      6   Port1L Open Drain control register bit 6
ODP1L.ODP1L5      5   Port1L Open Drain control register bit 5
ODP1L.ODP1L4      4   Port1L Open Drain control register bit 4
ODP1L.ODP1L3      3   Port1L Open Drain control register bit 3
ODP1L.ODP1L2      2   Port1L Open Drain control register bit 2
ODP1L.ODP1L1      1   Port1L Open Drain control register bit 1
ODP1L.ODP1L0      0   Port1L Open Drain control register bit 0
ODP1H            0xFE26   Port 1 Open Drain Control Register High
ODP1H.ODP1H7      7   Port1H Open Drain control register bit 7
ODP1H.ODP1H6      6   Port1H Open Drain control register bit 6
ODP1H.ODP1H5      5   Port1H Open Drain control register bit 5
ODP1H.ODP1H4      4   Port1H Open Drain control register bit 4
ODP1H.ODP1H3      3   Port1H Open Drain control register bit 3
ODP1H.ODP1H2      2   Port1H Open Drain control register bit 2
ODP1H.ODP1H1      1   Port1H Open Drain control register bit 1
ODP1H.ODP1H0      0   Port1H Open Drain control register bit 0
T2               0xFE40   GPT1 Timer 2 Register
T3               0xFE42   GPT1 Timer 3 Register
T4               0xFE44   GPT1 Timer 4 Register
T5               0xFE46   GPT2 Time
T6               0xFE48   GPT2 Timer 6 Register
CAPREL           0xFE4A   GPT1/2 Capture / Reload Register
GPTCLC           0xFE4C   GPT1/2 Clock Control Register
GPTCLC.EXDISR     3   External Disable Request
GPTCLC.SUSPEN     2   Peripheral Suspend Enable Bit for OCDS
GPTCLC.GPTDISS    1   GPT Disable Status Bit
GPTCLC.GPTDISR    0   GPT Disable Request Bit
P0LPUDSEL        0xFE60   Port 0 Low Pull-Up/Down Select Register
P0LPUDSEL.P0LPUDSEL7 7 Pulldown/Pullup Selection - bit 7
P0LPUDSEL.P0LPUDSEL6 6 Pulldown/Pullup Selection - bit 6
P0LPUDSEL.P0LPUDSEL5 5 Pulldown/Pullup Selection - bit 5
P0LPUDSEL.P0LPUDSEL4 4 Pulldown/Pullup Selection - bit 4
P0LPUDSEL.P0LPUDSEL3 3 Pulldown/Pullup Selection - bit 3
P0LPUDSEL.P0LPUDSEL2 2 Pulldown/Pullup Selection - bit 2
P0LPUDSEL.P0LPUDSEL1 1 Pulldown/Pullup Selection - bit 1
P0LPUDSEL.P0LPUDSEL0 0 Pulldown/Pullup Selection - bit 0
P0HPUDSEL        0xFE62   Port 0 High Pull-Up/Down Select Register
P0HPUDSEL.P0HPUDSEL7 7 Pulldown/Pullup Selection - bit 7
P0HPUDSEL.P0HPUDSEL6 6 Pulldown/Pullup Selection - bit 6
P0HPUDSEL.P0HPUDSEL5 5 Pulldown/Pullup Selection - bit 5
P0HPUDSEL.P0HPUDSEL4 4 Pulldown/Pullup Selection - bit 4
P0HPUDSEL.P0HPUDSEL3 3 Pulldown/Pullup Selection - bit 3
P0HPUDSEL.P0HPUDSEL2 2 Pulldown/Pullup Selection - bit 2
P0HPUDSEL.P0HPUDSEL1 1 Pulldown/Pullup Selection - bit 1
P0HPUDSEL.P0HPUDSEL0 0 Pulldown/Pullup Selection - bit 0
P0LPUDEN         0xFE64   Port 0 Low Pull Switch On/Off Register
P0LPUDEN.P0LPUDEN7 7 Pulldown/Pullup Enable - bit 7
P0LPUDEN.P0LPUDEN6 6 Pulldown/Pullup Enable - bit 6
P0LPUDEN.P0LPUDEN5 5 Pulldown/Pullup Enable - bit 5
P0LPUDEN.P0LPUDEN4 4 Pulldown/Pullup Enable - bit 4
P0LPUDEN.P0LPUDEN3 3 Pulldown/Pullup Enable - bit 3
P0LPUDEN.P0LPUDEN2 2 Pulldown/Pullup Enable - bit 2
P0LPUDEN.P0LPUDEN1 1 Pulldown/Pullup Enable - bit 1
P0LPUDEN.P0LPUDEN0 0 Pulldown/Pullup Enable - bit 0
P0HPUDEN         0xFE66   Port 0 High Pull Switch On/Off Register
P0HPUDEN.P0HPUDEN7 7 Pulldown/Pullup Enable - bit 7
P0HPUDEN.P0HPUDEN6 6 Pulldown/Pullup Enable - bit 6
P0HPUDEN.P0HPUDEN5 5 Pulldown/Pullup Enable - bit 5
P0HPUDEN.P0HPUDEN4 4 Pulldown/Pullup Enable - bit 4
P0HPUDEN.P0HPUDEN3 3 Pulldown/Pullup Enable - bit 3
P0HPUDEN.P0HPUDEN2 2 Pulldown/Pullup Enable - bit 2
P0HPUDEN.P0HPUDEN1 1 Pulldown/Pullup Enable - bit 1
P0HPUDEN.P0HPUDEN0 0 Pulldown/Pullup Enable - bit 0
P0LPHEN          0xFE68   Port 0 Low Pin Hold Enable Register
P0LPHEN.P0LPHEN7  7   Output Driver Enable in Power Down Mode - bit 7
P0LPHEN.P0LPHEN6  6   Output Driver Enable in Power Down Mode - bit 6
P0LPHEN.P0LPHEN5  5   Output Driver Enable in Power Down Mode - bit 5
P0LPHEN.P0LPHEN4  4   Output Driver Enable in Power Down Mode - bit 4
P0LPHEN.P0LPHEN3  3   Output Driver Enable in Power Down Mode - bit 3
P0LPHEN.P0LPHEN2  2   Output Driver Enable in Power Down Mode - bit 2
P0LPHEN.P0LPHEN1  1   Output Driver Enable in Power Down Mode - bit 1
P0LPHEN.P0LPHEN0  0   Output Driver Enable in Power Down Mode - bit 0
P0HPHEN          0xFE6A   Port 0 High Pin Hold Enable Register
P0HPHEN.P0HPHEN7  7   Output Driver Enable in Power Down Mode - bit 7
P0HPHEN.P0HPHEN6  6   Output Driver Enable in Power Down Mode - bit 6
P0HPHEN.P0HPHEN5  5   Output Driver Enable in Power Down Mode - bit 5
P0HPHEN.P0HPHEN4  4   Output Driver Enable in Power Down Mode - bit 4
P0HPHEN.P0HPHEN3  3   Output Driver Enable in Power Down Mode - bit 3
P0HPHEN.P0HPHEN2  2   Output Driver Enable in Power Down Mode - bit 2
P0HPHEN.P0HPHEN1  1   Output Driver Enable in Power Down Mode - bit 1
P0HPHEN.P0HPHEN0  0   Output Driver Enable in Power Down Mode - bit 0
P1LPUDSEL        0xFE6C   Port 1 Low Pull-Up/Down Select Register
P1LPUDSEL.P1LPUDSEL7 7 Pulldown/Pullup Selection - bit 7
P1LPUDSEL.P1LPUDSEL6 6 Pulldown/Pullup Selection - bit 6
P1LPUDSEL.P1LPUDSEL5 5 Pulldown/Pullup Selection - bit 5
P1LPUDSEL.P1LPUDSEL4 4 Pulldown/Pullup Selection - bit 4
P1LPUDSEL.P1LPUDSEL3 3 Pulldown/Pullup Selection - bit 3
P1LPUDSEL.P1LPUDSEL2 2 Pulldown/Pullup Selection - bit 2
P1LPUDSEL.P1LPUDSEL1 1 Pulldown/Pullup Selection - bit 1
P1LPUDSEL.P1LPUDSEL0 0 Pulldown/Pullup Selection - bit 0
P1HPUDSEL        0xFE6E   Port 1 High Pull-Up/Down Select Register
P1HPUDSEL.P1HPUDSEL7 7 Pulldown/Pullup Selection - bit 7
P1HPUDSEL.P1HPUDSEL6 6 Pulldown/Pullup Selection - bit 6
P1HPUDSEL.P1HPUDSEL5 5 Pulldown/Pullup Selection - bit 5
P1HPUDSEL.P1HPUDSEL4 4 Pulldown/Pullup Selection - bit 4
P1HPUDSEL.P1HPUDSEL3 3 Pulldown/Pullup Selection - bit 3
P1HPUDSEL.P1HPUDSEL2 2 Pulldown/Pullup Selection - bit 2
P1HPUDSEL.P1HPUDSEL1 1 Pulldown/Pullup Selection - bit 1
P1HPUDSEL.P1HPUDSEL0 0 Pulldown/Pullup Selection - bit 0
P1LPUDEN         0xFE70   Port 1 Low Pull Switch On/Off Register
P1LPUDEN.P1LPUDEN7 7 Pulldown/Pullup Enable - bit 7
P1LPUDEN.P1LPUDEN6 6 Pulldown/Pullup Enable - bit 6
P1LPUDEN.P1LPUDEN5 5 Pulldown/Pullup Enable - bit 5
P1LPUDEN.P1LPUDEN4 4 Pulldown/Pullup Enable - bit 4
P1LPUDEN.P1LPUDEN3 3 Pulldown/Pullup Enable - bit 3
P1LPUDEN.P1LPUDEN2 2 Pulldown/Pullup Enable - bit 2
P1LPUDEN.P1LPUDEN1 1 Pulldown/Pullup Enable - bit 1
P1LPUDEN.P1LPUDEN0 0 Pulldown/Pullup Enable - bit 0
P1HPUDEN         0xFE72   Port 1 High Pull Switch On/Off Register
P1HPUDEN.P1HPUDEN7 7 Pulldown/Pullup Enable - bit 7
P1HPUDEN.P1HPUDEN6 6 Pulldown/Pullup Enable - bit 6
P1HPUDEN.P1HPUDEN5 5 Pulldown/Pullup Enable - bit 5
P1HPUDEN.P1HPUDEN4 4 Pulldown/Pullup Enable - bit 4
P1HPUDEN.P1HPUDEN3 3 Pulldown/Pullup Enable - bit 3
P1HPUDEN.P1HPUDEN2 2 Pulldown/Pullup Enable - bit 2
P1HPUDEN.P1HPUDEN1 1 Pulldown/Pullup Enable - bit 1
P1HPUDEN.P1HPUDEN0 0 Pulldown/Pullup Enable - bit 0
P1LPHEN          0xFE74   Port 1 Low Pin Hold Enable Register
P1LPHEN.P1LPHEN7  7   Output Driver Enable in Power Down Mode - bit 7
P1LPHEN.P1LPHEN6  6   Output Driver Enable in Power Down Mode - bit 6
P1LPHEN.P1LPHEN5  5   Output Driver Enable in Power Down Mode - bit 5
P1LPHEN.P1LPHEN4  4   Output Driver Enable in Power Down Mode - bit 4
P1LPHEN.P1LPHEN3  3   Output Driver Enable in Power Down Mode - bit 3
P1LPHEN.P1LPHEN2  2   Output Driver Enable in Power Down Mode - bit 2
P1LPHEN.P1LPHEN1  1   Output Driver Enable in Power Down Mode - bit 1
P1LPHEN.P1LPHEN0  0   Output Driver Enable in Power Down Mode - bit 0
P1HPHEN          0xFE76   Port 1 High Pin Hold Enable Register
P1HPHEN.P1HPHEN7  7   Output Driver Enable in Power Down Mode - bit 7
P1HPHEN.P1HPHEN6  6   Output Driver Enable in Power Down Mode - bit 6
P1HPHEN.P1HPHEN5  5   Output Driver Enable in Power Down Mode - bit 5
P1HPHEN.P1HPHEN4  4   Output Driver Enable in Power Down Mode - bit 4
P1HPHEN.P1HPHEN3  3   Output Driver Enable in Power Down Mode - bit 3
P1HPHEN.P1HPHEN2  2   Output Driver Enable in Power Down Mode - bit 2
P1HPHEN.P1HPHEN1  1   Output Driver Enable in Power Down Mode - bit 1
P1HPHEN.P1HPHEN0  0   Output Driver Enable in Power Down Mode - bit 0
P2PUDSEL         0xFE78   Port 2 Pull-Up/Down Select Register
P2PUDSEL.P2PUDSEL7 7  Pulldown/Pullup Selection - bit 7
P2PUDSEL.P2PUDSEL6 6  Pulldown/Pullup Selection - bit 6
P2PUDSEL.P2PUDSEL5 5  Pulldown/Pullup Selection - bit 5
P2PUDSEL.P2PUDSEL4 4  Pulldown/Pullup Selection - bit 4
P2PUDSEL.P2PUDSEL3 3  Pulldown/Pullup Selection - bit 3
P2PUDSEL.P2PUDSEL2 2  Pulldown/Pullup Selection - bit 2
P2PUDSEL.P2PUDSEL1 1  Pulldown/Pullup Selection - bit 1
P2PUDSEL.P2PUDSEL0 0  Pulldown/Pullup Selection - bit 0
P2PUDEN          0xFE7A   Port 2 Pull Switch On/Off Register
P2PUDEN.P2PUDEN7  7   Pulldown/Pullup Enable - bit 7
P2PUDEN.P2PUDEN6  6   Pulldown/Pullup Enable - bit 6
P2PUDEN.P2PUDEN5  5   Pulldown/Pullup Enable - bit 5
P2PUDEN.P2PUDEN4  4   Pulldown/Pullup Enable - bit 4
P2PUDEN.P2PUDEN3  3   Pulldown/Pullup Enable - bit 3
P2PUDEN.P2PUDEN2  2   Pulldown/Pullup Enable - bit 2
P2PUDEN.P2PUDEN1  1   Pulldown/Pullup Enable - bit 1
P2PUDEN.P2PUDEN0  0   Pulldown/Pullup Enable - bit 0
P2PHEN           0xFE7C   Port 2 Pin Hold Enable Register
P2PHEN.P2PHEN7    7   Output Driver Enable in Power Down Mode - bit 7
P2PHEN.P2PHEN6    6   Output Driver Enable in Power Down Mode - bit 6
P2PHEN.P2PHEN5    5   Output Driver Enable in Power Down Mode - bit 5
P2PHEN.P2PHEN4    4   Output Driver Enable in Power Down Mode - bit 4
P2PHEN.P2PHEN3    3   Output Driver Enable in Power Down Mode - bit 3
P2PHEN.P2PHEN2    2   Output Driver Enable in Power Down Mode - bit 2
P2PHEN.P2PHEN1    1   Output Driver Enable in Power Down Mode - bit 1
P2PHEN.P2PHEN0    0   Output Driver Enable in Power Down Mode - bit 0
P3PUDSEL         0xFE7E   Port 3 Pull-Up/Down Select Register
P3PUDSEL.P3PUDSEL15 15 Pulldown/Pullup Selection - bit 15
P3PUDSEL.P3PUDSEL13 13 Pulldown/Pullup Selection - bit 13
P3PUDSEL.P3PUDSEL12 12 Pulldown/Pullup Selection - bit 12
P3PUDSEL.P3PUDSEL11 11 Pulldown/Pullup Selection - bit 11
P3PUDSEL.P3PUDSEL10 10 Pulldown/Pullup Selection - bit 10
P3PUDSEL.P3PUDSEL9  9  Pulldown/Pullup Selection - bit 9 
P3PUDSEL.P3PUDSEL8  8  Pulldown/Pullup Selection - bit 8 
P3PUDSEL.P3PUDSEL6  6  Pulldown/Pullup Selection - bit 6 
P3PUDSEL.P3PUDSEL5  5  Pulldown/Pullup Selection - bit 5 
P3PUDSEL.P3PUDSEL3  3  Pulldown/Pullup Selection - bit 3 
P3PUDEN          0xFE80   Port 3 Pull Switch On/Off Register
P3PUDEN.P3PUDEN15 15  Pulldown/Pullup Enable - bit 15
P3PUDEN.P3PUDEN13 13  Pulldown/Pullup Enable - bit 13
P3PUDEN.P3PUDEN12 12  Pulldown/Pullup Enable - bit 12
P3PUDEN.P3PUDEN11 11  Pulldown/Pullup Enable - bit 11
P3PUDEN.P3PUDEN10 10  Pulldown/Pullup Enable - bit 10
P3PUDEN.P3PUDEN9  9   Pulldown/Pullup Enable - bit 9
P3PUDEN.P3PUDEN8  8   Pulldown/Pullup Enable - bit 8
P3PUDEN.P3PUDEN6  6   Pulldown/Pullup Enable - bit 6
P3PUDEN.P3PUDEN5  5   Pulldown/Pullup Enable - bit 5
P3PUDEN.P3PUDEN3  3   Pulldown/Pullup Enable - bit 3
P3PHEN           0xFE82   Port 3 Pin Hold Enable Register
P3PHEN.P3PHEN15   15  Output Driver Enable in Power Down Mode - bit 15
P3PHEN.P3PHEN13   13  Output Driver Enable in Power Down Mode - bit 13
P3PHEN.P3PHEN12   12  Output Driver Enable in Power Down Mode - bit 12
P3PHEN.P3PHEN11   11  Output Driver Enable in Power Down Mode - bit 11
P3PHEN.P3PHEN10   10  Output Driver Enable in Power Down Mode - bit 10
P3PHEN.P3PHEN9    9   Output Driver Enable in Power Down Mode - bit 9 
P3PHEN.P3PHEN8    8   Output Driver Enable in Power Down Mode - bit 8 
P3PHEN.P3PHEN6    6   Output Driver Enable in Power Down Mode - bit 6 
P3PHEN.P3PHEN5    5   Output Driver Enable in Power Down Mode - bit 5 
P3PHEN.P3PHEN3    3   Output Driver Enable in Power Down Mode - bit 3 
P4PUDSEL         0xFE84   Port 4 Pull-Up/Down Select Register
P4PUDSEL.P4PUDSEL6 6  Pulldown/Pullup Selection - bit 6
P4PUDSEL.P4PUDSEL5 5  Pulldown/Pullup Selection - bit 5
P4PUDSEL.P4PUDSEL4 4  Pulldown/Pullup Selection - bit 4
P4PUDSEL.P4PUDSEL3 3  Pulldown/Pullup Selection - bit 3
P4PUDSEL.P4PUDSEL2 2  Pulldown/Pullup Selection - bit 2
P4PUDSEL.P4PUDSEL1 1  Pulldown/Pullup Selection - bit 1
P4PUDSEL.P4PUDSEL0 0  Pulldown/Pullup Selection - bit 0
P4PUDEN          0xFE86   Port 4 Pull Switch On/Off Register
P4PUDEN.P4PUDEN6  6   Pulldown/Pullup Enable - bit 6
P4PUDEN.P4PUDEN5  5   Pulldown/Pullup Enable - bit 5
P4PUDEN.P4PUDEN4  4   Pulldown/Pullup Enable - bit 4
P4PUDEN.P4PUDEN3  3   Pulldown/Pullup Enable - bit 3
P4PUDEN.P4PUDEN2  2   Pulldown/Pullup Enable - bit 2
P4PUDEN.P4PUDEN1  1   Pulldown/Pullup Enable - bit 1
P4PUDEN.P4PUDEN0  0   Pulldown/Pullup Enable - bit 0
P4PHEN           0xFE88   Port 4 Pin Hold Enable Register
P4PHEN.P4PHEN6    6   Output Driver Enable in Power Down Mode - bit 6
P4PHEN.P4PHEN5    5   Output Driver Enable in Power Down Mode - bit 5
P4PHEN.P4PHEN4    4   Output Driver Enable in Power Down Mode - bit 4
P4PHEN.P4PHEN3    3   Output Driver Enable in Power Down Mode - bit 3
P4PHEN.P4PHEN2    2   Output Driver Enable in Power Down Mode - bit 2
P4PHEN.P4PHEN1    1   Output Driver Enable in Power Down Mode - bit 1
P4PHEN.P4PHEN0    0   Output Driver Enable in Power Down Mode - bit 0
P6PUDSEL         0xFE90   Port 6 Pull-Up/Down Select Register
P6PUDSEL.P6PUDSEL7 7  Pulldown/Pullup Selection - bit 7
P6PUDSEL.P6PUDSEL6 6  Pulldown/Pullup Selection - bit 6
P6PUDSEL.P6PUDSEL5 5  Pulldown/Pullup Selection - bit 5
P6PUDSEL.P6PUDSEL4 4  Pulldown/Pullup Selection - bit 4
P6PUDSEL.P6PUDSEL3 3  Pulldown/Pullup Selection - bit 3
P6PUDSEL.P6PUDSEL2 2  Pulldown/Pullup Selection - bit 2
P6PUDSEL.P6PUDSEL1 1  Pulldown/Pullup Selection - bit 1
P6PUDSEL.P6PUDSEL0 0  Pulldown/Pullup Selection - bit 0
P6PUDEN          0xFE92   Port 6 Pull Switch On/Off Register
P6PUDEN.P6PUDEN7  7   Pulldown/Pullup Enable - bit 7
P6PUDEN.P6PUDEN6  6   Pulldown/Pullup Enable - bit 6
P6PUDEN.P6PUDEN5  5   Pulldown/Pullup Enable - bit 5
P6PUDEN.P6PUDEN4  4   Pulldown/Pullup Enable - bit 4
P6PUDEN.P6PUDEN3  3   Pulldown/Pullup Enable - bit 3
P6PUDEN.P6PUDEN2  2   Pulldown/Pullup Enable - bit 2
P6PUDEN.P6PUDEN1  1   Pulldown/Pullup Enable - bit 1
P6PUDEN.P6PUDEN0  0   Pulldown/Pullup Enable - bit 0
P6PHEN           0xFE94   Port 6 Pin Hold Enable Register
P6PHEN.P6PHEN7    7   Output Driver Enable in Power Down Mode - bit 7
P6PHEN.P6PHEN6    6   Output Driver Enable in Power Down Mode - bit 6
P6PHEN.P6PHEN5    5   Output Driver Enable in Power Down Mode - bit 5
P6PHEN.P6PHEN4    4   Output Driver Enable in Power Down Mode - bit 4
P6PHEN.P6PHEN3    3   Output Driver Enable in Power Down Mode - bit 3
P6PHEN.P6PHEN2    2   Output Driver Enable in Power Down Mode - bit 2
P6PHEN.P6PHEN1    1   Output Driver Enable in Power Down Mode - bit 1
P6PHEN.P6PHEN0    0   Output Driver Enable in Power Down Mode - bit 0
P7PUDSEL         0xFE96   Port 7 Pull-Up/Down Select Register
P7PUDSEL.P7PUDSEL5 5  Pulldown/Pullup Selection - bit 5
P7PUDSEL.P7PUDSEL4 4  Pulldown/Pullup Selection - bit 4
P7PUDSEL.P7PUDSEL3 3  Pulldown/Pullup Selection - bit 3
P7PUDSEL.P7PUDSEL2 2  Pulldown/Pullup Selection - bit 2
P7PUDSEL.P7PUDSEL1 1  Pulldown/Pullup Selection - bit 1
P7PUDSEL.P7PUDSEL0 0  Pulldown/Pullup Selection - bit 0
P7PUDEN          0xFE98   Port 7 Pull Switch On/Off Register
P7PUDEN.P7PUDEN5  5   Pulldown/Pullup Enable - bit 5
P7PUDEN.P7PUDEN4  4   Pulldown/Pullup Enable - bit 4
P7PUDEN.P7PUDEN3  3   Pulldown/Pullup Enable - bit 3
P7PUDEN.P7PUDEN2  2   Pulldown/Pullup Enable - bit 2
P7PUDEN.P7PUDEN1  1   Pulldown/Pullup Enable - bit 1
P7PUDEN.P7PUDEN0  0   Pulldown/Pullup Enable - bit 0
P7PHEN           0xFE9A   Port 7 Pin Hold Enable Register
P7PHEN.P7PHEN5    5   Output Driver Enable in Power Down Mode - bit 5
P7PHEN.P7PHEN4    4   Output Driver Enable in Power Down Mode - bit 4
P7PHEN.P7PHEN3    3   Output Driver Enable in Power Down Mode - bit 3
P7PHEN.P7PHEN2    2   Output Driver Enable in Power Down Mode - bit 2
P7PHEN.P7PHEN1    1   Output Driver Enable in Power Down Mode - bit 1
P7PHEN.P7PHEN0    0   Output Driver Enable in Power Down Mode - bit 0
S0PMW            0xFEAA   ASC IrDA PMW Control Regi
S0PMW.IRPW        8   IrDA Pulse Width Mode Control
S0PMW.PW_VALUE_7  7   IrDA Pulse Width Value - bit 7
S0PMW.PW_VALUE_6  6   IrDA Pulse Width Value - bit 6
S0PMW.PW_VALUE_5  5   IrDA Pulse Width Value - bit 5
S0PMW.PW_VALUE_4  4   IrDA Pulse Width Value - bit 4
S0PMW.PW_VALUE_3  3   IrDA Pulse Width Value - bit 3
S0PMW.PW_VALUE_2  2   IrDA Pulse Width Value - bit 2
S0PMW.PW_VALUE_1  1   IrDA Pulse Width Value - bit 1
S0PMW.PW_VALUE_0  0   IrDA Pulse Width Value - bit 0
WDT              0xFEAE   Watchdog Timer Register (RO)
S0TBUF           0xFEB0   Serial Channel 0 Transmit Buffer Register (WO)
S0TBUF.TD_VALUE_8 8   Transmit Data Register Value - bit 8
S0TBUF.TD_VALUE_7 7   Transmit Data Register Value - bit 7
S0TBUF.TD_VALUE_6 6   Transmit Data Register Value - bit 6
S0TBUF.TD_VALUE_5 5   Transmit Data Register Value - bit 5
S0TBUF.TD_VALUE_4 4   Transmit Data Register Value - bit 4
S0TBUF.TD_VALUE_3 3   Transmit Data Register Value - bit 3
S0TBUF.TD_VALUE_2 2   Transmit Data Register Value - bit 2
S0TBUF.TD_VALUE_1 1   Transmit Data Register Value - bit 1
S0TBUF.TD_VALUE_0 0   Transmit Data Register Value - bit 0
S0RBUF           0xFEB2   Serial Channel 0 Receive Buffer Register (RO)
S0RBUF.RD_VALUE_8 8   Receive Data Register Value - bit 8
S0RBUF.RD_VALUE_7 7   Receive Data Register Value - bit 7
S0RBUF.RD_VALUE_6 6   Receive Data Register Value - bit 6
S0RBUF.RD_VALUE_5 5   Receive Data Register Value - bit 5
S0RBUF.RD_VALUE_4 4   Receive Data Register Value - bit 4
S0RBUF.RD_VALUE_3 3   Receive Data Register Value - bit 3
S0RBUF.RD_VALUE_2 2   Receive Data Register Value - bit 2
S0RBUF.RD_VALUE_1 1   Receive Data Register Value - bit 1
S0RBUF.RD_VALUE_0 0   Receive Data Register Value - bit 0
S0BG             0xFEB4   Serial Chan
S0BG.BR_VALUE_12  12  Baudrate Timer/Reload Register Value - bit 12
S0BG.BR_VALUE_11  11  Baudrate Timer/Reload Register Value - bit 11
S0BG.BR_VALUE_10  10  Baudrate Timer/Reload Register Value - bit 10
S0BG.BR_VALUE_9   9   Baudrate Timer/Reload Register Value - bit 9 
S0BG.BR_VALUE_8   8   Baudrate Timer/Reload Register Value - bit 8 
S0BG.BR_VALUE_7   7   Baudrate Timer/Reload Register Value - bit 7 
S0BG.BR_VALUE_6   6   Baudrate Timer/Reload Register Value - bit 6 
S0BG.BR_VALUE_5   5   Baudrate Timer/Reload Register Value - bit 5 
S0BG.BR_VALUE_4   4   Baudrate Timer/Reload Register Value - bit 4 
S0BG.BR_VALUE_3   3   Baudrate Timer/Reload Register Value - bit 3 
S0BG.BR_VALUE_2   2   Baudrate Timer/Reload Register Value - bit 2 
S0BG.BR_VALUE_1   1   Baudrate Timer/Reload Register Value - bit 1 
S0BG.BR_VALUE_0   0   Baudrate Timer/Reload Register Value - bit 0 
S0FDV            0xFEB6   ASC Fracti
S0FDV.FD_VALUE_8  8   Fractional Divider Register Value - bit 8
S0FDV.FD_VALUE_7  7   Fractional Divider Register Value - bit 7
S0FDV.FD_VALUE_6  6   Fractional Divider Register Value - bit 6
S0FDV.FD_VALUE_5  5   Fractional Divider Register Value - bit 5
S0FDV.FD_VALUE_4  4   Fractional Divider Register Value - bit 4
S0FDV.FD_VALUE_3  3   Fractional Divider Register Value - bit 3
S0FDV.FD_VALUE_2  2   Fractional Divider Register Value - bit 2
S0FDV.FD_VALUE_1  1   Fractional Divider Register Value - bit 1
S0FDV.FD_VALUE_0  0   Fractional Divider Register Value - bit 0
PECC0            0xFEC0   PEC Channel 0 Control Register
PECC0.PT          15  Package Transfer
PECC0.CLT         12  Channel Link Toggle State
PECC0.CL          11  Channel Link Control
PECC0.INC_10      10  Increment Control - bit 10
PECC0.INC_9       9   Increment Control - bit 9 
PECC0.BWT         8   Byte/Word Transfer Selection
PECC0.COUNT_7     7   PEC Transfer Count - bit 7
PECC0.COUNT_6     6   PEC Transfer Count - bit 6
PECC0.COUNT_5     5   PEC Transfer Count - bit 5
PECC0.COUNT_4     4   PEC Transfer Count - bit 4
PECC0.COUNT_3     3   PEC Transfer Count - bit 3
PECC0.COUNT_2     2   PEC Transfer Count - bit 2
PECC0.COUNT_1     1   PEC Transfer Count - bit 1
PECC0.COUNT_0     0   PEC Transfer Count - bit 0
PECC1            0xFEC2   PEC Channel 1 Control Register
PECC1.PT          15  Package Transfer
PECC1.CLT         12  Channel Link Toggle State
PECC1.CL          11  Channel Link Control
PECC1.INC_10      10  Increment Control - bit 10
PECC1.INC_9       9   Increment Control - bit 9 
PECC1.BWT         8   Byte/Word Transfer Selection
PECC1.COUNT_7     7   PEC Transfer Count - bit 7
PECC1.COUNT_6     6   PEC Transfer Count - bit 6
PECC1.COUNT_5     5   PEC Transfer Count - bit 5
PECC1.COUNT_4     4   PEC Transfer Count - bit 4
PECC1.COUNT_3     3   PEC Transfer Count - bit 3
PECC1.COUNT_2     2   PEC Transfer Count - bit 2
PECC1.COUNT_1     1   PEC Transfer Count - bit 1
PECC1.COUNT_0     0   PEC Transfer Count - bit 0
PECC2            0xFEC4   PEC Channel 2 Control Register
PECC2.PT          15  Package Transfer
PECC2.CLT         12  Channel Link Toggle State
PECC2.CL          11  Channel Link Control
PECC2.INC_10      10  Increment Control - bit 10
PECC2.INC_9       9   Increment Control - bit 9 
PECC2.BWT         8   Byte/Word Transfer Selection
PECC2.COUNT_7     7   PEC Transfer Count - bit 7
PECC2.COUNT_6     6   PEC Transfer Count - bit 6
PECC2.COUNT_5     5   PEC Transfer Count - bit 5
PECC2.COUNT_4     4   PEC Transfer Count - bit 4
PECC2.COUNT_3     3   PEC Transfer Count - bit 3
PECC2.COUNT_2     2   PEC Transfer Count - bit 2
PECC2.COUNT_1     1   PEC Transfer Count - bit 1
PECC2.COUNT_0     0   PEC Transfer Count - bit 0
PECC3            0xFEC6   PEC Channel 3 Control Register
PECC3.PT          15  Package Transfer
PECC3.CLT         12  Channel Link Toggle State
PECC3.CL          11  Channel Link Control
PECC3.INC_10      10  Increment Control - bit 10
PECC3.INC_9       9   Increment Control - bit 9 
PECC3.BWT         8   Byte/Word Transfer Selection
PECC3.COUNT_7     7   PEC Transfer Count - bit 7
PECC3.COUNT_6     6   PEC Transfer Count - bit 6
PECC3.COUNT_5     5   PEC Transfer Count - bit 5
PECC3.COUNT_4     4   PEC Transfer Count - bit 4
PECC3.COUNT_3     3   PEC Transfer Count - bit 3
PECC3.COUNT_2     2   PEC Transfer Count - bit 2
PECC3.COUNT_1     1   PEC Transfer Count - bit 1
PECC3.COUNT_0     0   PEC Transfer Count - bit 0
PECC4            0xFEC8   PEC Channel 4 Control Register
PECC4.PT          15  Package Transfer
PECC4.CLT         12  Channel Link Toggle State
PECC4.CL          11  Channel Link Control
PECC4.INC_10      10  Increment Control - bit 10
PECC4.INC_9       9   Increment Control - bit 9 
PECC4.BWT         8   Byte/Word Transfer Selection
PECC4.COUNT_7     7   PEC Transfer Count - bit 7
PECC4.COUNT_6     6   PEC Transfer Count - bit 6
PECC4.COUNT_5     5   PEC Transfer Count - bit 5
PECC4.COUNT_4     4   PEC Transfer Count - bit 4
PECC4.COUNT_3     3   PEC Transfer Count - bit 3
PECC4.COUNT_2     2   PEC Transfer Count - bit 2
PECC4.COUNT_1     1   PEC Transfer Count - bit 1
PECC4.COUNT_0     0   PEC Transfer Count - bit 0
PECC5            0xFECA   PEC Channel 5 Control Register
PECC5.PT          15  Package Transfer
PECC5.CLT         12  Channel Link Toggle State
PECC5.CL          11  Channel Link Control
PECC5.INC_10      10  Increment Control - bit 10
PECC5.INC_9       9   Increment Control - bit 9 
PECC5.BWT         8   Byte/Word Transfer Selection
PECC5.COUNT_7     7   PEC Transfer Count - bit 7
PECC5.COUNT_6     6   PEC Transfer Count - bit 6
PECC5.COUNT_5     5   PEC Transfer Count - bit 5
PECC5.COUNT_4     4   PEC Transfer Count - bit 4
PECC5.COUNT_3     3   PEC Transfer Count - bit 3
PECC5.COUNT_2     2   PEC Transfer Count - bit 2
PECC5.COUNT_1     1   PEC Transfer Count - bit 1
PECC5.COUNT_0     0   PEC Transfer Count - bit 0
PECC6            0xFECC   PEC Channel 6 Control Register
PECC6.PT          15  Package Transfer
PECC6.CLT         12  Channel Link Toggle State
PECC6.CL          11  Channel Link Control
PECC6.INC_10      10  Increment Control - bit 10
PECC6.INC_9       9   Increment Control - bit 9 
PECC6.BWT         8   Byte/Word Transfer Selection
PECC6.COUNT_7     7   PEC Transfer Count - bit 7
PECC6.COUNT_6     6   PEC Transfer Count - bit 6
PECC6.COUNT_5     5   PEC Transfer Count - bit 5
PECC6.COUNT_4     4   PEC Transfer Count - bit 4
PECC6.COUNT_3     3   PEC Transfer Count - bit 3
PECC6.COUNT_2     2   PEC Transfer Count - bit 2
PECC6.COUNT_1     1   PEC Transfer Count - bit 1
PECC6.COUNT_0     0   PEC Transfer Count - bit 0
PECC7            0xFECE   PEC Channel 7 Control Register
PECC7.PT          15  Package Transfer
PECC7.CLT         12  Channel Link Toggle State
PECC7.CL          11  Channel Link Control
PECC7.INC_10      10  Increment Control - bit 10
PECC7.INC_9       9   Increment Control - bit 9 
PECC7.BWT         8   Byte/Word Transfer Selection
PECC7.COUNT_7     7   PEC Transfer Count - bit 7
PECC7.COUNT_6     6   PEC Transfer Count - bit 6
PECC7.COUNT_5     5   PEC Transfer Count - bit 5
PECC7.COUNT_4     4   PEC Transfer Count - bit 4
PECC7.COUNT_3     3   PEC Transfer Count - bit 3
PECC7.COUNT_2     2   PEC Transfer Count - bit 2
PECC7.COUNT_1     1   PEC Transfer Count - bit 1
PECC7.COUNT_0     0   PEC Transfer Count - bit 0
PECSN0           0xFED0   PEC Segment No Register
PECSN0.PECDSN_15  15  PEC Destination Segment Number - bit 15
PECSN0.PECDSN_14  14  PEC Destination Segment Number - bit 14
PECSN0.PECDSN_13  13  PEC Destination Segment Number - bit 13
PECSN0.PECDSN_12  12  PEC Destination Segment Number - bit 12
PECSN0.PECDSN_11  11  PEC Destination Segment Number - bit 11
PECSN0.PECDSN_10  10  PEC Destination Segment Number - bit 10
PECSN0.PECDSN_9   9   PEC Destination Segment Number - bit 9 
PECSN0.PECDSN_8   8   PEC Destination Segment Number - bit 8 
PECSN0.PECSSN_7   7   PEC Source Segment Number - bit 7
PECSN0.PECSSN_6   6   PEC Source Segment Number - bit 6
PECSN0.PECSSN_5   5   PEC Source Segment Number - bit 5
PECSN0.PECSSN_4   4   PEC Source Segment Number - bit 4
PECSN0.PECSSN_3   3   PEC Source Segment Number - bit 3
PECSN0.PECSSN_2   2   PEC Source Segment Number - bit 2
PECSN0.PECSSN_1   1   PEC Source Segment Number - bit 1
PECSN0.PECSSN_0   0   PEC Source Segment Number - bit 0
PECSN1           0xFED2   PEC Segment No Register
PECSN1.PECDSN_15  15  PEC Destination Segment Number - bit 15
PECSN1.PECDSN_14  14  PEC Destination Segment Number - bit 14
PECSN1.PECDSN_13  13  PEC Destination Segment Number - bit 13
PECSN1.PECDSN_12  12  PEC Destination Segment Number - bit 12
PECSN1.PECDSN_11  11  PEC Destination Segment Number - bit 11
PECSN1.PECDSN_10  10  PEC Destination Segment Number - bit 10
PECSN1.PECDSN_9   9   PEC Destination Segment Number - bit 9 
PECSN1.PECDSN_8   8   PEC Destination Segment Number - bit 8 
PECSN1.PECSSN_7   7   PEC Source Segment Number - bit 7
PECSN1.PECSSN_6   6   PEC Source Segment Number - bit 6
PECSN1.PECSSN_5   5   PEC Source Segment Number - bit 5
PECSN1.PECSSN_4   4   PEC Source Segment Number - bit 4
PECSN1.PECSSN_3   3   PEC Source Segment Number - bit 3
PECSN1.PECSSN_2   2   PEC Source Segment Number - bit 2
PECSN1.PECSSN_1   1   PEC Source Segment Number - bit 1
PECSN1.PECSSN_0   0   PEC Source Segment Number - bit 0
PECSN2           0xFED4   PEC Segment No Register
PECSN2.PECDSN_15  15  PEC Destination Segment Number - bit 15
PECSN2.PECDSN_14  14  PEC Destination Segment Number - bit 14
PECSN2.PECDSN_13  13  PEC Destination Segment Number - bit 13
PECSN2.PECDSN_12  12  PEC Destination Segment Number - bit 12
PECSN2.PECDSN_11  11  PEC Destination Segment Number - bit 11
PECSN2.PECDSN_10  10  PEC Destination Segment Number - bit 10
PECSN2.PECDSN_9   9   PEC Destination Segment Number - bit 9 
PECSN2.PECDSN_8   8   PEC Destination Segment Number - bit 8 
PECSN2.PECSSN_7   7   PEC Source Segment Number - bit 7
PECSN2.PECSSN_6   6   PEC Source Segment Number - bit 6
PECSN2.PECSSN_5   5   PEC Source Segment Number - bit 5
PECSN2.PECSSN_4   4   PEC Source Segment Number - bit 4
PECSN2.PECSSN_3   3   PEC Source Segment Number - bit 3
PECSN2.PECSSN_2   2   PEC Source Segment Number - bit 2
PECSN2.PECSSN_1   1   PEC Source Segment Number - bit 1
PECSN2.PECSSN_0   0   PEC Source Segment Number - bit 0
PECSN3           0xFED6   PEC Segment No Register
PECSN3.PECDSN_15  15  PEC Destination Segment Number - bit 15
PECSN3.PECDSN_14  14  PEC Destination Segment Number - bit 14
PECSN3.PECDSN_13  13  PEC Destination Segment Number - bit 13
PECSN3.PECDSN_12  12  PEC Destination Segment Number - bit 12
PECSN3.PECDSN_11  11  PEC Destination Segment Number - bit 11
PECSN3.PECDSN_10  10  PEC Destination Segment Number - bit 10
PECSN3.PECDSN_9   9   PEC Destination Segment Number - bit 9 
PECSN3.PECDSN_8   8   PEC Destination Segment Number - bit 8 
PECSN3.PECSSN_7   7   PEC Source Segment Number - bit 7
PECSN3.PECSSN_6   6   PEC Source Segment Number - bit 6
PECSN3.PECSSN_5   5   PEC Source Segment Number - bit 5
PECSN3.PECSSN_4   4   PEC Source Segment Number - bit 4
PECSN3.PECSSN_3   3   PEC Source Segment Number - bit 3
PECSN3.PECSSN_2   2   PEC Source Segment Number - bit 2
PECSN3.PECSSN_1   1   PEC Source Segment Number - bit 1
PECSN3.PECSSN_0   0   PEC Source Segment Number - bit 0
PECSN4           0xFED8   PEC Segment No Register
PECSN4.PECDSN_15  15  PEC Destination Segment Number - bit 15
PECSN4.PECDSN_14  14  PEC Destination Segment Number - bit 14
PECSN4.PECDSN_13  13  PEC Destination Segment Number - bit 13
PECSN4.PECDSN_12  12  PEC Destination Segment Number - bit 12
PECSN4.PECDSN_11  11  PEC Destination Segment Number - bit 11
PECSN4.PECDSN_10  10  PEC Destination Segment Number - bit 10
PECSN4.PECDSN_9   9   PEC Destination Segment Number - bit 9 
PECSN4.PECDSN_8   8   PEC Destination Segment Number - bit 8 
PECSN4.PECSSN_7   7   PEC Source Segment Number - bit 7
PECSN4.PECSSN_6   6   PEC Source Segment Number - bit 6
PECSN4.PECSSN_5   5   PEC Source Segment Number - bit 5
PECSN4.PECSSN_4   4   PEC Source Segment Number - bit 4
PECSN4.PECSSN_3   3   PEC Source Segment Number - bit 3
PECSN4.PECSSN_2   2   PEC Source Segment Number - bit 2
PECSN4.PECSSN_1   1   PEC Source Segment Number - bit 1
PECSN4.PECSSN_0   0   PEC Source Segment Number - bit 0
PECSN5           0xFEDA   PEC Segment No Register
PECSN5.PECDSN_15  15  PEC Destination Segment Number - bit 15
PECSN5.PECDSN_14  14  PEC Destination Segment Number - bit 14
PECSN5.PECDSN_13  13  PEC Destination Segment Number - bit 13
PECSN5.PECDSN_12  12  PEC Destination Segment Number - bit 12
PECSN5.PECDSN_11  11  PEC Destination Segment Number - bit 11
PECSN5.PECDSN_10  10  PEC Destination Segment Number - bit 10
PECSN5.PECDSN_9   9   PEC Destination Segment Number - bit 9 
PECSN5.PECDSN_8   8   PEC Destination Segment Number - bit 8 
PECSN5.PECSSN_7   7   PEC Source Segment Number - bit 7
PECSN5.PECSSN_6   6   PEC Source Segment Number - bit 6
PECSN5.PECSSN_5   5   PEC Source Segment Number - bit 5
PECSN5.PECSSN_4   4   PEC Source Segment Number - bit 4
PECSN5.PECSSN_3   3   PEC Source Segment Number - bit 3
PECSN5.PECSSN_2   2   PEC Source Segment Number - bit 2
PECSN5.PECSSN_1   1   PEC Source Segment Number - bit 1
PECSN5.PECSSN_0   0   PEC Source Segment Number - bit 0
PECSN6           0xFEDC   PEC Segment No Register
PECSN6.PECDSN_15  15  PEC Destination Segment Number - bit 15
PECSN6.PECDSN_14  14  PEC Destination Segment Number - bit 14
PECSN6.PECDSN_13  13  PEC Destination Segment Number - bit 13
PECSN6.PECDSN_12  12  PEC Destination Segment Number - bit 12
PECSN6.PECDSN_11  11  PEC Destination Segment Number - bit 11
PECSN6.PECDSN_10  10  PEC Destination Segment Number - bit 10
PECSN6.PECDSN_9   9   PEC Destination Segment Number - bit 9 
PECSN6.PECDSN_8   8   PEC Destination Segment Number - bit 8 
PECSN6.PECSSN_7   7   PEC Source Segment Number - bit 7
PECSN6.PECSSN_6   6   PEC Source Segment Number - bit 6
PECSN6.PECSSN_5   5   PEC Source Segment Number - bit 5
PECSN6.PECSSN_4   4   PEC Source Segment Number - bit 4
PECSN6.PECSSN_3   3   PEC Source Segment Number - bit 3
PECSN6.PECSSN_2   2   PEC Source Segment Number - bit 2
PECSN6.PECSSN_1   1   PEC Source Segment Number - bit 1
PECSN6.PECSSN_0   0   PEC Source Segment Number - bit 0
PECSN7           0xFEDE   PEC Segment No Register
PECSN7.PECDSN_15  15  PEC Destination Segment Number - bit 15
PECSN7.PECDSN_14  14  PEC Destination Segment Number - bit 14
PECSN7.PECDSN_13  13  PEC Destination Segment Number - bit 13
PECSN7.PECDSN_12  12  PEC Destination Segment Number - bit 12
PECSN7.PECDSN_11  11  PEC Destination Segment Number - bit 11
PECSN7.PECDSN_10  10  PEC Destination Segment Number - bit 10
PECSN7.PECDSN_9   9   PEC Destination Segment Number - bit 9 
PECSN7.PECDSN_8   8   PEC Destination Segment Number - bit 8 
PECSN7.PECSSN_7   7   PEC Source Segment Number - bit 7
PECSN7.PECSSN_6   6   PEC Source Segment Number - bit 6
PECSN7.PECSSN_5   5   PEC Source Segment Number - bit 5
PECSN7.PECSSN_4   4   PEC Source Segment Number - bit 4
PECSN7.PECSSN_3   3   PEC Source Segment Number - bit 3
PECSN7.PECSSN_2   2   PEC Source Segment Number - bit 2
PECSN7.PECSSN_1   1   PEC Source Segment Number - bit 1
PECSN7.PECSSN_0   0   PEC Source Segment Number - bit 0
PECXC0           0xFEF0   PEC Channel 0 Extended Control Register
PECXC0.COUNT2_15  15  Extended PEC Transfer Count - bit 15
PECXC0.COUNT2_14  14  Extended PEC Transfer Count - bit 14
PECXC0.COUNT2_13  13  Extended PEC Transfer Count - bit 13
PECXC0.COUNT2_12  12  Extended PEC Transfer Count - bit 12
PECXC0.COUNT2_11  11  Extended PEC Transfer Count - bit 11
PECXC0.COUNT2_10  10  Extended PEC Transfer Count - bit 10
PECXC0.COUNT2_9   9   Extended PEC Transfer Count - bit 9 
PECXC0.COUNT2_8   8   Extended PEC Transfer Count - bit 8 
PECXC0.COUNT2_7   7   Extended PEC Transfer Count - bit 7 
PECXC0.COUNT2_6   6   Extended PEC Transfer Count - bit 6 
PECXC0.COUNT2_5   5   Extended PEC Transfer Count - bit 5 
PECXC0.COUNT2_4   4   Extended PEC Transfer Count - bit 4 
PECXC0.COUNT2_3   3   Extended PEC Transfer Count - bit 3 
PECXC0.COUNT2_2   2   Extended PEC Transfer Count - bit 2 
PECXC0.COUNT2_1   1   Extended PEC Transfer Count - bit 1 
PECXC0.COUNT2_0   0   Extended PEC Transfer Count - bit 0 
PECXC2           0xFEF2   PEC Channel 2 Extended Control Register
PECXC2.COUNT2_15  15  Extended PEC Transfer Count - bit 15
PECXC2.COUNT2_14  14  Extended PEC Transfer Count - bit 14
PECXC2.COUNT2_13  13  Extended PEC Transfer Count - bit 13
PECXC2.COUNT2_12  12  Extended PEC Transfer Count - bit 12
PECXC2.COUNT2_11  11  Extended PEC Transfer Count - bit 11
PECXC2.COUNT2_10  10  Extended PEC Transfer Count - bit 10
PECXC2.COUNT2_9   9   Extended PEC Transfer Count - bit 9 
PECXC2.COUNT2_8   8   Extended PEC Transfer Count - bit 8 
PECXC2.COUNT2_7   7   Extended PEC Transfer Count - bit 7 
PECXC2.COUNT2_6   6   Extended PEC Transfer Count - bit 6 
PECXC2.COUNT2_5   5   Extended PEC Transfer Count - bit 5 
PECXC2.COUNT2_4   4   Extended PEC Transfer Count - bit 4 
PECXC2.COUNT2_3   3   Extended PEC Transfer Count - bit 3 
PECXC2.COUNT2_2   2   Extended PEC Transfer Count - bit 2 
PECXC2.COUNT2_1   1   Extended PEC Transfer Count - bit 1 
PECXC2.COUNT2_0   0   Extended PEC Transfer Count - bit 0 
ABS0CON          0xFEF8   ASC Autobaud Control Register
ABS0CON.RXINV     11  Receive Inverter Enable
ABS0CON.TXINV     10  Transmit Inverter Enable
ABS0CON.ABEM_9    9   Autobaud Echo Mode Enable - bit 9
ABS0CON.ABEM_8    8   Autobaud Echo Mode Enable - bit 8
ABS0CON.FCDETEN   4   First Character of Two-Byte Frame Detected Enable
ABS0CON.ABDETEN   3   Autobaud Detection Interrupt Enable
ABS0CON.ABSTEN    2   Start of Autobaud Detection Interrupt Enable
ABS0CON.AUREN     1   Automatic Autobaud Control of CON_REN
ABS0CON.ABEN      0   Autobaud Detection Enable
ABSTAT           0xFEFE   ASC Autobaud Status Register
ABSTAT.DETWAIT    4   Autobaud Detection is Waiting
ABSTAT.SCCDET     3   Second Character with Capital Letter Detected
ABSTAT.SCSDET     2   Second Character with Small Letter Detected
ABSTAT.FCCDET     1   First Character with Capital Letter Detected
ABSTAT.FCSDET     0   First Character with Small Letter Detected
P0L              0xFF00   Port 0 Low Register (Lower half)
P0L.P0L7          7   Port data register P0L bit 7
P0L.P0L6          6   Port data register P0L bit 6
P0L.P0L5          5   Port data register P0L bit 5
P0L.P0L4          4   Port data register P0L bit 4
P0L.P0L3          3   Port data register P0L bit 3
P0L.P0L2          2   Port data register P0L bit 2
P0L.P0L1          1   Port data register P0L bit 1
P0L.P0L0          0   Port data register P0L bit 0
P0H              0xFF02   Port 0 High Register (Upper half)
P0H.P0H7          7   Port data register P0H bit 7
P0H.P0H6          6   Port data register P0H bit 6
P0H.P0H5          5   Port data register P0H bit 5
P0H.P0H4          4   Port data register P0H bit 4
P0H.P0H3          3   Port data register P0H bit 3
P0H.P0H2          2   Port data register P0H bit 2
P0H.P0H1          1   Port data register P0H bit 1
P0H.P0H0          0   Port data register P0H bit 0
P1L              0xFF04   Port 1 Low Register (Lower half)
P1L.P1L7          7   Port data register P1L bit 7
P1L.P1L6          6   Port data register P1L bit 6
P1L.P1L5          5   Port data register P1L bit 5
P1L.P1L4          4   Port data register P1L bit 4
P1L.P1L3          3   Port data register P1L bit 3
P1L.P1L2          2   Port data register P1L bit 2
P1L.P1L1          1   Port data register P1L bit 1
P1L.P1L0          0   Port data register P1L bit 0
P1H              0xFF06   Port 1 High Register (Upper half)
P1H.P1H7          7   Port data register P1H bit 7
P1H.P1H6          6   Port data register P1H bit 6
P1H.P1H5          5   Port data register P1H bit 5
P1H.P1H4          4   Port data register P1H bit 4
P1H.P1H3          3   Port data register P1H bit 3
P1H.P1H2          2   Port data register P1H bit 2
P1H.P1H1          1   Port data register P1H bit 1
P1H.P1H0          0   Port data register P1H bit 0
BUSCON0          0xFF0C   Bus Configuration Register 0
BUSCON0.CSWEN0    15  Write Chip Select Enable
BUSCON0.CSREN0    14  Read Chip Select Enable
BUSCON0.RDYEN0    12  READY Input Enable
BUSCON0.BUSACT0   10  Bus Active Control
BUSCON0.ALECTL0   9   ALE Lengthening Control
BUSCON0.EWEN0     8   Early Write Enable
BUSCON0.BTYP_7    7   External Bus Configuration - bit 7
BUSCON0.BTYP_6    6   External Bus Configuration - bit 6
BUSCON0.MTTC0     5   Memory Tristate Time Control
BUSCON0.RWDC0     4   Read/Write Delay Control for BUSCON
BUSCON0.MCTC_3    3   Memory Cycle Time Control - bit 3
BUSCON0.MCTC_2    2   Memory Cycle Time Control - bit 2
BUSCON0.MCTC_1    1   Memory Cycle Time Control - bit 1
BUSCON0.MCTC_0    0   Memory Cycle Time Control - bit 0
MDC              0xFF0E   CPU Multiply Divide Control Register
MDC.MDRIU         4   Multiply/Divide Register In Use
PSW              0xFF10   CPU Program Status Word
PSW.ILVL_15       15  Interrupt and EBC Control Field - bit 15
PSW.ILVL_14       14  Interrupt and EBC Control Field - bit 14
PSW.ILVL_13       13  Interrupt and EBC Control Field - bit 13
PSW.ILVL_12       12  Interrupt and EBC Control Field - bit 12
PSW.IEN           11  Interrupt and EBC Control Field
PSW.HLDEN         10  Interrupt and EBC Control Field
PSW.USR0          6   User General Purpose Flag
PSW.MULIP         5   Multiplication/Division In Progress
PSW.E             4   End of Table Flag
PSW.Z             3   Zero F lag
PSW.V             2   Overflow Result
PSW.C             1   Carry Flag
PSW.N             0   Negative Result
SYSCON           0xFF12   CPU System Configuration Register
SYSCON.STKSZ_15   15  System Stack Size - bit 15
SYSCON.STKSZ_14   14  System Stack Size - bit 14
SYSCON.STKSZ_13   13  System Stack Size - bit 13
SYSCON.ROMS1      12  Internal ROM Mapping
SYSCON.SGTDIS     11  Segmentation Disable/Enable Control (Cleared after reset)
SYSCON.ROMEN      10  Internal ROM Enable (Set according to pin EA during reset)
SYSCON.BYTDIS     9   Disable/Enable Control for Pin BHE (Set according to data bus width)
SYSCON.CLKEN      8   System Clock Output Enable (CLKOUT, cleared after reset)
SYSCON.WRCFG      7   Write Configuration Control (Set according to pin P0H.0 during reset)
SYSCON.CSCFG      6   Chip Select Configuration Control (Cleared after reset)
SYSCON.OSCENBL    4   Oscillator Watchdog Enable Bit
SYSCON.XPEN       2   Peripheral Enable Bit
SYSCON.VISIBLE    1   Visible Mode Control
SYSCON.XPER_SHARE 0   XBUS Peripheral Share Mode Control
BUSCON1          0xFF14   Bus Configuration Register 1
BUSCON1.CSWEN1    15  Write Chip Select Enable
BUSCON1.CSREN1    14  Read Chip Select Enable
BUSCON1.RDYEN1    12  READY Input Enable
BUSCON1.BUSACT1   10  Bus Active Control
BUSCON1.ALECTL1   9   ALE Lengthening Control
BUSCON1.EWEN1     8   Early Write Enable
BUSCON1.BTYP_7    7   External Bus Configuration - bit 7
BUSCON1.BTYP_6    6   External Bus Configuration - bit 6
BUSCON1.MTTC1     5   Memory Tristate Time Control
BUSCON1.RWDC1     4   Read/Write Delay Control for BUSCON
BUSCON1.MCTC_3    3   Memory Cycle Time Control - bit 3
BUSCON1.MCTC_2    2   Memory Cycle Time Control - bit 2
BUSCON1.MCTC_1    1   Memory Cycle Time Control - bit 1
BUSCON1.MCTC_0    0   Memory Cycle Time Control - bit 0
BUSCON2          0xFF16   Bus Configuration Register 2
BUSCON2.CSWEN2    15  Write Chip Select Enable
BUSCON2.CSREN2    14  Read Chip Select Enable
BUSCON2.RDYEN2    12  READY Input Enable
BUSCON2.BUSACT2   10  Bus Active Control
BUSCON2.ALECTL2   9   ALE Lengthening Control
BUSCON2.EWEN2     8   Early Write Enable
BUSCON2.BTYP_7    7   External Bus Configuration - bit 7
BUSCON2.BTYP_6    6   External Bus Configuration - bit 6
BUSCON2.MTTC2     5   Memory Tristate Time Control
BUSCON2.RWDC2     4   Read/Write Delay Control for BUSCON
BUSCON2.MCTC_3    3   Memory Cycle Time Control - bit 3
BUSCON2.MCTC_2    2   Memory Cycle Time Control - bit 2
BUSCON2.MCTC_1    1   Memory Cycle Time Control - bit 1
BUSCON2.MCTC_0    0   Memory Cycle Time Control - bit 0
BUSCON3          0xFF18   Bus Configuration Register 3
BUSCON3.CSWEN3    15  Write Chip Select Enable
BUSCON3.CSREN3    14  Read Chip Select Enable
BUSCON3.RDYEN3    12  READY Input Enable
BUSCON3.BUSACT3   10  Bus Active Control
BUSCON3.ALECTL3   9   ALE Lengthening Control
BUSCON3.EWEN3     8   Early Write Enable
BUSCON3.BTYP_7    7   External Bus Configuration - bit 7
BUSCON3.BTYP_6    6   External Bus Configuration - bit 6
BUSCON3.MTTC3     5   Memory Tristate Time Control
BUSCON3.RWDC3     4   Read/Write Delay Control for BUSCON
BUSCON3.MCTC_3    3   Memory Cycle Time Control - bit 3
BUSCON3.MCTC_2    2   Memory Cycle Time Control - bit 2
BUSCON3.MCTC_1    1   Memory Cycle Time Control - bit 1
BUSCON3.MCTC_0    0   Memory Cycle Time Control - bit 0
BUSCON4          0xFF1A   Bus Configuration Register 4
BUSCON4.CSWEN4    15  Write Chip Select Enable
BUSCON4.CSREN4    14  Read Chip Select Enable
BUSCON4.RDYEN4    12  READY Input Enable
BUSCON4.BUSACT4   10  Bus Active Control
BUSCON4.ALECTL4   9   ALE Lengthening Control
BUSCON4.EWEN4     8   Early Write Enable
BUSCON4.BTYP_7    7   External Bus Configuration - bit 7
BUSCON4.BTYP_6    6   External Bus Configuration - bit 6
BUSCON4.MTTC4     5   Memory Tristate Time Control
BUSCON4.RWDC4     4   Read/Write Delay Control for BUSCON
BUSCON4.MCTC_3    3   Memory Cycle Time Control - bit 3
BUSCON4.MCTC_2    2   Memory Cycle Time Control - bit 2
BUSCON4.MCTC_1    1   Memory Cycle Time Control - bit 1
BUSCON4.MCTC_0    0   Memory Cycle Time Control - bit 0
ZEROS            0xFF1C   Constant Value 0sRegister'
ONES             0xFF1E   Constant Value 1sRegister'
T2CON            0xFF40   GPT1 Timer 2 Control Register
T2CON.T2IREN      15  Timer 2 Interrupt Enable
T2CON.T2RDIR      14  Timer 2 Rotation Direction
T2CON.T2CHDIR     13  Timer 2 Count Direction Change
T2CON.T2EDGE      12  Timer 2 Edge Detection
T2CON.T2RC        9   Timer 2 Remote Control
T2CON.T2UDE       8   Timer 2 External Up/Down Enable
T2CON.T2UD        7   Timer 2 Up / Down Control
T2CON.T2R         6   Timer 2 Run Bit
T2CON.T2M_5       5   Timer 2 Mode Control - bit 5
T2CON.T2M_4       4   Timer 2 Mode Control - bit 4
T2CON.T2M_3       3   Timer 2 Mode Control - bit 3
T2CON.T2I_2       2   Timer 2 Input Selection - bit 2
T2CON.T2I_1       1   Timer 2 Input Selection - bit 1
T2CON.T2I_0       0   Timer 2 Input Selection - bit 0
T3CON            0xFF42   GPT1 Timer 3 Control Register
T3CON.T3IREN      15  Timer 3 Interrupt Enable
T3CON.T3RDIR      14  Timer 3 Rotation Direction
T3CON.T3CHDIR     13  Timer 3 Count Direction Change
T3CON.T3EDGE      12  Timer 3 Edge Detection
T3CON.FM1         11  Fast Mode for Timer Block 1
T3CON.T3OTL       10  Timer 3 Output Toggle Latch
T3CON.T3OE        9   Alternate Output Function Enable
T3CON.T3UDE       8   Timer 3 External Up/Down Enable
T3CON.T3UD        7   Timer 3 Up / Down Control
T3CON.T3R         6   Timer 3 Run Bit
T3CON.T3M_5       5   Timer 3 Mode Control - bit 5
T3CON.T3M_4       4   Timer 3 Mode Control - bit 4
T3CON.T3M_3       3   Timer 3 Mode Control - bit 3
T3CON.T3I_2       2   Timer 3 Input Selection - bit 2
T3CON.T3I_1       1   Timer 3 Input Selection - bit 1
T3CON.T3I_0       0   Timer 3 Input Selection - bit 0
T4CON            0xFF44   GPT1 Timer 4 Control Register
T4CON.T4IREN      15  Timer 4 Interrupt Enable
T4CON.T4RDIR      14  Timer 4 Rotation Direction
T4CON.T4CHDIR     13  Timer 4 Count Direction Change
T4CON.T4EDGE      12  Timer 4 Edge Detection
T4CON.T4RC        9   Timer 4 Remote Control
T4CON.T4UD        7   Timer 4 Up / Down Control
T4CON.T4R         6   Timer 4 Run Bit
T4CON.T4M_5       5   Timer 4 Mode Control - bit 5
T4CON.T4M_4       4   Timer 4 Mode Control - bit 4
T4CON.T4M_3       3   Timer 4 Mode Control - bit 3
T4CON.T4I_2       2   Timer 4 Input Selection - bit 2
T4CON.T4I_1       1   Timer 4 Input Selection - bit 1
T4CON.T4I_0       0   Timer 4 Input Selection - bit 0
T5CON            0xFF46   GPT2 Timer 5 Control Register
T5CON.T5SC        15  Timer 5 Capture Mode Enable
T5CON.T5CLR       14  Timer 5 Clear Bit
T5CON.CI_13       13  Register CAPREL Capture Trigger Selection - bit 13
T5CON.CI_12       12  Register CAPREL Capture Trigger Selection - bit 12
T5CON.CC          11  Capture Correction
T5CON.T5RC        9   Timer 4 Remote Control
T5CON.T5UD        7   Timer 4 Up / Down Control
T5CON.T5R         6   Timer 4 Run Bit
T5CON.T5M_4       4   Timer 4 Mode Control - bit 4
T5CON.T5M_3       3   Timer 4 Mode Control - bit 3
T5CON.T5I_2       2   Timer 4 Input Selection - bit 2
T5CON.T5I_1       1   Timer 4 Input Selection - bit 1
T5CON.T5I_0       0   Timer 4 Input Selection - bit 0
T6CON            0xFF48   GPT2 Timer 6 Control Register
T6CON.T6SR        15  Timer 6 Reload Mode Enable
T6CON.T6CLR       14  Timer 6 Clear Bit
T6CON.FM2         11  Fast Mode for Timer Block 2
T6CON.T6OTL       10  Timer 6 Output Toggle Latch
T6CON.T6UD        7   Timer 6 Up / Down Control
T6CON.T6R         6   Timer 6 Run Bit
T6CON.T6M_5       5   Timer 6 Mode Control - bit 5
T6CON.T6M_4       4   Timer 6 Mode Control - bit 4
T6CON.T6M_3       3   Timer 6 Mode Control - bit 3
T6CON.T6I_2       2   Timer 6 Input Selection - bit 2
T6CON.T6I_1       1   Timer 6 Input Selection - bit 1
T6CON.T6I_0       0   Timer 6 Input Selection - bit 0
T2IC             0xFF60   GPT1 Timer 2 Interrupt Control Register
T2IC.T2IR         7   Interrupt Request Flag
T2IC.T2IE         6   Interrupt Enable Control Bit (individually enables/disables a specific source)
T2IC.ILVL_5       5   Interrupt Priority Level - bit 5
T2IC.ILVL_4       4   Interrupt Priority Level - bit 4
T2IC.ILVL_3       3   Interrupt Priority Level - bit 3
T2IC.ILVL_2       2   Interrupt Priority Level - bit 2
T2IC.GLVL_1       1   Group Level - bit 1
T2IC.GLVL_0       0   Group Level - bit 0
T3IC             0xFF62   GPT1 Timer 3 Interrupt Control Register
T3IC.T3IR         7   Interrupt Request Flag
T3IC.T3IE         6   Interrupt Enable Control Bit (individually enables/disables a specific source)
T3IC.ILVL_5       5   Interrupt Priority Level - bit 5
T3IC.ILVL_4       4   Interrupt Priority Level - bit 4
T3IC.ILVL_3       3   Interrupt Priority Level - bit 3
T3IC.ILVL_2       2   Interrupt Priority Level - bit 2
T3IC.GLVL_1       1   Group Level - bit 1
T3IC.GLVL_0       0   Group Level - bit 0
T4IC             0xFF64   GPT1 Timer 4 Interrupt Control Register
T4IC.T4IR         7   Interrupt Request Flag
T4IC.T4IE         6   Interrupt Enable Control Bit (individually enables/disables a specific source)
T4IC.ILVL_5       5   Interrupt Priority Level - bit 5
T4IC.ILVL_4       4   Interrupt Priority Level - bit 4
T4IC.ILVL_3       3   Interrupt Priority Level - bit 3
T4IC.ILVL_2       2   Interrupt Priority Level - bit 2
T4IC.GLVL_1       1   Group Level - bit 1
T4IC.GLVL_0       0   Group Level - bit 0
T5IC             0xFF66   GPT2 Timer 5 Interrupt Control Register
T5IC.T5IR         7   Interrupt Request Flag
T5IC.T5IE         6   Interrupt Enable Control Bit (individually enables/disables a specific source)
T5IC.ILVL_5       5   Interrupt Priority Level - bit 5
T5IC.ILVL_4       4   Interrupt Priority Level - bit 4
T5IC.ILVL_3       3   Interrupt Priority Level - bit 3
T5IC.ILVL_2       2   Interrupt Priority Level - bit 2
T5IC.GLVL_1       1   Group Level - bit 1
T5IC.GLVL_0       0   Group Level - bit 0
T6IC             0xFF68   GPT2 Timer 6 Interrupt Control Register
T6IC.T2IR         7   Interrupt Request Flag
T6IC.T2IE         6   Interrupt Enable Control Bit (individually enables/disables a specific source)
T6IC.ILVL_5       5   Interrupt Priority Level - bit 5
T6IC.ILVL_4       4   Interrupt Priority Level - bit 4
T6IC.ILVL_3       3   Interrupt Priority Level - bit 3
T6IC.ILVL_2       2   Interrupt Priority Level - bit 2
T6IC.GLVL_1       1   Group Level - bit 1
T6IC.GLVL_0       0   Group Level - bit 0
CRIC             0xFF6A   GPT2 CAPREL Interrupt Control Register
CRIC.CRIR         7   Interrupt Request Flag
CRIC.CRIE         6   Interrupt Enable Control Bit (individually enables/disables a specific source)
CRIC.ILVL_5       5   Interrupt Priority Level - bit 5
CRIC.ILVL_4       4   Interrupt Priority Level - bit 4
CRIC.ILVL_3       3   Interrupt Priority Level - bit 3
CRIC.ILVL_2       2   Interrupt Priority Level - bit 2
CRIC.GLVL_1       1   Group Level - bit 1
CRIC.GLVL_0       0   Group Level - bit 0
S0TIC            0xFF6C   Serial Channel 0 Transmit Interrupt Control Register
S0TIC.S0TIR       7   Interrupt Request Flag
S0TIC.S0TIE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
S0TIC.ILVL_5      5   Interrupt Priority Level - bit 5
S0TIC.ILVL_4      4   Interrupt Priority Level - bit 4
S0TIC.ILVL_3      3   Interrupt Priority Level - bit 3
S0TIC.ILVL_2      2   Interrupt Priority Level - bit 2
S0TIC.GLVL_1      1   Group Level - bit 1
S0TIC.GLVL_0      0   Group Level - bit 0
S0RIC            0xFF6E   Serial Channel 0 Receive Interrupt Control Register
S0RIC.S0RIR       7   Interrupt Request Flag
S0RIC.S0RIE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
S0RIC.ILVL_5      5   Interrupt Priority Level - bit 5
S0RIC.ILVL_4      4   Interrupt Priority Level - bit 4
S0RIC.ILVL_3      3   Interrupt Priority Level - bit 3
S0RIC.ILVL_2      2   Interrupt Priority Level - bit 2
S0RIC.GLVL_1      1   Group Level - bit 1
S0RIC.GLVL_0      0   Group Level - bit 0
S0EIC            0xFF70   Serial Channel 0 Error Interrupt Control Register
S0EIC.S0EIR       7   Interrupt Request Flag
S0EIC.S0EIE       6   Interrupt Enable Control Bit (individually enables/disables a specific source)
S0EIC.ILVL_5      5   Interrupt Priority Level - bit 5
S0EIC.ILVL_4      4   Interrupt Priority Level - bit 4
S0EIC.ILVL_3      3   Interrupt Priority Level - bit 3
S0EIC.ILVL_2      2   Interrupt Priority Level - bit 2
S0EIC.GLVL_1      1   Group Level - bit 1
S0EIC.GLVL_0      0   Group Level - bit 0
SSCTIC           0xFF72   SSC Transmit Interrupt Control Register
SSCTIC.SSCTIR     7   Interrupt Request Flag
SSCTIC.SSCTIE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
SSCTIC.ILVL_5     5   Interrupt Priority Level - bit 5
SSCTIC.ILVL_4     4   Interrupt Priority Level - bit 4
SSCTIC.ILVL_3     3   Interrupt Priority Level - bit 3
SSCTIC.ILVL_2     2   Interrupt Priority Level - bit 2
SSCTIC.GLVL_1     1   Group Level - bit 1
SSCTIC.GLVL_0     0   Group Level - bit 0
SSCRIC           0xFF74   SSC Receive Interrupt Control Register
SSCRIC.SSCRIR     7   Interrupt Request Flag
SSCRIC.SSCRIE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
SSCRIC.ILVL_5     5   Interrupt Priority Level - bit 5
SSCRIC.ILVL_4     4   Interrupt Priority Level - bit 4
SSCRIC.ILVL_3     3   Interrupt Priority Level - bit 3
SSCRIC.ILVL_2     2   Interrupt Priority Level - bit 2
SSCRIC.GLVL_1     1   Group Level - bit 1
SSCRIC.GLVL_0     0   Group Level - bit 0
SSCEIC           0xFF76   SSC Error Interrupt Control Register
SSCEIC.SSCEIR     7   Interrupt Request Flag
SSCEIC.SSCEIE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
SSCEIC.ILVL_5     5   Interrupt Priority Level - bit 5
SSCEIC.ILVL_4     4   Interrupt Priority Level - bit 4
SSCEIC.ILVL_3     3   Interrupt Priority Level - bit 3
SSCEIC.ILVL_2     2   Interrupt Priority Level - bit 2
SSCEIC.GLVL_1     1   Group Level - bit 1
SSCEIC.GLVL_0     0   Group Level - bit 0
URD3IC           0xFF78   UDC RX Done3  Interrupt Control Register
URD3IC.URD3IR     7   Interrupt Request Flag
URD3IC.URD3IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
URD3IC.ILVL_5     5   Interrupt Priority Level - bit 5
URD3IC.ILVL_4     4   Interrupt Priority Level - bit 4
URD3IC.ILVL_3     3   Interrupt Priority Level - bit 3
URD3IC.ILVL_2     2   Interrupt Priority Level - bit 2
URD3IC.GLVL_1     1   Group Level - bit 1
URD3IC.GLVL_0     0   Group Level - bit 0
URD4IC           0xFF7A   UDC RX Done4  Interrupt Control Register
URD4IC.URD4IR     7   Interrupt Request Flag
URD4IC.URD4IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
URD4IC.ILVL_5     5   Interrupt Priority Level - bit 5
URD4IC.ILVL_4     4   Interrupt Priority Level - bit 4
URD4IC.ILVL_3     3   Interrupt Priority Level - bit 3
URD4IC.ILVL_2     2   Interrupt Priority Level - bit 2
URD4IC.GLVL_1     1   Group Level - bit 1
URD4IC.GLVL_0     0   Group Level - bit 0
URD5IC           0xFF7C   UDC RX Done5  Interrupt Control Register
URD5IC.URD5IR     7   Interrupt Request Flag
URD5IC.URD5IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
URD5IC.ILVL_5     5   Interrupt Priority Level - bit 5
URD5IC.ILVL_4     4   Interrupt Priority Level - bit 4
URD5IC.ILVL_3     3   Interrupt Priority Level - bit 3
URD5IC.ILVL_2     2   Interrupt Priority Level - bit 2
URD5IC.GLVL_1     1   Group Level - bit 1
URD5IC.GLVL_0     0   Group Level - bit 0
URD6IC           0xFF7E   UDC RX Done6  Interrupt Control Register
URD6IC.URD6IR     7   Interrupt Request Flag
URD6IC.URD6IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
URD6IC.ILVL_5     5   Interrupt Priority Level - bit 5
URD6IC.ILVL_4     4   Interrupt Priority Level - bit 4
URD6IC.ILVL_3     3   Interrupt Priority Level - bit 3
URD6IC.ILVL_2     2   Interrupt Priority Level - bit 2
URD6IC.GLVL_1     1   Group Level - bit 1
URD6IC.GLVL_0     0   Group Level - bit 0
URD7IC           0xFF80   UDC RX Done7  Interrupt Control Register
URD7IC.URD7IR     7   Interrupt Request Flag
URD7IC.URD7IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
URD7IC.ILVL_5     5   Interrupt Priority Level - bit 5
URD7IC.ILVL_4     4   Interrupt Priority Level - bit 4
URD7IC.ILVL_3     3   Interrupt Priority Level - bit 3
URD7IC.ILVL_2     2   Interrupt Priority Level - bit 2
URD7IC.GLVL_1     1   Group Level - bit 1
URD7IC.GLVL_0     0   Group Level - bit 0
UTD0IC           0xFF82   UDC TX Done0  Interrupt Control Register
UTD0IC.UTD0IR     7   Interrupt Request Flag
UTD0IC.UTD0IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
UTD0IC.ILVL_5     5   Interrupt Priority Level - bit 5
UTD0IC.ILVL_4     4   Interrupt Priority Level - bit 4
UTD0IC.ILVL_3     3   Interrupt Priority Level - bit 3
UTD0IC.ILVL_2     2   Interrupt Priority Level - bit 2
UTD0IC.GLVL_1     1   Group Level - bit 1
UTD0IC.GLVL_0     0   Group Level - bit 0
UTD1IC           0xFF84   UDC TX Done1  Interrupt Control Register
UTD1IC.UTD1IR     7   Interrupt Request Flag
UTD1IC.UTD1IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
UTD1IC.ILVL_5     5   Interrupt Priority Level - bit 5
UTD1IC.ILVL_4     4   Interrupt Priority Level - bit 4
UTD1IC.ILVL_3     3   Interrupt Priority Level - bit 3
UTD1IC.ILVL_2     2   Interrupt Priority Level - bit 2
UTD1IC.GLVL_1     1   Group Level - bit 1
UTD1IC.GLVL_0     0   Group Level - bit 0
UTD2IC           0xFF86   UDC TX Done2  Interrupt Control Register
UTD2IC.UTD2IR     7   Interrupt Request Flag
UTD2IC.UTD2IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
UTD2IC.ILVL_5     5   Interrupt Priority Level - bit 5
UTD2IC.ILVL_4     4   Interrupt Priority Level - bit 4
UTD2IC.ILVL_3     3   Interrupt Priority Level - bit 3
UTD2IC.ILVL_2     2   Interrupt Priority Level - bit 2
UTD2IC.GLVL_1     1   Group Level - bit 1
UTD2IC.GLVL_0     0   Group Level - bit 0
FEI0IC           0xFF88   Fast External Interrupt 0 Control Register
FEI0IC.FEI0IR     7   Interrupt Request Flag
FEI0IC.FEI0IE     6   Interrupt Enable Control Bit (individually enables/disables a specific source)
FEI0IC.ILVL_5     5   Interrupt Priority Level - bit 5
FEI0IC.ILVL_4     4   Interrupt Priority Level - bit 4
FEI0IC.ILVL_3     3   Interrupt Priority Level - bit 3
FEI0IC.ILVL_2     2   Interrupt Priority Level - bit 2
FEI0IC.GLVL_1     1   Group Level - bit 1
FEI0IC.GLVL_0     0   Group Level - bit 0
FEI1IC           0xFF8A   Fast External Interrupt 1 Control Register
FEI1IC.FEI1IR     7   Interrupt Request Flag
FEI1IC.FEI1IE     6   Interrupt Enable Control Bit
FEI1IC.ILVL_5     5   Interrupt Priority Level - bit 5
FEI1IC.ILVL_4     4   Interrupt Priority Level - bit 4
FEI1IC.ILVL_3     3   Interrupt Priority Level - bit 3
FEI1IC.ILVL_2     2   Interrupt Priority Level - bit 2
FEI1IC.GLVL_1     1   Group Level - bit 1
FEI1IC.GLVL_0     0   Group Level - bit 0
FEI2IC           0xFF8C   Fast External Interrupt 2 Control Register
FEI2IC.FEI2IR     7   Interrupt Request Flag
FEI2IC.FEI2IE     6   Interrupt Enable Control Bit
FEI2IC.ILVL_5     5   Interrupt Priority Level - bit 5
FEI2IC.ILVL_4     4   Interrupt Priority Level - bit 4
FEI2IC.ILVL_3     3   Interrupt Priority Level - bit 3
FEI2IC.ILVL_2     2   Interrupt Priority Level - bit 2
FEI2IC.GLVL_1     1   Group Level - bit 1
FEI2IC.GLVL_0     0   Group Level - bit 0
FEI3IC           0xFF8E   Fast External Interrupt 3 Control Register
FEI3IC.FEI3IR     7   Interrupt Request Flag
FEI3IC.FEI3IE     6   Interrupt Enable Control Bit
FEI3IC.ILVL_5     5   Interrupt Priority Level - bit 5
FEI3IC.ILVL_4     4   Interrupt Priority Level - bit 4
FEI3IC.ILVL_3     3   Interrupt Priority Level - bit 3
FEI3IC.ILVL_2     2   Interrupt Priority Level - bit 2
FEI3IC.GLVL_1     1   Group Level - bit 1
FEI3IC.GLVL_0     0   Group Level - bit 0
FEI4IC           0xFF90   Fast External Interrupt 4 Control Register
FEI4IC.FEI4IR     7   Interrupt Request Flag
FEI4IC.FEI4IE     6   Interrupt Enable Control Bit
FEI4IC.ILVL_5     5   Interrupt Priority Level - bit 5
FEI4IC.ILVL_4     4   Interrupt Priority Level - bit 4
FEI4IC.ILVL_3     3   Interrupt Priority Level - bit 3
FEI4IC.ILVL_2     2   Interrupt Priority Level - bit 2
FEI4IC.GLVL_1     1   Group Level - bit 1
FEI4IC.GLVL_0     0   Group Level - bit 0
FEI5IC           0xFF92   Fast External Interrupt 5 Control Register
FEI5IC.FEI5IR     7   Interrupt Request Flag
FEI5IC.FEI5IE     6   Interrupt Enable Control Bit
FEI5IC.ILVL_5     5   Interrupt Priority Level - bit 5
FEI5IC.ILVL_4     4   Interrupt Priority Level - bit 4
FEI5IC.ILVL_3     3   Interrupt Priority Level - bit 3
FEI5IC.ILVL_2     2   Interrupt Priority Level - bit 2
FEI5IC.GLVL_1     1   Group Level - bit 1
FEI5IC.GLVL_0     0   Group Level - bit 0
FEI6IC           0xFF94   Fast External Interrupt 6 Control Register
FEI6IC.FEI6IR     7   Interrupt Request Flag
FEI6IC.FEI6IE     6   Interrupt Enable Control Bit
FEI6IC.ILVL_5     5   Interrupt Priority Level - bit 5
FEI6IC.ILVL_4     4   Interrupt Priority Level - bit 4
FEI6IC.ILVL_3     3   Interrupt Priority Level - bit 3
FEI6IC.ILVL_2     2   Interrupt Priority Level - bit 2
FEI6IC.GLVL_1     1   Group Level - bit 1
FEI6IC.GLVL_0     0   Group Level - bit 0
FEI7IC           0xFF96   Fast External Interrupt 7 Control Register
FEI7IC.FEI7IR     7   Interrupt Request Flag
FEI7IC.FEI7IE     6   Interrupt Enable Control Bit
FEI7IC.ILVL_5     5   Interrupt Priority Level - bit 5
FEI7IC.ILVL_4     4   Interrupt Priority Level - bit 4
FEI7IC.ILVL_3     3   Interrupt Priority Level - bit 3
FEI7IC.ILVL_2     2   Interrupt Priority Level - bit 2
FEI7IC.GLVL_1     1   Group Level - bit 1
FEI7IC.GLVL_0     0   Group Level - bit 0
RES4IC           0xFF98   reserved
IOMIOIC          0xFF9A   IOM-2 IO Interrupt Control Register
IOMIOIC.IOMIOIR   7   Interrupt Request Flag           
IOMIOIC.IOMIOIE   6   Interrupt Enable Control Bit     
IOMIOIC.ILVL_5    5   Interrupt Priority Level - bit 5 
IOMIOIC.ILVL_4    4   Interrupt Priority Level - bit 4 
IOMIOIC.ILVL_3    3   Interrupt Priority Level - bit 3 
IOMIOIC.ILVL_2    2   Interrupt Priority Level - bit 2 
IOMIOIC.GLVL_1    1   Group Level - bit 1              
IOMIOIC.GLVL_0    0   Group Level - bit 0              
URD2IC           0xFF9C   UDC RX Done2  Interrupt Control Register
URD2IC.URD2IR     7   Interrupt Request Flag          
URD2IC.URD2IE     6   Interrupt Enable Control Bit    
URD2IC.ILVL_5     5   Interrupt Priority Level - bit 5
URD2IC.ILVL_4     4   Interrupt Priority Level - bit 4
URD2IC.ILVL_3     3   Interrupt Priority Level - bit 3
URD2IC.ILVL_2     2   Interrupt Priority Level - bit 2
URD2IC.GLVL_1     1   Group Level - bit 1             
URD2IC.GLVL_0     0   Group Level - bit 0             
URD1IC           0xFF9E   UDC RX Done1  Interrupt Control Register
URD1IC.URD1IR     7   Interrupt Request Flag          
URD1IC.URD1IE     6   Interrupt Enable Control Bit    
URD1IC.ILVL_5     5   Interrupt Priority Level - bit 5
URD1IC.ILVL_4     4   Interrupt Priority Level - bit 4
URD1IC.ILVL_3     3   Interrupt Priority Level - bit 3
URD1IC.ILVL_2     2   Interrupt Priority Level - bit 2
URD1IC.GLVL_1     1   Group Level - bit 1             
URD1IC.GLVL_0     0   Group Level - bit 0             
CLISNC           0xFFA8   The channel link interrupt subnode register
CLISNC.C6IR       13  Channel Service Request Flag
CLISNC.C6IE       12  Channel Link Interrupt Enable Bit
CLISNC.C4IR       9   Channel Service Request Flag
CLISNC.C4IE       8   Channel Link Interrupt Enable Bit
CLISNC.C2IR       5   Channel Service Request Flag
CLISNC.C2IE       4   Channel Link Interrupt Enable Bit
CLISNC.C0IR       1   Channel Service Request Flag
CLISNC.C0IE       0   Channel Link Interrupt Enable Bit
FOCON            0xFFAA   Frequency Output Control Register
FOCON.FOEN        15  Frequency Output Enable
FOCON.FOSS        14  Frequency Output Signal Select
FOCON.FORV_13     13  Frequency Output Reload Value - bit 13
FOCON.FORV_12     12  Frequency Output Reload Value - bit 12
FOCON.FORV_11     11  Frequency Output Reload Value - bit 11
FOCON.FORV_10     10  Frequency Output Reload Value - bit 10
FOCON.FORV_9      9   Frequency Output Reload Value - bit 9 
FOCON.FORV_8      8   Frequency Output Reload Value - bit 8 
FOCON.FOTL        6   Frequency Output Toggle Latch
FOCON.FOCNT_5     5   Frequency Output Counter - bit 5
FOCON.FOCNT_4     4   Frequency Output Counter - bit 4
FOCON.FOCNT_3     3   Frequency Output Counter - bit 3
FOCON.FOCNT_2     2   Frequency Output Counter - bit 2
FOCON.FOCNT_1     1   Frequency Output Counter - bit 1
FOCON.FOCNT_0     0   Frequency Output Counter - bit 0
TFR              0xFFAC   Trap Flag Register
TFR.NMI           15  Non Maskable Interrupt Flag
TFR.STKOF         14  Stack Overflow Flag
TFR.STKUF         13  Stack Underflow Flag
TFR.UNDOPC        7   Undefined Opcode Flag
TFR.PRTFLT        3   Protection Fault Flag
TFR.ILLOPA        2   Illegal Word Operand Access Flag
TFR.ILLINA        1   Illegal Instruction Access Flag
TFR.ILLBUS        0   Illegal External Bus Access Flag
WDTCON           0xFFAE   Watchdog Timer Control Register
WDTCON.WDTREL_15  15  Watchdog Timer Reload Value - bit 15
WDTCON.WDTREL_14  14  Watchdog Timer Reload Value - bit 14
WDTCON.WDTREL_13  13  Watchdog Timer Reload Value - bit 13
WDTCON.WDTREL_12  12  Watchdog Timer Reload Value - bit 12
WDTCON.WDTREL_11  11  Watchdog Timer Reload Value - bit 11
WDTCON.WDTREL_10  10  Watchdog Timer Reload Value - bit 10
WDTCON.WDTREL_9   9   Watchdog Timer Reload Value - bit 9 
WDTCON.WDTREL_8   8   Watchdog Timer Reload Value - bit 8 
WDTCON.LHWR       4   Long Hardware Reset Indication Flag
WDTCON.SHWR       3   Short Hardware Reset Indication Flag
WDTCON.SWR        2   Software Reset Indication Flag
WDTCON.WDTR       1   Watchdog Timer Reset Indication Flag
WDTCON.WDTIN      0   Watchdog Timer Input Frequency Select
S0CON            0xFFB0   Serial Channel 0 Control Register
S0CON.R           15  Baudrate Generator Run Bit
S0CON.LB          14  LoopBack Mode Enable Bit
S0CON.BRS         13  Baudrate Selection Bit
S0CON.ODD         12  Parity Selection Bit
S0CON.FDE         11  Fractional Divider Enable
S0CON.OE          10  Overrun Error Flag
S0CON.FE          9   Framing Error Flag
S0CON.PE          8   Parity Error Flag
S0CON.OEN         7   Overrun Check Enable Bit
S0CON.FEN         6   Framing Check Enable Bit
S0CON.PEN_RXDI    5   Parity Check Enable / IrDA Input Inverter Enable
S0CON.REN         4   Receiver Enable Bit
S0CON.STP         3   Number of Stop Bits Selection
S0CON.M_2         2   ASC0 Mode Control - bit 2
S0CON.M_1         1   ASC0 Mode Control - bit 1
S0CON.M_0         0   ASC0 Mode Control - bit 0
SSCCON           0xFFB2   SSC Control Register
S0CLC            0xFFBA   ASC Clock Control Register
S0CLC.EXDISR      3   External Disable Request
S0CLC.SUSPEN      2   Peripheral Suspend Enable Bit for OCDS
S0CLC.S0DISS      1   ASC Disable Status Bit
S0CLC.S0DISR      0   ASC Disable Request Bit
P2               0xFFC0   Port 2 Register
P2.P2_7           7   Port data register P2 bit 7 
P2.P2_6           6   Port data register P2 bit 6 
P2.P2_5           5   Port data register P2 bit 5 
P2.P2_4           4   Port data register P2 bit 4 
P2.P2_3           3   Port data register P2 bit 3 
P2.P2_2           2   Port data register P2 bit 2 
P2.P2_1           1   Port data register P2 bit 1 
P2.P2_0           0   Port data register P2 bit 0 
DP2              0xFFC2   Port 2 Direction Control Register
DP2.DP2_7         7   Port direction register DP2 bit 7
DP2.DP2_6         6   Port direction register DP2 bit 6
DP2.DP2_5         5   Port direction register DP2 bit 5
DP2.DP2_4         4   Port direction register DP2 bit 4
DP2.DP2_3         3   Port direction register DP2 bit 3
DP2.DP2_2         2   Port direction register DP2 bit 2
DP2.DP2_1         1   Port direction register DP2 bit 1
DP2.DP2_0         0   Port direction register DP2 bit 0
P3               0xFFC4   Port 3 Register
P3.P3_15          15  Port data register P3 bit 15
P3.P3_13          13  Port data register P3 bit 13
P3.P3_12          12  Port data register P3 bit 12
P3.P3_11          11  Port data register P3 bit 11
P3.P3_10          10  Port data register P3 bit 10
P3.P3_9           9   Port data register P3 bit 9 
P3.P3_8           8   Port data register P3 bit 8 
P3.P3_6           6   Port data register P3 bit 6 
P3.P3_5           5   Port data register P3 bit 5 
P3.P3_3           3   Port data register P3 bit 3 
DP3              0xFFC6   Port 3 Direction Control Register
DP3.DP3_15        15  Port direction register DP3 bit 15
DP3.DP3_13        13  Port direction register DP3 bit 13
DP3.DP3_12        12  Port direction register DP3 bit 12
DP3.DP3_11        11  Port direction register DP3 bit 11
DP3.DP3_10        10  Port direction register DP3 bit 10
DP3.DP3_9         9   Port direction register DP3 bit 9 
DP3.DP3_8         8   Port direction register DP3 bit 8 
DP3.DP3_6         6   Port direction register DP3 bit 6 
DP3.DP3_5         5   Port direction register DP3 bit 5 
DP3.DP3_3         3   Port direction register DP3 bit 3 
P4               0xFFC8   Port 4 Register (8 bits)
P4.P4_6           6   Port data register P4 bit 6
P4.P4_5           5   Port data register P4 bit 5
P4.P4_4           4   Port data register P4 bit 4 
P4.P4_3           3   Port data register P4 bit 3 
P4.P4_2           2   Port data register P4 bit 2 
P4.P4_1           1   Port data register P4 bit 1 
P4.P4_0           0   Port data register P4 bit 0 
DP4              0xFFCA   Port 4 Direction Control Register
DP4.DP4_6         6   Port direction register DP4 bit 6
DP4.DP4_5         5   Port direction register DP4 bit 5
DP4.DP4_4         4   Port direction register DP4 bit 4 
DP4.DP4_3         3   Port direction register DP4 bit 3 
DP4.DP4_2         2   Port direction register DP4 bit 2 
DP4.DP4_1         1   Port direction register DP4 bit 1 
DP4.DP4_0         0   Port direction register DP4 bit 0 
P6               0xFFCC   Port 6 Register (8 bits)
P6.P6_7           7   Port data register P6 bit 7 
P6.P6_6           6   Port data register P6 bit 6 
P6.P6_5           5   Port data register P6 bit 5 
P6.P6_4           4   Port data register P6 bit 4
P6.P6_3           3   Port data register P6 bit 3 
P6.P6_2           2   Port data register P6 bit 2 
P6.P6_1           1   Port data register P6 bit 1 
P6.P6_0           0   Port data register P6 bit 0 
DP6              0xFFCE   Port 6 Direction Control Register
DP6.DP6_7         7   Port direction register DP6 bit 7 
DP6.DP6_6         6   Port direction register DP6 bit 6 
DP6.DP6_5         5   Port direction register DP6 bit 5 
DP6.DP6_4         4   Port direction register DP6 bit 4
DP6.DP6_3         3   Port direction register DP6 bit 3 
DP6.DP6_2         2   Port direction register DP6 bit 2 
DP6.DP6_1         1   Port direction register DP6 bit 1 
DP6.DP6_0         0   Port direction register DP6 bit 0 
P7               0xFFD0   Port 7 Register (8 bits)
P7.P7_5           5   Port data register P7 bit 5 
P7.P7_4           4   Port data register P7 bit 4 
P7.P7_3           3   Port data register P7 bit 3 
P7.P7_2           2   Port data register P7 bit 2 
P7.P7_1           1   Port data register P7 bit 1 
P7.P7_0           0   Port data register P7 bit 0 
DP7              0xFFD2   Port 7 Direction Control Register
DP7.DP7_5         5   Port direction register DP7 bit 5
DP7.DP7_4         4   Port direction register DP7 bit 4
DP7.DP7_3         3   Port direction register DP7 bit 3
DP7.DP7_2         2   Port direction register DP7 bit 2
DP7.DP7_1         1   Port direction register DP7 bit 1
DP7.DP7_0         0   Port direction register DP7 bit 0


.C167CR_SR
; 167crum.pdf, 167crds.pdf

; C167CR-LM     (RAM 4 KB)
; C167CR-L33M   (RAM 4 KB)
; C167CR-4RM    (ROM 32 KB RAM 4 KB)
; C167CR-16RM   (ROM 128 KB RAM 4 KB)
; C167SR-LM     (RAM 4 KB)
; C167CS-LM     (RAM 11 KB)
; C167CS-4RM    (ROM 32 KB RAM 11 KB)


; MEMORY MAP
area CODE ROM            0x0000:0x8000   Internal ROM area
area CODE MEM_EXT        0x8000:0xE000   Ext. Memory
area DATA XRAM           0xE000:0xE800
area BSS  RESERVED       0xE800:0xEF00
area DATA CAN1           0xEF00:0xF000
area DATA E_SFR          0xF000:0xF200   ESFR Area
area BSS  RESERVED       0xF200:0xF600
area CODE IRAM           0xF600:0xFE00
area DATA SFR            0xFE00:0x10000  SFR Area


; Interrupt and reset vector assignments
entry RESET     0x0000   RESET
entry NMITRAP   0x0008   NMITRAP Non-Maskable Interrupt (Class A Hardware Traps)
entry STOTRAP   0x0010   STOTRAP Stack Overflow (Class A Hardware Traps)
entry STUTRAP   0x0018   STUTRAP Stack Underflow (Class A Hardware Traps)
entry BTRAP     0x0028   BTRAP Class B Hardware Traps
entry CC0INT    0x0040   CAPCOM Register 0
entry CC1INT    0x0044   CAPCOM Register 1
entry CC2INT    0x0048   CAPCOM Register 2
entry CC3INT    0x004C   CAPCOM Register 3
entry CC4INT    0x0050   CAPCOM Register 4
entry CC5INT    0x0054   CAPCOM Register 5
entry CC6INT    0x0058   CAPCOM Register 6
entry CC7INT    0x005C   CAPCOM Register 7
entry CC8INT    0x0060   CAPCOM Register 8
entry CC9INT    0x0064   CAPCOM Register 9
entry CC10INT   0x0068   CAPCOM Register 10
entry CC11INT   0x006C   CAPCOM Register 11
entry CC12INT   0x0070   CAPCOM Register 12
entry CC13INT   0x0074   CAPCOM Register 13
entry CC14INT   0x0078   CAPCOM Register 14
entry CC15INT   0x007C   CAPCOM Register 15
entry T0INT     0x0080   CAPCOM Timer 0 
entry T1INT     0x0084   CAPCOM Timer 1 
entry T2INT     0x0088   GPT1 Timer 2 
entry T3INT     0x008C   GPT1 Timer 3 
entry T4INT     0x0090   GPT1 Timer 4 
entry T5INT     0x0094   GPT2 Timer 5 
entry T6INT     0x0098   GPT2 Timer 6 
entry CRINT     0x009C   GPT2 CAPREL Reg. 
entry ADCINT    0x00A0   A/D Conversion Complete 
entry ADEINT    0x00A4   A/D Overrun Error 
entry S0TINT    0x00A8   ASC0 Transmit 
entry S0RINT    0x00AC   ASC0 Receive 
entry S0EINT    0x00B0   ASC0 Error 
entry SCTINT    0x00B4   SSC Transmit 
entry SCRINT    0x00B8   SSC Receive 
entry SCEINT    0x00BC   SSC Error 
entry CC16INT   0x00C0   CAPCOM Register 16 
entry CC17INT   0x00C4   CAPCOM Register 17 
entry CC18INT   0x00C8   CAPCOM Register 18 
entry CC19INT   0x00CC   CAPCOM Register 19 
entry CC20INT   0x00D0   CAPCOM Register 20 
entry CC21INT   0x00D4   CAPCOM Register 21 
entry CC22INT   0x00D8   CAPCOM Register 22 
entry CC23INT   0x00DC   CAPCOM Register 23 
entry CC24INT   0x00E0   CAPCOM Register 24 
entry CC25INT   0x00E4   CAPCOM Register 25 
entry CC26INT   0x00E8   CAPCOM Register 26 
entry CC27INT   0x00EC   CAPCOM Register 27 
entry CC28INT   0x00F0   CAPCOM Register 28 
entry T7INT     0x00F4   CAPCOM Timer 7 
entry T8INT     0x00F8   CAPCOM Timer 8 
entry PWMINT    0x00FC   PWM Channel 0_3 
entry XP0INT    0x0100   CAN1 
entry XP1INT    0x0104   Unassigned node 
entry XP2INT    0x0108   Unassigned node 
entry XP3INT    0x010C   PLL/OWD 
entry CC29INT   0x0110   CAPCOM Register 29 
entry CC30INT   0x0114   CAPCOM Register 30 
entry CC31INT   0x0118   CAPCOM Register 31 
entry S0TBINT   0x011C   ASC0 Transmit Buffer 


; INPUT/OUTPUT PORTS
CSR              0xEF00   CAN1 Control/Status Register
CSR.BOFF          15  Busoff Status
CSR.EWRN          14  Error Warning Status
CSR.RXOK          12  Received Message Successfully
CSR.TXOK          11  Transmitted Message Successfully
CSR.LEC10         10  Last Error Code bit 10
CSR.LEC9          9   Last Error Code bit 9 
CSR.LEC8          8   Last Error Code bit 8 
CSR.TM            7   Test Mode
CSR.CCE           6   Configuration Change Enable
CSR.CPS           4   Clock Prescaler Control Bit
CSR.EIE           3   Error Interrupt Enable
CSR.SIE           2   Status Change Interrupt Enable
CSR.IE            1   Interrupt Enable
CSR.INIT          0   Initialization
IR               0xEF02   CAN1 Interrupt Register
IR.INTID7         7   Interrupt Identifier bit 7
IR.INTID6         6   Interrupt Identifier bit 6
IR.INTID5         5   Interrupt Identifier bit 5
IR.INTID4         4   Interrupt Identifier bit 4
IR.INTID3         3   Interrupt Identifier bit 3
IR.INTID2         2   Interrupt Identifier bit 2
IR.INTID1         1   Interrupt Identifier bit 1
IR.INTID0         0   Interrupt Identifier bit 0
BTR              0xEF04   CAN1 Bit Timing Register
BTR.TSEG2_14      14  Time Segment after sample point bit 14
BTR.TSEG2_13      13  Time Segment after sample point bit 13
BTR.TSEG2_12      12  Time Segment after sample point bit 12
BTR.TSEG1_11      11  Time Segment before sample point bit 11
BTR.TSEG1_10      10  Time Segment before sample point bit 10
BTR.TSEG1_9       9   Time Segment before sample point bit 9 
BTR.TSEG1_8       8   Time Segment before sample point bit 8 
BTR.SJW7          7   (Re)Synchronization Jump Width bit 7
BTR.SJW6          6   (Re)Synchronization Jump Width bit 6
BTR.BRP5          5   Baud Rate Prescaler bit 5
BTR.BRP4          4   Baud Rate Prescaler bit 4
BTR.BRP3          3   Baud Rate Prescaler bit 3
BTR.BRP2          2   Baud Rate Prescaler bit 2
BTR.BRP1          1   Baud Rate Prescaler bit 1
BTR.BRP0          0   Baud Rate Prescaler bit 0
GMS              0xEF06   CAN1 Global Mask Short
GMS.ID20          15  Identifier 20
GMS.ID19          14  Identifier 19
GMS.ID18          13  Identifier 18
GMS.ID28          7   Identifier 28
GMS.ID27          6   Identifier 27
GMS.ID26          5   Identifier 26
GMS.ID25          4   Identifier 25
GMS.ID24          3   Identifier 24
GMS.ID23          2   Identifier 23
GMS.ID22          1   Identifier 22
GMS.ID21          0   Identifier 21
UGML             0xEF08   CAN1 Upper Global Mask Long
UGML.ID20         15  Identifier 20
UGML.ID19         14  Identifier 19
UGML.ID18         13  Identifier 18
UGML.ID17         12  Identifier 17
UGML.ID16         11  Identifier 16
UGML.ID15         10  Identifier 15
UGML.ID14         9   Identifier 14
UGML.ID13         8   Identifier 13
UGML.ID28         7   Identifier 28
UGML.ID27         6   Identifier 27
UGML.ID26         5   Identifier 26
UGML.ID25         4   Identifier 25
UGML.ID24         3   Identifier 24
UGML.ID23         2   Identifier 23
UGML.ID22         1   Identifier 22
UGML.ID21         0   Identifier 21
LGML             0xEF0A   CAN1 Lower Global Mask Long
LGML.ID4          15  Identifier 4 
LGML.ID3          14  Identifier 3 
LGML.ID2          13  Identifier 2 
LGML.ID1          12  Identifier 1 
LGML.ID0          11  Identifier 0 
LGML.ID12         7   Identifier 12
LGML.ID11         6   Identifier 11
LGML.ID10         5   Identifier 10
LGML.ID9          4   Identifier 9 
LGML.ID8          3   Identifier 8 
LGML.ID7          2   Identifier 7 
LGML.ID6          1   Identifier 6 
LGML.ID5          0   Identifier 5 
UMLM             0xEF0C   CAN1 Upper Mask of Last Message
UMLM.ID20         15  Identifier 20
UMLM.ID19         14  Identifier 19
UMLM.ID18         13  Identifier 18
UMLM.ID17         12  Identifier 17
UMLM.ID16         11  Identifier 16
UMLM.ID15         10  Identifier 15
UMLM.ID14         9   Identifier 14
UMLM.ID13         8   Identifier 13
UMLM.ID28         7   Identifier 28
UMLM.ID27         6   Identifier 27
UMLM.ID26         5   Identifier 26
UMLM.ID25         4   Identifier 25
UMLM.ID24         3   Identifier 24
UMLM.ID23         2   Identifier 23
UMLM.ID22         1   Identifier 22
UMLM.ID21         0   Identifier 21
LMLM             0xEF0E   CAN1 Lower Mask of Last Message
LMLM.ID4          15  Identifier 4 
LMLM.ID3          14  Identifier 3 
LMLM.ID2          13  Identifier 2 
LMLM.ID1          12  Identifier 1 
LMLM.ID0          11  Identifier 0 
LMLM.ID12         7   Identifier 12
LMLM.ID11         6   Identifier 11
LMLM.ID10         5   Identifier 10
LMLM.ID9          4   Identifier 9 
LMLM.ID8          3   Identifier 8 
LMLM.ID7          2   Identifier 7 
LMLM.ID6          1   Identifier 6 
LMLM.ID5          0   Identifier 5 
C1MCR1                  0xEF10  CAN1 Message Ctrl. Reg. (msg. 1)
C1MCR1.RMTPND15          15  Remote Pending bit 15
C1MCR1.RMTPND14          14  Remote Pending bit 14
C1MCR1.TXRQ13            13  Transmit Request bit 13
C1MCR1.TXRQ12            12  Transmit Request bit 12
C1MCR1.MSGLST_CPUUPD11   11  Message Lost_CPU Update bit 11
C1MCR1.MSGLST_CPUUPD10   10  Message Lost_CPU Update bit 10
C1MCR1.NEWDAT9           9   New Data bit 9
C1MCR1.NEWDAT8           8   New Data bit 8
C1MCR1.MSGVAL7           7   Message Valid bit 7
C1MCR1.MSGVAL6           6   Message Valid bit 6
C1MCR1.TXIE5             5   Transmit Interrupt Enable bit 5
C1MCR1.TXIE4             4   Transmit Interrupt Enable bit 4
C1MCR1.RXIE3             3   Receive Interrupt Enable bit 3
C1MCR1.RXIE2             2   Receive Interrupt Enable bit 2
C1MCR1.INTPND1           1   Interrupt Pending bit 1
C1MCR1.INTPND0           0   Interrupt Pending bit 0
C1UAR1                  0xEF12  CAN1 Upper Arbitration Reg. (msg. 1)
C1UAR1.ID20              15  Identifier bit 20
C1UAR1.ID19              14  Identifier bit 19
C1UAR1.ID18              13  Identifier bit 18
C1UAR1.ID17              12  Identifier bit 17
C1UAR1.ID16              11  Identifier bit 16
C1UAR1.ID15              10  Identifier bit 15
C1UAR1.ID14              9   Identifier bit 14
C1UAR1.ID13              8   Identifier bit 13
C1UAR1.ID28              7   Identifier bit 28
C1UAR1.ID27              6   Identifier bit 27
C1UAR1.ID26              5   Identifier bit 26
C1UAR1.ID25              4   Identifier bit 25
C1UAR1.ID24              3   Identifier bit 24
C1UAR1.ID23              2   Identifier bit 23
C1UAR1.ID22              1   Identifier bit 22
C1UAR1.ID21              0   Identifier bit 21
C1LAR1                  0xEF14  CAN1 Lower Arbitration Reg. (msg. 1)
C1LAR1.ID4               15  Identifier bit 4 
C1LAR1.ID3               14  Identifier bit 3 
C1LAR1.ID2               13  Identifier bit 2 
C1LAR1.ID1               12  Identifier bit 1 
C1LAR1.ID0               11  Identifier bit 0 
C1LAR1.ID12              7   Identifier bit 12
C1LAR1.ID11              6   Identifier bit 11
C1LAR1.ID10              5   Identifier bit 10
C1LAR1.ID9               4   Identifier bit 9 
C1LAR1.ID8               3   Identifier bit 8 
C1LAR1.ID7               2   Identifier bit 7 
C1LAR1.ID6               1   Identifier bit 6 
C1LAR1.ID5               0   Identifier bit 5 
C1MCFG1                 0xEF16  CAN1 Message Configuration Register (msg. 1)
C1MCFG1.DLC7             7   Data Length Code bit 7
C1MCFG1.DLC6             6   Data Length Code bit 6
C1MCFG1.DLC5             5   Data Length Code bit 5
C1MCFG1.DLC4             4   Data Length Code bit 4
C1MCFG1.DIR              3   Message Direction
C1MCFG1.XTD              2   Extended Identifier
C1MCR2                  0xEF20  CAN1 Message Ctrl. Reg. (msg. 2)
C1MCR2.RMTPND15          15  Remote Pending bit 15          
C1MCR2.RMTPND14          14  Remote Pending bit 14          
C1MCR2.TXRQ13            13  Transmit Request bit 13        
C1MCR2.TXRQ12            12  Transmit Request bit 12        
C1MCR2.MSGLST_CPUUPD11   11  Message Lost_CPU Update bit 11 
C1MCR2.MSGLST_CPUUPD10   10  Message Lost_CPU Update bit 10 
C1MCR2.NEWDAT9           9   New Data bit 9                 
C1MCR2.NEWDAT8           8   New Data bit 8                 
C1MCR2.MSGVAL7           7   Message Valid bit 7            
C1MCR2.MSGVAL6           6   Message Valid bit 6            
C1MCR2.TXIE5             5   Transmit Interrupt Enable bit 5
C1MCR2.TXIE4             4   Transmit Interrupt Enable bit 4
C1MCR2.RXIE3             3   Receive Interrupt Enable bit 3 
C1MCR2.RXIE2             2   Receive Interrupt Enable bit 2 
C1MCR2.INTPND1           1   Interrupt Pending bit 1        
C1MCR2.INTPND0           0   Interrupt Pending bit 0        
C1UAR2                  0xEF22  CAN1 Upper Arbitration Reg. (msg. 2)
C1UAR2.ID20              15  Identifier bit 20
C1UAR2.ID19              14  Identifier bit 19
C1UAR2.ID18              13  Identifier bit 18
C1UAR2.ID17              12  Identifier bit 17
C1UAR2.ID16              11  Identifier bit 16
C1UAR2.ID15              10  Identifier bit 15
C1UAR2.ID14              9   Identifier bit 14
C1UAR2.ID13              8   Identifier bit 13
C1UAR2.ID28              7   Identifier bit 28
C1UAR2.ID27              6   Identifier bit 27
C1UAR2.ID26              5   Identifier bit 26
C1UAR2.ID25              4   Identifier bit 25
C1UAR2.ID24              3   Identifier bit 24
C1UAR2.ID23              2   Identifier bit 23
C1UAR2.ID22              1   Identifier bit 22
C1UAR2.ID21              0   Identifier bit 21
C1LAR2                  0xEF24  CAN1 Lower Arbitration Reg. (msg. 2)
C1LAR2.ID4               15  Identifier bit 4 
C1LAR2.ID3               14  Identifier bit 3 
C1LAR2.ID2               13  Identifier bit 2 
C1LAR2.ID1               12  Identifier bit 1 
C1LAR2.ID0               11  Identifier bit 0 
C1LAR2.ID12              7   Identifier bit 12
C1LAR2.ID11              6   Identifier bit 11
C1LAR2.ID10              5   Identifier bit 10
C1LAR2.ID9               4   Identifier bit 9 
C1LAR2.ID8               3   Identifier bit 8 
C1LAR2.ID7               2   Identifier bit 7 
C1LAR2.ID6               1   Identifier bit 6 
C1LAR2.ID5               0   Identifier bit 5 
C1MCFG2         0xEF26  CAN1 Message Configuration Register (msg. 2)
C1MCFG2.DLC7     7   Data Length Code bit 7
C1MCFG2.DLC6     6   Data Length Code bit 6
C1MCFG2.DLC5     5   Data Length Code bit 5
C1MCFG2.DLC4     4   Data Length Code bit 4
C1MCFG2.DIR      3   Message Direction
C1MCFG2.XTD      2   Extended Identifier
C1MCR3                  0xEF30  CAN1 Message Ctrl. Reg. (msg. 3)
C1MCR3.RMTPND15          15  Remote Pending bit 15          
C1MCR3.RMTPND14          14  Remote Pending bit 14          
C1MCR3.TXRQ13            13  Transmit Request bit 13        
C1MCR3.TXRQ12            12  Transmit Request bit 12        
C1MCR3.MSGLST_CPUUPD11   11  Message Lost_CPU Update bit 11 
C1MCR3.MSGLST_CPUUPD10   10  Message Lost_CPU Update bit 10 
C1MCR3.NEWDAT9           9   New Data bit 9                 
C1MCR3.NEWDAT8           8   New Data bit 8                 
C1MCR3.MSGVAL7           7   Message Valid bit 7            
C1MCR3.MSGVAL6           6   Message Valid bit 6            
C1MCR3.TXIE5             5   Transmit Interrupt Enable bit 5
C1MCR3.TXIE4             4   Transmit Interrupt Enable bit 4
C1MCR3.RXIE3             3   Receive Interrupt Enable bit 3 
C1MCR3.RXIE2             2   Receive Interrupt Enable bit 2 
C1MCR3.INTPND1           1   Interrupt Pending bit 1        
C1MCR3.INTPND0           0   Interrupt Pending bit 0        
C1UAR3                  0xEF32  CAN1 Upper Arbitration Reg. (msg. 3)
C1UAR3.ID20              15  Identifier bit 20
C1UAR3.ID19              14  Identifier bit 19
C1UAR3.ID18              13  Identifier bit 18
C1UAR3.ID17              12  Identifier bit 17
C1UAR3.ID16              11  Identifier bit 16
C1UAR3.ID15              10  Identifier bit 15
C1UAR3.ID14              9   Identifier bit 14
C1UAR3.ID13              8   Identifier bit 13
C1UAR3.ID28              7   Identifier bit 28
C1UAR3.ID27              6   Identifier bit 27
C1UAR3.ID26              5   Identifier bit 26
C1UAR3.ID25              4   Identifier bit 25
C1UAR3.ID24              3   Identifier bit 24
C1UAR3.ID23              2   Identifier bit 23
C1UAR3.ID22              1   Identifier bit 22
C1UAR3.ID21              0   Identifier bit 21
C1LAR3                  0xEF34  CAN1 Lower Arbitration Reg. (msg. 3)
C1LAR3.ID4               15  Identifier bit 4 
C1LAR3.ID3               14  Identifier bit 3 
C1LAR3.ID2               13  Identifier bit 2 
C1LAR3.ID1               12  Identifier bit 1 
C1LAR3.ID0               11  Identifier bit 0 
C1LAR3.ID12              7   Identifier bit 12
C1LAR3.ID11              6   Identifier bit 11
C1LAR3.ID10              5   Identifier bit 10
C1LAR3.ID9               4   Identifier bit 9 
C1LAR3.ID8               3   Identifier bit 8 
C1LAR3.ID7               2   Identifier bit 7 
C1LAR3.ID6               1   Identifier bit 6 
C1LAR3.ID5               0   Identifier bit 5 
C1MCFG3         0xEF36  CAN1 Message Configuration Register (msg. 3)
C1MCFG3.DLC7     7   Data Length Code bit 7
C1MCFG3.DLC6     6   Data Length Code bit 6
C1MCFG3.DLC5     5   Data Length Code bit 5
C1MCFG3.DLC4     4   Data Length Code bit 4
C1MCFG3.DIR      3   Message Direction
C1MCFG3.XTD      2   Extended Identifier
C1MCR4                  0xEF40  CAN1 Message Ctrl. Reg. (msg. 4)
C1MCR4.RMTPND15          15  Remote Pending bit 15          
C1MCR4.RMTPND14          14  Remote Pending bit 14          
C1MCR4.TXRQ13            13  Transmit Request bit 13        
C1MCR4.TXRQ12            12  Transmit Request bit 12        
C1MCR4.MSGLST_CPUUPD11   11  Message Lost_CPU Update bit 11 
C1MCR4.MSGLST_CPUUPD10   10  Message Lost_CPU Update bit 10 
C1MCR4.NEWDAT9           9   New Data bit 9                 
C1MCR4.NEWDAT8           8   New Data bit 8                 
C1MCR4.MSGVAL7           7   Message Valid bit 7            
C1MCR4.MSGVAL6           6   Message Valid bit 6            
C1MCR4.TXIE5             5   Transmit Interrupt Enable bit 5
C1MCR4.TXIE4             4   Transmit Interrupt Enable bit 4
C1MCR4.RXIE3             3   Receive Interrupt Enable bit 3 
C1MCR4.RXIE2             2   Receive Interrupt Enable bit 2 
C1MCR4.INTPND1           1   Interrupt Pending bit 1        
C1MCR4.INTPND0           0   Interrupt Pending bit 0        
C1UAR4                  0xEF42  CAN1 Upper Arbitration Reg. (msg. 4)
C1UAR4.ID20              15  Identifier bit 20
C1UAR4.ID19              14  Identifier bit 19
C1UAR4.ID18              13  Identifier bit 18
C1UAR4.ID17              12  Identifier bit 17
C1UAR4.ID16              11  Identifier bit 16
C1UAR4.ID15              10  Identifier bit 15
C1UAR4.ID14              9   Identifier bit 14
C1UAR4.ID13              8   Identifier bit 13
C1UAR4.ID28              7   Identifier bit 28
C1UAR4.ID27              6   Identifier bit 27
C1UAR4.ID26              5   Identifier bit 26
C1UAR4.ID25              4   Identifier bit 25
C1UAR4.ID24              3   Identifier bit 24
C1UAR4.ID23              2   Identifier bit 23
C1UAR4.ID22              1   Identifier bit 22
C1UAR4.ID21              0   Identifier bit 21
C1LAR4                  0xEF44  CAN1 Lower Arbitration Reg. (msg. 4)
C1LAR4.ID4               15  Identifier bit 4 
C1LAR4.ID3               14  Identifier bit 3 
C1LAR4.ID2               13  Identifier bit 2 
C1LAR4.ID1               12  Identifier bit 1 
C1LAR4.ID0               11  Identifier bit 0 
C1LAR4.ID12              7   Identifier bit 12
C1LAR4.ID11              6   Identifier bit 11
C1LAR4.ID10              5   Identifier bit 10
C1LAR4.ID9               4   Identifier bit 9 
C1LAR4.ID8               3   Identifier bit 8 
C1LAR4.ID7               2   Identifier bit 7 
C1LAR4.ID6               1   Identifier bit 6 
C1LAR4.ID5               0   Identifier bit 5 
C1MCFG4         0xEF46  CAN1 Message Configuration Register (msg. 4)
C1MCFG4.DLC7     7   Data Length Code bit 7
C1MCFG4.DLC6     6   Data Length Code bit 6
C1MCFG4.DLC5     5   Data Length Code bit 5
C1MCFG4.DLC4     4   Data Length Code bit 4
C1MCFG4.DIR      3   Message Direction
C1MCFG4.XTD      2   Extended Identifier
C1MCR5                  0xEF50  CAN1 Message Ctrl. Reg. (msg. 5)
C1MCR5.RMTPND15          15  Remote Pending bit 15          
C1MCR5.RMTPND14          14  Remote Pending bit 14          
C1MCR5.TXRQ13            13  Transmit Request bit 13        
C1MCR5.TXRQ12            12  Transmit Request bit 12        
C1MCR5.MSGLST_CPUUPD11   11  Message Lost_CPU Update bit 11 
C1MCR5.MSGLST_CPUUPD10   10  Message Lost_CPU Update bit 10 
C1MCR5.NEWDAT9           9   New Data bit 9                 
C1MCR5.NEWDAT8           8   New Data bit 8                 
C1MCR5.MSGVAL7           7   Message Valid bit 7            
C1MCR5.MSGVAL6           6   Message Valid bit 6            
C1MCR5.TXIE5             5   Transmit Interrupt Enable bit 5
C1MCR5.TXIE4             4   Transmit Interrupt Enable bit 4
C1MCR5.RXIE3             3   Receive Interrupt Enable bit 3 
C1MCR5.RXIE2             2   Receive Interrupt Enable bit 2 
C1MCR5.INTPND1           1   Interrupt Pending bit 1        
C1MCR5.INTPND0           0   Interrupt Pending bit 0        
C1UAR5                  0xEF52  CAN1 Upper Arbitration Reg. (msg. 5)
C1UAR5.ID20              15  Identifier bit 20
C1UAR5.ID19              14  Identifier bit 19
C1UAR5.ID18              13  Identifier bit 18
C1UAR5.ID17              12  Identifier bit 17
C1UAR5.ID16              11  Identifier bit 16
C1UAR5.ID15              10  Identifier bit 15
C1UAR5.ID14              9   Identifier bit 14
C1UAR5.ID13              8   Identifier bit 13
C1UAR5.ID28              7   Identifier bit 28
C1UAR5.ID27              6   Identifier bit 27
C1UAR5.ID26              5   Identifier bit 26
C1UAR5.ID25              4   Identifier bit 25
C1UAR5.ID24              3   Identifier bit 24
C1UAR5.ID23              2   Identifier bit 23
C1UAR5.ID22              1   Identifier bit 22
C1UAR5.ID21              0   Identifier bit 21
C1LAR5                  0xEF54  CAN1 Lower Arbitration Reg. (msg. 5)
C1LAR5.ID4               15  Identifier bit 4 
C1LAR5.ID3               14  Identifier bit 3 
C1LAR5.ID2               13  Identifier bit 2 
C1LAR5.ID1               12  Identifier bit 1 
C1LAR5.ID0               11  Identifier bit 0 
C1LAR5.ID12              7   Identifier bit 12
C1LAR5.ID11              6   Identifier bit 11
C1LAR5.ID10              5   Identifier bit 10
C1LAR5.ID9               4   Identifier bit 9 
C1LAR5.ID8               3   Identifier bit 8 
C1LAR5.ID7               2   Identifier bit 7 
C1LAR5.ID6               1   Identifier bit 6 
C1LAR5.ID5               0   Identifier bit 5 
C1MCFG5         0xEF56  CAN1 Message Configuration Register (msg. 5)
C1MCFG5.DLC7     7   Data Length Code bit 7
C1MCFG5.DLC6     6   Data Length Code bit 6
C1MCFG5.DLC5     5   Data Length Code bit 5
C1MCFG5.DLC4     4   Data Length Code bit 4
C1MCFG5.DIR      3   Message Direction
C1MCFG5.XTD      2   Extended Identifier
C1MCR6                  0xEF60  CAN1 Message Ctrl. Reg. (msg. 6)
C1MCR6.RMTPND15          15  Remote Pending bit 15          
C1MCR6.RMTPND14          14  Remote Pending bit 14          
C1MCR6.TXRQ13            13  Transmit Request bit 13        
C1MCR6.TXRQ12            12  Transmit Request bit 12        
C1MCR6.MSGLST_CPUUPD11   11  Message Lost_CPU Update bit 11 
C1MCR6.MSGLST_CPUUPD10   10  Message Lost_CPU Update bit 10 
C1MCR6.NEWDAT9           9   New Data bit 9                 
C1MCR6.NEWDAT8           8   New Data bit 8                 
C1MCR6.MSGVAL7           7   Message Valid bit 7            
C1MCR6.MSGVAL6           6   Message Valid bit 6            
C1MCR6.TXIE5             5   Transmit Interrupt Enable bit 5
C1MCR6.TXIE4             4   Transmit Interrupt Enable bit 4
C1MCR6.RXIE3             3   Receive Interrupt Enable bit 3 
C1MCR6.RXIE2             2   Receive Interrupt Enable bit 2 
C1MCR6.INTPND1           1   Interrupt Pending bit 1        
C1MCR6.INTPND0           0   Interrupt Pending bit 0        
C1UAR6                  0xEF62  CAN1 Upper Arbitration Reg. (msg. 6)
C1UAR6.ID20              15  Identifier bit 20
C1UAR6.ID19              14  Identifier bit 19
C1UAR6.ID18              13  Identifier bit 18
C1UAR6.ID17              12  Identifier bit 17
C1UAR6.ID16              11  Identifier bit 16
C1UAR6.ID15              10  Identifier bit 15
C1UAR6.ID14              9   Identifier bit 14
C1UAR6.ID13              8   Identifier bit 13
C1UAR6.ID28              7   Identifier bit 28
C1UAR6.ID27              6   Identifier bit 27
C1UAR6.ID26              5   Identifier bit 26
C1UAR6.ID25              4   Identifier bit 25
C1UAR6.ID24              3   Identifier bit 24
C1UAR6.ID23              2   Identifier bit 23
C1UAR6.ID22              1   Identifier bit 22
C1UAR6.ID21              0   Identifier bit 21
C1LAR6                  0xEF64  CAN1 Lower Arbitration Reg. (msg. 6)
C1LAR6.ID4               15  Identifier bit 4 
C1LAR6.ID3               14  Identifier bit 3 
C1LAR6.ID2               13  Identifier bit 2 
C1LAR6.ID1               12  Identifier bit 1 
C1LAR6.ID0               11  Identifier bit 0 
C1LAR6.ID12              7   Identifier bit 12
C1LAR6.ID11              6   Identifier bit 11
C1LAR6.ID10              5   Identifier bit 10
C1LAR6.ID9               4   Identifier bit 9 
C1LAR6.ID8               3   Identifier bit 8 
C1LAR6.ID7               2   Identifier bit 7 
C1LAR6.ID6               1   Identifier bit 6 
C1LAR6.ID5               0   Identifier bit 5 
C1MCFG6         0xEF66  CAN1 Message Configuration Register (msg. 6)
C1MCFG6.DLC7     7   Data Length Code bit 7
C1MCFG6.DLC6     6   Data Length Code bit 6
C1MCFG6.DLC5     5   Data Length Code bit 5
C1MCFG6.DLC4     4   Data Length Code bit 4
C1MCFG6.DIR      3   Message Direction
C1MCFG6.XTD      2   Extended Identifier
C1MCR7                  0xEF70  CAN1 Message Ctrl. Reg. (msg. 7)
C1MCR7.RMTPND15          15  Remote Pending bit 15          
C1MCR7.RMTPND14          14  Remote Pending bit 14          
C1MCR7.TXRQ13            13  Transmit Request bit 13        
C1MCR7.TXRQ12            12  Transmit Request bit 12        
C1MCR7.MSGLST_CPUUPD11   11  Message Lost_CPU Update bit 11 
C1MCR7.MSGLST_CPUUPD10   10  Message Lost_CPU Update bit 10 
C1MCR7.NEWDAT9           9   New Data bit 9                 
C1MCR7.NEWDAT8           8   New Data bit 8                 
C1MCR7.MSGVAL7           7   Message Valid bit 7            
C1MCR7.MSGVAL6           6   Message Valid bit 6            
C1MCR7.TXIE5             5   Transmit Interrupt Enable bit 5
C1MCR7.TXIE4             4   Transmit Interrupt Enable bit 4
C1MCR7.RXIE3             3   Receive Interrupt Enable bit 3 
C1MCR7.RXIE2             2   Receive Interrupt Enable bit 2 
C1MCR7.INTPND1           1   Interrupt Pending bit 1        
C1MCR7.INTPND0           0   Interrupt Pending bit 0        
C1UAR7                  0xEF72  CAN1 Upper Arbitration Reg. (msg. 7)
C1UAR7.ID20              15  Identifier bit 20
C1UAR7.ID19              14  Identifier bit 19
C1UAR7.ID18              13  Identifier bit 18
C1UAR7.ID17              12  Identifier bit 17
C1UAR7.ID16              11  Identifier bit 16
C1UAR7.ID15              10  Identifier bit 15
C1UAR7.ID14              9   Identifier bit 14
C1UAR7.ID13              8   Identifier bit 13
C1UAR7.ID28              7   Identifier bit 28
C1UAR7.ID27              6   Identifier bit 27
C1UAR7.ID26              5   Identifier bit 26
C1UAR7.ID25              4   Identifier bit 25
C1UAR7.ID24              3   Identifier bit 24
C1UAR7.ID23              2   Identifier bit 23
C1UAR7.ID22              1   Identifier bit 22
C1UAR7.ID21              0   Identifier bit 21
C1LAR7                  0xEF74  CAN1 Lower Arbitration Reg. (msg. 7)
C1LAR7.ID4               15  Identifier bit 4 
C1LAR7.ID3               14  Identifier bit 3 
C1LAR7.ID2               13  Identifier bit 2 
C1LAR7.ID1               12  Identifier bit 1 
C1LAR7.ID0               11  Identifier bit 0 
C1LAR7.ID12              7   Identifier bit 12
C1LAR7.ID11              6   Identifier bit 11
C1LAR7.ID10              5   Identifier bit 10
C1LAR7.ID9               4   Identifier bit 9 
C1LAR7.ID8               3   Identifier bit 8 
C1LAR7.ID7               2   Identifier bit 7 
C1LAR7.ID6               1   Identifier bit 6 
C1LAR7.ID5               0   Identifier bit 5 
C1MCFG7         0xEF76  CAN1 Message Configuration Register (msg. 7)
C1MCFG7.DLC7     7   Data Length Code bit 7
C1MCFG7.DLC6     6   Data Length Code bit 6
C1MCFG7.DLC5     5   Data Length Code bit 5
C1MCFG7.DLC4     4   Data Length Code bit 4
C1MCFG7.DIR      3   Message Direction
C1MCFG7.XTD      2   Extended Identifier
C1MCR8                  0xEF80  CAN1 Message Ctrl. Reg. (msg. 8)
C1MCR8.RMTPND15          15  Remote Pending bit 15          
C1MCR8.RMTPND14          14  Remote Pending bit 14          
C1MCR8.TXRQ13            13  Transmit Request bit 13        
C1MCR8.TXRQ12            12  Transmit Request bit 12        
C1MCR8.MSGLST_CPUUPD11   11  Message Lost_CPU Update bit 11 
C1MCR8.MSGLST_CPUUPD10   10  Message Lost_CPU Update bit 10 
C1MCR8.NEWDAT9           9   New Data bit 9                 
C1MCR8.NEWDAT8           8   New Data bit 8                 
C1MCR8.MSGVAL7           7   Message Valid bit 7            
C1MCR8.MSGVAL6           6   Message Valid bit 6            
C1MCR8.TXIE5             5   Transmit Interrupt Enable bit 5
C1MCR8.TXIE4             4   Transmit Interrupt Enable bit 4
C1MCR8.RXIE3             3   Receive Interrupt Enable bit 3 
C1MCR8.RXIE2             2   Receive Interrupt Enable bit 2 
C1MCR8.INTPND1           1   Interrupt Pending bit 1        
C1MCR8.INTPND0           0   Interrupt Pending bit 0        
C1UAR8                  0xEF82  CAN1 Upper Arbitration Reg. (msg. 8)
C1UAR8.ID20              15  Identifier bit 20
C1UAR8.ID19              14  Identifier bit 19
C1UAR8.ID18              13  Identifier bit 18
C1UAR8.ID17              12  Identifier bit 17
C1UAR8.ID16              11  Identifier bit 16
C1UAR8.ID15              10  Identifier bit 15
C1UAR8.ID14              9   Identifier bit 14
C1UAR8.ID13              8   Identifier bit 13
C1UAR8.ID28              7   Identifier bit 28
C1UAR8.ID27              6   Identifier bit 27
C1UAR8.ID26              5   Identifier bit 26
C1UAR8.ID25              4   Identifier bit 25
C1UAR8.ID24              3   Identifier bit 24
C1UAR8.ID23              2   Identifier bit 23
C1UAR8.ID22              1   Identifier bit 22
C1UAR8.ID21              0   Identifier bit 21
C1LAR8                  0xEF84  CAN1 Lower Arbitration Reg. (msg. 8)
C1LAR8.ID4               15  Identifier bit 4 
C1LAR8.ID3               14  Identifier bit 3 
C1LAR8.ID2               13  Identifier bit 2 
C1LAR8.ID1               12  Identifier bit 1 
C1LAR8.ID0               11  Identifier bit 0 
C1LAR8.ID12              7   Identifier bit 12
C1LAR8.ID11              6   Identifier bit 11
C1LAR8.ID10              5   Identifier bit 10
C1LAR8.ID9               4   Identifier bit 9 
C1LAR8.ID8               3   Identifier bit 8 
C1LAR8.ID7               2   Identifier bit 7 
C1LAR8.ID6               1   Identifier bit 6 
C1LAR8.ID5               0   Identifier bit 5 
C1MCFG8         0xEF86  CAN1 Message Configuration Register (msg. 8)
C1MCFG8.DLC7     7   Data Length Code bit 7
C1MCFG8.DLC6     6   Data Length Code bit 6
C1MCFG8.DLC5     5   Data Length Code bit 5
C1MCFG8.DLC4     4   Data Length Code bit 4
C1MCFG8.DIR      3   Message Direction
C1MCFG8.XTD      2   Extended Identifier
C1MCR9                  0xEF90  CAN1 Message Ctrl. Reg. (msg. 9)
C1MCR9.RMTPND15          15  Remote Pending bit 15          
C1MCR9.RMTPND14          14  Remote Pending bit 14          
C1MCR9.TXRQ13            13  Transmit Request bit 13        
C1MCR9.TXRQ12            12  Transmit Request bit 12        
C1MCR9.MSGLST_CPUUPD11   11  Message Lost_CPU Update bit 11 
C1MCR9.MSGLST_CPUUPD10   10  Message Lost_CPU Update bit 10 
C1MCR9.NEWDAT9           9   New Data bit 9                 
C1MCR9.NEWDAT8           8   New Data bit 8                 
C1MCR9.MSGVAL7           7   Message Valid bit 7            
C1MCR9.MSGVAL6           6   Message Valid bit 6            
C1MCR9.TXIE5             5   Transmit Interrupt Enable bit 5
C1MCR9.TXIE4             4   Transmit Interrupt Enable bit 4
C1MCR9.RXIE3             3   Receive Interrupt Enable bit 3 
C1MCR9.RXIE2             2   Receive Interrupt Enable bit 2 
C1MCR9.INTPND1           1   Interrupt Pending bit 1        
C1MCR9.INTPND0           0   Interrupt Pending bit 0        
C1UAR9                  0xEF92  CAN1 Upper Arbitration Reg. (msg. 9)
C1UAR9.ID20              15  Identifier bit 20
C1UAR9.ID19              14  Identifier bit 19
C1UAR9.ID18              13  Identifier bit 18
C1UAR9.ID17              12  Identifier bit 17
C1UAR9.ID16              11  Identifier bit 16
C1UAR9.ID15              10  Identifier bit 15
C1UAR9.ID14              9   Identifier bit 14
C1UAR9.ID13              8   Identifier bit 13
C1UAR9.ID28              7   Identifier bit 28
C1UAR9.ID27              6   Identifier bit 27
C1UAR9.ID26              5   Identifier bit 26
C1UAR9.ID25              4   Identifier bit 25
C1UAR9.ID24              3   Identifier bit 24
C1UAR9.ID23              2   Identifier bit 23
C1UAR9.ID22              1   Identifier bit 22
C1UAR9.ID21              0   Identifier bit 21
C1LAR9                  0xEF94  CAN1 Lower Arbitration Reg. (msg. 9)
C1LAR9.ID4               15  Identifier bit 4 
C1LAR9.ID3               14  Identifier bit 3 
C1LAR9.ID2               13  Identifier bit 2 
C1LAR9.ID1               12  Identifier bit 1 
C1LAR9.ID0               11  Identifier bit 0 
C1LAR9.ID12              7   Identifier bit 12
C1LAR9.ID11              6   Identifier bit 11
C1LAR9.ID10              5   Identifier bit 10
C1LAR9.ID9               4   Identifier bit 9 
C1LAR9.ID8               3   Identifier bit 8 
C1LAR9.ID7               2   Identifier bit 7 
C1LAR9.ID6               1   Identifier bit 6 
C1LAR9.ID5               0   Identifier bit 5 
C1MCFG9         0xEF96  CAN1 Message Configuration Register (msg. 9)
C1MCFG9.DLC7     7   Data Length Code bit 7
C1MCFG9.DLC6     6   Data Length Code bit 6
C1MCFG9.DLC5     5   Data Length Code bit 5
C1MCFG9.DLC4     4   Data Length Code bit 4
C1MCFG9.DIR      3   Message Direction
C1MCFG9.XTD      2   Extended Identifier
C1MCRA                  0xEFA0  CAN1 Message Ctrl. Reg. (msg. A)
C1MCRA.RMTPND15          15  Remote Pending bit 15          
C1MCRA.RMTPND14          14  Remote Pending bit 14          
C1MCRA.TXRQ13            13  Transmit Request bit 13        
C1MCRA.TXRQ12            12  Transmit Request bit 12        
C1MCRA.MSGLST_CPUUPD11   11  Message Lost_CPU Update bit 11 
C1MCRA.MSGLST_CPUUPD10   10  Message Lost_CPU Update bit 10 
C1MCRA.NEWDAT9           9   New Data bit 9                 
C1MCRA.NEWDAT8           8   New Data bit 8                 
C1MCRA.MSGVAL7           7   Message Valid bit 7            
C1MCRA.MSGVAL6           6   Message Valid bit 6            
C1MCRA.TXIE5             5   Transmit Interrupt Enable bit 5
C1MCRA.TXIE4             4   Transmit Interrupt Enable bit 4
C1MCRA.RXIE3             3   Receive Interrupt Enable bit 3 
C1MCRA.RXIE2             2   Receive Interrupt Enable bit 2 
C1MCRA.INTPND1           1   Interrupt Pending bit 1        
C1MCRA.INTPND0           0   Interrupt Pending bit 0        
C1UARA          0xEFA2  CAN1 Upper Arbitration Reg. (msg. A)
C1UARA.ID20      15  Identifier bit 20
C1UARA.ID19      14  Identifier bit 19
C1UARA.ID18      13  Identifier bit 18
C1UARA.ID17      12  Identifier bit 17
C1UARA.ID16      11  Identifier bit 16
C1UARA.ID15      10  Identifier bit 15
C1UARA.ID14      9   Identifier bit 14
C1UARA.ID13      8   Identifier bit 13
C1UARA.ID28      7   Identifier bit 28
C1UARA.ID27      6   Identifier bit 27
C1UARA.ID26      5   Identifier bit 26
C1UARA.ID25      4   Identifier bit 25
C1UARA.ID24      3   Identifier bit 24
C1UARA.ID23      2   Identifier bit 23
C1UARA.ID22      1   Identifier bit 22
C1UARA.ID21      0   Identifier bit 21
C1LARA          0xEFA4  CAN1 Lower Arbitration Reg. (msg. A)
C1LARA.ID4       15  Identifier bit 4 
C1LARA.ID3       14  Identifier bit 3 
C1LARA.ID2       13  Identifier bit 2 
C1LARA.ID1       12  Identifier bit 1 
C1LARA.ID0       11  Identifier bit 0 
C1LARA.ID12      7   Identifier bit 12
C1LARA.ID11      6   Identifier bit 11
C1LARA.ID10      5   Identifier bit 10
C1LARA.ID9       4   Identifier bit 9 
C1LARA.ID8       3   Identifier bit 8 
C1LARA.ID7       2   Identifier bit 7 
C1LARA.ID6       1   Identifier bit 6 
C1LARA.ID5       0   Identifier bit 5 
C1MCFGA         0xEFA6  CAN1 Message Configuration Register (msg. A)
C1MCFGA.DLC7     7   Data Length Code bit 7
C1MCFGA.DLC6     6   Data Length Code bit 6
C1MCFGA.DLC5     5   Data Length Code bit 5
C1MCFGA.DLC4     4   Data Length Code bit 4
C1MCFGA.DIR      3   Message Direction
C1MCFGA.XTD      2   Extended Identifier
C1MCRB                  0xEFB0  CAN1 Message Ctrl. Reg. (msg. B)
C1MCRB.RMTPND15          15  Remote Pending bit 15          
C1MCRB.RMTPND14          14  Remote Pending bit 14          
C1MCRB.TXRQ13            13  Transmit Request bit 13        
C1MCRB.TXRQ12            12  Transmit Request bit 12        
C1MCRB.MSGLST_CPUUPD11   11  Message Lost_CPU Update bit 11 
C1MCRB.MSGLST_CPUUPD10   10  Message Lost_CPU Update bit 10 
C1MCRB.NEWDAT9           9   New Data bit 9                 
C1MCRB.NEWDAT8           8   New Data bit 8                 
C1MCRB.MSGVAL7           7   Message Valid bit 7            
C1MCRB.MSGVAL6           6   Message Valid bit 6            
C1MCRB.TXIE5             5   Transmit Interrupt Enable bit 5
C1MCRB.TXIE4             4   Transmit Interrupt Enable bit 4
C1MCRB.RXIE3             3   Receive Interrupt Enable bit 3 
C1MCRB.RXIE2             2   Receive Interrupt Enable bit 2 
C1MCRB.INTPND1           1   Interrupt Pending bit 1        
C1MCRB.INTPND0           0   Interrupt Pending bit 0        
C1UARB          0xEFB2  CAN1 Upper Arbitration Reg. (msg. B)
C1UARB.ID20      15  Identifier bit 20
C1UARB.ID19      14  Identifier bit 19
C1UARB.ID18      13  Identifier bit 18
C1UARB.ID17      12  Identifier bit 17
C1UARB.ID16      11  Identifier bit 16
C1UARB.ID15      10  Identifier bit 15
C1UARB.ID14      9   Identifier bit 14
C1UARB.ID13      8   Identifier bit 13
C1UARB.ID28      7   Identifier bit 28
C1UARB.ID27      6   Identifier bit 27
C1UARB.ID26      5   Identifier bit 26
C1UARB.ID25      4   Identifier bit 25
C1UARB.ID24      3   Identifier bit 24
C1UARB.ID23      2   Identifier bit 23
C1UARB.ID22      1   Identifier bit 22
C1UARB.ID21      0   Identifier bit 21
C1LARB          0xEFB4  CAN1 Lower Arbitration Reg. (msg. B)
C1LARB.ID4       15  Identifier bit 4 
C1LARB.ID3       14  Identifier bit 3 
C1LARB.ID2       13  Identifier bit 2 
C1LARB.ID1       12  Identifier bit 1 
C1LARB.ID0       11  Identifier bit 0 
C1LARB.ID12      7   Identifier bit 12
C1LARB.ID11      6   Identifier bit 11
C1LARB.ID10      5   Identifier bit 10
C1LARB.ID9       4   Identifier bit 9 
C1LARB.ID8       3   Identifier bit 8 
C1LARB.ID7       2   Identifier bit 7 
C1LARB.ID6       1   Identifier bit 6 
C1LARB.ID5       0   Identifier bit 5 
C1MCFGB         0xEFB6  CAN1 Message Configuration Register (msg. B)
C1MCFGB.DLC7     7   Data Length Code bit 7
C1MCFGB.DLC6     6   Data Length Code bit 6
C1MCFGB.DLC5     5   Data Length Code bit 5
C1MCFGB.DLC4     4   Data Length Code bit 4
C1MCFGB.DIR      3   Message Direction
C1MCFGB.XTD      2   Extended Identifier
C1MCRC                  0xEFC0  CAN1 Message Ctrl. Reg. (msg. C)
C1MCRC.RMTPND15          15  Remote Pending bit 15          
C1MCRC.RMTPND14          14  Remote Pending bit 14          
C1MCRC.TXRQ13            13  Transmit Request bit 13        
C1MCRC.TXRQ12            12  Transmit Request bit 12        
C1MCRC.MSGLST_CPUUPD11   11  Message Lost_CPU Update bit 11 
C1MCRC.MSGLST_CPUUPD10   10  Message Lost_CPU Update bit 10 
C1MCRC.NEWDAT9           9   New Data bit 9                 
C1MCRC.NEWDAT8           8   New Data bit 8                 
C1MCRC.MSGVAL7           7   Message Valid bit 7            
C1MCRC.MSGVAL6           6   Message Valid bit 6            
C1MCRC.TXIE5             5   Transmit Interrupt Enable bit 5
C1MCRC.TXIE4             4   Transmit Interrupt Enable bit 4
C1MCRC.RXIE3             3   Receive Interrupt Enable bit 3 
C1MCRC.RXIE2             2   Receive Interrupt Enable bit 2 
C1MCRC.INTPND1           1   Interrupt Pending bit 1        
C1MCRC.INTPND0           0   Interrupt Pending bit 0        
C1UARC                  0xEFC2  CAN1 Upper Arbitration Reg. (msg. C)
C1UARC.ID20              15  Identifier bit 20
C1UARC.ID19              14  Identifier bit 19
C1UARC.ID18              13  Identifier bit 18
C1UARC.ID17              12  Identifier bit 17
C1UARC.ID16              11  Identifier bit 16
C1UARC.ID15              10  Identifier bit 15
C1UARC.ID14              9   Identifier bit 14
C1UARC.ID13              8   Identifier bit 13
C1UARC.ID28              7   Identifier bit 28
C1UARC.ID27              6   Identifier bit 27
C1UARC.ID26              5   Identifier bit 26
C1UARC.ID25              4   Identifier bit 25
C1UARC.ID24              3   Identifier bit 24
C1UARC.ID23              2   Identifier bit 23
C1UARC.ID22              1   Identifier bit 22
C1UARC.ID21              0   Identifier bit 21
C1LARC                  0xEFC4  CAN1 Lower Arbitration Reg. (msg. C)
C1LARC.ID4               15  Identifier bit 4 
C1LARC.ID3               14  Identifier bit 3 
C1LARC.ID2               13  Identifier bit 2 
C1LARC.ID1               12  Identifier bit 1 
C1LARC.ID0               11  Identifier bit 0 
C1LARC.ID12              7   Identifier bit 12
C1LARC.ID11              6   Identifier bit 11
C1LARC.ID10              5   Identifier bit 10
C1LARC.ID9               4   Identifier bit 9 
C1LARC.ID8               3   Identifier bit 8 
C1LARC.ID7               2   Identifier bit 7 
C1LARC.ID6               1   Identifier bit 6 
C1LARC.ID5               0   Identifier bit 5 
C1MCFGC         0xEFC6  CAN1 Message Configuration Register (msg. C)
C1MCFGC.DLC7     7   Data Length Code bit 7
C1MCFGC.DLC6     6   Data Length Code bit 6
C1MCFGC.DLC5     5   Data Length Code bit 5
C1MCFGC.DLC4     4   Data Length Code bit 4
C1MCFGC.DIR      3   Message Direction
C1MCFGC.XTD      2   Extended Identifier
C1MCRD                  0xEFD0  CAN1 Message Ctrl. Reg. (msg. D)
C1MCRD.RMTPND15          15  Remote Pending bit 15          
C1MCRD.RMTPND14          14  Remote Pending bit 14          
C1MCRD.TXRQ13            13  Transmit Request bit 13        
C1MCRD.TXRQ12            12  Transmit Request bit 12        
C1MCRD.MSGLST_CPUUPD11   11  Message Lost_CPU Update bit 11 
C1MCRD.MSGLST_CPUUPD10   10  Message Lost_CPU Update bit 10 
C1MCRD.NEWDAT9           9   New Data bit 9                 
C1MCRD.NEWDAT8           8   New Data bit 8                 
C1MCRD.MSGVAL7           7   Message Valid bit 7            
C1MCRD.MSGVAL6           6   Message Valid bit 6            
C1MCRD.TXIE5             5   Transmit Interrupt Enable bit 5
C1MCRD.TXIE4             4   Transmit Interrupt Enable bit 4
C1MCRD.RXIE3             3   Receive Interrupt Enable bit 3 
C1MCRD.RXIE2             2   Receive Interrupt Enable bit 2 
C1MCRD.INTPND1           1   Interrupt Pending bit 1        
C1MCRD.INTPND0           0   Interrupt Pending bit 0        
C1UARD                  0xEFD2  CAN1 Upper Arbitration Reg. (msg. D)
C1UARD.ID20              15  Identifier bit 20
C1UARD.ID19              14  Identifier bit 19
C1UARD.ID18              13  Identifier bit 18
C1UARD.ID17              12  Identifier bit 17
C1UARD.ID16              11  Identifier bit 16
C1UARD.ID15              10  Identifier bit 15
C1UARD.ID14              9   Identifier bit 14
C1UARD.ID13              8   Identifier bit 13
C1UARD.ID28              7   Identifier bit 28
C1UARD.ID27              6   Identifier bit 27
C1UARD.ID26              5   Identifier bit 26
C1UARD.ID25              4   Identifier bit 25
C1UARD.ID24              3   Identifier bit 24
C1UARD.ID23              2   Identifier bit 23
C1UARD.ID22              1   Identifier bit 22
C1UARD.ID21              0   Identifier bit 21
C1LARD                  0xEFD4  CAN1 Lower Arbitration Reg. (msg. D)
C1LARD.ID4               15  Identifier bit 4 
C1LARD.ID3               14  Identifier bit 3 
C1LARD.ID2               13  Identifier bit 2 
C1LARD.ID1               12  Identifier bit 1 
C1LARD.ID0               11  Identifier bit 0 
C1LARD.ID12              7   Identifier bit 12
C1LARD.ID11              6   Identifier bit 11
C1LARD.ID10              5   Identifier bit 10
C1LARD.ID9               4   Identifier bit 9 
C1LARD.ID8               3   Identifier bit 8 
C1LARD.ID7               2   Identifier bit 7 
C1LARD.ID6               1   Identifier bit 6 
C1LARD.ID5               0   Identifier bit 5 
C1MCFGD         0xEFD6  CAN1 Message Configuration Register (msg. D)
C1MCFGD.DLC7     7   Data Length Code bit 7
C1MCFGD.DLC6     6   Data Length Code bit 6
C1MCFGD.DLC5     5   Data Length Code bit 5
C1MCFGD.DLC4     4   Data Length Code bit 4
C1MCFGD.DIR      3   Message Direction
C1MCFGD.XTD      2   Extended Identifier
C1MCRE                  0xEFE0  CAN1 Message Ctrl. Reg. (msg. E)
C1MCRE.RMTPND15          15  Remote Pending bit 15          
C1MCRE.RMTPND14          14  Remote Pending bit 14          
C1MCRE.TXRQ13            13  Transmit Request bit 13        
C1MCRE.TXRQ12            12  Transmit Request bit 12        
C1MCRE.MSGLST_CPUUPD11   11  Message Lost_CPU Update bit 11 
C1MCRE.MSGLST_CPUUPD10   10  Message Lost_CPU Update bit 10 
C1MCRE.NEWDAT9           9   New Data bit 9                 
C1MCRE.NEWDAT8           8   New Data bit 8                 
C1MCRE.MSGVAL7           7   Message Valid bit 7            
C1MCRE.MSGVAL6           6   Message Valid bit 6            
C1MCRE.TXIE5             5   Transmit Interrupt Enable bit 5
C1MCRE.TXIE4             4   Transmit Interrupt Enable bit 4
C1MCRE.RXIE3             3   Receive Interrupt Enable bit 3 
C1MCRE.RXIE2             2   Receive Interrupt Enable bit 2 
C1MCRE.INTPND1           1   Interrupt Pending bit 1        
C1MCRE.INTPND0           0   Interrupt Pending bit 0        
C1UARE                  0xEFE2  CAN1 Upper Arbitration Reg. (msg. E)
C1UARE.ID20              15  Identifier bit 20
C1UARE.ID19              14  Identifier bit 19
C1UARE.ID18              13  Identifier bit 18
C1UARE.ID17              12  Identifier bit 17
C1UARE.ID16              11  Identifier bit 16
C1UARE.ID15              10  Identifier bit 15
C1UARE.ID14              9   Identifier bit 14
C1UARE.ID13              8   Identifier bit 13
C1UARE.ID28              7   Identifier bit 28
C1UARE.ID27              6   Identifier bit 27
C1UARE.ID26              5   Identifier bit 26
C1UARE.ID25              4   Identifier bit 25
C1UARE.ID24              3   Identifier bit 24
C1UARE.ID23              2   Identifier bit 23
C1UARE.ID22              1   Identifier bit 22
C1UARE.ID21              0   Identifier bit 21
C1LARE                  0xEFE4  CAN1 Lower Arbitration Reg. (msg. E)
C1LARE.ID4               15  Identifier bit 4 
C1LARE.ID3               14  Identifier bit 3 
C1LARE.ID2               13  Identifier bit 2 
C1LARE.ID1               12  Identifier bit 1 
C1LARE.ID0               11  Identifier bit 0 
C1LARE.ID12              7   Identifier bit 12
C1LARE.ID11              6   Identifier bit 11
C1LARE.ID10              5   Identifier bit 10
C1LARE.ID9               4   Identifier bit 9 
C1LARE.ID8               3   Identifier bit 8 
C1LARE.ID7               2   Identifier bit 7 
C1LARE.ID6               1   Identifier bit 6 
C1LARE.ID5               0   Identifier bit 5 
C1MCFGE         0xEFE6  CAN1 Message Configuration Register (msg. E)
C1MCFGE.DLC7     7   Data Length Code bit 7
C1MCFGE.DLC6     6   Data Length Code bit 6
C1MCFGE.DLC5     5   Data Length Code bit 5
C1MCFGE.DLC4     4   Data Length Code bit 4
C1MCFGE.DIR      3   Message Direction
C1MCFGE.XTD      2   Extended Identifier
C1MCRF                  0xEFF0  CAN1 Message Ctrl. Reg. (msg. F)
C1MCRF.RMTPND15          15  Remote Pending bit 15          
C1MCRF.RMTPND14          14  Remote Pending bit 14          
C1MCRF.TXRQ13            13  Transmit Request bit 13        
C1MCRF.TXRQ12            12  Transmit Request bit 12        
C1MCRF.MSGLST_CPUUPD11   11  Message Lost_CPU Update bit 11 
C1MCRF.MSGLST_CPUUPD10   10  Message Lost_CPU Update bit 10 
C1MCRF.NEWDAT9           9   New Data bit 9                 
C1MCRF.NEWDAT8           8   New Data bit 8                 
C1MCRF.MSGVAL7           7   Message Valid bit 7            
C1MCRF.MSGVAL6           6   Message Valid bit 6            
C1MCRF.TXIE5             5   Transmit Interrupt Enable bit 5
C1MCRF.TXIE4             4   Transmit Interrupt Enable bit 4
C1MCRF.RXIE3             3   Receive Interrupt Enable bit 3 
C1MCRF.RXIE2             2   Receive Interrupt Enable bit 2 
C1MCRF.INTPND1           1   Interrupt Pending bit 1        
C1MCRF.INTPND0           0   Interrupt Pending bit 0        
C1UARF                  0xEFF2  CAN1 Upper Arbitration Reg. (msg. F)
C1UARF.ID20              15  Identifier bit 20
C1UARF.ID19              14  Identifier bit 19
C1UARF.ID18              13  Identifier bit 18
C1UARF.ID17              12  Identifier bit 17
C1UARF.ID16              11  Identifier bit 16
C1UARF.ID15              10  Identifier bit 15
C1UARF.ID14              9   Identifier bit 14
C1UARF.ID13              8   Identifier bit 13
C1UARF.ID28              7   Identifier bit 28
C1UARF.ID27              6   Identifier bit 27
C1UARF.ID26              5   Identifier bit 26
C1UARF.ID25              4   Identifier bit 25
C1UARF.ID24              3   Identifier bit 24
C1UARF.ID23              2   Identifier bit 23
C1UARF.ID22              1   Identifier bit 22
C1UARF.ID21              0   Identifier bit 21
C1LARF                  0xEFF4  CAN1 Lower Arbitration Reg. (msg. F)
C1LARF.ID4               15  Identifier bit 4 
C1LARF.ID3               14  Identifier bit 3 
C1LARF.ID2               13  Identifier bit 2 
C1LARF.ID1               12  Identifier bit 1 
C1LARF.ID0               11  Identifier bit 0 
C1LARF.ID12              7   Identifier bit 12
C1LARF.ID11              6   Identifier bit 11
C1LARF.ID10              5   Identifier bit 10
C1LARF.ID9               4   Identifier bit 9 
C1LARF.ID8               3   Identifier bit 8 
C1LARF.ID7               2   Identifier bit 7 
C1LARF.ID6               1   Identifier bit 6 
C1LARF.ID5               0   Identifier bit 5 
C1MCFGF         0xEFF6  CAN1 Message Configuration Register (msg. F)
C1MCFGF.DLC7     7   Data Length Code bit 7
C1MCFGF.DLC6     6   Data Length Code bit 6
C1MCFGF.DLC5     5   Data Length Code bit 5
C1MCFGF.DLC4     4   Data Length Code bit 4
C1MCFGF.DIR      3   Message Direction
C1MCFGF.XTD      2   Extended Identifier
PT0              0xF030 PWM Module Up/Down Counter 0
PT1              0xF032 PWM Module Up/Down Counter 1
PT2              0xF034 PWM Module Up/Down Counter 2
PT3              0xF036 PWM Module Up/Down Counter 3
PP0              0xF038 PWM Module Period Register 0
PP1              0xF03A PWM Module Period Register 1
PP2              0xF03C PWM Module Period Register 2
PP3              0xF03E PWM Module Period Register 3
T7               0xF050 CAPCOM Timer 7 Register
T8               0xF052 CAPCOM Timer 8 Register
T7REL            0xF054 CAPCOM Timer 7 Reload Register
T8REL            0xF056 CAPCOM Timer 8 Reload Register
ADDAT2           0xF0A0 A/D Converter 2 Result Register
ADDAT2.CHNR15     15  Channel Number bit 15
ADDAT2.CHNR14     14  Channel Number bit 14
ADDAT2.CHNR13     13  Channel Number bit 13
ADDAT2.CHNR12     12  Channel Number bit 12
ADDAT2.ADRES9     9   A/D Conversion Result bit 9
ADDAT2.ADRES8     8   A/D Conversion Result bit 8
ADDAT2.ADRES7     7   A/D Conversion Result bit 7
ADDAT2.ADRES6     6   A/D Conversion Result bit 6
ADDAT2.ADRES5     5   A/D Conversion Result bit 5
ADDAT2.ADRES4     4   A/D Conversion Result bit 4
ADDAT2.ADRES3     3   A/D Conversion Result bit 3
ADDAT2.ADRES2     2   A/D Conversion Result bit 2
ADDAT2.ADRES1     1   A/D Conversion Result bit 1
ADDAT2.ADRES0     0   A/D Conversion Result bit 0
PDCR             0xF0AA   Port Driver Control Reg.
PDCR.NBPEC        4   Non-Bus Pins Edge Characteristic
PDCR.BIPEC        0   Bus Interface Pins Edge Characteristic
SSCTB            0xF0B0 SSC Transmit Buffer
SSCRB            0xF0B2 SSC Receive Buffer
SSCBR            0xF0B4 SSC Baudrate Register
DP0L             0xF100 P0L Direction Control Register
DP0L.DP0L7        7   Port direction register DP0L bit 7
DP0L.DP0L6        6   Port direction register DP0L bit 6
DP0L.DP0L5        5   Port direction register DP0L bit 5
DP0L.DP0L4        4   Port direction register DP0L bit 4
DP0L.DP0L3        3   Port direction register DP0L bit 3
DP0L.DP0L2        2   Port direction register DP0L bit 2
DP0L.DP0L1        1   Port direction register DP0L bit 1
DP0L.DP0L0        0   Port direction register DP0L bit 0
DP0H             0xF102 P0H Direction Control Register
DP0H.DP0H7        7   Port direction register DP0H bit 7
DP0H.DP0H6        6   Port direction register DP0H bit 6
DP0H.DP0H5        5   Port direction register DP0H bit 5
DP0H.DP0H4        4   Port direction register DP0H bit 4
DP0H.DP0H3        3   Port direction register DP0H bit 3
DP0H.DP0H2        2   Port direction register DP0H bit 2
DP0H.DP0H1        1   Port direction register DP0H bit 1
DP0H.DP0H0        0   Port direction register DP0H bit 0
DP1L             0xF104 P1L Direction Control Register
DP1L.DP1L7        7   Port direction register DP1L bit 7
DP1L.DP1L6        6   Port direction register DP1L bit 6
DP1L.DP1L5        5   Port direction register DP1L bit 5
DP1L.DP1L4        4   Port direction register DP1L bit 4
DP1L.DP1L3        3   Port direction register DP1L bit 3
DP1L.DP1L2        2   Port direction register DP1L bit 2
DP1L.DP1L1        1   Port direction register DP1L bit 1
DP1L.DP1L0        0   Port direction register DP1L bit 0
DP1H             0xF106 P1H Direction Control Register
DP1H.DP1H7        7   Port direction register DP1H bit 7
DP1H.DP1H6        6   Port direction register DP1H bit 6
DP1H.DP1H5        5   Port direction register DP1H bit 5
DP1H.DP1H4        4   Port direction register DP1H bit 4
DP1H.DP1H3        3   Port direction register DP1H bit 3
DP1H.DP1H2        2   Port direction register DP1H bit 2
DP1H.DP1H1        1   Port direction register DP1H bit 1
DP1H.DP1H0        0   Port direction register DP1H bit 0
RP0H             0xF108 System Startup Configuration Register (read only)
RP0H.CLKCFG7      7   Clock Generation Mode Configuration bit 7
RP0H.CLKCFG6      6   Clock Generation Mode Configuration bit 6
RP0H.CLKCFG5      5   Clock Generation Mode Configuration bit 5
RP0H.SALSEL4      4   Segment Address Line Selection bit 4
RP0H.SALSEL3      3   Segment Address Line Selection bit 3
RP0H.CSSEL2       2   Chip Select Line Selection bit 2
RP0H.CSSEL1       1   Chip Select Line Selection bit 1
RP0H.WRC          0   Write Configuration
CC16IC           0xF160 CAPCOM Register 16 Interrupt Ctrl. Reg.
CC16IC.CC16IR     7
CC16IC.CC16IE     6
CC16IC.ILVL5      5
CC16IC.ILVL4      4
CC16IC.ILVL3      3
CC16IC.ILVL2      2
CC16IC.GLVL1      1
CC16IC.GLVL0      0
CC17IC           0xF162 CAPCOM Register 17 Interrupt Ctrl. Reg.
CC17IC.CC17IR     7
CC17IC.CC17IE     6
CC17IC.ILVL5      5
CC17IC.ILVL4      4
CC17IC.ILVL3      3
CC17IC.ILVL2      2
CC17IC.GLVL1      1
CC17IC.GLVL0      0
CC18IC           0xF164 CAPCOM Register 18 Interrupt Ctrl. Reg.
CC18IC.CC18IR     7
CC18IC.CC18IE     6
CC18IC.ILVL5      5
CC18IC.ILVL4      4
CC18IC.ILVL3      3
CC18IC.ILVL2      2
CC18IC.GLVL1      1
CC18IC.GLVL0      0
CC19IC           0xF166 CAPCOM Register 19 Interrupt Ctrl. Reg.
CC19IC.CC19IR     7
CC19IC.CC19IE     6
CC19IC.ILVL5      5
CC19IC.ILVL4      4
CC19IC.ILVL3      3
CC19IC.ILVL2      2
CC19IC.GLVL1      1
CC19IC.GLVL0      0
CC20IC           0xF168 CAPCOM Register 20 Interrupt Ctrl. Reg.
CC20IC.CC20IR     7
CC20IC.CC20IE     6
CC20IC.ILVL5      5
CC20IC.ILVL4      4
CC20IC.ILVL3      3
CC20IC.ILVL2      2
CC20IC.GLVL1      1
CC20IC.GLVL0      0
CC21IC           0xF16A CAPCOM Register 21 Interrupt Ctrl. Reg.
CC21IC.CC21IR     7
CC21IC.CC21IE     6
CC21IC.ILVL5      5
CC21IC.ILVL4      4
CC21IC.ILVL3      3
CC21IC.ILVL2      2
CC21IC.GLVL1      1
CC21IC.GLVL0      0
CC22IC           0xF16C CAPCOM Register 22 Interrupt Ctrl. Reg.
CC22IC.CC22IR     7
CC22IC.CC22IE     6
CC22IC.ILVL5      5
CC22IC.ILVL4      4
CC22IC.ILVL3      3
CC22IC.ILVL2      2
CC22IC.GLVL1      1
CC22IC.GLVL0      0
CC23IC           0xF16E CAPCOM Register 23 Interrupt Ctrl. Reg.
CC23IC.CC23IR     7
CC23IC.CC23IE     6
CC23IC.ILVL5      5
CC23IC.ILVL4      4
CC23IC.ILVL3      3
CC23IC.ILVL2      2
CC23IC.GLVL1      1
CC23IC.GLVL0      0
CC24IC           0xF170 CAPCOM Register 24 Interrupt Ctrl. Reg.
CC24IC.CC24IR     7
CC24IC.CC24IE     6
CC24IC.ILVL5      5
CC24IC.ILVL4      4
CC24IC.ILVL3      3
CC24IC.ILVL2      2
CC24IC.GLVL1      1
CC24IC.GLVL0      0
CC25IC           0xF172 CAPCOM Register 25 Interrupt Ctrl. Reg.
CC25IC.CC25IR     7
CC25IC.CC25IE     6
CC25IC.ILVL5      5
CC25IC.ILVL4      4
CC25IC.ILVL3      3
CC25IC.ILVL2      2
CC25IC.GLVL1      1
CC25IC.GLVL0      0
CC26IC           0xF174 CAPCOM Register 26 Interrupt Ctrl. Reg.
CC26IC.CC26IR     7
CC26IC.CC26IE     6
CC26IC.ILVL5      5
CC26IC.ILVL4      4
CC26IC.ILVL3      3
CC26IC.ILVL2      2
CC26IC.GLVL1      1
CC26IC.GLVL0      0
CC27IC           0xF176 CAPCOM Register 27 Interrupt Ctrl. Reg.
CC27IC.CC27IR     7
CC27IC.CC27IE     6
CC27IC.ILVL5      5
CC27IC.ILVL4      4
CC27IC.ILVL3      3
CC27IC.ILVL2      2
CC27IC.GLVL1      1
CC27IC.GLVL0      0
CC28IC           0xF178 CAPCOM Register 28 Interrupt Ctrl. Reg.
CC28IC.CC28IR     7
CC28IC.CC28IE     6
CC28IC.ILVL5      5
CC28IC.ILVL4      4
CC28IC.ILVL3      3
CC28IC.ILVL2      2
CC28IC.GLVL1      1
CC28IC.GLVL0      0
T7IC             0xF17A CAPCOM Timer 7 Interrupt Ctrl. Reg.
T7IC.T7IR         7
T7IC.T7IE         6
T7IC.ILVL5        5
T7IC.ILVL4        4
T7IC.ILVL3        3
T7IC.ILVL2        2
T7IC.GLVL1        1
T7IC.GLVL0        0
T8IC             0xF17C CAPCOM Timer 8 Interrupt Ctrl. Reg.
T8IC.T8IR         7
T8IC.T8IE         6
T8IC.ILVL5        5
T8IC.ILVL4        4
T8IC.ILVL3        3
T8IC.ILVL2        2
T8IC.GLVL1        1
T8IC.GLVL0        0
PWMIC            0xF17E PWM Module Interrupt Control Register
PWMIC.PWMIR       7
PWMIC.PWMIE       6
PWMIC.ILVL5       5
PWMIC.ILVL4       4
PWMIC.ILVL3       3
PWMIC.ILVL2       2
PWMIC.GLVL1       1
PWMIC.GLVL0       0
CC29IC           0xF184 CAPCOM Register 29 Interrupt Ctrl. Reg.
CC29IC.CC29IR     7
CC29IC.CC29IE     6
CC29IC.ILVL5      5
CC29IC.ILVL4      4
CC29IC.ILVL3      3
CC29IC.ILVL2      2
CC29IC.GLVL1      1
CC29IC.GLVL0      0
XP0IC            0xF186 CAN1 Interrupt Control Register
XP0IC.XP0IR       7
XP0IC.XP0IE       6
CC30IC           0xF18C CAPCOM Register 30 Interrupt Ctrl. Reg.
CC30IC.CC30IR     7
CC30IC.CC30IE     6
CC30IC.ILVL5      5
CC30IC.ILVL4      4
CC30IC.ILVL3      3
CC30IC.ILVL2      2
CC30IC.GLVL1      1
CC30IC.GLVL0      0
XP1IC            0xF18E Unassigned Interrupt Control Register
XP1IC.XP1IR       7
XP1IC.XP1IE       6
CC31IC           0xF194 CAPCOM Register 31 Interrupt Ctrl. Reg.
CC31IC.CC31IR     7
CC31IC.CC31IE     6
CC31IC.ILVL5      5
CC31IC.ILVL4      4
CC31IC.ILVL3      3
CC31IC.ILVL2      2
CC31IC.GLVL1      1
CC31IC.GLVL0      0
XP2IC            0xF196 Unassigned Interrupt Control Register
XP2IC.XP2IR       7
XP2IC.XP2IE       6
S0TBIC           0xF19C Serial Channel 0 Transmit Buffer Interrupt Control Register
S0TBIC.S0TBIR     7
S0TBIC.S0TBIE     6
S0TBIC.ILVL5      5
S0TBIC.ILVL4      4
S0TBIC.ILVL3      3
S0TBIC.ILVL2      2
S0TBIC.GLVL1      1
S0TBIC.GLVL0      0
XP3IC            0xF19E PLL/OWD Interrupt Control Register
XP3IC.XP3IR       7
XP3IC.XP3IE       6
EXICON           0xF1C0 External Interrupt Control Register
EXICON.EXI7ES     7   External Interrupt 7 Edge Selection Field
EXICON.EXI6ES     6   External Interrupt 6 Edge Selection Field
EXICON.EXI5ES     5   External Interrupt 5 Edge Selection Field
EXICON.EXI4ES     4   External Interrupt 4 Edge Selection Field
EXICON.EXI3ES     3   External Interrupt 3 Edge Selection Field
EXICON.EXI2ES     2   External Interrupt 2 Edge Selection Field
EXICON.EXI1ES     1   External Interrupt 1 Edge Selection Field
EXICON.EXI0ES     0   External Interrupt 0 Edge Selection Field
ODP2             0xF1C2 Port 2 Open Drain Control Register
ODP2.ODP2_15      15  Port 2 Open Drain control register bit 15
ODP2.ODP2_14      14  Port 2 Open Drain control register bit 14
ODP2.ODP2_13      13  Port 2 Open Drain control register bit 13
ODP2.ODP2_12      12  Port 2 Open Drain control register bit 12
ODP2.ODP2_11      11  Port 2 Open Drain control register bit 11
ODP2.ODP2_10      10  Port 2 Open Drain control register bit 10
ODP2.ODP2_9       9   Port 2 Open Drain control register bit 9 
ODP2.ODP2_8       8   Port 2 Open Drain control register bit 8 
ODP2.ODP2_7       7   Port 2 Open Drain control register bit 7 
ODP2.ODP2_6       6   Port 2 Open Drain control register bit 6 
ODP2.ODP2_5       5   Port 2 Open Drain control register bit 5 
ODP2.ODP2_4       4   Port 2 Open Drain control register bit 4 
ODP2.ODP2_3       3   Port 2 Open Drain control register bit 3 
ODP2.ODP2_2       2   Port 2 Open Drain control register bit 2 
ODP2.ODP2_1       1   Port 2 Open Drain control register bit 1 
ODP2.ODP2_0       0   Port 2 Open Drain control register bit 0 
PICON            0xF1C4   Port Input Control Reg.
PICON.P8LIN       7   Port 8 Low Byte Input Level Selection
PICON.P7LIN       6   Port 7 Low Byte Input Level Selection
PICON.P6LIN       5   Port 6 Low Byte Input Level Selection
PICON.P3HIN       3   Port 3 High Byte Input Level Selection
PICON.P3LIN       2   Port 3 Low Byte Input Level Selection
PICON.P2HIN       1   Port 2 High Byte Input Level Selection
PICON.P2LIN       0   Port 2 Low Byte Input Level Selection
ODP3             0xF1C6 Port 3 Open Drain Control Register
ODP3.ODP3_13      13  Port 3 Open Drain control register bit 13
ODP3.ODP3_11      11  Port 3 Open Drain control register bit 11
ODP3.ODP3_10      10  Port 3 Open Drain control register bit 10
ODP3.ODP3_9       9   Port 3 Open Drain control register bit 9 
ODP3.ODP3_8       8   Port 3 Open Drain control register bit 8 
ODP3.ODP3_7       7   Port 3 Open Drain control register bit 7 
ODP3.ODP3_6       6   Port 3 Open Drain control register bit 6 
ODP3.ODP3_5       5   Port 3 Open Drain control register bit 5 
ODP3.ODP3_4       4   Port 3 Open Drain control register bit 4 
ODP3.ODP3_3       3   Port 3 Open Drain control register bit 3 
ODP3.ODP3_2       2   Port 3 Open Drain control register bit 2 
ODP3.ODP3_1       1   Port 3 Open Drain control register bit 1 
ODP3.ODP3_0       0   Port 3 Open Drain control register bit 0 
ODP6             0xF1CE Port 6 Open Drain Control Register
ODP6.ODP6_7       7   Port 6 Open Drain control register bit 7
ODP6.ODP6_6       6   Port 6 Open Drain control register bit 6
ODP6.ODP6_5       5   Port 6 Open Drain control register bit 5
ODP6.ODP6_4       4   Port 6 Open Drain control register bit 4
ODP6.ODP6_3       3   Port 6 Open Drain control register bit 3
ODP6.ODP6_2       2   Port 6 Open Drain control register bit 2
ODP6.ODP6_1       1   Port 6 Open Drain control register bit 1
ODP6.ODP6_0       0   Port 6 Open Drain control register bit 0
ODP7             0xF1D2 Port 7 Open Drain Control Register
ODP7.ODP7_7       7   Port 7 Open Drain control register bit 7
ODP7.ODP7_6       6   Port 7 Open Drain control register bit 6
ODP7.ODP7_5       5   Port 7 Open Drain control register bit 5
ODP7.ODP7_4       4   Port 7 Open Drain control register bit 4
ODP7.ODP7_3       3   Port 7 Open Drain control register bit 3
ODP7.ODP7_2       2   Port 7 Open Drain control register bit 2
ODP7.ODP7_1       1   Port 7 Open Drain control register bit 1
ODP7.ODP7_0       0   Port 7 Open Drain control register bit 0
ODP8             0xF1D6 Port 8 Open Drain Control Register
ODP8.ODP8_7       7   Port 8 Open Drain control register bit 7
ODP8.ODP8_6       6   Port 8 Open Drain control register bit 6
ODP8.ODP8_5       5   Port 8 Open Drain control register bit 5
ODP8.ODP8_4       4   Port 8 Open Drain control register bit 4
ODP8.ODP8_3       3   Port 8 Open Drain control register bit 3
ODP8.ODP8_2       2   Port 8 Open Drain control register bit 2
ODP8.ODP8_1       1   Port 8 Open Drain control register bit 1
ODP8.ODP8_0       0   Port 8 Open Drain control register bit 0
DPP0             0xFE00 CPU Data Page Pointer 0 Register (10 bits)
DPP0.DPP0PN9      9   Data Page Number of DPP0 bit 9
DPP0.DPP0PN8      8   Data Page Number of DPP0 bit 8
DPP0.DPP0PN7      7   Data Page Number of DPP0 bit 7
DPP0.DPP0PN6      6   Data Page Number of DPP0 bit 6
DPP0.DPP0PN5      5   Data Page Number of DPP0 bit 5
DPP0.DPP0PN4      4   Data Page Number of DPP0 bit 4
DPP0.DPP0PN3      3   Data Page Number of DPP0 bit 3
DPP0.DPP0PN2      2   Data Page Number of DPP0 bit 2
DPP0.DPP0PN1      1   Data Page Number of DPP0 bit 1
DPP0.DPP0PN0      0   Data Page Number of DPP0 bit 0
DPP1             0xFE02 CPU Data Page Pointer 1 Register (10 bits)
DPP1.DPP1PN9      9   Data Page Number of DPP1 bit 9
DPP1.DPP1PN8      8   Data Page Number of DPP1 bit 8
DPP1.DPP1PN7      7   Data Page Number of DPP1 bit 7
DPP1.DPP1PN6      6   Data Page Number of DPP1 bit 6
DPP1.DPP1PN5      5   Data Page Number of DPP1 bit 5
DPP1.DPP1PN4      4   Data Page Number of DPP1 bit 4
DPP1.DPP1PN3      3   Data Page Number of DPP1 bit 3
DPP1.DPP1PN2      2   Data Page Number of DPP1 bit 2
DPP1.DPP1PN1      1   Data Page Number of DPP1 bit 1
DPP1.DPP1PN0      0   Data Page Number of DPP1 bit 0
DPP2             0xFE04 CPU Data Page Pointer 2 Register (10 bits)
DPP2.DPP2PN9      9   Data Page Number of DPP2 bit 9
DPP2.DPP2PN8      8   Data Page Number of DPP2 bit 8
DPP2.DPP2PN7      7   Data Page Number of DPP2 bit 7
DPP2.DPP2PN6      6   Data Page Number of DPP2 bit 6
DPP2.DPP2PN5      5   Data Page Number of DPP2 bit 5
DPP2.DPP2PN4      4   Data Page Number of DPP2 bit 4
DPP2.DPP2PN3      3   Data Page Number of DPP2 bit 3
DPP2.DPP2PN2      2   Data Page Number of DPP2 bit 2
DPP2.DPP2PN1      1   Data Page Number of DPP2 bit 1
DPP2.DPP2PN0      0   Data Page Number of DPP2 bit 0
DPP3             0xFE06 CPU Data Page Pointer 3 Register (10 bits)
DPP3.DPP3PN9      9   Data Page Number of DPP3 bit 9
DPP3.DPP3PN8      8   Data Page Number of DPP3 bit 8
DPP3.DPP3PN7      7   Data Page Number of DPP3 bit 7
DPP3.DPP3PN6      6   Data Page Number of DPP3 bit 6
DPP3.DPP3PN5      5   Data Page Number of DPP3 bit 5
DPP3.DPP3PN4      4   Data Page Number of DPP3 bit 4
DPP3.DPP3PN3      3   Data Page Number of DPP3 bit 3
DPP3.DPP3PN2      2   Data Page Number of DPP3 bit 2
DPP3.DPP3PN1      1   Data Page Number of DPP3 bit 1
DPP3.DPP3PN0      0   Data Page Number of DPP3 bit 0
CSP              0xFE08 CPU Code Segment Pointer Register (8 bits, not directly writeable)
CSP.SEGNR7        7   Segment Number 7
CSP.SEGNR6        6   Segment Number 6
CSP.SEGNR5        5   Segment Number 5
CSP.SEGNR4        4   Segment Number 4
CSP.SEGNR3        3   Segment Number 3
CSP.SEGNR2        2   Segment Number 2
CSP.SEGNR1        1   Segment Number 1
CSP.SEGNR0        0   Segment Number 0
MDH              0xFE0C   Multiply/Divide High Reg.
MDH.MDH15         15
MDH.MDH14         14
MDH.MDH13         13
MDH.MDH12         12
MDH.MDH11         11
MDH.MDH10         10
MDH.MDH9          9
MDH.MDH8          8
MDH.MDH7          7
MDH.MDH6          6
MDH.MDH5          5
MDH.MDH4          4
MDH.MDH3          3
MDH.MDH2          2
MDH.MDH1          1
MDH.MDH0          0
MDL              0xFE0E   Multiply/Divide Low Reg.
MDL.MDL15         15
MDL.MDL14         14
MDL.MDL13         13
MDL.MDL12         12
MDL.MDL11         11
MDL.MDL10         10
MDL.MDL9          9
MDL.MDL8          8
MDL.MDL7          7
MDL.MDL6          6
MDL.MDL5          5
MDL.MDL4          4
MDL.MDL3          3
MDL.MDL2          2
MDL.MDL1          1
MDL.MDL0          0
CP               0xFE10 CPU Context Pointer Register
CP.CP11           11  Modifiable portion of register CP bit 11
CP.CP10           10  Modifiable portion of register CP bit 10
CP.CP9            9   Modifiable portion of register CP bit 9 
CP.CP8            8   Modifiable portion of register CP bit 8 
CP.CP7            7   Modifiable portion of register CP bit 7 
CP.CP6            6   Modifiable portion of register CP bit 6 
CP.CP5            5   Modifiable portion of register CP bit 5 
CP.CP4            4   Modifiable portion of register CP bit 4 
CP.CP3            3   Modifiable portion of register CP bit 3 
CP.CP2            2   Modifiable portion of register CP bit 2 
CP.CP1            1   Modifiable portion of register CP bit 1 
SP               0xFE12 CPU System Stack Pointer Register
SP.SP11           11  Modifiable portion of register SP bit 11
SP.SP10           10  Modifiable portion of register SP bit 10
SP.SP9            9   Modifiable portion of register SP bit 9 
SP.SP8            8   Modifiable portion of register SP bit 8 
SP.SP7            7   Modifiable portion of register SP bit 7 
SP.SP6            6   Modifiable portion of register SP bit 6 
SP.SP5            5   Modifiable portion of register SP bit 5 
SP.SP4            4   Modifiable portion of register SP bit 4 
SP.SP3            3   Modifiable portion of register SP bit 3 
SP.SP2            2   Modifiable portion of register SP bit 2 
SP.SP1            1   Modifiable portion of register SP bit 1 
STKOV            0xFE14 CPU Stack Overflow Pointer Register
STKOV.STKOV11     11  Modifiable portion of register STKOV bit 11
STKOV.STKOV10     10  Modifiable portion of register STKOV bit 10
STKOV.STKOV9      9   Modifiable portion of register STKOV bit 9 
STKOV.STKOV8      8   Modifiable portion of register STKOV bit 8 
STKOV.STKOV7      7   Modifiable portion of register STKOV bit 7 
STKOV.STKOV6      6   Modifiable portion of register STKOV bit 6 
STKOV.STKOV5      5   Modifiable portion of register STKOV bit 5 
STKOV.STKOV4      4   Modifiable portion of register STKOV bit 4 
STKOV.STKOV3      3   Modifiable portion of register STKOV bit 3 
STKOV.STKOV2      2   Modifiable portion of register STKOV bit 2 
STKOV.STKOV1      1   Modifiable portion of register STKOV bit 1 
STKUN            0xFE16 CPU Stack Underflow Pointer Register
STKUN.STKUN11     11  Modifiable portion of register STKUN bit 11
STKUN.STKUN10     10  Modifiable portion of register STKUN bit 10
STKUN.STKUN9      9   Modifiable portion of register STKUN bit 9 
STKUN.STKUN8      8   Modifiable portion of register STKUN bit 8 
STKUN.STKUN7      7   Modifiable portion of register STKUN bit 7 
STKUN.STKUN6      6   Modifiable portion of register STKUN bit 6 
STKUN.STKUN5      5   Modifiable portion of register STKUN bit 5 
STKUN.STKUN4      4   Modifiable portion of register STKUN bit 4 
STKUN.STKUN3      3   Modifiable portion of register STKUN bit 3 
STKUN.STKUN2      2   Modifiable portion of register STKUN bit 2 
STKUN.STKUN1      1   Modifiable portion of register STKUN bit 1 
ADDRSEL1         0xFE18 Address Select Register 1
ADDRSEL1.RGSAD15  15  Range Start Address bit 15
ADDRSEL1.RGSAD14  14  Range Start Address bit 14
ADDRSEL1.RGSAD13  13  Range Start Address bit 13
ADDRSEL1.RGSAD12  12  Range Start Address bit 12
ADDRSEL1.RGSAD11  11  Range Start Address bit 11
ADDRSEL1.RGSAD10  10  Range Start Address bit 10
ADDRSEL1.RGSAD9   9   Range Start Address bit 9 
ADDRSEL1.RGSAD8   8   Range Start Address bit 8 
ADDRSEL1.RGSAD7   7   Range Start Address bit 7 
ADDRSEL1.RGSAD6   6   Range Start Address bit 6 
ADDRSEL1.RGSAD5   5   Range Start Address bit 5 
ADDRSEL1.RGSAD4   4   Range Start Address bit 4 
ADDRSEL1.RGSZ3    3   Range Size Selection bit 3
ADDRSEL1.RGSZ2    2   Range Size Selection bit 2
ADDRSEL1.RGSZ1    1   Range Size Selection bit 1
ADDRSEL1.RGSZ0    0   Range Size Selection bit 0
ADDRSEL2         0xFE1A Address Select Register 2
ADDRSEL2.RGSAD15  15  Range Start Address bit 15
ADDRSEL2.RGSAD14  14  Range Start Address bit 14
ADDRSEL2.RGSAD13  13  Range Start Address bit 13
ADDRSEL2.RGSAD12  12  Range Start Address bit 12
ADDRSEL2.RGSAD11  11  Range Start Address bit 11
ADDRSEL2.RGSAD10  10  Range Start Address bit 10
ADDRSEL2.RGSAD9   9   Range Start Address bit 9 
ADDRSEL2.RGSAD8   8   Range Start Address bit 8 
ADDRSEL2.RGSAD7   7   Range Start Address bit 7 
ADDRSEL2.RGSAD6   6   Range Start Address bit 6 
ADDRSEL2.RGSAD5   5   Range Start Address bit 5 
ADDRSEL2.RGSAD4   4   Range Start Address bit 4 
ADDRSEL2.RGSZ3    3   Range Size Selection bit 3
ADDRSEL2.RGSZ2    2   Range Size Selection bit 2
ADDRSEL2.RGSZ1    1   Range Size Selection bit 1
ADDRSEL2.RGSZ0    0   Range Size Selection bit 0
ADDRSEL3         0xFE1C Address Select Register 3
ADDRSEL3.RGSAD15  15  Range Start Address bit 15
ADDRSEL3.RGSAD14  14  Range Start Address bit 14
ADDRSEL3.RGSAD13  13  Range Start Address bit 13
ADDRSEL3.RGSAD12  12  Range Start Address bit 12
ADDRSEL3.RGSAD11  11  Range Start Address bit 11
ADDRSEL3.RGSAD10  10  Range Start Address bit 10
ADDRSEL3.RGSAD9   9   Range Start Address bit 9 
ADDRSEL3.RGSAD8   8   Range Start Address bit 8 
ADDRSEL3.RGSAD7   7   Range Start Address bit 7 
ADDRSEL3.RGSAD6   6   Range Start Address bit 6 
ADDRSEL3.RGSAD5   5   Range Start Address bit 5 
ADDRSEL3.RGSAD4   4   Range Start Address bit 4 
ADDRSEL3.RGSZ3    3   Range Size Selection bit 3
ADDRSEL3.RGSZ2    2   Range Size Selection bit 2
ADDRSEL3.RGSZ1    1   Range Size Selection bit 1
ADDRSEL3.RGSZ0    0   Range Size Selection bit 0
ADDRSEL4         0xFE1E Address Select Register 4
ADDRSEL4.RGSAD15  15  Range Start Address bit 15
ADDRSEL4.RGSAD14  14  Range Start Address bit 14
ADDRSEL4.RGSAD13  13  Range Start Address bit 13
ADDRSEL4.RGSAD12  12  Range Start Address bit 12
ADDRSEL4.RGSAD11  11  Range Start Address bit 11
ADDRSEL4.RGSAD10  10  Range Start Address bit 10
ADDRSEL4.RGSAD9   9   Range Start Address bit 9 
ADDRSEL4.RGSAD8   8   Range Start Address bit 8 
ADDRSEL4.RGSAD7   7   Range Start Address bit 7 
ADDRSEL4.RGSAD6   6   Range Start Address bit 6 
ADDRSEL4.RGSAD5   5   Range Start Address bit 5 
ADDRSEL4.RGSAD4   4   Range Start Address bit 4 
ADDRSEL4.RGSZ3    3   Range Size Selection bit 3
ADDRSEL4.RGSZ2    2   Range Size Selection bit 2
ADDRSEL4.RGSZ1    1   Range Size Selection bit 1
ADDRSEL4.RGSZ0    0   Range Size Selection bit 0
PW0              0xFE30 PWM Module Pulse Width Register 0
PW1              0xFE32 PWM Module Pulse Width Register 1
PW2              0xFE34 PWM Module Pulse Width Register 2
PW3              0xFE36 PWM Module Pulse Width Register 3
T2               0xFE40 GPT1 Timer 2 Register
T3               0xFE42 GPT1 Timer 3 Register
T4               0xFE44 GPT1 Timer 4 Register
T5               0xFE46 GPT2 Timer 5 Register
T6               0xFE48 GPT2 Timer 6 Register
CAPREL           0xFE4A GPT2 Capture/Reload Register
T0               0xFE50 CAPCOM Timer 0 Register
T1               0xFE52 CAPCOM Timer 1 Register
T0REL            0xFE54 CAPCOM Timer 0 Reload Register
T1REL            0xFE56 CAPCOM Timer 1 Reload Register
CC16             0xFE60 CAPCOM Register 16
CC17             0xFE62 CAPCOM Register 17
CC18             0xFE64 CAPCOM Register 18
CC19             0xFE66 CAPCOM Register 19
CC20             0xFE68 CAPCOM Register 20
CC21             0xFE6A CAPCOM Register 21
CC22             0xFE6C CAPCOM Register 22
CC23             0xFE6E CAPCOM Register 23
CC24             0xFE70 CAPCOM Register 24
CC25             0xFE72 CAPCOM Register 25
CC26             0xFE74 CAPCOM Register 26
CC27             0xFE76 CAPCOM Register 27
CC28             0xFE78 CAPCOM Register 28
CC29             0xFE7A CAPCOM Register 29
CC30             0xFE7C CAPCOM Register 30
CC31             0xFE7E CAPCOM Register 31
CC0              0xFE80 CAPCOM Register 0
CC1              0xFE82 CAPCOM Register 1
CC2              0xFE84 CAPCOM Register 2
CC3              0xFE86 CAPCOM Register 3
CC4              0xFE88 CAPCOM Register 4
CC5              0xFE8A CAPCOM Register 5
CC6              0xFE8C CAPCOM Register 6
CC7              0xFE8E CAPCOM Register 7
CC8              0xFE90 CAPCOM Register 8
CC9              0xFE92 CAPCOM Register 9
CC10             0xFE94 CAPCOM Register 10
CC11             0xFE96 CAPCOM Register 11
CC12             0xFE98 CAPCOM Register 12
CC13             0xFE9A CAPCOM Register 13
CC14             0xFE9C CAPCOM Register 14
CC15             0xFE9E CAPCOM Register 15
ADDAT            0xFEA0 A/D Converter Result Register
ADDAT.CHNR15      15  Channel Number bit 15      
ADDAT.CHNR14      14  Channel Number bit 14      
ADDAT.CHNR13      13  Channel Number bit 13      
ADDAT.CHNR12      12  Channel Number bit 12      
ADDAT.ADRES9      9   A/D Conversion Result bit 9
ADDAT.ADRES8      8   A/D Conversion Result bit 8
ADDAT.ADRES7      7   A/D Conversion Result bit 7
ADDAT.ADRES6      6   A/D Conversion Result bit 6
ADDAT.ADRES5      5   A/D Conversion Result bit 5
ADDAT.ADRES4      4   A/D Conversion Result bit 4
ADDAT.ADRES3      3   A/D Conversion Result bit 3
ADDAT.ADRES2      2   A/D Conversion Result bit 2
ADDAT.ADRES1      1   A/D Conversion Result bit 1
ADDAT.ADRES0      0   A/D Conversion Result bit 0
WDT              0xFEAE Watchdog Timer Register (read only)
S0TBUF           0xFEB0 Serial Channel 0 Transmit Buffer Register
S0RBUF           0xFEB2 Serial Channel 0 Receive Buffer Register (read only)
S0BG             0xFEB4 Serial Channel 0 Baud Rate Generator Reload Register
PECC0            0xFEC0 PEC Channel 0 Control Register
PECC0.INC10       10  Increment Control bit 10
PECC0.INC9        9   Increment Control bit 9 
PECC0.BWT         8   Byte/Word Transfer Selection
PECC0.COUNT7      7   PEC Transfer Count bit 7
PECC0.COUNT6      6   PEC Transfer Count bit 6
PECC0.COUNT5      5   PEC Transfer Count bit 5
PECC0.COUNT4      4   PEC Transfer Count bit 4
PECC0.COUNT3      3   PEC Transfer Count bit 3
PECC0.COUNT2      2   PEC Transfer Count bit 2
PECC0.COUNT1      1   PEC Transfer Count bit 1
PECC0.COUNT0      0   PEC Transfer Count bit 0
PECC1            0xFEC2 PEC Channel 1 Control Register
PECC1.INC10       10  Increment Control bit 10    
PECC1.INC9        9   Increment Control bit 9     
PECC1.BWT         8   Byte/Word Transfer Selection
PECC1.COUNT7      7   PEC Transfer Count bit 7    
PECC1.COUNT6      6   PEC Transfer Count bit 6    
PECC1.COUNT5      5   PEC Transfer Count bit 5    
PECC1.COUNT4      4   PEC Transfer Count bit 4    
PECC1.COUNT3      3   PEC Transfer Count bit 3    
PECC1.COUNT2      2   PEC Transfer Count bit 2    
PECC1.COUNT1      1   PEC Transfer Count bit 1    
PECC1.COUNT0      0   PEC Transfer Count bit 0    
PECC2            0xFEC4 PEC Channel 2 Control Register
PECC2.INC10       10  Increment Control bit 10    
PECC2.INC9        9   Increment Control bit 9     
PECC2.BWT         8   Byte/Word Transfer Selection
PECC2.COUNT7      7   PEC Transfer Count bit 7    
PECC2.COUNT6      6   PEC Transfer Count bit 6    
PECC2.COUNT5      5   PEC Transfer Count bit 5    
PECC2.COUNT4      4   PEC Transfer Count bit 4    
PECC2.COUNT3      3   PEC Transfer Count bit 3    
PECC2.COUNT2      2   PEC Transfer Count bit 2    
PECC2.COUNT1      1   PEC Transfer Count bit 1    
PECC2.COUNT0      0   PEC Transfer Count bit 0    
PECC3            0xFEC6 PEC Channel 3 Control Register
PECC3.INC10       10  Increment Control bit 10    
PECC3.INC9        9   Increment Control bit 9     
PECC3.BWT         8   Byte/Word Transfer Selection
PECC3.COUNT7      7   PEC Transfer Count bit 7    
PECC3.COUNT6      6   PEC Transfer Count bit 6    
PECC3.COUNT5      5   PEC Transfer Count bit 5    
PECC3.COUNT4      4   PEC Transfer Count bit 4    
PECC3.COUNT3      3   PEC Transfer Count bit 3    
PECC3.COUNT2      2   PEC Transfer Count bit 2    
PECC3.COUNT1      1   PEC Transfer Count bit 1    
PECC3.COUNT0      0   PEC Transfer Count bit 0    
PECC4            0xFEC8 PEC Channel 4 Control Register
PECC4.INC10       10  Increment Control bit 10    
PECC4.INC9        9   Increment Control bit 9     
PECC4.BWT         8   Byte/Word Transfer Selection
PECC4.COUNT7      7   PEC Transfer Count bit 7    
PECC4.COUNT6      6   PEC Transfer Count bit 6    
PECC4.COUNT5      5   PEC Transfer Count bit 5    
PECC4.COUNT4      4   PEC Transfer Count bit 4    
PECC4.COUNT3      3   PEC Transfer Count bit 3    
PECC4.COUNT2      2   PEC Transfer Count bit 2    
PECC4.COUNT1      1   PEC Transfer Count bit 1    
PECC4.COUNT0      0   PEC Transfer Count bit 0    
PECC5            0xFECA PEC Channel 5 Control Register
PECC5.INC10       10  Increment Control bit 10    
PECC5.INC9        9   Increment Control bit 9     
PECC5.BWT         8   Byte/Word Transfer Selection
PECC5.COUNT7      7   PEC Transfer Count bit 7    
PECC5.COUNT6      6   PEC Transfer Count bit 6    
PECC5.COUNT5      5   PEC Transfer Count bit 5    
PECC5.COUNT4      4   PEC Transfer Count bit 4    
PECC5.COUNT3      3   PEC Transfer Count bit 3    
PECC5.COUNT2      2   PEC Transfer Count bit 2    
PECC5.COUNT1      1   PEC Transfer Count bit 1    
PECC5.COUNT0      0   PEC Transfer Count bit 0    
PECC6            0xFECC PEC Channel 6 Control Register
PECC6.INC10       10  Increment Control bit 10    
PECC6.INC9        9   Increment Control bit 9     
PECC6.BWT         8   Byte/Word Transfer Selection
PECC6.COUNT7      7   PEC Transfer Count bit 7    
PECC6.COUNT6      6   PEC Transfer Count bit 6    
PECC6.COUNT5      5   PEC Transfer Count bit 5    
PECC6.COUNT4      4   PEC Transfer Count bit 4    
PECC6.COUNT3      3   PEC Transfer Count bit 3    
PECC6.COUNT2      2   PEC Transfer Count bit 2    
PECC6.COUNT1      1   PEC Transfer Count bit 1    
PECC6.COUNT0      0   PEC Transfer Count bit 0    
PECC7            0xFECE PEC Channel 7 Control Register
PECC7.INC10       10  Increment Control bit 10    
PECC7.INC9        9   Increment Control bit 9     
PECC7.BWT         8   Byte/Word Transfer Selection
PECC7.COUNT7      7   PEC Transfer Count bit 7    
PECC7.COUNT6      6   PEC Transfer Count bit 6    
PECC7.COUNT5      5   PEC Transfer Count bit 5    
PECC7.COUNT4      4   PEC Transfer Count bit 4    
PECC7.COUNT3      3   PEC Transfer Count bit 3    
PECC7.COUNT2      2   PEC Transfer Count bit 2    
PECC7.COUNT1      1   PEC Transfer Count bit 1    
PECC7.COUNT0      0   PEC Transfer Count bit 0    
P0L              0xFF00 Port 0 Low Register (Lower half of PORT0)
P0L.P0L7          7   Port data register P0L bit 7
P0L.P0L6          6   Port data register P0L bit 6
P0L.P0L5          5   Port data register P0L bit 5
P0L.P0L4          4   Port data register P0L bit 4
P0L.P0L3          3   Port data register P0L bit 3
P0L.P0L2          2   Port data register P0L bit 2
P0L.P0L1          1   Port data register P0L bit 1
P0L.P0L0          0   Port data register P0L bit 0
P0H              0xFF02 Port 0 High Register (Upper half of PORT0)
P0H.P0H7          7   Port data register P0H bit 7
P0H.P0H6          6   Port data register P0H bit 6
P0H.P0H5          5   Port data register P0H bit 5
P0H.P0H4          4   Port data register P0H bit 4
P0H.P0H3          3   Port data register P0H bit 3
P0H.P0H2          2   Port data register P0H bit 2
P0H.P0H1          1   Port data register P0H bit 1
P0H.P0H0          0   Port data register P0H bit 0
P1L              0xFF04 Port 1 Low Register (Lower half of PORT1)
P1L.P1L7          7   Port data register P1L bit 7
P1L.P1L6          6   Port data register P1L bit 6
P1L.P1L5          5   Port data register P1L bit 5
P1L.P1L4          4   Port data register P1L bit 4
P1L.P1L3          3   Port data register P1L bit 3
P1L.P1L2          2   Port data register P1L bit 2
P1L.P1L1          1   Port data register P1L bit 1
P1L.P1L0          0   Port data register P1L bit 0
P1H              0xFF06 Port 1 High Register (Upper half of PORT1)
P1H.P1H7          7   Port data register P1H bit 7
P1H.P1H6          6   Port data register P1H bit 6
P1H.P1H5          5   Port data register P1H bit 5
P1H.P1H4          4   Port data register P1H bit 4
P1H.P1H3          3   Port data register P1H bit 3
P1H.P1H2          2   Port data register P1H bit 2
P1H.P1H1          1   Port data register P1H bit 1
P1H.P1H0          0   Port data register P1H bit 0
BUSCON0          0xFF0C Bus Configuration Register 0
BUSCON0.CSWEN0    15  Write Chip Select Enable
BUSCON0.CSREN0    14  Read Chip Select Enable
BUSCON0.RDYEN0    12  READY Input Enable
BUSCON0.BUSACT0   10  Bus Active Control
BUSCON0.ALECTL0   9   ALE Lengthening Control
BUSCON0.BTYP7     7   External Bus Configuration bit 7
BUSCON0.BTYP6     6   External Bus Configuration bit 6
BUSCON0.MTTC0     5   Memory Tristate Time Control
BUSCON0.RWDC0     4   Read/Write Delay Control for BUSCON
BUSCON0.MCTC3     3   Memory Cycle Time Control bit 3
BUSCON0.MCTC2     2   Memory Cycle Time Control bit 2
BUSCON0.MCTC1     1   Memory Cycle Time Control bit 1
BUSCON0.MCTC0     0   Memory Cycle Time Control bit 0
MDC              0xFF0E CPU Multiply Divide Control Register
MDC.MDRIU         4   Multiply/Divide Register In Use
PSW              0xFF10 CPU Program Status Word
PSW.ILVL15        15  ILVL15 - Interrupt and EBC Control Fields
PSW.ILVL14        14  ILVL14 - Interrupt and EBC Control Fields
PSW.ILVL13        13  ILVL13 - Interrupt and EBC Control Fields
PSW.ILVL12        12  ILVL12 - Interrupt and EBC Control Fields
PSW.IEN           11  IEN    - Interrupt and EBC Control Fields
PSW.HLDEN         10  HLDEN  - Interrupt and EBC Control Fields
PSW.USR0          6   User General Purpose Flag
PSW.MULIP         5   Multiplication/Division In Progress
PSW.E             4   End of Table Flag
PSW.Z             3   Zero Flag
PSW.V             2   Overflow Result
PSW.C             1   Carry Flag
PSW.N             0   Negative Result
SYSCON               0xFF12 CPU System Configuration Register
SYSCON.STKSZ15        15  System Stack Size bit 15
SYSCON.STKSZ14        14  System Stack Size bit 14
SYSCON.STKSZ13        13  System Stack Size bit 13
SYSCON.ROMS1          12  Internal ROM Mapping
SYSCON.SGTDIS         11  Segmentation Disable/Enable Control
SYSCON.ROMEN          10  Internal ROM Enable
SYSCON.BYTDIS         9   Disable/Enable Control for Pin BHE
SYSCON.CLKEN          8   System Clock Output Enable
SYSCON.WRCFG          7   Write Configuration Control
SYSCON.CSCFG          6   Chip Select Configuration Control
SYSCON.OWDDIS         4   Oscillator Watchdog Disable Bit
SYSCON.BDRSTEN        3   Bidirectional Reset Enable Bit
SYSCON.XPEN           2   XBUS Peripheral Enable Bit
SYSCON.VISIBLE        1   Visible Mode Control
SYSCON.XPER_SHARE     0   XBUS Peripheral Share Mode Control
BUSCON1          0xFF14 Bus Configuration Register 1
BUSCON1.CSWEN1    15  Write Chip Select Enable           
BUSCON1.CSREN1    14  Read Chip Select Enable            
BUSCON1.RDYEN1    12  READY Input Enable                 
BUSCON1.BUSACT1   10  Bus Active Control                 
BUSCON1.ALECTL1   9   ALE Lengthening Control            
BUSCON1.BTYP7     7   External Bus Configuration bit 7   
BUSCON1.BTYP6     6   External Bus Configuration bit 6   
BUSCON1.MTTC1     5   Memory Tristate Time Control       
BUSCON1.RWDC1     4   Read/Write Delay Control for BUSCON
BUSCON1.MCTC3     3   Memory Cycle Time Control bit 3    
BUSCON1.MCTC2     2   Memory Cycle Time Control bit 2    
BUSCON1.MCTC1     1   Memory Cycle Time Control bit 1    
BUSCON1.MCTC0     0   Memory Cycle Time Control bit 0    
BUSCON2          0xFF16 Bus Configuration Register 2
BUSCON2.CSWEN2    15  Write Chip Select Enable           
BUSCON2.CSREN2    14  Read Chip Select Enable            
BUSCON2.RDYEN2    12  READY Input Enable                 
BUSCON2.BUSACT2   10  Bus Active Control                 
BUSCON2.ALECTL2   9   ALE Lengthening Control            
BUSCON2.BTYP7     7   External Bus Configuration bit 7   
BUSCON2.BTYP6     6   External Bus Configuration bit 6   
BUSCON2.MTTC2     5   Memory Tristate Time Control       
BUSCON2.RWDC2     4   Read/Write Delay Control for BUSCON
BUSCON2.MCTC3     3   Memory Cycle Time Control bit 3    
BUSCON2.MCTC2     2   Memory Cycle Time Control bit 2    
BUSCON2.MCTC1     1   Memory Cycle Time Control bit 1    
BUSCON2.MCTC0     0   Memory Cycle Time Control bit 0    
BUSCON3          0xFF18 Bus Configuration Register 3
BUSCON3.CSWEN3    15  Write Chip Select Enable           
BUSCON3.CSREN3    14  Read Chip Select Enable            
BUSCON3.RDYEN3    12  READY Input Enable                 
BUSCON3.BUSACT3   10  Bus Active Control                 
BUSCON3.ALECTL3   9   ALE Lengthening Control            
BUSCON3.BTYP7     7   External Bus Configuration bit 7   
BUSCON3.BTYP6     6   External Bus Configuration bit 6   
BUSCON3.MTTC3     5   Memory Tristate Time Control       
BUSCON3.RWDC3     4   Read/Write Delay Control for BUSCON
BUSCON3.MCTC3     3   Memory Cycle Time Control bit 3    
BUSCON3.MCTC2     2   Memory Cycle Time Control bit 2    
BUSCON3.MCTC1     1   Memory Cycle Time Control bit 1    
BUSCON3.MCTC0     0   Memory Cycle Time Control bit 0    
BUSCON4          0xFF1A Bus Configuration Register 4
BUSCON4.CSWEN4    15  Write Chip Select Enable           
BUSCON4.CSREN4    14  Read Chip Select Enable            
BUSCON4.RDYEN4    12  READY Input Enable                 
BUSCON4.BUSACT4   10  Bus Active Control                 
BUSCON4.ALECTL4   9   ALE Lengthening Control            
BUSCON4.BTYP7     7   External Bus Configuration bit 7   
BUSCON4.BTYP6     6   External Bus Configuration bit 6   
BUSCON4.MTTC4     5   Memory Tristate Time Control       
BUSCON4.RWDC4     4   Read/Write Delay Control for BUSCON
BUSCON4.MCTC3     3   Memory Cycle Time Control bit 3    
BUSCON4.MCTC2     2   Memory Cycle Time Control bit 2    
BUSCON4.MCTC1     1   Memory Cycle Time Control bit 1    
BUSCON4.MCTC0     0   Memory Cycle Time Control bit 0    
ZEROS            0xFF1C Constant Value 0's Register (read only)
ONES             0xFF1E Constant Value 1's Register (read only)
T78CON           0xFF20 CAPCOM Timer 7 and 8 Control Register
T78CON.T8R        14  Timer/Counter 8 Run Control
T78CON.T8M        11  Timer/Counter 8 Mode Selection
T78CON.T8I10      10  Timer/Counter 8 Input Selection bit 10
T78CON.T8I9       9   Timer/Counter 8 Input Selection bit 9 
T78CON.T8I8       8   Timer/Counter 8 Input Selection bit 8 
T78CON.T7R        6   Timer/Counter 7 Run Control
T78CON.T7M        3   Timer/Counter 7 Mode Selection
T78CON.T7I2       2   Timer/Counter 7 Input Selection bit 2
T78CON.T7I1       1   Timer/Counter 7 Input Selection bit 1
T78CON.T7I0       0   Timer/Counter 7 Input Selection bit 0
CCM4             0xFF22 CAPCOM Mode Control Register 4
CCM4.ACC19        15  Allocation Bit for Capture/Compare Register CC4
CCM4.CCMOD19_14   14  Mode Selection for Capture/Compare Register CC4 bit 14
CCM4.CCMOD19_13   13  Mode Selection for Capture/Compare Register CC4 bit 13
CCM4.CCMOD19_12   12  Mode Selection for Capture/Compare Register CC4 bit 12
CCM4.ACC18        11  Allocation Bit for Capture/Compare Register CC4       
CCM4.CCMOD18_10   10  Mode Selection for Capture/Compare Register CC4 bit 10
CCM4.CCMOD18_9    9   Mode Selection for Capture/Compare Register CC4 bit 9 
CCM4.CCMOD18_8    8   Mode Selection for Capture/Compare Register CC4 bit 8 
CCM4.ACC17        7   Allocation Bit for Capture/Compare Register CC4       
CCM4.CCMOD17_6    6   Mode Selection for Capture/Compare Register CC4 bit 6 
CCM4.CCMOD17_5    5   Mode Selection for Capture/Compare Register CC4 bit 5 
CCM4.CCMOD17_4    4   Mode Selection for Capture/Compare Register CC4 bit 4 
CCM4.ACC16        3   Allocation Bit for Capture/Compare Register CC4       
CCM4.CCMOD16_2    2   Mode Selection for Capture/Compare Register CC4 bit 2 
CCM4.CCMOD16_1    1   Mode Selection for Capture/Compare Register CC4 bit 1 
CCM4.CCMOD16_0    0   Mode Selection for Capture/Compare Register CC4 bit 0 
CCM5             0xFF24 CAPCOM Mode Control Register 5
CCM5.ACC23        15  Allocation Bit for Capture/Compare Register CC4       
CCM5.CCMOD23_14   14  Mode Selection for Capture/Compare Register CC4 bit 14
CCM5.CCMOD23_13   13  Mode Selection for Capture/Compare Register CC4 bit 13
CCM5.CCMOD23_12   12  Mode Selection for Capture/Compare Register CC4 bit 12
CCM5.ACC22        11  Allocation Bit for Capture/Compare Register CC4       
CCM5.CCMOD22_10   10  Mode Selection for Capture/Compare Register CC4 bit 10
CCM5.CCMOD22_9    9   Mode Selection for Capture/Compare Register CC4 bit 9 
CCM5.CCMOD22_8    8   Mode Selection for Capture/Compare Register CC4 bit 8 
CCM5.ACC21        7   Allocation Bit for Capture/Compare Register CC4       
CCM5.CCMOD21_6    6   Mode Selection for Capture/Compare Register CC4 bit 6 
CCM5.CCMOD21_5    5   Mode Selection for Capture/Compare Register CC4 bit 5 
CCM5.CCMOD21_4    4   Mode Selection for Capture/Compare Register CC4 bit 4 
CCM5.ACC20        3   Allocation Bit for Capture/Compare Register CC4       
CCM5.CCMOD20_2    2   Mode Selection for Capture/Compare Register CC4 bit 2 
CCM5.CCMOD20_1    1   Mode Selection for Capture/Compare Register CC4 bit 1 
CCM5.CCMOD20_0    0   Mode Selection for Capture/Compare Register CC4 bit 0 
CCM6             0xFF26 CAPCOM Mode Control Register 6
CCM6.ACC27        15  Allocation Bit for Capture/Compare Register CC4       
CCM6.CCMOD27_14   14  Mode Selection for Capture/Compare Register CC4 bit 14
CCM6.CCMOD27_13   13  Mode Selection for Capture/Compare Register CC4 bit 13
CCM6.CCMOD27_12   12  Mode Selection for Capture/Compare Register CC4 bit 12
CCM6.ACC26        11  Allocation Bit for Capture/Compare Register CC4       
CCM6.CCMOD26_10   10  Mode Selection for Capture/Compare Register CC4 bit 10
CCM6.CCMOD26_9    9   Mode Selection for Capture/Compare Register CC4 bit 9 
CCM6.CCMOD26_8    8   Mode Selection for Capture/Compare Register CC4 bit 8 
CCM6.ACC25        7   Allocation Bit for Capture/Compare Register CC4       
CCM6.CCMOD25_6    6   Mode Selection for Capture/Compare Register CC4 bit 6 
CCM6.CCMOD25_5    5   Mode Selection for Capture/Compare Register CC4 bit 5 
CCM6.CCMOD25_4    4   Mode Selection for Capture/Compare Register CC4 bit 4 
CCM6.ACC24        3   Allocation Bit for Capture/Compare Register CC4       
CCM6.CCMOD24_2    2   Mode Selection for Capture/Compare Register CC4 bit 2 
CCM6.CCMOD24_1    1   Mode Selection for Capture/Compare Register CC4 bit 1 
CCM6.CCMOD24_0    0   Mode Selection for Capture/Compare Register CC4 bit 0 
CCM7             0xFF28 CAPCOM Mode Control Register 7
CCM7.ACC31        15  Allocation Bit for Capture/Compare Register CC4       
CCM7.CCMOD31_14   14  Mode Selection for Capture/Compare Register CC4 bit 14
CCM7.CCMOD31_13   13  Mode Selection for Capture/Compare Register CC4 bit 13
CCM7.CCMOD31_12   12  Mode Selection for Capture/Compare Register CC4 bit 12
CCM7.ACC30        11  Allocation Bit for Capture/Compare Register CC4       
CCM7.CCMOD30_10   10  Mode Selection for Capture/Compare Register CC4 bit 10
CCM7.CCMOD30_9    9   Mode Selection for Capture/Compare Register CC4 bit 9 
CCM7.CCMOD30_8    8   Mode Selection for Capture/Compare Register CC4 bit 8 
CCM7.ACC29        7   Allocation Bit for Capture/Compare Register CC4       
CCM7.CCMOD29_6    6   Mode Selection for Capture/Compare Register CC4 bit 6 
CCM7.CCMOD29_5    5   Mode Selection for Capture/Compare Register CC4 bit 5 
CCM7.CCMOD29_4    4   Mode Selection for Capture/Compare Register CC4 bit 4 
CCM7.ACC28        3   Allocation Bit for Capture/Compare Register CC4       
CCM7.CCMOD28_2    2   Mode Selection for Capture/Compare Register CC4 bit 2 
CCM7.CCMOD28_1    1   Mode Selection for Capture/Compare Register CC4 bit 1 
CCM7.CCMOD28_0    0   Mode Selection for Capture/Compare Register CC4 bit 0 
PWMCON0          0xFF30 PWM Control Register 0
PWMCON0.PIR3      15  PWM Channel 3 Interrupt Request Flag
PWMCON0.PIR2      14  PWM Channel 2 Interrupt Request Flag
PWMCON0.PIR1      13  PWM Channel 1 Interrupt Request Flag
PWMCON0.PIR0      12  PWM Channel 0 Interrupt Request Flag
PWMCON0.PIE3      11  PWM Channel 3 Interrupt Enable Flag
PWMCON0.PIE2      10  PWM Channel 2 Interrupt Enable Flag
PWMCON0.PIE1      9   PWM Channel 1 Interrupt Enable Flag
PWMCON0.PIE0      8   PWM Channel 0 Interrupt Enable Flag
PWMCON0.PTI3      7   PWM Timer 3 Input Clock Selection
PWMCON0.PTI2      6   PWM Timer 2 Input Clock Selection
PWMCON0.PTI1      5   PWM Timer 1 Input Clock Selection
PWMCON0.PTI0      4   PWM Timer 0 Input Clock Selection
PWMCON0.PTR3      3   PWM Timer 3 Run Control Bit
PWMCON0.PTR2      2   PWM Timer 2 Run Control Bit
PWMCON0.PTR1      1   PWM Timer 1 Run Control Bit
PWMCON0.PTR0      0   PWM Timer 0 Run Control Bit
PWMCON1          0xFF32 PWM Control Register 1
PWMCON1.PS3       15  PWM Channel 3 Single Shot Mode Control Bit
PWMCON1.PS2       14  PWM Channel 2 Single Shot Mode Control Bit
PWMCON1.PB01      12  PWM Channel 0/1 Burst Mode Control Bit
PWMCON1.PM3       7   PWM Channel 3 Mode Control Bit
PWMCON1.PM2       6   PWM Channel 2 Mode Control Bit
PWMCON1.PM1       5   PWM Channel 1 Mode Control Bit
PWMCON1.PM0       4   PWM Channel 0 Mode Control Bit
PWMCON1.PEN3      3   PWM Channel 3 Output Enable Bit
PWMCON1.PEN2      2   PWM Channel 2 Output Enable Bit
PWMCON1.PEN1      1   PWM Channel 1 Output Enable Bit
PWMCON1.PEN0      0   PWM Channel 0 Output Enable Bit
T2CON            0xFF40 GPT1 Timer 2 Control Register
T2CON.T2UDE       8   Timer 2 External Up/Down Enable
T2CON.T2UD        7   Timer 2 Up/Down Control
T2CON.T2R         6   Timer 2 Run Bit
T2CON.T2M5        5   Timer 2 Mode Control bit 5
T2CON.T2M4        4   Timer 2 Mode Control bit 4
T2CON.T2M3        3   Timer 2 Mode Control bit 3
T2CON.T2I2        2   Timer 2 Input Selection bit 2
T2CON.T2I1        1   Timer 2 Input Selection bit 1
T2CON.T2I0        0   Timer 2 Input Selection bit 0
T3CON            0xFF42 GPT1 Timer 3 Control Register
T3CON.T3OTL       10  Timer 3 Output Toggle Latch
T3CON.T3OE        9   Alternate Output Function Enable
T3CON.T3UDE       8   Timer 3 External Up/Down Enable
T3CON.T3UD        7   Timer 3 Up/Down Control
T3CON.T3R         6   Timer 3 Run Bit
T3CON.T3M5        5   Timer 3 Mode Control bit 5
T3CON.T3M4        4   Timer 3 Mode Control bit 4
T3CON.T3M3        3   Timer 3 Mode Control bit 3
T3CON.T3I2        2   Timer 3 Input Selection bit 2
T3CON.T3I1        1   Timer 3 Input Selection bit 1
T3CON.T3I0        0   Timer 3 Input Selection bit 0
T4CON            0xFF44 GPT1 Timer 4 Control Register
T4CON.T4UDE       8   Timer 4 External Up/Down Enable
T4CON.T4UD        7   Timer 4 Up/Down Control
T4CON.T4R         6   Timer 4 Run Bit
T4CON.T4M5        5   Timer 4 Mode Control bit 5
T4CON.T4M4        4   Timer 4 Mode Control bit 4
T4CON.T4M3        3   Timer 4 Mode Control bit 3
T4CON.T4I2        2   Timer 4 Input Selection bit 2
T4CON.T4I1        1   Timer 4 Input Selection bit 1
T4CON.T4I0        0   Timer 4 Input Selection bit 0
T5CON            0xFF46 GPT2 Timer 5 Control Register
T5CON.T5SC        15  Timer 5 Capture Mode Enable
T5CON.T5CLR       14  Timer 5 Clear Bit
T5CON.CI13        13  Register CAPREL Capture Trigger Selection bit 13
T5CON.CI12        12  Register CAPREL Capture Trigger Selection bit 12
T5CON.CT3         10  Timer 3 Capture Trigger Enable
T5CON.T5UDE       8   Timer 5 External Up/Down Enable
T5CON.T5UD        7   Timer 5 Up / Down Control
T5CON.T5R         6   Timer 5 Run Bit
T5CON.T5M5        5   Timer 5 Mode Control bit 5
T5CON.T5M4        4   Timer 5 Mode Control bit 4
T5CON.T5M3        3   Timer 5 Mode Control bit 3
T5CON.T5I2        2   Timer 5 Input Selection bit 2
T5CON.T5I1        1   Timer 5 Input Selection bit 1
T5CON.T5I0        0   Timer 5 Input Selection bit 0
T6CON            0xFF48 GPT2 Timer 6 Control Register
T6CON.T6SR        15  Timer 6 Reload Mode Enable
T6CON.T6OTL       10  Timer 6 Output Toggle Latch
T6CON.T6OE        9   Alternate Output Function Enable
T6CON.T6UDE       8   Timer 6 External Up/Down Enable
T6CON.T6UD        7   Timer 6 Up/Down Control
T6CON.T6R         6   Timer 6 Run Bit
T6CON.T6M5        5   Timer 6 Mode Control bit 5
T6CON.T6M4        4   Timer 6 Mode Control bit 4
T6CON.T6M3        3   Timer 6 Mode Control bit 3
T6CON.T6I2        2   Timer 6 Input Selection bit 2
T6CON.T6I1        1   Timer 6 Input Selection bit 1
T6CON.T6I0        0   Timer 6 Input Selection bit 0
T01CON           0xFF50 CAPCOM Timer 0 and Timer 1 Ctrl. Reg.
T01CON.T1R        14  Timer/Counter 1 Run Control
T01CON.T1M        11  Timer/Counter 1 Mode Selection
T01CON.T1I10      10  Timer/Counter 1 Input Selection bit 10
T01CON.T1I9       9   Timer/Counter 1 Input Selection bit 9 
T01CON.T1I8       8   Timer/Counter 1 Input Selection bit 8 
T01CON.T0R        6   Timer/Counter 0 Run Control
T01CON.T0M        3   Timer/Counter 0 Mode Selection
T01CON.T0I2       2   Timer/Counter 0 Input Selection bit 2
T01CON.T0I1       1   Timer/Counter 0 Input Selection bit 1
T01CON.T0I0       0   Timer/Counter 0 Input Selection bit 0
CCM0             0xFF52 CAPCOM Mode Control Register 0
CCM0.ACC3         15  Allocation Bit for Capture/Compare Register CC0       
CCM0.CCMOD3_14    14  Mode Selection for Capture/Compare Register CC0 bit 14
CCM0.CCMOD3_13    13  Mode Selection for Capture/Compare Register CC0 bit 13
CCM0.CCMOD3_12    12  Mode Selection for Capture/Compare Register CC0 bit 12
CCM0.ACC2         11  Allocation Bit for Capture/Compare Register CC0       
CCM0.CCMOD2_10    10  Mode Selection for Capture/Compare Register CC0 bit 10
CCM0.CCMOD2_9     9   Mode Selection for Capture/Compare Register CC0 bit 9 
CCM0.CCMOD2_8     8   Mode Selection for Capture/Compare Register CC0 bit 8 
CCM0.ACC1         7   Allocation Bit for Capture/Compare Register CC0       
CCM0.CCMOD1_6     6   Mode Selection for Capture/Compare Register CC0 bit 6 
CCM0.CCMOD1_5     5   Mode Selection for Capture/Compare Register CC0 bit 5 
CCM0.CCMOD1_4     4   Mode Selection for Capture/Compare Register CC0 bit 4 
CCM0.ACC0         3   Allocation Bit for Capture/Compare Register CC0       
CCM0.CCMOD0_2     2   Mode Selection for Capture/Compare Register CC0 bit 2 
CCM0.CCMOD0_1     1   Mode Selection for Capture/Compare Register CC0 bit 1 
CCM0.CCMOD0_0     0   Mode Selection for Capture/Compare Register CC0 bit 0 
CCM1             0xFF54 CAPCOM Mode Control Register 1
CCM1.ACC7         15  Allocation Bit for Capture/Compare Register CC1       
CCM1.CCMOD7_14    14  Mode Selection for Capture/Compare Register CC1 bit 14
CCM1.CCMOD7_13    13  Mode Selection for Capture/Compare Register CC1 bit 13
CCM1.CCMOD7_12    12  Mode Selection for Capture/Compare Register CC1 bit 12
CCM1.ACC6         11  Allocation Bit for Capture/Compare Register CC1       
CCM1.CCMOD6_10    10  Mode Selection for Capture/Compare Register CC1 bit 10
CCM1.CCMOD6_9     9   Mode Selection for Capture/Compare Register CC1 bit 9 
CCM1.CCMOD6_8     8   Mode Selection for Capture/Compare Register CC1 bit 8 
CCM1.ACC5         7   Allocation Bit for Capture/Compare Register CC1       
CCM1.CCMOD5_6     6   Mode Selection for Capture/Compare Register CC1 bit 6 
CCM1.CCMOD5_5     5   Mode Selection for Capture/Compare Register CC1 bit 5 
CCM1.CCMOD5_4     4   Mode Selection for Capture/Compare Register CC1 bit 4 
CCM1.ACC4         3   Allocation Bit for Capture/Compare Register CC1       
CCM1.CCMOD4_2     2   Mode Selection for Capture/Compare Register CC1 bit 2 
CCM1.CCMOD4_1     1   Mode Selection for Capture/Compare Register CC1 bit 1 
CCM1.CCMOD4_0     0   Mode Selection for Capture/Compare Register CC1 bit 0 
CCM2             0xFF56 CAPCOM Mode Control Register 2
CCM2.ACC11        15  Allocation Bit for Capture/Compare Register CC2
CCM2.CCMOD11_14   14  Mode Selection for Capture/Compare Register CC2 bit 14
CCM2.CCMOD11_13   13  Mode Selection for Capture/Compare Register CC2 bit 13
CCM2.CCMOD11_12   12  Mode Selection for Capture/Compare Register CC2 bit 12
CCM2.ACC10        11  Allocation Bit for Capture/Compare Register CC2     
CCM2.CCMOD10_10   10  Mode Selection for Capture/Compare Register CC2 bit 10
CCM2.CCMOD10_9    9   Mode Selection for Capture/Compare Register CC2 bit 9 
CCM2.CCMOD10_8    8   Mode Selection for Capture/Compare Register CC2 bit 8 
CCM2.ACC9         7   Allocation Bit for Capture/Compare Register CC2     
CCM2.CCMOD9_6     6   Mode Selection for Capture/Compare Register CC2 bit 6
CCM2.CCMOD9_5     5   Mode Selection for Capture/Compare Register CC2 bit 5
CCM2.CCMOD9_4     4   Mode Selection for Capture/Compare Register CC2 bit 4
CCM2.ACC8         3   Allocation Bit for Capture/Compare Register CC2      
CCM2.CCMOD8_2     2   Mode Selection for Capture/Compare Register CC2 bit 2
CCM2.CCMOD8_1     1   Mode Selection for Capture/Compare Register CC2 bit 1
CCM2.CCMOD8_0     0   Mode Selection for Capture/Compare Register CC2 bit 0
CCM3             0xFF58 CAPCOM Mode Control Register 3
CCM3.ACC15        15  Allocation Bit for Capture/Compare Register CC3       
CCM3.CCMOD15_14   14  Mode Selection for Capture/Compare Register CC3 bit 14
CCM3.CCMOD15_13   13  Mode Selection for Capture/Compare Register CC3 bit 13
CCM3.CCMOD15_12   12  Mode Selection for Capture/Compare Register CC3 bit 12
CCM3.ACC14        11  Allocation Bit for Capture/Compare Register CC3       
CCM3.CCMOD14_10   10  Mode Selection for Capture/Compare Register CC3 bit 10
CCM3.CCMOD14_9    9   Mode Selection for Capture/Compare Register CC3 bit 9 
CCM3.CCMOD14_8    8   Mode Selection for Capture/Compare Register CC3 bit 8 
CCM3.ACC13        7   Allocation Bit for Capture/Compare Register CC3       
CCM3.CCMOD13_6    6   Mode Selection for Capture/Compare Register CC3 bit 6 
CCM3.CCMOD13_5    5   Mode Selection for Capture/Compare Register CC3 bit 5 
CCM3.CCMOD13_4    4   Mode Selection for Capture/Compare Register CC3 bit 4 
CCM3.ACC12        3   Allocation Bit for Capture/Compare Register CC3       
CCM3.CCMOD12_2    2   Mode Selection for Capture/Compare Register CC3 bit 2 
CCM3.CCMOD12_1    1   Mode Selection for Capture/Compare Register CC3 bit 1 
CCM3.CCMOD12_0    0   Mode Selection for Capture/Compare Register CC3 bit 0 
T2IC             0xFF60 GPT1 Timer 2 Interrupt Control Register
T2IC.T2IR         7
T2IC.T2IE         6
T2IC.ILVL5        5
T2IC.ILVL4        4
T2IC.ILVL3        3
T2IC.ILVL2        2
T2IC.GLVL1        1
T2IC.GLVL0        0
T3IC             0xFF62 GPT1 Timer 3 Interrupt Control Register
T3IC.T3IR         7
T3IC.T3IE         6
T3IC.ILVL5        5
T3IC.ILVL4        4
T3IC.ILVL3        3
T3IC.ILVL2        2
T3IC.GLVL1        1
T3IC.GLVL0        0
T4IC             0xFF64 GPT1 Timer 4 Interrupt Control Register
T4IC.T4IR         7
T4IC.T4IE         6
T4IC.ILVL5        5
T4IC.ILVL4        4
T4IC.ILVL3        3
T4IC.ILVL2        2
T4IC.GLVL1        1
T4IC.GLVL0        0
T5IC             0xFF66 GPT2 Timer 5 Interrupt Control Register
T5IC.T5IR         7
T5IC.T5IE         6
T5IC.ILVL5        5
T5IC.ILVL4        4
T5IC.ILVL3        3
T5IC.ILVL2        2
T5IC.GLVL1        1
T5IC.GLVL0        0
T6IC             0xFF68 GPT2 Timer 6 Interrupt Control Register
T6IC.T6IR         7
T6IC.T6IE         6
T6IC.ILVL5        5
T6IC.ILVL4        4
T6IC.ILVL3        3
T6IC.ILVL2        2
T6IC.GLVL1        1
T6IC.GLVL0        0
CRIC             0xFF6A GPT2 CAPREL Interrupt Control Register
CRIC.CRIR         7
CRIC.CRIE         6
CRIC.ILVL5        5
CRIC.ILVL4        4
CRIC.ILVL3        3
CRIC.ILVL2        2
CRIC.GLVL1        1
CRIC.GLVL0        0
S0TIC            0xFF6C Serial Channel 0 Transmit Interrupt Control Register
S0TIC.S0TIR       7
S0TIC.S0TIE       6
S0TIC.ILVL5       5
S0TIC.ILVL4       4
S0TIC.ILVL3       3
S0TIC.ILVL2       2
S0TIC.GLVL1       1
S0TIC.GLVL0       0
S0RIC            0xFF6E Serial Channel 0 Receive Interrupt Control Register
S0RIC.S0RIR       7
S0RIC.S0RIE       6
S0RIC.ILVL5       5
S0RIC.ILVL4       4
S0RIC.ILVL3       3
S0RIC.ILVL2       2
S0RIC.GLVL1       1
S0RIC.GLVL0       0
S0EIC            0xFF70 Serial Channel 0 Error Interrupt Ctrl. Reg.
S0EIC.S0EIR       7
S0EIC.S0EIE       6
S0EIC.ILVL5       5
S0EIC.ILVL4       4
S0EIC.ILVL3       3
S0EIC.ILVL2       2
S0EIC.GLVL1       1
S0EIC.GLVL0       0
SSCTIC           0xFF72 SSC Transmit Interrupt Control Register
SSCTIC.SSCTIR     7
SSCTIC.SSCTIE     6
SSCTIC.ILVL5      5
SSCTIC.ILVL4      4
SSCTIC.ILVL3      3
SSCTIC.ILVL2      2
SSCTIC.GLVL1      1
SSCTIC.GLVL0      0
SSCRIC           0xFF74 SSC Receive Interrupt Control Register
SSCRIC.SSCRIR     7
SSCRIC.SSCRIE     6
SSCRIC.ILVL5      5
SSCRIC.ILVL4      4
SSCRIC.ILVL3      3
SSCRIC.ILVL2      2
SSCRIC.GLVL1      1
SSCRIC.GLVL0      0
SSCEIC           0xFF76 SSC Error Interrupt Control Register
SSCEIC.SSCEIR     7
SSCEIC.SSCEIE     6
SSCEIC.ILVL5      5
SSCEIC.ILVL4      4
SSCEIC.ILVL3      3
SSCEIC.ILVL2      2
SSCEIC.GLVL1      1
SSCEIC.GLVL0      0
CC0IC            0xFF78 CAPCOM Register 0 Interrupt Ctrl. Reg.
CC0IC.CC0IR       7
CC0IC.CC0IE       6
CC0IC.ILVL5       5
CC0IC.ILVL4       4
CC0IC.ILVL3       3
CC0IC.ILVL2       2
CC0IC.GLVL1       1
CC0IC.GLVL0       0
CC1IC            0xFF7A CAPCOM Register 1 Interrupt Ctrl. Reg.
CC1IC.CC1IR       7
CC1IC.CC1IE       6
CC1IC.ILVL5       5
CC1IC.ILVL4       4
CC1IC.ILVL3       3
CC1IC.ILVL2       2
CC1IC.GLVL1       1
CC1IC.GLVL0       0
CC2IC            0xFF7C CAPCOM Register 2 Interrupt Ctrl. Reg.
CC2IC.CC2IR       7
CC2IC.CC2IE       6
CC2IC.ILVL5       5
CC2IC.ILVL4       4
CC2IC.ILVL3       3
CC2IC.ILVL2       2
CC2IC.GLVL1       1
CC2IC.GLVL0       0
CC3IC            0xFF7E CAPCOM Register 3 Interrupt Ctrl. Reg.
CC3IC.CC3IR       7
CC3IC.CC3IE       6
CC3IC.ILVL5       5
CC3IC.ILVL4       4
CC3IC.ILVL3       3
CC3IC.ILVL2       2
CC3IC.GLVL1       1
CC3IC.GLVL0       0
CC4IC            0xFF80 CAPCOM Register 4 Interrupt Ctrl. Reg.
CC4IC.CC4IR       7
CC4IC.CC4IE       6
CC4IC.ILVL5       5
CC4IC.ILVL4       4
CC4IC.ILVL3       3
CC4IC.ILVL2       2
CC4IC.GLVL1       1
CC4IC.GLVL0       0
CC5IC            0xFF82 CAPCOM Register 5 Interrupt Ctrl. Reg.
CC5IC.CC5IR       7
CC5IC.CC5IE       6
CC5IC.ILVL5       5
CC5IC.ILVL4       4
CC5IC.ILVL3       3
CC5IC.ILVL2       2
CC5IC.GLVL1       1
CC5IC.GLVL0       0
CC6IC            0xFF84 CAPCOM Register 6Interrupt Ctrl. Reg.
CC6IC.CC6IR       7
CC6IC.CC6IE       6
CC6IC.ILVL5       5
CC6IC.ILVL4       4
CC6IC.ILVL3       3
CC6IC.ILVL2       2
CC6IC.GLVL1       1
CC6IC.GLVL0       0
CC7IC            0xFF86 CAPCOM Register 7 Interrupt Ctrl. Reg.
CC7IC.CC7IR       7
CC7IC.CC7IE       6
CC7IC.ILVL5       5
CC7IC.ILVL4       4
CC7IC.ILVL3       3
CC7IC.ILVL2       2
CC7IC.GLVL1       1
CC7IC.GLVL0       0
CC8IC            0xFF88 CAPCOM Register 8 Interrupt Ctrl. Reg.
CC8IC.CC8IR       7
CC8IC.CC8IE       6
CC8IC.ILVL5       5
CC8IC.ILVL4       4
CC8IC.ILVL3       3
CC8IC.ILVL2       2
CC8IC.GLVL1       1
CC8IC.GLVL0       0
CC9IC            0xFF8A CAPCOM Register 9 Interrupt Ctrl. Reg.
CC9IC.CC9IR       7
CC9IC.CC9IE       6
CC9IC.ILVL5       5
CC9IC.ILVL4       4
CC9IC.ILVL3       3
CC9IC.ILVL2       2
CC9IC.GLVL1       1
CC9IC.GLVL0       0
CC10IC           0xFF8C CAPCOM Register 10 Interrupt Ctrl. Reg.
CC10IC.CC10IR     7
CC10IC.CC10IE     6
CC10IC.ILVL5      5
CC10IC.ILVL4      4
CC10IC.ILVL3      3
CC10IC.ILVL2      2
CC10IC.GLVL1      1
CC10IC.GLVL0      0
CC11IC           0xFF8E CAPCOM Register 11 Interrupt Ctrl. Reg.
CC11IC.CC11IR     7
CC11IC.CC11IE     6
CC11IC.ILVL5      5
CC11IC.ILVL4      4
CC11IC.ILVL3      3
CC11IC.ILVL2      2
CC11IC.GLVL1      1
CC11IC.GLVL0      0
CC12IC           0xFF90 CAPCOM Register 12 Interrupt Ctrl. Reg.
CC12IC.CC12IR     7
CC12IC.CC12IE     6
CC12IC.ILVL5      5
CC12IC.ILVL4      4
CC12IC.ILVL3      3
CC12IC.ILVL2      2
CC12IC.GLVL1      1
CC12IC.GLVL0      0
CC13IC           0xFF92 CAPCOM Register 13 Interrupt Ctrl. Reg.
CC13IC.CC13IR     7
CC13IC.CC13IE     6
CC13IC.ILVL5      5
CC13IC.ILVL4      4
CC13IC.ILVL3      3
CC13IC.ILVL2      2
CC13IC.GLVL1      1
CC13IC.GLVL0      0
CC14IC           0xFF94 CAPCOM Register 14 Interrupt Ctrl. Reg.
CC14IC.CC14IR     7
CC14IC.CC14IE     6
CC14IC.ILVL5      5
CC14IC.ILVL4      4
CC14IC.ILVL3      3
CC14IC.ILVL2      2
CC14IC.GLVL1      1
CC14IC.GLVL0      0
CC15IC           0xFF96 CAPCOM Register 15 Interrupt Ctrl. Reg.
CC15IC.CC15IR     7
CC15IC.CC15IE     6
CC15IC.ILVL5      5
CC15IC.ILVL4      4
CC15IC.ILVL3      3
CC15IC.ILVL2      2
CC15IC.GLVL1      1
CC15IC.GLVL0      0
ADCIC            0xFF98 A/D Converter End of Conversion Interrupt Control Register
ADCIC.ADCIR       7
ADCIC.ADCIE       6
ADCIC.ILVL5       5
ADCIC.ILVL4       4
ADCIC.ILVL3       3
ADCIC.ILVL2       2
ADCIC.GLVL1       1
ADCIC.GLVL0       0
ADEIC            0xFF9A A/D Converter Overrun Error Interrupt Control Register
ADEIC.ADEIR       7
ADEIC.ADEIE       6
ADEIC.ILVL5       5
ADEIC.ILVL4       4
ADEIC.ILVL3       3
ADEIC.ILVL2       2
ADEIC.GLVL1       1
ADEIC.GLVL0       0
T0IC             0xFF9C CAPCOM Timer 0 Interrupt Ctrl. Reg.
T0IC.T0IR         7
T0IC.T0IE         6
T0IC.ILVL5        5
T0IC.ILVL4        4
T0IC.ILVL3        3
T0IC.ILVL2        2
T0IC.GLVL1        1
T0IC.GLVL0        0
T1IC             0xFF9E CAPCOM Timer 1 Interrupt Ctrl. Reg.
T1IC.T1IR         7
T1IC.T1IE         6
T1IC.ILVL5        5
T1IC.ILVL4        4
T1IC.ILVL3        3
T1IC.ILVL2        2
T1IC.GLVL1        1
T1IC.GLVL0        0
ADCON            0xFFA0 A/D Converter Control Register
ADCON.ADCTC15     15  ADC Conversion Time Control bit 15
ADCON.ADCTC14     14  ADC Conversion Time Control bit 14
ADCON.ADSTC13     13  ADC Sample Time Control bit 13
ADCON.ADSTC12     12  ADC Sample Time Control bit 12
ADCON.ADCRQ       11  ADC Channel Injection Request Flag
ADCON.ADCIN       10  ADC Channel Injection Enable
ADCON.ADWR        9   ADC Wait for Read Control
ADCON.ADBSY       8   ADC Busy Flag
ADCON.ADST        7   ADC Start Bit
ADCON.ADM5        5   ADC Mode Selection bit 5
ADCON.ADM4        4   ADC Mode Selection bit 4
ADCON.ADCH3       3   ADC Analog Channel Input Selection bit 3
ADCON.ADCH2       2   ADC Analog Channel Input Selection bit 2
ADCON.ADCH1       1   ADC Analog Channel Input Selection bit 1
ADCON.ADCH0       0   ADC Analog Channel Input Selection bit 0
P5               0xFFA2 Port 5 Register (read only)
P5.P5_15          15  Port data register P5 bit 15
P5.P5_14          14  Port data register P5 bit 14
P5.P5_13          13  Port data register P5 bit 13
P5.P5_12          12  Port data register P5 bit 12
P5.P5_11          11  Port data register P5 bit 11
P5.P5_10          10  Port data register P5 bit 10
P5.P5_9           9   Port data register P5 bit 9 
P5.P5_8           8   Port data register P5 bit 8 
P5.P5_7           7   Port data register P5 bit 7 
P5.P5_6           6   Port data register P5 bit 6 
P5.P5_5           5   Port data register P5 bit 5 
P5.P5_4           4   Port data register P5 bit 4 
P5.P5_3           3   Port data register P5 bit 3 
P5.P5_2           2   Port data register P5 bit 2 
P5.P5_1           1   Port data register P5 bit 1 
P5.P5_0           0   Port data register P5 bit 0 
P5DIDIS          0xFFA4 Port 5 Digital Inp.Disable Reg.
P5DIDIS.P5D15     15  Port 5 Bit 15 Digital Input Control
P5DIDIS.P5D14     14  Port 5 Bit 14 Digital Input Control
P5DIDIS.P5D13     13  Port 5 Bit 13 Digital Input Control
P5DIDIS.P5D12     12  Port 5 Bit 12 Digital Input Control
P5DIDIS.P5D11     11  Port 5 Bit 11 Digital Input Control
P5DIDIS.P5D10     10  Port 5 Bit 10 Digital Input Control
P5DIDIS.P5D9      9   Port 5 Bit 9 Digital Input Control
P5DIDIS.P5D8      8   Port 5 Bit 8 Digital Input Control
P5DIDIS.P5D7      7   Port 5 Bit 7 Digital Input Control
P5DIDIS.P5D6      6   Port 5 Bit 6 Digital Input Control
P5DIDIS.P5D5      5   Port 5 Bit 5 Digital Input Control
P5DIDIS.P5D4      4   Port 5 Bit 4 Digital Input Control
P5DIDIS.P5D3      3   Port 5 Bit 3 Digital Input Control
P5DIDIS.P5D2      2   Port 5 Bit 2 Digital Input Control
P5DIDIS.P5D1      1   Port 5 Bit 1 Digital Input Control
P5DIDIS.P5D0      0   Port 5 Bit 0 Digital Input Control
TFR              0xFFAC Trap Flag Register
TFR.NMI           15  Non Maskable Interrupt Flag
TFR.STKOF         14  Stack Overflow Flag
TFR.STKUF         13  Stack Underflow Flag
TFR.UNDOPC        7   Undefined Opcode Flag
TFR.PRTFLT        3   Protection Fault Flag
TFR.ILLOPA        2   Illegal Word Operand Access Flag
TFR.ILLINA        1   Illegal Instruction Access Flag
TFR.ILLBUS        0   Illegal External Bus Access Flag
WDTCON           0xFFAE Watchdog Timer Control Register
WDTCON.WDTREL15   15  Watchdog Timer Reload Value bit 15
WDTCON.WDTREL14   14  Watchdog Timer Reload Value bit 14
WDTCON.WDTREL13   13  Watchdog Timer Reload Value bit 13
WDTCON.WDTREL12   12  Watchdog Timer Reload Value bit 12
WDTCON.WDTREL11   11  Watchdog Timer Reload Value bit 11
WDTCON.WDTREL10   10  Watchdog Timer Reload Value bit 10
WDTCON.WDTREL9    9   Watchdog Timer Reload Value bit 9 
WDTCON.WDTREL8    8   Watchdog Timer Reload Value bit 8 
WDTCON.LHWR       4   Long Hardware Reset Indication Flag
WDTCON.SHWR       3   Short Hardware Reset Indication Flag
WDTCON.SWR        2   Software Reset Indication Flag
WDTCON.WDTR       1   Watchdog Timer Reset Indication Flag
WDTCON.WDTIN      0   Watchdog Timer Input Frequency Select
S0CON            0xFFB0 Serial Channel 0 Control Register
S0CON.S0R         15  Baudrate Generator Run Bit
S0CON.S0LB        14  LoopBack Mode Enable Bit
S0CON.S0BRS       13  Baudrate Selection Bit
S0CON.S0ODD       12  Parity Selection Bit
S0CON.S0OE        10  Overrun Error Flag
S0CON.S0FE        9   Framing Error Flag
S0CON.S0PE        8   Parity Error Flag
S0CON.S0OEN       7   Overrun Check Enable Bit
S0CON.S0FEN       6   Framing Check Enable Bit
S0CON.S0PEN       5   Parity Check Enable Bit
S0CON.S0REN       4   Receiver Enable Bit
S0CON.S0STP       3   Number of Stop Bits Selection
S0CON.S0M2        2   ASC0 Mode Control bit 2
S0CON.S0M1        1   ASC0 Mode Control bit 1
S0CON.S0M0        0   ASC0 Mode Control bit 0
SSCCON           0xFFB2 SSC Control Register
P2               0xFFC0 Port 2 Register
P2.P2_15          15  Port data register P2 bit 15
P2.P2_14          14  Port data register P2 bit 14
P2.P2_13          13  Port data register P2 bit 13
P2.P2_12          12  Port data register P2 bit 12
P2.P2_11          11  Port data register P2 bit 11
P2.P2_10          10  Port data register P2 bit 10
P2.P2_9           9   Port data register P2 bit 9 
P2.P2_8           8   Port data register P2 bit 8 
P2.P2_7           7   Port data register P2 bit 7 
P2.P2_6           6   Port data register P2 bit 6 
P2.P2_5           5   Port data register P2 bit 5 
P2.P2_4           4   Port data register P2 bit 4 
P2.P2_3           3   Port data register P2 bit 3 
P2.P2_2           2   Port data register P2 bit 2 
P2.P2_1           1   Port data register P2 bit 1 
P2.P2_0           0   Port data register P2 bit 0 
DP2              0xFFC2 Port 2 Direction Control Register
DP2.DP2_15        15  Port direction register DP2 bit 15
DP2.DP2_14        14  Port direction register DP2 bit 14
DP2.DP2_13        13  Port direction register DP2 bit 13
DP2.DP2_12        12  Port direction register DP2 bit 12
DP2.DP2_11        11  Port direction register DP2 bit 11
DP2.DP2_10        10  Port direction register DP2 bit 10
DP2.DP2_9         9   Port direction register DP2 bit 9 
DP2.DP2_8         8   Port direction register DP2 bit 8 
DP2.DP2_7         7   Port direction register DP2 bit 7 
DP2.DP2_6         6   Port direction register DP2 bit 6 
DP2.DP2_5         5   Port direction register DP2 bit 5 
DP2.DP2_4         4   Port direction register DP2 bit 4 
DP2.DP2_3         3   Port direction register DP2 bit 3 
DP2.DP2_2         2   Port direction register DP2 bit 2 
DP2.DP2_1         1   Port direction register DP2 bit 1 
DP2.DP2_0         0   Port direction register DP2 bit 0 
P3               0xFFC4 Port 3 Register
P3.P3_15          15  Port data register P3 bit 15
P3.P3_13          13  Port data register P3 bit 13
P3.P3_12          12  Port data register P3 bit 12
P3.P3_11          11  Port data register P3 bit 11
P3.P3_10          10  Port data register P3 bit 10
P3.P3_9           9   Port data register P3 bit 9 
P3.P3_8           8   Port data register P3 bit 8 
P3.P3_7           7   Port data register P3 bit 7 
P3.P3_6           6   Port data register P3 bit 6 
P3.P3_5           5   Port data register P3 bit 5 
P3.P3_4           4   Port data register P3 bit 4 
P3.P3_3           3   Port data register P3 bit 3 
P3.P3_2           2   Port data register P3 bit 2 
P3.P3_1           1   Port data register P3 bit 1 
P3.P3_0           0   Port data register P3 bit 0 
DP3              0xFFC6 Port 3 Direction Control Register
DP3.DP3_15        15  Port direction register DP3 bit 15
DP3.DP3_13        13  Port direction register DP3 bit 13
DP3.DP3_12        12  Port direction register DP3 bit 12
DP3.DP3_11        11  Port direction register DP3 bit 11
DP3.DP3_10        10  Port direction register DP3 bit 10
DP3.DP3_9         9   Port direction register DP3 bit 9 
DP3.DP3_8         8   Port direction register DP3 bit 8 
DP3.DP3_7         7   Port direction register DP3 bit 7 
DP3.DP3_6         6   Port direction register DP3 bit 6 
DP3.DP3_5         5   Port direction register DP3 bit 5 
DP3.DP3_4         4   Port direction register DP3 bit 4 
DP3.DP3_3         3   Port direction register DP3 bit 3 
DP3.DP3_2         2   Port direction register DP3 bit 2 
DP3.DP3_1         1   Port direction register DP3 bit 1 
DP3.DP3_0         0   Port direction register DP3 bit 0 
P4               0xFFC8 Port 4 Register (7 bits)
P4.P4_7           7   Port data register P4 bit 7
P4.P4_6           6   Port data register P4 bit 6
P4.P4_5           5   Port data register P4 bit 5
P4.P4_4           4   Port data register P4 bit 4
P4.P4_3           3   Port data register P4 bit 3
P4.P4_2           2   Port data register P4 bit 2
P4.P4_1           1   Port data register P4 bit 1
P4.P4_0           0   Port data register P4 bit 0
DP4              0xFFCA Port 4 Direction Control Register
DP4.DP4_7         7   Port direction register DP4 bit 7 
DP4.DP4_6         6   Port direction register DP4 bit 6 
DP4.DP4_5         5   Port direction register DP4 bit 5 
DP4.DP4_4         4   Port direction register DP4 bit 4 
DP4.DP4_3         3   Port direction register DP4 bit 3 
DP4.DP4_2         2   Port direction register DP4 bit 2 
DP4.DP4_1         1   Port direction register DP4 bit 1 
DP4.DP4_0         0   Port direction register DP4 bit 0 
P6               0xFFCC Port 6 Register (8 bits)
P6.P6_7           7   Port data register P6 bit 7
P6.P6_6           6   Port data register P6 bit 6
P6.P6_5           5   Port data register P6 bit 5
P6.P6_4           4   Port data register P6 bit 4
P6.P6_3           3   Port data register P6 bit 3
P6.P6_2           2   Port data register P6 bit 2
P6.P6_1           1   Port data register P6 bit 1
P6.P6_0           0   Port data register P6 bit 0
DP6              0xFFCE Port 6 Direction Control Register
DP6.DP6_7         7   Port direction register DP6 bit 7
DP6.DP6_6         6   Port direction register DP6 bit 6
DP6.DP6_5         5   Port direction register DP6 bit 5
DP6.DP6_4         4   Port direction register DP6 bit 4
DP6.DP6_3         3   Port direction register DP6 bit 3
DP6.DP6_2         2   Port direction register DP6 bit 2
DP6.DP6_1         1   Port direction register DP6 bit 1
DP6.DP6_0         0   Port direction register DP6 bit 0
P7               0xFFD0 Port 7 Register (8 bits)
P7.P7_7           7   Port data register P7 bit 7
P7.P7_6           6   Port data register P7 bit 6
P7.P7_5           5   Port data register P7 bit 5
P7.P7_4           4   Port data register P7 bit 4
P7.P7_3           3   Port data register P7 bit 3
P7.P7_2           2   Port data register P7 bit 2
P7.P7_1           1   Port data register P7 bit 1
P7.P7_0           0   Port data register P7 bit 0
DP7              0xFFD2 Port 7 Direction Control Register
DP7.DP7_7         7   Port direction register DP7 bit 7
DP7.DP7_6         6   Port direction register DP7 bit 6
DP7.DP7_5         5   Port direction register DP7 bit 5
DP7.DP7_4         4   Port direction register DP7 bit 4
DP7.DP7_3         3   Port direction register DP7 bit 3
DP7.DP7_2         2   Port direction register DP7 bit 2
DP7.DP7_1         1   Port direction register DP7 bit 1
DP7.DP7_0         0   Port direction register DP7 bit 0
P8               0xFFD4 Port 8 Register (8 bits)
P8.P8_7           7   Port data register P8 bit 7
P8.P8_6           6   Port data register P8 bit 6
P8.P8_5           5   Port data register P8 bit 5
P8.P8_4           4   Port data register P8 bit 4
P8.P8_3           3   Port data register P8 bit 3
P8.P8_2           2   Port data register P8 bit 2
P8.P8_1           1   Port data register P8 bit 1
P8.P8_0           0   Port data register P8 bit 0
DP8              0xFFD6 Port 8 Direction Control Register
DP8.DP8_7         7   Port direction register DP8 bit 7
DP8.DP8_6         6   Port direction register DP8 bit 6
DP8.DP8_5         5   Port direction register DP8 bit 5
DP8.DP8_4         4   Port direction register DP8 bit 4
DP8.DP8_3         3   Port direction register DP8 bit 3
DP8.DP8_2         2   Port direction register DP8 bit 2
DP8.DP8_1         1   Port direction register DP8 bit 1
DP8.DP8_0         0   Port direction register DP8 bit 0


.C167CS
; c167cs_um_v2.0_2000_07.pdf


; MEMORY MAP
area CODE ROM            0x0000:0x8000   Internal ROM area
area CODE MEM_EXT        0x8000:0xC000   Ext. Memory
area DATA XRAM_1         0xC000:0xD800
area BSS  RESERVED       0xD800:0xE000
area DATA XRAM_2         0xE000:0xE800
area BSS  RESERVED       0xE800:0xEE00
area DATA CAN2           0xEE00:0xEF00
area DATA CAN1           0xEF00:0xF000
area DATA E_SFR          0xF000:0xF200   ESFR Area
area CODE IRAM           0xF200:0xFE00
area DATA SFR            0xFE00:0x10000  SFR Area


; Interrupt and reset vector assignments
entry RESET     0x0000   RESET
entry NMITRAP   0x0008   NMITRAP Non-Maskable Interrupt (Class A Hardware Traps)
entry STOTRAP   0x0010   STOTRAP Stack Overflow (Class A Hardware Traps)
entry STUTRAP   0x0018   STUTRAP Stack Underflow (Class A Hardware Traps)
entry BTRAP     0x0028   BTRAP Class B Hardware Traps
entry CC0INT    0x0040   CAPCOM Register 0
entry CC1INT    0x0044   CAPCOM Register 1
entry CC2INT    0x0048   CAPCOM Register 2
entry CC3INT    0x004C   CAPCOM Register 3
entry CC4INT    0x0050   CAPCOM Register 4
entry CC5INT    0x0054   CAPCOM Register 5
entry CC6INT    0x0058   CAPCOM Register 6
entry CC7INT    0x005C   CAPCOM Register 7
entry CC8INT    0x0060   CAPCOM Register 8
entry CC9INT    0x0064   CAPCOM Register 9
entry CC10INT   0x0068   CAPCOM Register 10
entry CC11INT   0x006C   CAPCOM Register 11
entry CC12INT   0x0070   CAPCOM Register 12
entry CC13INT   0x0074   CAPCOM Register 13
entry CC14INT   0x0078   CAPCOM Register 14
entry CC15INT   0x007C   CAPCOM Register 15
entry T0INT     0x0080   CAPCOM Timer 0 
entry T1INT     0x0084   CAPCOM Timer 1 
entry T2INT     0x0088   GPT1 Timer 2 
entry T3INT     0x008C   GPT1 Timer 3 
entry T4INT     0x0090   GPT1 Timer 4 
entry T5INT     0x0094   GPT2 Timer 5 
entry T6INT     0x0098   GPT2 Timer 6 
entry CRINT     0x009C   GPT2 CAPREL Register 
entry ADCINT    0x00A0   A/D Conversion Complete 
entry ADEINT    0x00A4   A/D Overrun Error 
entry S0TINT    0x00A8   ASC0 Transmit 
entry S0RINT    0x00AC   ASC0 Receive 
entry S0EINT    0x00B0   ASC0 Error 
entry SCTINT    0x00B4   SSC Transmit 
entry SCRINT    0x00B8   SSC Receive 
entry SCEINT    0x00BC   SSC Error 
entry CC16INT   0x00C0   CAPCOM Register 16 
entry CC17INT   0x00C4   CAPCOM Register 17 
entry CC18INT   0x00C8   CAPCOM Register 18 
entry CC19INT   0x00CC   CAPCOM Register 19 
entry CC20INT   0x00D0   CAPCOM Register 20 
entry CC21INT   0x00D4   CAPCOM Register 21 
entry CC22INT   0x00D8   CAPCOM Register 22 
entry CC23INT   0x00DC   CAPCOM Register 23 
entry CC24INT   0x00E0   CAPCOM Register 24 
entry CC25INT   0x00E4   CAPCOM Register 25 
entry CC26INT   0x00E8   CAPCOM Register 26 
entry CC27INT   0x00EC   CAPCOM Register 27 
entry CC28INT   0x00F0   CAPCOM Register 28 
entry T7INT     0x00F4   CAPCOM Timer 7 
entry T8INT     0x00F8   CAPCOM Timer 8 
entry PWMINT    0x00FC   PWM Channel 0_3 
entry XP0INT    0x0100   CAN1 
entry XP1INT    0x0104   CAN2
entry XP2INT    0x0108   Unassigned node 
entry XP3INT    0x010C   PLL/OWD, RTC
entry CC29INT   0x0110   CAPCOM Register 29 
entry CC30INT   0x0114   CAPCOM Register 30 
entry CC31INT   0x0118   CAPCOM Register 31 
entry S0TBINT   0x011C   ASC0 Transmit Buffer 


; INPUT/OUTPUT PORTS
; CAN2
C2CSR            0xEE00   CAN2 Control/Status Register
C2CSR.BOFF        15  Busoff Status
C2CSR.EWRN        14  Error Warning Status
C2CSR.RXOK        12  Received Message Successfully
C2CSR.TXOK        11  Transmitted Message Successfully
C2CSR.LEC10       10  Last Error Code bit 10
C2CSR.LEC9        9   Last Error Code bit 9
C2CSR.LEC8        8   Last Error Code bit 8
C2CSR.TM          7   Test Mode
C2CSR.CCE         6   Configuration Change Enable
C2CSR.CPS         4   Clock Prescaler Control Bit
C2CSR.EIE         3   Error Interrupt Enable
C2CSR.SIE         2   Status Change Interrupt Enable
C2CSR.IE          1   Interrupt Enable
C2CSR.INIT        0   Initialization
C2PCIR           0xEE02   CAN2 Port Control and Interrupt Register
C2PCIR.IPC10      10  Interface Port Control bit 10
C2PCIR.IPC9       9   Interface Port Control bit 9 
C2PCIR.IPC8       8   Interface Port Control bit 8 
C2PCIR.INTID7     7   Interrupt Identifier bit 7
C2PCIR.INTID6     6   Interrupt Identifier bit 6
C2PCIR.INTID5     5   Interrupt Identifier bit 5
C2PCIR.INTID4     4   Interrupt Identifier bit 4
C2PCIR.INTID3     3   Interrupt Identifier bit 3
C2PCIR.INTID2     2   Interrupt Identifier bit 2
C2PCIR.INTID1     1   Interrupt Identifier bit 1
C2PCIR.INTID0     0   Interrupt Identifier bit 0
C2BTR            0xEE04   CAN2 Bit Timing Register
C2BTR.TSEG2_14    14  Time Segment after sample point bit 14
C2BTR.TSEG2_13    13  Time Segment after sample point bit 13
C2BTR.TSEG2_12    12  Time Segment after sample point bit 12
C2BTR.TSEG1_11    11  Time Segment before sample point bit 11
C2BTR.TSEG1_10    10  Time Segment before sample point bit 10
C2BTR.TSEG1_9     9   Time Segment before sample point bit 9
C2BTR.TSEG1_8     8   Time Segment before sample point bit 8
C2BTR.SJW7        7   (Re)Synchronization Jump Width bit 7
C2BTR.SJW6        6   (Re)Synchronization Jump Width bit 6
C2BTR.BRP5        5   Baud Rate Prescaler bit 5
C2BTR.BRP4        4   Baud Rate Prescaler bit 4
C2BTR.BRP3        3   Baud Rate Prescaler bit 3
C2BTR.BRP2        2   Baud Rate Prescaler bit 2
C2BTR.BRP1        1   Baud Rate Prescaler bit 1
C2BTR.BRP0        0   Baud Rate Prescaler bit 0
C2GMS            0xEE06   CAN2 Global Mask Short
C2GMS.ID20        15  Identifier 20
C2GMS.ID19        14  Identifier 19
C2GMS.ID18        13  Identifier 18
C2GMS.ID28        7   Identifier 28
C2GMS.ID27        6   Identifier 27
C2GMS.ID26        5   Identifier 26
C2GMS.ID25        4   Identifier 25
C2GMS.ID24        3   Identifier 24
C2GMS.ID23        2   Identifier 23
C2GMS.ID22        1   Identifier 22
C2GMS.ID21        0   Identifier 21
C2UGML           0xEE08   CAN2 Upper Global Mask Long
C2UGML.ID20       15  Identifier 20
C2UGML.ID19       14  Identifier 19
C2UGML.ID18       13  Identifier 18
C2UGML.ID17       12  Identifier 17
C2UGML.ID16       11  Identifier 16
C2UGML.ID15       10  Identifier 15
C2UGML.ID14       9   Identifier 14
C2UGML.ID13       8   Identifier 13
C2UGML.ID28       7   Identifier 28
C2UGML.ID27       6   Identifier 27
C2UGML.ID26       5   Identifier 26
C2UGML.ID25       4   Identifier 25
C2UGML.ID24       3   Identifier 24
C2UGML.ID23       2   Identifier 23
C2UGML.ID22       1   Identifier 22
C2UGML.ID21       0   Identifier 21
C2LGML           0xEE0A   CAN2 Lower Global Mask Long
C2LGML.ID4        15  Identifier 4
C2LGML.ID3        14  Identifier 3
C2LGML.ID2        13  Identifier 2
C2LGML.ID1        12  Identifier 1
C2LGML.ID0        11  Identifier 0
C2LGML.ID12       7   Identifier 12
C2LGML.ID11       6   Identifier 11
C2LGML.ID10       5   Identifier 10
C2LGML.ID9        4   Identifier 9
C2LGML.ID8        3   Identifier 8
C2LGML.ID7        2   Identifier 7
C2LGML.ID6        1   Identifier 6
C2LGML.ID5        0   Identifier 5
C2UMLM           0xEE0C   CAN2 Upper Mask of Last Message
C2UMLM.ID20       15  Identifier 20
C2UMLM.ID19       14  Identifier 19
C2UMLM.ID18       13  Identifier 18
C2UMLM.ID17       12  Identifier 17
C2UMLM.ID16       11  Identifier 16
C2UMLM.ID15       10  Identifier 15
C2UMLM.ID14       9   Identifier 14
C2UMLM.ID13       8   Identifier 13
C2UMLM.ID28       7   Identifier 28
C2UMLM.ID27       6   Identifier 27
C2UMLM.ID26       5   Identifier 26
C2UMLM.ID25       4   Identifier 25
C2UMLM.ID24       3   Identifier 24
C2UMLM.ID23       2   Identifier 23
C2UMLM.ID22       1   Identifier 22
C2UMLM.ID21       0   Identifier 21
C2LMLM           0xEE0E   CAN2 Lower Mask of Last Message
C2LMLM.ID4        15  Identifier 4
C2LMLM.ID3        14  Identifier 3
C2LMLM.ID2        13  Identifier 2
C2LMLM.ID1        12  Identifier 1
C2LMLM.ID0        11  Identifier 0
C2LMLM.ID12       7   Identifier 12
C2LMLM.ID11       6   Identifier 11
C2LMLM.ID10       5   Identifier 10
C2LMLM.ID9        4   Identifier 9
C2LMLM.ID8        3   Identifier 8
C2LMLM.ID7        2   Identifier 7
C2LMLM.ID6        1   Identifier 6
C2LMLM.ID5        0   Identifier 5
C2MCR1                  0xEE10  CAN2 Message Ctrl. Reg. (msg. 1)
C2MCR1.RMTPND15          15  Remote Pending bit 15
C2MCR1.RMTPND14          14  Remote Pending bit 14
C2MCR1.TXRQ13            13  Transmit Request bit 13
C2MCR1.TXRQ12            12  Transmit Request bit 12
C2MCR1.MSGLST_CPUUPD11   11  Message Lost_CPU Update bit 11
C2MCR1.MSGLST_CPUUPD10   10  Message Lost_CPU Update bit 10
C2MCR1.NEWDAT9           9   New Data bit 9
C2MCR1.NEWDAT8           8   New Data bit 8
C2MCR1.MSGVAL7           7   Message Valid bit 7
C2MCR1.MSGVAL6           6   Message Valid bit 6
C2MCR1.TXIE5             5   Transmit Interrupt Enable bit 5
C2MCR1.TXIE4             4   Transmit Interrupt Enable bit 4
C2MCR1.RXIE3             3   Receive Interrupt Enable bit 3
C2MCR1.RXIE2             2   Receive Interrupt Enable bit 2
C2MCR1.INTPND1           1   Interrupt Pending bit 1
C2MCR1.INTPND0           0   Interrupt Pending bit 0
C2UAR1                  0xEE12  CAN2 Upper Arbitration Reg. (msg. 1)
C2UAR1.ID20              15  Identifier bit 20
C2UAR1.ID19              14  Identifier bit 19
C2UAR1.ID18              13  Identifier bit 18
C2UAR1.ID17              12  Identifier bit 17
C2UAR1.ID16              11  Identifier bit 16
C2UAR1.ID15              10  Identifier bit 15
C2UAR1.ID14              9   Identifier bit 14
C2UAR1.ID13              8   Identifier bit 13
C2UAR1.ID28              7   Identifier bit 28
C2UAR1.ID27              6   Identifier bit 27
C2UAR1.ID26              5   Identifier bit 26
C2UAR1.ID25              4   Identifier bit 25
C2UAR1.ID24              3   Identifier bit 24
C2UAR1.ID23              2   Identifier bit 23
C2UAR1.ID22              1   Identifier bit 22
C2UAR1.ID21              0   Identifier bit 21
C2LAR1                  0xEE14  CAN2 Lower Arbitration Reg. (msg. 1)
C2LAR1.ID4               15  Identifier bit 4 
C2LAR1.ID3               14  Identifier bit 3 
C2LAR1.ID2               13  Identifier bit 2 
C2LAR1.ID1               12  Identifier bit 1 
C2LAR1.ID0               11  Identifier bit 0 
C2LAR1.ID12              7   Identifier bit 12
C2LAR1.ID11              6   Identifier bit 11
C2LAR1.ID10              5   Identifier bit 10
C2LAR1.ID9               4   Identifier bit 9 
C2LAR1.ID8               3   Identifier bit 8 
C2LAR1.ID7               2   Identifier bit 7 
C2LAR1.ID6               1   Identifier bit 6 
C2LAR1.ID5               0   Identifier bit 5 
C2MCFG1                 0xEE16  CAN2 Message Configuration Register (msg. 1)
C2MCFG1.DLC7             7   Data Length Code bit 7
C2MCFG1.DLC6             6   Data Length Code bit 6
C2MCFG1.DLC5             5   Data Length Code bit 5
C2MCFG1.DLC4             4   Data Length Code bit 4
C2MCFG1.DIR              3   Message Direction
C2MCFG1.XTD              2   Extended Identifier
C2MCR2                  0xEE20  CAN2 Message Ctrl. Reg. (msg. 2)
C2MCR2.RMTPND15          15  Remote Pending bit 15          
C2MCR2.RMTPND14          14  Remote Pending bit 14          
C2MCR2.TXRQ13            13  Transmit Request bit 13        
C2MCR2.TXRQ12            12  Transmit Request bit 12        
C2MCR2.MSGLST_CPUUPD11   11  Message Lost_CPU Update bit 11 
C2MCR2.MSGLST_CPUUPD10   10  Message Lost_CPU Update bit 10 
C2MCR2.NEWDAT9           9   New Data bit 9                 
C2MCR2.NEWDAT8           8   New Data bit 8                 
C2MCR2.MSGVAL7           7   Message Valid bit 7            
C2MCR2.MSGVAL6           6   Message Valid bit 6            
C2MCR2.TXIE5             5   Transmit Interrupt Enable bit 5
C2MCR2.TXIE4             4   Transmit Interrupt Enable bit 4
C2MCR2.RXIE3             3   Receive Interrupt Enable bit 3 
C2MCR2.RXIE2             2   Receive Interrupt Enable bit 2 
C2MCR2.INTPND1           1   Interrupt Pending bit 1        
C2MCR2.INTPND0           0   Interrupt Pending bit 0        
C2UAR2                  0xEE22  CAN2 Upper Arbitration Reg. (msg. 2)
C2UAR2.ID20              15  Identifier bit 20
C2UAR2.ID19              14  Identifier bit 19
C2UAR2.ID18              13  Identifier bit 18
C2UAR2.ID17              12  Identifier bit 17
C2UAR2.ID16              11  Identifier bit 16
C2UAR2.ID15              10  Identifier bit 15
C2UAR2.ID14              9   Identifier bit 14
C2UAR2.ID13              8   Identifier bit 13
C2UAR2.ID28              7   Identifier bit 28
C2UAR2.ID27              6   Identifier bit 27
C2UAR2.ID26              5   Identifier bit 26
C2UAR2.ID25              4   Identifier bit 25
C2UAR2.ID24              3   Identifier bit 24
C2UAR2.ID23              2   Identifier bit 23
C2UAR2.ID22              1   Identifier bit 22
C2UAR2.ID21              0   Identifier bit 21
C2LAR2                  0xEE24  CAN2 Lower Arbitration Reg. (msg. 2)
C2LAR2.ID4               15  Identifier bit 4 
C2LAR2.ID3               14  Identifier bit 3 
C2LAR2.ID2               13  Identifier bit 2 
C2LAR2.ID1               12  Identifier bit 1 
C2LAR2.ID0               11  Identifier bit 0 
C2LAR2.ID12              7   Identifier bit 12
C2LAR2.ID11              6   Identifier bit 11
C2LAR2.ID10              5   Identifier bit 10
C2LAR2.ID9               4   Identifier bit 9 
C2LAR2.ID8               3   Identifier bit 8 
C2LAR2.ID7               2   Identifier bit 7 
C2LAR2.ID6               1   Identifier bit 6 
C2LAR2.ID5               0   Identifier bit 5 
C2MCFG2         0xEE26  CAN2 Message Configuration Register (msg. 2)
C2MCFG2.DLC7     7   Data Length Code bit 7
C2MCFG2.DLC6     6   Data Length Code bit 6
C2MCFG2.DLC5     5   Data Length Code bit 5
C2MCFG2.DLC4     4   Data Length Code bit 4
C2MCFG2.DIR      3   Message Direction
C2MCFG2.XTD      2   Extended Identifier
C2MCR3                  0xEE30  CAN2 Message Ctrl. Reg. (msg. 3)
C2MCR3.RMTPND15          15  Remote Pending bit 15          
C2MCR3.RMTPND14          14  Remote Pending bit 14          
C2MCR3.TXRQ13            13  Transmit Request bit 13        
C2MCR3.TXRQ12            12  Transmit Request bit 12        
C2MCR3.MSGLST_CPUUPD11   11  Message Lost_CPU Update bit 11 
C2MCR3.MSGLST_CPUUPD10   10  Message Lost_CPU Update bit 10 
C2MCR3.NEWDAT9           9   New Data bit 9                 
C2MCR3.NEWDAT8           8   New Data bit 8                 
C2MCR3.MSGVAL7           7   Message Valid bit 7            
C2MCR3.MSGVAL6           6   Message Valid bit 6            
C2MCR3.TXIE5             5   Transmit Interrupt Enable bit 5
C2MCR3.TXIE4             4   Transmit Interrupt Enable bit 4
C2MCR3.RXIE3             3   Receive Interrupt Enable bit 3 
C2MCR3.RXIE2             2   Receive Interrupt Enable bit 2 
C2MCR3.INTPND1           1   Interrupt Pending bit 1        
C2MCR3.INTPND0           0   Interrupt Pending bit 0        
C2UAR3                  0xEE32  CAN2 Upper Arbitration Reg. (msg. 3)
C2UAR3.ID20              15  Identifier bit 20
C2UAR3.ID19              14  Identifier bit 19
C2UAR3.ID18              13  Identifier bit 18
C2UAR3.ID17              12  Identifier bit 17
C2UAR3.ID16              11  Identifier bit 16
C2UAR3.ID15              10  Identifier bit 15
C2UAR3.ID14              9   Identifier bit 14
C2UAR3.ID13              8   Identifier bit 13
C2UAR3.ID28              7   Identifier bit 28
C2UAR3.ID27              6   Identifier bit 27
C2UAR3.ID26              5   Identifier bit 26
C2UAR3.ID25              4   Identifier bit 25
C2UAR3.ID24              3   Identifier bit 24
C2UAR3.ID23              2   Identifier bit 23
C2UAR3.ID22              1   Identifier bit 22
C2UAR3.ID21              0   Identifier bit 21
C2LAR3                  0xEE34  CAN2 Lower Arbitration Reg. (msg. 3)
C2LAR3.ID4               15  Identifier bit 4 
C2LAR3.ID3               14  Identifier bit 3 
C2LAR3.ID2               13  Identifier bit 2 
C2LAR3.ID1               12  Identifier bit 1 
C2LAR3.ID0               11  Identifier bit 0 
C2LAR3.ID12              7   Identifier bit 12
C2LAR3.ID11              6   Identifier bit 11
C2LAR3.ID10              5   Identifier bit 10
C2LAR3.ID9               4   Identifier bit 9 
C2LAR3.ID8               3   Identifier bit 8 
C2LAR3.ID7               2   Identifier bit 7 
C2LAR3.ID6               1   Identifier bit 6 
C2LAR3.ID5               0   Identifier bit 5 
C2MCFG3         0xEE36  CAN2 Message Configuration Register (msg. 3)
C2MCFG3.DLC7     7   Data Length Code bit 7
C2MCFG3.DLC6     6   Data Length Code bit 6
C2MCFG3.DLC5     5   Data Length Code bit 5
C2MCFG3.DLC4     4   Data Length Code bit 4
C2MCFG3.DIR      3   Message Direction
C2MCFG3.XTD      2   Extended Identifier
C2MCR4                  0xEE40  CAN2 Message Ctrl. Reg. (msg. 4)
C2MCR4.RMTPND15          15  Remote Pending bit 15          
C2MCR4.RMTPND14          14  Remote Pending bit 14          
C2MCR4.TXRQ13            13  Transmit Request bit 13        
C2MCR4.TXRQ12            12  Transmit Request bit 12        
C2MCR4.MSGLST_CPUUPD11   11  Message Lost_CPU Update bit 11 
C2MCR4.MSGLST_CPUUPD10   10  Message Lost_CPU Update bit 10 
C2MCR4.NEWDAT9           9   New Data bit 9                 
C2MCR4.NEWDAT8           8   New Data bit 8                 
C2MCR4.MSGVAL7           7   Message Valid bit 7            
C2MCR4.MSGVAL6           6   Message Valid bit 6            
C2MCR4.TXIE5             5   Transmit Interrupt Enable bit 5
C2MCR4.TXIE4             4   Transmit Interrupt Enable bit 4
C2MCR4.RXIE3             3   Receive Interrupt Enable bit 3 
C2MCR4.RXIE2             2   Receive Interrupt Enable bit 2 
C2MCR4.INTPND1           1   Interrupt Pending bit 1        
C2MCR4.INTPND0           0   Interrupt Pending bit 0        
C2UAR4                  0xEE42  CAN2 Upper Arbitration Reg. (msg. 4)
C2UAR4.ID20              15  Identifier bit 20
C2UAR4.ID19              14  Identifier bit 19
C2UAR4.ID18              13  Identifier bit 18
C2UAR4.ID17              12  Identifier bit 17
C2UAR4.ID16              11  Identifier bit 16
C2UAR4.ID15              10  Identifier bit 15
C2UAR4.ID14              9   Identifier bit 14
C2UAR4.ID13              8   Identifier bit 13
C2UAR4.ID28              7   Identifier bit 28
C2UAR4.ID27              6   Identifier bit 27
C2UAR4.ID26              5   Identifier bit 26
C2UAR4.ID25              4   Identifier bit 25
C2UAR4.ID24              3   Identifier bit 24
C2UAR4.ID23              2   Identifier bit 23
C2UAR4.ID22              1   Identifier bit 22
C2UAR4.ID21              0   Identifier bit 21
C2LAR4                  0xEE44  CAN2 Lower Arbitration Reg. (msg. 4)
C2LAR4.ID4               15  Identifier bit 4 
C2LAR4.ID3               14  Identifier bit 3 
C2LAR4.ID2               13  Identifier bit 2 
C2LAR4.ID1               12  Identifier bit 1 
C2LAR4.ID0               11  Identifier bit 0 
C2LAR4.ID12              7   Identifier bit 12
C2LAR4.ID11              6   Identifier bit 11
C2LAR4.ID10              5   Identifier bit 10
C2LAR4.ID9               4   Identifier bit 9 
C2LAR4.ID8               3   Identifier bit 8 
C2LAR4.ID7               2   Identifier bit 7 
C2LAR4.ID6               1   Identifier bit 6 
C2LAR4.ID5               0   Identifier bit 5 
C2MCFG4         0xEE46  CAN2 Message Configuration Register (msg. 4)
C2MCFG4.DLC7     7   Data Length Code bit 7
C2MCFG4.DLC6     6   Data Length Code bit 6
C2MCFG4.DLC5     5   Data Length Code bit 5
C2MCFG4.DLC4     4   Data Length Code bit 4
C2MCFG4.DIR      3   Message Direction
C2MCFG4.XTD      2   Extended Identifier
C2MCR5                  0xEE50  CAN2 Message Ctrl. Reg. (msg. 5)
C2MCR5.RMTPND15          15  Remote Pending bit 15          
C2MCR5.RMTPND14          14  Remote Pending bit 14          
C2MCR5.TXRQ13            13  Transmit Request bit 13        
C2MCR5.TXRQ12            12  Transmit Request bit 12        
C2MCR5.MSGLST_CPUUPD11   11  Message Lost_CPU Update bit 11 
C2MCR5.MSGLST_CPUUPD10   10  Message Lost_CPU Update bit 10 
C2MCR5.NEWDAT9           9   New Data bit 9                 
C2MCR5.NEWDAT8           8   New Data bit 8                 
C2MCR5.MSGVAL7           7   Message Valid bit 7            
C2MCR5.MSGVAL6           6   Message Valid bit 6            
C2MCR5.TXIE5             5   Transmit Interrupt Enable bit 5
C2MCR5.TXIE4             4   Transmit Interrupt Enable bit 4
C2MCR5.RXIE3             3   Receive Interrupt Enable bit 3 
C2MCR5.RXIE2             2   Receive Interrupt Enable bit 2 
C2MCR5.INTPND1           1   Interrupt Pending bit 1        
C2MCR5.INTPND0           0   Interrupt Pending bit 0        
C2UAR5                  0xEE52  CAN2 Upper Arbitration Reg. (msg. 5)
C2UAR5.ID20              15  Identifier bit 20
C2UAR5.ID19              14  Identifier bit 19
C2UAR5.ID18              13  Identifier bit 18
C2UAR5.ID17              12  Identifier bit 17
C2UAR5.ID16              11  Identifier bit 16
C2UAR5.ID15              10  Identifier bit 15
C2UAR5.ID14              9   Identifier bit 14
C2UAR5.ID13              8   Identifier bit 13
C2UAR5.ID28              7   Identifier bit 28
C2UAR5.ID27              6   Identifier bit 27
C2UAR5.ID26              5   Identifier bit 26
C2UAR5.ID25              4   Identifier bit 25
C2UAR5.ID24              3   Identifier bit 24
C2UAR5.ID23              2   Identifier bit 23
C2UAR5.ID22              1   Identifier bit 22
C2UAR5.ID21              0   Identifier bit 21
C2LAR5                  0xEE54  CAN2 Lower Arbitration Reg. (msg. 5)
C2LAR5.ID4               15  Identifier bit 4 
C2LAR5.ID3               14  Identifier bit 3 
C2LAR5.ID2               13  Identifier bit 2 
C2LAR5.ID1               12  Identifier bit 1 
C2LAR5.ID0               11  Identifier bit 0 
C2LAR5.ID12              7   Identifier bit 12
C2LAR5.ID11              6   Identifier bit 11
C2LAR5.ID10              5   Identifier bit 10
C2LAR5.ID9               4   Identifier bit 9 
C2LAR5.ID8               3   Identifier bit 8 
C2LAR5.ID7               2   Identifier bit 7 
C2LAR5.ID6               1   Identifier bit 6 
C2LAR5.ID5               0   Identifier bit 5 
C2MCFG5         0xEE56  CAN2 Message Configuration Register (msg. 5)
C2MCFG5.DLC7     7   Data Length Code bit 7
C2MCFG5.DLC6     6   Data Length Code bit 6
C2MCFG5.DLC5     5   Data Length Code bit 5
C2MCFG5.DLC4     4   Data Length Code bit 4
C2MCFG5.DIR      3   Message Direction
C2MCFG5.XTD      2   Extended Identifier
C2MCR6                  0xEE60  CAN2 Message Ctrl. Reg. (msg. 6)
C2MCR6.RMTPND15          15  Remote Pending bit 15          
C2MCR6.RMTPND14          14  Remote Pending bit 14          
C2MCR6.TXRQ13            13  Transmit Request bit 13        
C2MCR6.TXRQ12            12  Transmit Request bit 12        
C2MCR6.MSGLST_CPUUPD11   11  Message Lost_CPU Update bit 11 
C2MCR6.MSGLST_CPUUPD10   10  Message Lost_CPU Update bit 10 
C2MCR6.NEWDAT9           9   New Data bit 9                 
C2MCR6.NEWDAT8           8   New Data bit 8                 
C2MCR6.MSGVAL7           7   Message Valid bit 7            
C2MCR6.MSGVAL6           6   Message Valid bit 6            
C2MCR6.TXIE5             5   Transmit Interrupt Enable bit 5
C2MCR6.TXIE4             4   Transmit Interrupt Enable bit 4
C2MCR6.RXIE3             3   Receive Interrupt Enable bit 3 
C2MCR6.RXIE2             2   Receive Interrupt Enable bit 2 
C2MCR6.INTPND1           1   Interrupt Pending bit 1        
C2MCR6.INTPND0           0   Interrupt Pending bit 0        
C2UAR6                  0xEE62  CAN2 Upper Arbitration Reg. (msg. 6)
C2UAR6.ID20              15  Identifier bit 20
C2UAR6.ID19              14  Identifier bit 19
C2UAR6.ID18              13  Identifier bit 18
C2UAR6.ID17              12  Identifier bit 17
C2UAR6.ID16              11  Identifier bit 16
C2UAR6.ID15              10  Identifier bit 15
C2UAR6.ID14              9   Identifier bit 14
C2UAR6.ID13              8   Identifier bit 13
C2UAR6.ID28              7   Identifier bit 28
C2UAR6.ID27              6   Identifier bit 27
C2UAR6.ID26              5   Identifier bit 26
C2UAR6.ID25              4   Identifier bit 25
C2UAR6.ID24              3   Identifier bit 24
C2UAR6.ID23              2   Identifier bit 23
C2UAR6.ID22              1   Identifier bit 22
C2UAR6.ID21              0   Identifier bit 21
C2LAR6                  0xEE64  CAN2 Lower Arbitration Reg. (msg. 6)
C2LAR6.ID4               15  Identifier bit 4 
C2LAR6.ID3               14  Identifier bit 3 
C2LAR6.ID2               13  Identifier bit 2 
C2LAR6.ID1               12  Identifier bit 1 
C2LAR6.ID0               11  Identifier bit 0 
C2LAR6.ID12              7   Identifier bit 12
C2LAR6.ID11              6   Identifier bit 11
C2LAR6.ID10              5   Identifier bit 10
C2LAR6.ID9               4   Identifier bit 9 
C2LAR6.ID8               3   Identifier bit 8 
C2LAR6.ID7               2   Identifier bit 7 
C2LAR6.ID6               1   Identifier bit 6 
C2LAR6.ID5               0   Identifier bit 5 
C2MCFG6         0xEE66  CAN2 Message Configuration Register (msg. 6)
C2MCFG6.DLC7     7   Data Length Code bit 7
C2MCFG6.DLC6     6   Data Length Code bit 6
C2MCFG6.DLC5     5   Data Length Code bit 5
C2MCFG6.DLC4     4   Data Length Code bit 4
C2MCFG6.DIR      3   Message Direction
C2MCFG6.XTD      2   Extended Identifier
C2MCR7                  0xEE70  CAN2 Message Ctrl. Reg. (msg. 7)
C2MCR7.RMTPND15          15  Remote Pending bit 15          
C2MCR7.RMTPND14          14  Remote Pending bit 14          
C2MCR7.TXRQ13            13  Transmit Request bit 13        
C2MCR7.TXRQ12            12  Transmit Request bit 12        
C2MCR7.MSGLST_CPUUPD11   11  Message Lost_CPU Update bit 11 
C2MCR7.MSGLST_CPUUPD10   10  Message Lost_CPU Update bit 10 
C2MCR7.NEWDAT9           9   New Data bit 9                 
C2MCR7.NEWDAT8           8   New Data bit 8                 
C2MCR7.MSGVAL7           7   Message Valid bit 7            
C2MCR7.MSGVAL6           6   Message Valid bit 6            
C2MCR7.TXIE5             5   Transmit Interrupt Enable bit 5
C2MCR7.TXIE4             4   Transmit Interrupt Enable bit 4
C2MCR7.RXIE3             3   Receive Interrupt Enable bit 3 
C2MCR7.RXIE2             2   Receive Interrupt Enable bit 2 
C2MCR7.INTPND1           1   Interrupt Pending bit 1        
C2MCR7.INTPND0           0   Interrupt Pending bit 0        
C2UAR7                  0xEE72  CAN2 Upper Arbitration Reg. (msg. 7)
C2UAR7.ID20              15  Identifier bit 20
C2UAR7.ID19              14  Identifier bit 19
C2UAR7.ID18              13  Identifier bit 18
C2UAR7.ID17              12  Identifier bit 17
C2UAR7.ID16              11  Identifier bit 16
C2UAR7.ID15              10  Identifier bit 15
C2UAR7.ID14              9   Identifier bit 14
C2UAR7.ID13              8   Identifier bit 13
C2UAR7.ID28              7   Identifier bit 28
C2UAR7.ID27              6   Identifier bit 27
C2UAR7.ID26              5   Identifier bit 26
C2UAR7.ID25              4   Identifier bit 25
C2UAR7.ID24              3   Identifier bit 24
C2UAR7.ID23              2   Identifier bit 23
C2UAR7.ID22              1   Identifier bit 22
C2UAR7.ID21              0   Identifier bit 21
C2LAR7                  0xEE74  CAN2 Lower Arbitration Reg. (msg. 7)
C2LAR7.ID4               15  Identifier bit 4 
C2LAR7.ID3               14  Identifier bit 3 
C2LAR7.ID2               13  Identifier bit 2 
C2LAR7.ID1               12  Identifier bit 1 
C2LAR7.ID0               11  Identifier bit 0 
C2LAR7.ID12              7   Identifier bit 12
C2LAR7.ID11              6   Identifier bit 11
C2LAR7.ID10              5   Identifier bit 10
C2LAR7.ID9               4   Identifier bit 9 
C2LAR7.ID8               3   Identifier bit 8 
C2LAR7.ID7               2   Identifier bit 7 
C2LAR7.ID6               1   Identifier bit 6 
C2LAR7.ID5               0   Identifier bit 5 
C2MCFG7         0xEE76  CAN2 Message Configuration Register (msg. 7)
C2MCFG7.DLC7     7   Data Length Code bit 7
C2MCFG7.DLC6     6   Data Length Code bit 6
C2MCFG7.DLC5     5   Data Length Code bit 5
C2MCFG7.DLC4     4   Data Length Code bit 4
C2MCFG7.DIR      3   Message Direction
C2MCFG7.XTD      2   Extended Identifier
C2MCR8                  0xEE80  CAN2 Message Ctrl. Reg. (msg. 8)
C2MCR8.RMTPND15          15  Remote Pending bit 15          
C2MCR8.RMTPND14          14  Remote Pending bit 14          
C2MCR8.TXRQ13            13  Transmit Request bit 13        
C2MCR8.TXRQ12            12  Transmit Request bit 12        
C2MCR8.MSGLST_CPUUPD11   11  Message Lost_CPU Update bit 11 
C2MCR8.MSGLST_CPUUPD10   10  Message Lost_CPU Update bit 10 
C2MCR8.NEWDAT9           9   New Data bit 9                 
C2MCR8.NEWDAT8           8   New Data bit 8                 
C2MCR8.MSGVAL7           7   Message Valid bit 7            
C2MCR8.MSGVAL6           6   Message Valid bit 6            
C2MCR8.TXIE5             5   Transmit Interrupt Enable bit 5
C2MCR8.TXIE4             4   Transmit Interrupt Enable bit 4
C2MCR8.RXIE3             3   Receive Interrupt Enable bit 3 
C2MCR8.RXIE2             2   Receive Interrupt Enable bit 2 
C2MCR8.INTPND1           1   Interrupt Pending bit 1        
C2MCR8.INTPND0           0   Interrupt Pending bit 0        
C2UAR8                  0xEE82  CAN2 Upper Arbitration Reg. (msg. 8)
C2UAR8.ID20              15  Identifier bit 20
C2UAR8.ID19              14  Identifier bit 19
C2UAR8.ID18              13  Identifier bit 18
C2UAR8.ID17              12  Identifier bit 17
C2UAR8.ID16              11  Identifier bit 16
C2UAR8.ID15              10  Identifier bit 15
C2UAR8.ID14              9   Identifier bit 14
C2UAR8.ID13              8   Identifier bit 13
C2UAR8.ID28              7   Identifier bit 28
C2UAR8.ID27              6   Identifier bit 27
C2UAR8.ID26              5   Identifier bit 26
C2UAR8.ID25              4   Identifier bit 25
C2UAR8.ID24              3   Identifier bit 24
C2UAR8.ID23              2   Identifier bit 23
C2UAR8.ID22              1   Identifier bit 22
C2UAR8.ID21              0   Identifier bit 21
C2LAR8                  0xEE84  CAN2 Lower Arbitration Reg. (msg. 8)
C2LAR8.ID4               15  Identifier bit 4 
C2LAR8.ID3               14  Identifier bit 3 
C2LAR8.ID2               13  Identifier bit 2 
C2LAR8.ID1               12  Identifier bit 1 
C2LAR8.ID0               11  Identifier bit 0 
C2LAR8.ID12              7   Identifier bit 12
C2LAR8.ID11              6   Identifier bit 11
C2LAR8.ID10              5   Identifier bit 10
C2LAR8.ID9               4   Identifier bit 9 
C2LAR8.ID8               3   Identifier bit 8 
C2LAR8.ID7               2   Identifier bit 7 
C2LAR8.ID6               1   Identifier bit 6 
C2LAR8.ID5               0   Identifier bit 5 
C2MCFG8         0xEE86  CAN2 Message Configuration Register (msg. 8)
C2MCFG8.DLC7     7   Data Length Code bit 7
C2MCFG8.DLC6     6   Data Length Code bit 6
C2MCFG8.DLC5     5   Data Length Code bit 5
C2MCFG8.DLC4     4   Data Length Code bit 4
C2MCFG8.DIR      3   Message Direction
C2MCFG8.XTD      2   Extended Identifier
C2MCR9                  0xEE90  CAN2 Message Ctrl. Reg. (msg. 9)
C2MCR9.RMTPND15          15  Remote Pending bit 15          
C2MCR9.RMTPND14          14  Remote Pending bit 14          
C2MCR9.TXRQ13            13  Transmit Request bit 13        
C2MCR9.TXRQ12            12  Transmit Request bit 12        
C2MCR9.MSGLST_CPUUPD11   11  Message Lost_CPU Update bit 11 
C2MCR9.MSGLST_CPUUPD10   10  Message Lost_CPU Update bit 10 
C2MCR9.NEWDAT9           9   New Data bit 9                 
C2MCR9.NEWDAT8           8   New Data bit 8                 
C2MCR9.MSGVAL7           7   Message Valid bit 7            
C2MCR9.MSGVAL6           6   Message Valid bit 6            
C2MCR9.TXIE5             5   Transmit Interrupt Enable bit 5
C2MCR9.TXIE4             4   Transmit Interrupt Enable bit 4
C2MCR9.RXIE3             3   Receive Interrupt Enable bit 3 
C2MCR9.RXIE2             2   Receive Interrupt Enable bit 2 
C2MCR9.INTPND1           1   Interrupt Pending bit 1        
C2MCR9.INTPND0           0   Interrupt Pending bit 0        
C2UAR9                  0xEE92  CAN2 Upper Arbitration Reg. (msg. 9)
C2UAR9.ID20              15  Identifier bit 20
C2UAR9.ID19              14  Identifier bit 19
C2UAR9.ID18              13  Identifier bit 18
C2UAR9.ID17              12  Identifier bit 17
C2UAR9.ID16              11  Identifier bit 16
C2UAR9.ID15              10  Identifier bit 15
C2UAR9.ID14              9   Identifier bit 14
C2UAR9.ID13              8   Identifier bit 13
C2UAR9.ID28              7   Identifier bit 28
C2UAR9.ID27              6   Identifier bit 27
C2UAR9.ID26              5   Identifier bit 26
C2UAR9.ID25              4   Identifier bit 25
C2UAR9.ID24              3   Identifier bit 24
C2UAR9.ID23              2   Identifier bit 23
C2UAR9.ID22              1   Identifier bit 22
C2UAR9.ID21              0   Identifier bit 21
C2LAR9                  0xEE94  CAN2 Lower Arbitration Reg. (msg. 9)
C2LAR9.ID4               15  Identifier bit 4 
C2LAR9.ID3               14  Identifier bit 3 
C2LAR9.ID2               13  Identifier bit 2 
C2LAR9.ID1               12  Identifier bit 1 
C2LAR9.ID0               11  Identifier bit 0 
C2LAR9.ID12              7   Identifier bit 12
C2LAR9.ID11              6   Identifier bit 11
C2LAR9.ID10              5   Identifier bit 10
C2LAR9.ID9               4   Identifier bit 9 
C2LAR9.ID8               3   Identifier bit 8 
C2LAR9.ID7               2   Identifier bit 7 
C2LAR9.ID6               1   Identifier bit 6 
C2LAR9.ID5               0   Identifier bit 5 
C2MCFG9         0xEE96  CAN2 Message Configuration Register (msg. 9)
C2MCFG9.DLC7     7   Data Length Code bit 7
C2MCFG9.DLC6     6   Data Length Code bit 6
C2MCFG9.DLC5     5   Data Length Code bit 5
C2MCFG9.DLC4     4   Data Length Code bit 4
C2MCFG9.DIR      3   Message Direction
C2MCFG9.XTD      2   Extended Identifier
C2MCRA                  0xEEA0  CAN2 Message Ctrl. Reg. (msg. A)
C2MCRA.RMTPND15          15  Remote Pending bit 15          
C2MCRA.RMTPND14          14  Remote Pending bit 14          
C2MCRA.TXRQ13            13  Transmit Request bit 13        
C2MCRA.TXRQ12            12  Transmit Request bit 12        
C2MCRA.MSGLST_CPUUPD11   11  Message Lost_CPU Update bit 11 
C2MCRA.MSGLST_CPUUPD10   10  Message Lost_CPU Update bit 10 
C2MCRA.NEWDAT9           9   New Data bit 9                 
C2MCRA.NEWDAT8           8   New Data bit 8                 
C2MCRA.MSGVAL7           7   Message Valid bit 7            
C2MCRA.MSGVAL6           6   Message Valid bit 6            
C2MCRA.TXIE5             5   Transmit Interrupt Enable bit 5
C2MCRA.TXIE4             4   Transmit Interrupt Enable bit 4
C2MCRA.RXIE3             3   Receive Interrupt Enable bit 3 
C2MCRA.RXIE2             2   Receive Interrupt Enable bit 2 
C2MCRA.INTPND1           1   Interrupt Pending bit 1        
C2MCRA.INTPND0           0   Interrupt Pending bit 0        
C2UARA          0xEEA2  CAN2 Upper Arbitration Reg. (msg. A)
C2UARA.ID20      15  Identifier bit 20
C2UARA.ID19      14  Identifier bit 19
C2UARA.ID18      13  Identifier bit 18
C2UARA.ID17      12  Identifier bit 17
C2UARA.ID16      11  Identifier bit 16
C2UARA.ID15      10  Identifier bit 15
C2UARA.ID14      9   Identifier bit 14
C2UARA.ID13      8   Identifier bit 13
C2UARA.ID28      7   Identifier bit 28
C2UARA.ID27      6   Identifier bit 27
C2UARA.ID26      5   Identifier bit 26
C2UARA.ID25      4   Identifier bit 25
C2UARA.ID24      3   Identifier bit 24
C2UARA.ID23      2   Identifier bit 23
C2UARA.ID22      1   Identifier bit 22
C2UARA.ID21      0   Identifier bit 21
C2LARA          0xEEA4  CAN2 Lower Arbitration Reg. (msg. A)
C2LARA.ID4       15  Identifier bit 4 
C2LARA.ID3       14  Identifier bit 3 
C2LARA.ID2       13  Identifier bit 2 
C2LARA.ID1       12  Identifier bit 1 
C2LARA.ID0       11  Identifier bit 0 
C2LARA.ID12      7   Identifier bit 12
C2LARA.ID11      6   Identifier bit 11
C2LARA.ID10      5   Identifier bit 10
C2LARA.ID9       4   Identifier bit 9 
C2LARA.ID8       3   Identifier bit 8 
C2LARA.ID7       2   Identifier bit 7 
C2LARA.ID6       1   Identifier bit 6 
C2LARA.ID5       0   Identifier bit 5 
C2MCFGA         0xEEA6  CAN2 Message Configuration Register (msg. A)
C2MCFGA.DLC7     7   Data Length Code bit 7
C2MCFGA.DLC6     6   Data Length Code bit 6
C2MCFGA.DLC5     5   Data Length Code bit 5
C2MCFGA.DLC4     4   Data Length Code bit 4
C2MCFGA.DIR      3   Message Direction
C2MCFGA.XTD      2   Extended Identifier
C2MCRB                  0xEEB0  CAN2 Message Ctrl. Reg. (msg. B)
C2MCRB.RMTPND15          15  Remote Pending bit 15          
C2MCRB.RMTPND14          14  Remote Pending bit 14          
C2MCRB.TXRQ13            13  Transmit Request bit 13        
C2MCRB.TXRQ12            12  Transmit Request bit 12        
C2MCRB.MSGLST_CPUUPD11   11  Message Lost_CPU Update bit 11 
C2MCRB.MSGLST_CPUUPD10   10  Message Lost_CPU Update bit 10 
C2MCRB.NEWDAT9           9   New Data bit 9                 
C2MCRB.NEWDAT8           8   New Data bit 8                 
C2MCRB.MSGVAL7           7   Message Valid bit 7            
C2MCRB.MSGVAL6           6   Message Valid bit 6            
C2MCRB.TXIE5             5   Transmit Interrupt Enable bit 5
C2MCRB.TXIE4             4   Transmit Interrupt Enable bit 4
C2MCRB.RXIE3             3   Receive Interrupt Enable bit 3 
C2MCRB.RXIE2             2   Receive Interrupt Enable bit 2 
C2MCRB.INTPND1           1   Interrupt Pending bit 1        
C2MCRB.INTPND0           0   Interrupt Pending bit 0        
C2UARB          0xEEB2  CAN2 Upper Arbitration Reg. (msg. B)
C2UARB.ID20      15  Identifier bit 20
C2UARB.ID19      14  Identifier bit 19
C2UARB.ID18      13  Identifier bit 18
C2UARB.ID17      12  Identifier bit 17
C2UARB.ID16      11  Identifier bit 16
C2UARB.ID15      10  Identifier bit 15
C2UARB.ID14      9   Identifier bit 14
C2UARB.ID13      8   Identifier bit 13
C2UARB.ID28      7   Identifier bit 28
C2UARB.ID27      6   Identifier bit 27
C2UARB.ID26      5   Identifier bit 26
C2UARB.ID25      4   Identifier bit 25
C2UARB.ID24      3   Identifier bit 24
C2UARB.ID23      2   Identifier bit 23
C2UARB.ID22      1   Identifier bit 22
C2UARB.ID21      0   Identifier bit 21
C2LARB          0xEEB4  CAN2 Lower Arbitration Reg. (msg. B)
C2LARB.ID4       15  Identifier bit 4 
C2LARB.ID3       14  Identifier bit 3 
C2LARB.ID2       13  Identifier bit 2 
C2LARB.ID1       12  Identifier bit 1 
C2LARB.ID0       11  Identifier bit 0 
C2LARB.ID12      7   Identifier bit 12
C2LARB.ID11      6   Identifier bit 11
C2LARB.ID10      5   Identifier bit 10
C2LARB.ID9       4   Identifier bit 9 
C2LARB.ID8       3   Identifier bit 8 
C2LARB.ID7       2   Identifier bit 7 
C2LARB.ID6       1   Identifier bit 6 
C2LARB.ID5       0   Identifier bit 5 
C2MCFGB         0xEEB6  CAN2 Message Configuration Register (msg. B)
C2MCFGB.DLC7     7   Data Length Code bit 7
C2MCFGB.DLC6     6   Data Length Code bit 6
C2MCFGB.DLC5     5   Data Length Code bit 5
C2MCFGB.DLC4     4   Data Length Code bit 4
C2MCFGB.DIR      3   Message Direction
C2MCFGB.XTD      2   Extended Identifier
C2MCRC                  0xEEC0  CAN2 Message Ctrl. Reg. (msg. C)
C2MCRC.RMTPND15          15  Remote Pending bit 15          
C2MCRC.RMTPND14          14  Remote Pending bit 14          
C2MCRC.TXRQ13            13  Transmit Request bit 13        
C2MCRC.TXRQ12            12  Transmit Request bit 12        
C2MCRC.MSGLST_CPUUPD11   11  Message Lost_CPU Update bit 11 
C2MCRC.MSGLST_CPUUPD10   10  Message Lost_CPU Update bit 10 
C2MCRC.NEWDAT9           9   New Data bit 9                 
C2MCRC.NEWDAT8           8   New Data bit 8                 
C2MCRC.MSGVAL7           7   Message Valid bit 7            
C2MCRC.MSGVAL6           6   Message Valid bit 6            
C2MCRC.TXIE5             5   Transmit Interrupt Enable bit 5
C2MCRC.TXIE4             4   Transmit Interrupt Enable bit 4
C2MCRC.RXIE3             3   Receive Interrupt Enable bit 3 
C2MCRC.RXIE2             2   Receive Interrupt Enable bit 2 
C2MCRC.INTPND1           1   Interrupt Pending bit 1        
C2MCRC.INTPND0           0   Interrupt Pending bit 0        
C2UARC                  0xEEC2  CAN2 Upper Arbitration Reg. (msg. C)
C2UARC.ID20              15  Identifier bit 20
C2UARC.ID19              14  Identifier bit 19
C2UARC.ID18              13  Identifier bit 18
C2UARC.ID17              12  Identifier bit 17
C2UARC.ID16              11  Identifier bit 16
C2UARC.ID15              10  Identifier bit 15
C2UARC.ID14              9   Identifier bit 14
C2UARC.ID13              8   Identifier bit 13
C2UARC.ID28              7   Identifier bit 28
C2UARC.ID27              6   Identifier bit 27
C2UARC.ID26              5   Identifier bit 26
C2UARC.ID25              4   Identifier bit 25
C2UARC.ID24              3   Identifier bit 24
C2UARC.ID23              2   Identifier bit 23
C2UARC.ID22              1   Identifier bit 22
C2UARC.ID21              0   Identifier bit 21
C2LARC                  0xEEC4  CAN2 Lower Arbitration Reg. (msg. C)
C2LARC.ID4               15  Identifier bit 4 
C2LARC.ID3               14  Identifier bit 3 
C2LARC.ID2               13  Identifier bit 2 
C2LARC.ID1               12  Identifier bit 1 
C2LARC.ID0               11  Identifier bit 0 
C2LARC.ID12              7   Identifier bit 12
C2LARC.ID11              6   Identifier bit 11
C2LARC.ID10              5   Identifier bit 10
C2LARC.ID9               4   Identifier bit 9 
C2LARC.ID8               3   Identifier bit 8 
C2LARC.ID7               2   Identifier bit 7 
C2LARC.ID6               1   Identifier bit 6 
C2LARC.ID5               0   Identifier bit 5 
C2MCFGC         0xEEC6  CAN2 Message Configuration Register (msg. C)
C2MCFGC.DLC7     7   Data Length Code bit 7
C2MCFGC.DLC6     6   Data Length Code bit 6
C2MCFGC.DLC5     5   Data Length Code bit 5
C2MCFGC.DLC4     4   Data Length Code bit 4
C2MCFGC.DIR      3   Message Direction
C2MCFGC.XTD      2   Extended Identifier
C2MCRD                  0xEED0  CAN2 Message Ctrl. Reg. (msg. D)
C2MCRD.RMTPND15          15  Remote Pending bit 15          
C2MCRD.RMTPND14          14  Remote Pending bit 14          
C2MCRD.TXRQ13            13  Transmit Request bit 13        
C2MCRD.TXRQ12            12  Transmit Request bit 12        
C2MCRD.MSGLST_CPUUPD11   11  Message Lost_CPU Update bit 11 
C2MCRD.MSGLST_CPUUPD10   10  Message Lost_CPU Update bit 10 
C2MCRD.NEWDAT9           9   New Data bit 9                 
C2MCRD.NEWDAT8           8   New Data bit 8                 
C2MCRD.MSGVAL7           7   Message Valid bit 7            
C2MCRD.MSGVAL6           6   Message Valid bit 6            
C2MCRD.TXIE5             5   Transmit Interrupt Enable bit 5
C2MCRD.TXIE4             4   Transmit Interrupt Enable bit 4
C2MCRD.RXIE3             3   Receive Interrupt Enable bit 3 
C2MCRD.RXIE2             2   Receive Interrupt Enable bit 2 
C2MCRD.INTPND1           1   Interrupt Pending bit 1        
C2MCRD.INTPND0           0   Interrupt Pending bit 0        
C2UARD                  0xEED2  CAN2 Upper Arbitration Reg. (msg. D)
C2UARD.ID20              15  Identifier bit 20
C2UARD.ID19              14  Identifier bit 19
C2UARD.ID18              13  Identifier bit 18
C2UARD.ID17              12  Identifier bit 17
C2UARD.ID16              11  Identifier bit 16
C2UARD.ID15              10  Identifier bit 15
C2UARD.ID14              9   Identifier bit 14
C2UARD.ID13              8   Identifier bit 13
C2UARD.ID28              7   Identifier bit 28
C2UARD.ID27              6   Identifier bit 27
C2UARD.ID26              5   Identifier bit 26
C2UARD.ID25              4   Identifier bit 25
C2UARD.ID24              3   Identifier bit 24
C2UARD.ID23              2   Identifier bit 23
C2UARD.ID22              1   Identifier bit 22
C2UARD.ID21              0   Identifier bit 21
C2LARD                  0xEED4  CAN2 Lower Arbitration Reg. (msg. D)
C2LARD.ID4               15  Identifier bit 4 
C2LARD.ID3               14  Identifier bit 3 
C2LARD.ID2               13  Identifier bit 2 
C2LARD.ID1               12  Identifier bit 1 
C2LARD.ID0               11  Identifier bit 0 
C2LARD.ID12              7   Identifier bit 12
C2LARD.ID11              6   Identifier bit 11
C2LARD.ID10              5   Identifier bit 10
C2LARD.ID9               4   Identifier bit 9 
C2LARD.ID8               3   Identifier bit 8 
C2LARD.ID7               2   Identifier bit 7 
C2LARD.ID6               1   Identifier bit 6 
C2LARD.ID5               0   Identifier bit 5 
C2MCFGD         0xEED6  CAN2 Message Configuration Register (msg. D)
C2MCFGD.DLC7     7   Data Length Code bit 7
C2MCFGD.DLC6     6   Data Length Code bit 6
C2MCFGD.DLC5     5   Data Length Code bit 5
C2MCFGD.DLC4     4   Data Length Code bit 4
C2MCFGD.DIR      3   Message Direction
C2MCFGD.XTD      2   Extended Identifier
C2MCRE                  0xEEE0  CAN2 Message Ctrl. Reg. (msg. E)
C2MCRE.RMTPND15          15  Remote Pending bit 15          
C2MCRE.RMTPND14          14  Remote Pending bit 14          
C2MCRE.TXRQ13            13  Transmit Request bit 13        
C2MCRE.TXRQ12            12  Transmit Request bit 12        
C2MCRE.MSGLST_CPUUPD11   11  Message Lost_CPU Update bit 11 
C2MCRE.MSGLST_CPUUPD10   10  Message Lost_CPU Update bit 10 
C2MCRE.NEWDAT9           9   New Data bit 9                 
C2MCRE.NEWDAT8           8   New Data bit 8                 
C2MCRE.MSGVAL7           7   Message Valid bit 7            
C2MCRE.MSGVAL6           6   Message Valid bit 6            
C2MCRE.TXIE5             5   Transmit Interrupt Enable bit 5
C2MCRE.TXIE4             4   Transmit Interrupt Enable bit 4
C2MCRE.RXIE3             3   Receive Interrupt Enable bit 3 
C2MCRE.RXIE2             2   Receive Interrupt Enable bit 2 
C2MCRE.INTPND1           1   Interrupt Pending bit 1        
C2MCRE.INTPND0           0   Interrupt Pending bit 0        
C2UARE                  0xEEE2  CAN2 Upper Arbitration Reg. (msg. E)
C2UARE.ID20              15  Identifier bit 20
C2UARE.ID19              14  Identifier bit 19
C2UARE.ID18              13  Identifier bit 18
C2UARE.ID17              12  Identifier bit 17
C2UARE.ID16              11  Identifier bit 16
C2UARE.ID15              10  Identifier bit 15
C2UARE.ID14              9   Identifier bit 14
C2UARE.ID13              8   Identifier bit 13
C2UARE.ID28              7   Identifier bit 28
C2UARE.ID27              6   Identifier bit 27
C2UARE.ID26              5   Identifier bit 26
C2UARE.ID25              4   Identifier bit 25
C2UARE.ID24              3   Identifier bit 24
C2UARE.ID23              2   Identifier bit 23
C2UARE.ID22              1   Identifier bit 22
C2UARE.ID21              0   Identifier bit 21
C2LARE                  0xEEE4  CAN2 Lower Arbitration Reg. (msg. E)
C2LARE.ID4               15  Identifier bit 4 
C2LARE.ID3               14  Identifier bit 3 
C2LARE.ID2               13  Identifier bit 2 
C2LARE.ID1               12  Identifier bit 1 
C2LARE.ID0               11  Identifier bit 0 
C2LARE.ID12              7   Identifier bit 12
C2LARE.ID11              6   Identifier bit 11
C2LARE.ID10              5   Identifier bit 10
C2LARE.ID9               4   Identifier bit 9 
C2LARE.ID8               3   Identifier bit 8 
C2LARE.ID7               2   Identifier bit 7 
C2LARE.ID6               1   Identifier bit 6 
C2LARE.ID5               0   Identifier bit 5 
C2MCFGE         0xEEE6  CAN2 Message Configuration Register (msg. E)
C2MCFGE.DLC7     7   Data Length Code bit 7
C2MCFGE.DLC6     6   Data Length Code bit 6
C2MCFGE.DLC5     5   Data Length Code bit 5
C2MCFGE.DLC4     4   Data Length Code bit 4
C2MCFGE.DIR      3   Message Direction
C2MCFGE.XTD      2   Extended Identifier
C2MCRF                  0xEEF0  CAN2 Message Ctrl. Reg. (msg. F)
C2MCRF.RMTPND15          15  Remote Pending bit 15          
C2MCRF.RMTPND14          14  Remote Pending bit 14          
C2MCRF.TXRQ13            13  Transmit Request bit 13        
C2MCRF.TXRQ12            12  Transmit Request bit 12        
C2MCRF.MSGLST_CPUUPD11   11  Message Lost_CPU Update bit 11 
C2MCRF.MSGLST_CPUUPD10   10  Message Lost_CPU Update bit 10 
C2MCRF.NEWDAT9           9   New Data bit 9                 
C2MCRF.NEWDAT8           8   New Data bit 8                 
C2MCRF.MSGVAL7           7   Message Valid bit 7            
C2MCRF.MSGVAL6           6   Message Valid bit 6            
C2MCRF.TXIE5             5   Transmit Interrupt Enable bit 5
C2MCRF.TXIE4             4   Transmit Interrupt Enable bit 4
C2MCRF.RXIE3             3   Receive Interrupt Enable bit 3 
C2MCRF.RXIE2             2   Receive Interrupt Enable bit 2 
C2MCRF.INTPND1           1   Interrupt Pending bit 1        
C2MCRF.INTPND0           0   Interrupt Pending bit 0        
C2UARF                  0xEEF2  CAN2 Upper Arbitration Reg. (msg. F)
C2UARF.ID20              15  Identifier bit 20
C2UARF.ID19              14  Identifier bit 19
C2UARF.ID18              13  Identifier bit 18
C2UARF.ID17              12  Identifier bit 17
C2UARF.ID16              11  Identifier bit 16
C2UARF.ID15              10  Identifier bit 15
C2UARF.ID14              9   Identifier bit 14
C2UARF.ID13              8   Identifier bit 13
C2UARF.ID28              7   Identifier bit 28
C2UARF.ID27              6   Identifier bit 27
C2UARF.ID26              5   Identifier bit 26
C2UARF.ID25              4   Identifier bit 25
C2UARF.ID24              3   Identifier bit 24
C2UARF.ID23              2   Identifier bit 23
C2UARF.ID22              1   Identifier bit 22
C2UARF.ID21              0   Identifier bit 21
C2LARF                  0xEEF4  CAN2 Lower Arbitration Reg. (msg. F)
C2LARF.ID4               15  Identifier bit 4 
C2LARF.ID3               14  Identifier bit 3 
C2LARF.ID2               13  Identifier bit 2 
C2LARF.ID1               12  Identifier bit 1 
C2LARF.ID0               11  Identifier bit 0 
C2LARF.ID12              7   Identifier bit 12
C2LARF.ID11              6   Identifier bit 11
C2LARF.ID10              5   Identifier bit 10
C2LARF.ID9               4   Identifier bit 9 
C2LARF.ID8               3   Identifier bit 8 
C2LARF.ID7               2   Identifier bit 7 
C2LARF.ID6               1   Identifier bit 6 
C2LARF.ID5               0   Identifier bit 5 
C2MCFGF         0xEEF6  CAN2 Message Configuration Register (msg. F)
C2MCFGF.DLC7     7   Data Length Code bit 7
C2MCFGF.DLC6     6   Data Length Code bit 6
C2MCFGF.DLC5     5   Data Length Code bit 5
C2MCFGF.DLC4     4   Data Length Code bit 4
C2MCFGF.DIR      3   Message Direction
C2MCFGF.XTD      2   Extended Identifier

; CAN1
C1CSR            0xEF00   CAN1 Control/Status Register
C1CSR.BOFF        15  Busoff Status
C1CSR.EWRN        14  Error Warning Status
C1CSR.RXOK        12  Received Message Successfully
C1CSR.TXOK        11  Transmitted Message Successfully
C1CSR.LEC10       10  Last Error Code bit 10
C1CSR.LEC9        9   Last Error Code bit 9
C1CSR.LEC8        8   Last Error Code bit 8
C1CSR.TM          7   Test Mode
C1CSR.CCE         6   Configuration Change Enable
C1CSR.CPS         4   Clock Prescaler Control Bit
C1CSR.EIE         3   Error Interrupt Enable
C1CSR.SIE         2   Status Change Interrupt Enable
C1CSR.IE          1   Interrupt Enable
C1CSR.INIT        0   Initialization
C1PCIR           0xEF02   CAN1 Port Control and Interrupt Register
C1PCIR.IPC10      10  Interface Port Control bit 10
C1PCIR.IPC9       9   Interface Port Control bit 9 
C1PCIR.IPC8       8   Interface Port Control bit 8 
C1PCIR.INTID7     7   Interrupt Identifier bit 7
C1PCIR.INTID6     6   Interrupt Identifier bit 6
C1PCIR.INTID5     5   Interrupt Identifier bit 5
C1PCIR.INTID4     4   Interrupt Identifier bit 4
C1PCIR.INTID3     3   Interrupt Identifier bit 3
C1PCIR.INTID2     2   Interrupt Identifier bit 2
C1PCIR.INTID1     1   Interrupt Identifier bit 1
C1PCIR.INTID0     0   Interrupt Identifier bit 0
C1BTR            0xEF04   CAN1 Bit Timing Register
C1BTR.TSEG2_14    14  Time Segment after sample point bit 14
C1BTR.TSEG2_13    13  Time Segment after sample point bit 13
C1BTR.TSEG2_12    12  Time Segment after sample point bit 12
C1BTR.TSEG1_11    11  Time Segment before sample point bit 11
C1BTR.TSEG1_10    10  Time Segment before sample point bit 10
C1BTR.TSEG1_9     9   Time Segment before sample point bit 9
C1BTR.TSEG1_8     8   Time Segment before sample point bit 8
C1BTR.SJW7        7   (Re)Synchronization Jump Width bit 7
C1BTR.SJW6        6   (Re)Synchronization Jump Width bit 6
C1BTR.BRP5        5   Baud Rate Prescaler bit 5
C1BTR.BRP4        4   Baud Rate Prescaler bit 4
C1BTR.BRP3        3   Baud Rate Prescaler bit 3
C1BTR.BRP2        2   Baud Rate Prescaler bit 2
C1BTR.BRP1        1   Baud Rate Prescaler bit 1
C1BTR.BRP0        0   Baud Rate Prescaler bit 0
C1GMS            0xEF06   CAN1 Global Mask Short
C1GMS.ID20        15  Identifier 20
C1GMS.ID19        14  Identifier 19
C1GMS.ID18        13  Identifier 18
C1GMS.ID28        7   Identifier 28
C1GMS.ID27        6   Identifier 27
C1GMS.ID26        5   Identifier 26
C1GMS.ID25        4   Identifier 25
C1GMS.ID24        3   Identifier 24
C1GMS.ID23        2   Identifier 23
C1GMS.ID22        1   Identifier 22
C1GMS.ID21        0   Identifier 21
C1UGML           0xEF08   CAN1 Upper Global Mask Long
C1UGML.ID20       15  Identifier 20
C1UGML.ID19       14  Identifier 19
C1UGML.ID18       13  Identifier 18
C1UGML.ID17       12  Identifier 17
C1UGML.ID16       11  Identifier 16
C1UGML.ID15       10  Identifier 15
C1UGML.ID14       9   Identifier 14
C1UGML.ID13       8   Identifier 13
C1UGML.ID28       7   Identifier 28
C1UGML.ID27       6   Identifier 27
C1UGML.ID26       5   Identifier 26
C1UGML.ID25       4   Identifier 25
C1UGML.ID24       3   Identifier 24
C1UGML.ID23       2   Identifier 23
C1UGML.ID22       1   Identifier 22
C1UGML.ID21       0   Identifier 21
C1LGML           0xEF0A   CAN1 Lower Global Mask Long
C1LGML.ID4        15  Identifier 4
C1LGML.ID3        14  Identifier 3
C1LGML.ID2        13  Identifier 2
C1LGML.ID1        12  Identifier 1
C1LGML.ID0        11  Identifier 0
C1LGML.ID12       7   Identifier 12
C1LGML.ID11       6   Identifier 11
C1LGML.ID10       5   Identifier 10
C1LGML.ID9        4   Identifier 9
C1LGML.ID8        3   Identifier 8
C1LGML.ID7        2   Identifier 7
C1LGML.ID6        1   Identifier 6
C1LGML.ID5        0   Identifier 5
C1UMLM           0xEF0C   CAN1 Upper Mask of Last Message
C1UMLM.ID20       15  Identifier 20
C1UMLM.ID19       14  Identifier 19
C1UMLM.ID18       13  Identifier 18
C1UMLM.ID17       12  Identifier 17
C1UMLM.ID16       11  Identifier 16
C1UMLM.ID15       10  Identifier 15
C1UMLM.ID14       9   Identifier 14
C1UMLM.ID13       8   Identifier 13
C1UMLM.ID28       7   Identifier 28
C1UMLM.ID27       6   Identifier 27
C1UMLM.ID26       5   Identifier 26
C1UMLM.ID25       4   Identifier 25
C1UMLM.ID24       3   Identifier 24
C1UMLM.ID23       2   Identifier 23
C1UMLM.ID22       1   Identifier 22
C1UMLM.ID21       0   Identifier 21
C1LMLM           0xEF0E   CAN1 Lower Mask of Last Message
C1LMLM.ID4        15  Identifier 4
C1LMLM.ID3        14  Identifier 3
C1LMLM.ID2        13  Identifier 2
C1LMLM.ID1        12  Identifier 1
C1LMLM.ID0        11  Identifier 0
C1LMLM.ID12       7   Identifier 12
C1LMLM.ID11       6   Identifier 11
C1LMLM.ID10       5   Identifier 10
C1LMLM.ID9        4   Identifier 9
C1LMLM.ID8        3   Identifier 8
C1LMLM.ID7        2   Identifier 7
C1LMLM.ID6        1   Identifier 6
C1LMLM.ID5        0   Identifier 5
C1MCR1                  0xEF10  CAN1 Message Ctrl. Reg. (msg. 1)
C1MCR1.RMTPND15          15  Remote Pending bit 15
C1MCR1.RMTPND14          14  Remote Pending bit 14
C1MCR1.TXRQ13            13  Transmit Request bit 13
C1MCR1.TXRQ12            12  Transmit Request bit 12
C1MCR1.MSGLST_CPUUPD11   11  Message Lost_CPU Update bit 11
C1MCR1.MSGLST_CPUUPD10   10  Message Lost_CPU Update bit 10
C1MCR1.NEWDAT9           9   New Data bit 9
C1MCR1.NEWDAT8           8   New Data bit 8
C1MCR1.MSGVAL7           7   Message Valid bit 7
C1MCR1.MSGVAL6           6   Message Valid bit 6
C1MCR1.TXIE5             5   Transmit Interrupt Enable bit 5
C1MCR1.TXIE4             4   Transmit Interrupt Enable bit 4
C1MCR1.RXIE3             3   Receive Interrupt Enable bit 3
C1MCR1.RXIE2             2   Receive Interrupt Enable bit 2
C1MCR1.INTPND1           1   Interrupt Pending bit 1
C1MCR1.INTPND0           0   Interrupt Pending bit 0
C1UAR1                  0xEF12  CAN1 Upper Arbitration Reg. (msg. 1)
C1UAR1.ID20              15  Identifier bit 20
C1UAR1.ID19              14  Identifier bit 19
C1UAR1.ID18              13  Identifier bit 18
C1UAR1.ID17              12  Identifier bit 17
C1UAR1.ID16              11  Identifier bit 16
C1UAR1.ID15              10  Identifier bit 15
C1UAR1.ID14              9   Identifier bit 14
C1UAR1.ID13              8   Identifier bit 13
C1UAR1.ID28              7   Identifier bit 28
C1UAR1.ID27              6   Identifier bit 27
C1UAR1.ID26              5   Identifier bit 26
C1UAR1.ID25              4   Identifier bit 25
C1UAR1.ID24              3   Identifier bit 24
C1UAR1.ID23              2   Identifier bit 23
C1UAR1.ID22              1   Identifier bit 22
C1UAR1.ID21              0   Identifier bit 21
C1LAR1                  0xEF14  CAN1 Lower Arbitration Reg. (msg. 1)
C1LAR1.ID4               15  Identifier bit 4 
C1LAR1.ID3               14  Identifier bit 3 
C1LAR1.ID2               13  Identifier bit 2 
C1LAR1.ID1               12  Identifier bit 1 
C1LAR1.ID0               11  Identifier bit 0 
C1LAR1.ID12              7   Identifier bit 12
C1LAR1.ID11              6   Identifier bit 11
C1LAR1.ID10              5   Identifier bit 10
C1LAR1.ID9               4   Identifier bit 9 
C1LAR1.ID8               3   Identifier bit 8 
C1LAR1.ID7               2   Identifier bit 7 
C1LAR1.ID6               1   Identifier bit 6 
C1LAR1.ID5               0   Identifier bit 5 
C1MCFG1                 0xEF16  CAN1 Message Configuration Register (msg. 1)
C1MCFG1.DLC7             7   Data Length Code bit 7
C1MCFG1.DLC6             6   Data Length Code bit 6
C1MCFG1.DLC5             5   Data Length Code bit 5
C1MCFG1.DLC4             4   Data Length Code bit 4
C1MCFG1.DIR              3   Message Direction
C1MCFG1.XTD              2   Extended Identifier
C1MCR2                  0xEF20  CAN1 Message Ctrl. Reg. (msg. 2)
C1MCR2.RMTPND15          15  Remote Pending bit 15          
C1MCR2.RMTPND14          14  Remote Pending bit 14          
C1MCR2.TXRQ13            13  Transmit Request bit 13        
C1MCR2.TXRQ12            12  Transmit Request bit 12        
C1MCR2.MSGLST_CPUUPD11   11  Message Lost_CPU Update bit 11 
C1MCR2.MSGLST_CPUUPD10   10  Message Lost_CPU Update bit 10 
C1MCR2.NEWDAT9           9   New Data bit 9                 
C1MCR2.NEWDAT8           8   New Data bit 8                 
C1MCR2.MSGVAL7           7   Message Valid bit 7            
C1MCR2.MSGVAL6           6   Message Valid bit 6            
C1MCR2.TXIE5             5   Transmit Interrupt Enable bit 5
C1MCR2.TXIE4             4   Transmit Interrupt Enable bit 4
C1MCR2.RXIE3             3   Receive Interrupt Enable bit 3 
C1MCR2.RXIE2             2   Receive Interrupt Enable bit 2 
C1MCR2.INTPND1           1   Interrupt Pending bit 1        
C1MCR2.INTPND0           0   Interrupt Pending bit 0        
C1UAR2                  0xEF22  CAN1 Upper Arbitration Reg. (msg. 2)
C1UAR2.ID20              15  Identifier bit 20
C1UAR2.ID19              14  Identifier bit 19
C1UAR2.ID18              13  Identifier bit 18
C1UAR2.ID17              12  Identifier bit 17
C1UAR2.ID16              11  Identifier bit 16
C1UAR2.ID15              10  Identifier bit 15
C1UAR2.ID14              9   Identifier bit 14
C1UAR2.ID13              8   Identifier bit 13
C1UAR2.ID28              7   Identifier bit 28
C1UAR2.ID27              6   Identifier bit 27
C1UAR2.ID26              5   Identifier bit 26
C1UAR2.ID25              4   Identifier bit 25
C1UAR2.ID24              3   Identifier bit 24
C1UAR2.ID23              2   Identifier bit 23
C1UAR2.ID22              1   Identifier bit 22
C1UAR2.ID21              0   Identifier bit 21
C1LAR2                  0xEF24  CAN1 Lower Arbitration Reg. (msg. 2)
C1LAR2.ID4               15  Identifier bit 4 
C1LAR2.ID3               14  Identifier bit 3 
C1LAR2.ID2               13  Identifier bit 2 
C1LAR2.ID1               12  Identifier bit 1 
C1LAR2.ID0               11  Identifier bit 0 
C1LAR2.ID12              7   Identifier bit 12
C1LAR2.ID11              6   Identifier bit 11
C1LAR2.ID10              5   Identifier bit 10
C1LAR2.ID9               4   Identifier bit 9 
C1LAR2.ID8               3   Identifier bit 8 
C1LAR2.ID7               2   Identifier bit 7 
C1LAR2.ID6               1   Identifier bit 6 
C1LAR2.ID5               0   Identifier bit 5 
C1MCFG2         0xEF26  CAN1 Message Configuration Register (msg. 2)
C1MCFG2.DLC7     7   Data Length Code bit 7
C1MCFG2.DLC6     6   Data Length Code bit 6
C1MCFG2.DLC5     5   Data Length Code bit 5
C1MCFG2.DLC4     4   Data Length Code bit 4
C1MCFG2.DIR      3   Message Direction
C1MCFG2.XTD      2   Extended Identifier
C1MCR3                  0xEF30  CAN1 Message Ctrl. Reg. (msg. 3)
C1MCR3.RMTPND15          15  Remote Pending bit 15          
C1MCR3.RMTPND14          14  Remote Pending bit 14          
C1MCR3.TXRQ13            13  Transmit Request bit 13        
C1MCR3.TXRQ12            12  Transmit Request bit 12        
C1MCR3.MSGLST_CPUUPD11   11  Message Lost_CPU Update bit 11 
C1MCR3.MSGLST_CPUUPD10   10  Message Lost_CPU Update bit 10 
C1MCR3.NEWDAT9           9   New Data bit 9                 
C1MCR3.NEWDAT8           8   New Data bit 8                 
C1MCR3.MSGVAL7           7   Message Valid bit 7            
C1MCR3.MSGVAL6           6   Message Valid bit 6            
C1MCR3.TXIE5             5   Transmit Interrupt Enable bit 5
C1MCR3.TXIE4             4   Transmit Interrupt Enable bit 4
C1MCR3.RXIE3             3   Receive Interrupt Enable bit 3 
C1MCR3.RXIE2             2   Receive Interrupt Enable bit 2 
C1MCR3.INTPND1           1   Interrupt Pending bit 1        
C1MCR3.INTPND0           0   Interrupt Pending bit 0        
C1UAR3                  0xEF32  CAN1 Upper Arbitration Reg. (msg. 3)
C1UAR3.ID20              15  Identifier bit 20
C1UAR3.ID19              14  Identifier bit 19
C1UAR3.ID18              13  Identifier bit 18
C1UAR3.ID17              12  Identifier bit 17
C1UAR3.ID16              11  Identifier bit 16
C1UAR3.ID15              10  Identifier bit 15
C1UAR3.ID14              9   Identifier bit 14
C1UAR3.ID13              8   Identifier bit 13
C1UAR3.ID28              7   Identifier bit 28
C1UAR3.ID27              6   Identifier bit 27
C1UAR3.ID26              5   Identifier bit 26
C1UAR3.ID25              4   Identifier bit 25
C1UAR3.ID24              3   Identifier bit 24
C1UAR3.ID23              2   Identifier bit 23
C1UAR3.ID22              1   Identifier bit 22
C1UAR3.ID21              0   Identifier bit 21
C1LAR3                  0xEF34  CAN1 Lower Arbitration Reg. (msg. 3)
C1LAR3.ID4               15  Identifier bit 4 
C1LAR3.ID3               14  Identifier bit 3 
C1LAR3.ID2               13  Identifier bit 2 
C1LAR3.ID1               12  Identifier bit 1 
C1LAR3.ID0               11  Identifier bit 0 
C1LAR3.ID12              7   Identifier bit 12
C1LAR3.ID11              6   Identifier bit 11
C1LAR3.ID10              5   Identifier bit 10
C1LAR3.ID9               4   Identifier bit 9 
C1LAR3.ID8               3   Identifier bit 8 
C1LAR3.ID7               2   Identifier bit 7 
C1LAR3.ID6               1   Identifier bit 6 
C1LAR3.ID5               0   Identifier bit 5 
C1MCFG3         0xEF36  CAN1 Message Configuration Register (msg. 3)
C1MCFG3.DLC7     7   Data Length Code bit 7
C1MCFG3.DLC6     6   Data Length Code bit 6
C1MCFG3.DLC5     5   Data Length Code bit 5
C1MCFG3.DLC4     4   Data Length Code bit 4
C1MCFG3.DIR      3   Message Direction
C1MCFG3.XTD      2   Extended Identifier
C1MCR4                  0xEF40  CAN1 Message Ctrl. Reg. (msg. 4)
C1MCR4.RMTPND15          15  Remote Pending bit 15          
C1MCR4.RMTPND14          14  Remote Pending bit 14          
C1MCR4.TXRQ13            13  Transmit Request bit 13        
C1MCR4.TXRQ12            12  Transmit Request bit 12        
C1MCR4.MSGLST_CPUUPD11   11  Message Lost_CPU Update bit 11 
C1MCR4.MSGLST_CPUUPD10   10  Message Lost_CPU Update bit 10 
C1MCR4.NEWDAT9           9   New Data bit 9                 
C1MCR4.NEWDAT8           8   New Data bit 8                 
C1MCR4.MSGVAL7           7   Message Valid bit 7            
C1MCR4.MSGVAL6           6   Message Valid bit 6            
C1MCR4.TXIE5             5   Transmit Interrupt Enable bit 5
C1MCR4.TXIE4             4   Transmit Interrupt Enable bit 4
C1MCR4.RXIE3             3   Receive Interrupt Enable bit 3 
C1MCR4.RXIE2             2   Receive Interrupt Enable bit 2 
C1MCR4.INTPND1           1   Interrupt Pending bit 1        
C1MCR4.INTPND0           0   Interrupt Pending bit 0        
C1UAR4                  0xEF42  CAN1 Upper Arbitration Reg. (msg. 4)
C1UAR4.ID20              15  Identifier bit 20
C1UAR4.ID19              14  Identifier bit 19
C1UAR4.ID18              13  Identifier bit 18
C1UAR4.ID17              12  Identifier bit 17
C1UAR4.ID16              11  Identifier bit 16
C1UAR4.ID15              10  Identifier bit 15
C1UAR4.ID14              9   Identifier bit 14
C1UAR4.ID13              8   Identifier bit 13
C1UAR4.ID28              7   Identifier bit 28
C1UAR4.ID27              6   Identifier bit 27
C1UAR4.ID26              5   Identifier bit 26
C1UAR4.ID25              4   Identifier bit 25
C1UAR4.ID24              3   Identifier bit 24
C1UAR4.ID23              2   Identifier bit 23
C1UAR4.ID22              1   Identifier bit 22
C1UAR4.ID21              0   Identifier bit 21
C1LAR4                  0xEF44  CAN1 Lower Arbitration Reg. (msg. 4)
C1LAR4.ID4               15  Identifier bit 4 
C1LAR4.ID3               14  Identifier bit 3 
C1LAR4.ID2               13  Identifier bit 2 
C1LAR4.ID1               12  Identifier bit 1 
C1LAR4.ID0               11  Identifier bit 0 
C1LAR4.ID12              7   Identifier bit 12
C1LAR4.ID11              6   Identifier bit 11
C1LAR4.ID10              5   Identifier bit 10
C1LAR4.ID9               4   Identifier bit 9 
C1LAR4.ID8               3   Identifier bit 8 
C1LAR4.ID7               2   Identifier bit 7 
C1LAR4.ID6               1   Identifier bit 6 
C1LAR4.ID5               0   Identifier bit 5 
C1MCFG4         0xEF46  CAN1 Message Configuration Register (msg. 4)
C1MCFG4.DLC7     7   Data Length Code bit 7
C1MCFG4.DLC6     6   Data Length Code bit 6
C1MCFG4.DLC5     5   Data Length Code bit 5
C1MCFG4.DLC4     4   Data Length Code bit 4
C1MCFG4.DIR      3   Message Direction
C1MCFG4.XTD      2   Extended Identifier
C1MCR5                  0xEF50  CAN1 Message Ctrl. Reg. (msg. 5)
C1MCR5.RMTPND15          15  Remote Pending bit 15          
C1MCR5.RMTPND14          14  Remote Pending bit 14          
C1MCR5.TXRQ13            13  Transmit Request bit 13        
C1MCR5.TXRQ12            12  Transmit Request bit 12        
C1MCR5.MSGLST_CPUUPD11   11  Message Lost_CPU Update bit 11 
C1MCR5.MSGLST_CPUUPD10   10  Message Lost_CPU Update bit 10 
C1MCR5.NEWDAT9           9   New Data bit 9                 
C1MCR5.NEWDAT8           8   New Data bit 8                 
C1MCR5.MSGVAL7           7   Message Valid bit 7            
C1MCR5.MSGVAL6           6   Message Valid bit 6            
C1MCR5.TXIE5             5   Transmit Interrupt Enable bit 5
C1MCR5.TXIE4             4   Transmit Interrupt Enable bit 4
C1MCR5.RXIE3             3   Receive Interrupt Enable bit 3 
C1MCR5.RXIE2             2   Receive Interrupt Enable bit 2 
C1MCR5.INTPND1           1   Interrupt Pending bit 1        
C1MCR5.INTPND0           0   Interrupt Pending bit 0        
C1UAR5                  0xEF52  CAN1 Upper Arbitration Reg. (msg. 5)
C1UAR5.ID20              15  Identifier bit 20
C1UAR5.ID19              14  Identifier bit 19
C1UAR5.ID18              13  Identifier bit 18
C1UAR5.ID17              12  Identifier bit 17
C1UAR5.ID16              11  Identifier bit 16
C1UAR5.ID15              10  Identifier bit 15
C1UAR5.ID14              9   Identifier bit 14
C1UAR5.ID13              8   Identifier bit 13
C1UAR5.ID28              7   Identifier bit 28
C1UAR5.ID27              6   Identifier bit 27
C1UAR5.ID26              5   Identifier bit 26
C1UAR5.ID25              4   Identifier bit 25
C1UAR5.ID24              3   Identifier bit 24
C1UAR5.ID23              2   Identifier bit 23
C1UAR5.ID22              1   Identifier bit 22
C1UAR5.ID21              0   Identifier bit 21
C1LAR5                  0xEF54  CAN1 Lower Arbitration Reg. (msg. 5)
C1LAR5.ID4               15  Identifier bit 4 
C1LAR5.ID3               14  Identifier bit 3 
C1LAR5.ID2               13  Identifier bit 2 
C1LAR5.ID1               12  Identifier bit 1 
C1LAR5.ID0               11  Identifier bit 0 
C1LAR5.ID12              7   Identifier bit 12
C1LAR5.ID11              6   Identifier bit 11
C1LAR5.ID10              5   Identifier bit 10
C1LAR5.ID9               4   Identifier bit 9 
C1LAR5.ID8               3   Identifier bit 8 
C1LAR5.ID7               2   Identifier bit 7 
C1LAR5.ID6               1   Identifier bit 6 
C1LAR5.ID5               0   Identifier bit 5 
C1MCFG5         0xEF56  CAN1 Message Configuration Register (msg. 5)
C1MCFG5.DLC7     7   Data Length Code bit 7
C1MCFG5.DLC6     6   Data Length Code bit 6
C1MCFG5.DLC5     5   Data Length Code bit 5
C1MCFG5.DLC4     4   Data Length Code bit 4
C1MCFG5.DIR      3   Message Direction
C1MCFG5.XTD      2   Extended Identifier
C1MCR6                  0xEF60  CAN1 Message Ctrl. Reg. (msg. 6)
C1MCR6.RMTPND15          15  Remote Pending bit 15          
C1MCR6.RMTPND14          14  Remote Pending bit 14          
C1MCR6.TXRQ13            13  Transmit Request bit 13        
C1MCR6.TXRQ12            12  Transmit Request bit 12        
C1MCR6.MSGLST_CPUUPD11   11  Message Lost_CPU Update bit 11 
C1MCR6.MSGLST_CPUUPD10   10  Message Lost_CPU Update bit 10 
C1MCR6.NEWDAT9           9   New Data bit 9                 
C1MCR6.NEWDAT8           8   New Data bit 8                 
C1MCR6.MSGVAL7           7   Message Valid bit 7            
C1MCR6.MSGVAL6           6   Message Valid bit 6            
C1MCR6.TXIE5             5   Transmit Interrupt Enable bit 5
C1MCR6.TXIE4             4   Transmit Interrupt Enable bit 4
C1MCR6.RXIE3             3   Receive Interrupt Enable bit 3 
C1MCR6.RXIE2             2   Receive Interrupt Enable bit 2 
C1MCR6.INTPND1           1   Interrupt Pending bit 1        
C1MCR6.INTPND0           0   Interrupt Pending bit 0        
C1UAR6                  0xEF62  CAN1 Upper Arbitration Reg. (msg. 6)
C1UAR6.ID20              15  Identifier bit 20
C1UAR6.ID19              14  Identifier bit 19
C1UAR6.ID18              13  Identifier bit 18
C1UAR6.ID17              12  Identifier bit 17
C1UAR6.ID16              11  Identifier bit 16
C1UAR6.ID15              10  Identifier bit 15
C1UAR6.ID14              9   Identifier bit 14
C1UAR6.ID13              8   Identifier bit 13
C1UAR6.ID28              7   Identifier bit 28
C1UAR6.ID27              6   Identifier bit 27
C1UAR6.ID26              5   Identifier bit 26
C1UAR6.ID25              4   Identifier bit 25
C1UAR6.ID24              3   Identifier bit 24
C1UAR6.ID23              2   Identifier bit 23
C1UAR6.ID22              1   Identifier bit 22
C1UAR6.ID21              0   Identifier bit 21
C1LAR6                  0xEF64  CAN1 Lower Arbitration Reg. (msg. 6)
C1LAR6.ID4               15  Identifier bit 4 
C1LAR6.ID3               14  Identifier bit 3 
C1LAR6.ID2               13  Identifier bit 2 
C1LAR6.ID1               12  Identifier bit 1 
C1LAR6.ID0               11  Identifier bit 0 
C1LAR6.ID12              7   Identifier bit 12
C1LAR6.ID11              6   Identifier bit 11
C1LAR6.ID10              5   Identifier bit 10
C1LAR6.ID9               4   Identifier bit 9 
C1LAR6.ID8               3   Identifier bit 8 
C1LAR6.ID7               2   Identifier bit 7 
C1LAR6.ID6               1   Identifier bit 6 
C1LAR6.ID5               0   Identifier bit 5 
C1MCFG6         0xEF66  CAN1 Message Configuration Register (msg. 6)
C1MCFG6.DLC7     7   Data Length Code bit 7
C1MCFG6.DLC6     6   Data Length Code bit 6
C1MCFG6.DLC5     5   Data Length Code bit 5
C1MCFG6.DLC4     4   Data Length Code bit 4
C1MCFG6.DIR      3   Message Direction
C1MCFG6.XTD      2   Extended Identifier
C1MCR7                  0xEF70  CAN1 Message Ctrl. Reg. (msg. 7)
C1MCR7.RMTPND15          15  Remote Pending bit 15          
C1MCR7.RMTPND14          14  Remote Pending bit 14          
C1MCR7.TXRQ13            13  Transmit Request bit 13        
C1MCR7.TXRQ12            12  Transmit Request bit 12        
C1MCR7.MSGLST_CPUUPD11   11  Message Lost_CPU Update bit 11 
C1MCR7.MSGLST_CPUUPD10   10  Message Lost_CPU Update bit 10 
C1MCR7.NEWDAT9           9   New Data bit 9                 
C1MCR7.NEWDAT8           8   New Data bit 8                 
C1MCR7.MSGVAL7           7   Message Valid bit 7            
C1MCR7.MSGVAL6           6   Message Valid bit 6            
C1MCR7.TXIE5             5   Transmit Interrupt Enable bit 5
C1MCR7.TXIE4             4   Transmit Interrupt Enable bit 4
C1MCR7.RXIE3             3   Receive Interrupt Enable bit 3 
C1MCR7.RXIE2             2   Receive Interrupt Enable bit 2 
C1MCR7.INTPND1           1   Interrupt Pending bit 1        
C1MCR7.INTPND0           0   Interrupt Pending bit 0        
C1UAR7                  0xEF72  CAN1 Upper Arbitration Reg. (msg. 7)
C1UAR7.ID20              15  Identifier bit 20
C1UAR7.ID19              14  Identifier bit 19
C1UAR7.ID18              13  Identifier bit 18
C1UAR7.ID17              12  Identifier bit 17
C1UAR7.ID16              11  Identifier bit 16
C1UAR7.ID15              10  Identifier bit 15
C1UAR7.ID14              9   Identifier bit 14
C1UAR7.ID13              8   Identifier bit 13
C1UAR7.ID28              7   Identifier bit 28
C1UAR7.ID27              6   Identifier bit 27
C1UAR7.ID26              5   Identifier bit 26
C1UAR7.ID25              4   Identifier bit 25
C1UAR7.ID24              3   Identifier bit 24
C1UAR7.ID23              2   Identifier bit 23
C1UAR7.ID22              1   Identifier bit 22
C1UAR7.ID21              0   Identifier bit 21
C1LAR7                  0xEF74  CAN1 Lower Arbitration Reg. (msg. 7)
C1LAR7.ID4               15  Identifier bit 4 
C1LAR7.ID3               14  Identifier bit 3 
C1LAR7.ID2               13  Identifier bit 2 
C1LAR7.ID1               12  Identifier bit 1 
C1LAR7.ID0               11  Identifier bit 0 
C1LAR7.ID12              7   Identifier bit 12
C1LAR7.ID11              6   Identifier bit 11
C1LAR7.ID10              5   Identifier bit 10
C1LAR7.ID9               4   Identifier bit 9 
C1LAR7.ID8               3   Identifier bit 8 
C1LAR7.ID7               2   Identifier bit 7 
C1LAR7.ID6               1   Identifier bit 6 
C1LAR7.ID5               0   Identifier bit 5 
C1MCFG7         0xEF76  CAN1 Message Configuration Register (msg. 7)
C1MCFG7.DLC7     7   Data Length Code bit 7
C1MCFG7.DLC6     6   Data Length Code bit 6
C1MCFG7.DLC5     5   Data Length Code bit 5
C1MCFG7.DLC4     4   Data Length Code bit 4
C1MCFG7.DIR      3   Message Direction
C1MCFG7.XTD      2   Extended Identifier
C1MCR8                  0xEF80  CAN1 Message Ctrl. Reg. (msg. 8)
C1MCR8.RMTPND15          15  Remote Pending bit 15          
C1MCR8.RMTPND14          14  Remote Pending bit 14          
C1MCR8.TXRQ13            13  Transmit Request bit 13        
C1MCR8.TXRQ12            12  Transmit Request bit 12        
C1MCR8.MSGLST_CPUUPD11   11  Message Lost_CPU Update bit 11 
C1MCR8.MSGLST_CPUUPD10   10  Message Lost_CPU Update bit 10 
C1MCR8.NEWDAT9           9   New Data bit 9                 
C1MCR8.NEWDAT8           8   New Data bit 8                 
C1MCR8.MSGVAL7           7   Message Valid bit 7            
C1MCR8.MSGVAL6           6   Message Valid bit 6            
C1MCR8.TXIE5             5   Transmit Interrupt Enable bit 5
C1MCR8.TXIE4             4   Transmit Interrupt Enable bit 4
C1MCR8.RXIE3             3   Receive Interrupt Enable bit 3 
C1MCR8.RXIE2             2   Receive Interrupt Enable bit 2 
C1MCR8.INTPND1           1   Interrupt Pending bit 1        
C1MCR8.INTPND0           0   Interrupt Pending bit 0        
C1UAR8                  0xEF82  CAN1 Upper Arbitration Reg. (msg. 8)
C1UAR8.ID20              15  Identifier bit 20
C1UAR8.ID19              14  Identifier bit 19
C1UAR8.ID18              13  Identifier bit 18
C1UAR8.ID17              12  Identifier bit 17
C1UAR8.ID16              11  Identifier bit 16
C1UAR8.ID15              10  Identifier bit 15
C1UAR8.ID14              9   Identifier bit 14
C1UAR8.ID13              8   Identifier bit 13
C1UAR8.ID28              7   Identifier bit 28
C1UAR8.ID27              6   Identifier bit 27
C1UAR8.ID26              5   Identifier bit 26
C1UAR8.ID25              4   Identifier bit 25
C1UAR8.ID24              3   Identifier bit 24
C1UAR8.ID23              2   Identifier bit 23
C1UAR8.ID22              1   Identifier bit 22
C1UAR8.ID21              0   Identifier bit 21
C1LAR8                  0xEF84  CAN1 Lower Arbitration Reg. (msg. 8)
C1LAR8.ID4               15  Identifier bit 4 
C1LAR8.ID3               14  Identifier bit 3 
C1LAR8.ID2               13  Identifier bit 2 
C1LAR8.ID1               12  Identifier bit 1 
C1LAR8.ID0               11  Identifier bit 0 
C1LAR8.ID12              7   Identifier bit 12
C1LAR8.ID11              6   Identifier bit 11
C1LAR8.ID10              5   Identifier bit 10
C1LAR8.ID9               4   Identifier bit 9 
C1LAR8.ID8               3   Identifier bit 8 
C1LAR8.ID7               2   Identifier bit 7 
C1LAR8.ID6               1   Identifier bit 6 
C1LAR8.ID5               0   Identifier bit 5 
C1MCFG8         0xEF86  CAN1 Message Configuration Register (msg. 8)
C1MCFG8.DLC7     7   Data Length Code bit 7
C1MCFG8.DLC6     6   Data Length Code bit 6
C1MCFG8.DLC5     5   Data Length Code bit 5
C1MCFG8.DLC4     4   Data Length Code bit 4
C1MCFG8.DIR      3   Message Direction
C1MCFG8.XTD      2   Extended Identifier
C1MCR9                  0xEF90  CAN1 Message Ctrl. Reg. (msg. 9)
C1MCR9.RMTPND15          15  Remote Pending bit 15          
C1MCR9.RMTPND14          14  Remote Pending bit 14          
C1MCR9.TXRQ13            13  Transmit Request bit 13        
C1MCR9.TXRQ12            12  Transmit Request bit 12        
C1MCR9.MSGLST_CPUUPD11   11  Message Lost_CPU Update bit 11 
C1MCR9.MSGLST_CPUUPD10   10  Message Lost_CPU Update bit 10 
C1MCR9.NEWDAT9           9   New Data bit 9                 
C1MCR9.NEWDAT8           8   New Data bit 8                 
C1MCR9.MSGVAL7           7   Message Valid bit 7            
C1MCR9.MSGVAL6           6   Message Valid bit 6            
C1MCR9.TXIE5             5   Transmit Interrupt Enable bit 5
C1MCR9.TXIE4             4   Transmit Interrupt Enable bit 4
C1MCR9.RXIE3             3   Receive Interrupt Enable bit 3 
C1MCR9.RXIE2             2   Receive Interrupt Enable bit 2 
C1MCR9.INTPND1           1   Interrupt Pending bit 1        
C1MCR9.INTPND0           0   Interrupt Pending bit 0        
C1UAR9                  0xEF92  CAN1 Upper Arbitration Reg. (msg. 9)
C1UAR9.ID20              15  Identifier bit 20
C1UAR9.ID19              14  Identifier bit 19
C1UAR9.ID18              13  Identifier bit 18
C1UAR9.ID17              12  Identifier bit 17
C1UAR9.ID16              11  Identifier bit 16
C1UAR9.ID15              10  Identifier bit 15
C1UAR9.ID14              9   Identifier bit 14
C1UAR9.ID13              8   Identifier bit 13
C1UAR9.ID28              7   Identifier bit 28
C1UAR9.ID27              6   Identifier bit 27
C1UAR9.ID26              5   Identifier bit 26
C1UAR9.ID25              4   Identifier bit 25
C1UAR9.ID24              3   Identifier bit 24
C1UAR9.ID23              2   Identifier bit 23
C1UAR9.ID22              1   Identifier bit 22
C1UAR9.ID21              0   Identifier bit 21
C1LAR9                  0xEF94  CAN1 Lower Arbitration Reg. (msg. 9)
C1LAR9.ID4               15  Identifier bit 4 
C1LAR9.ID3               14  Identifier bit 3 
C1LAR9.ID2               13  Identifier bit 2 
C1LAR9.ID1               12  Identifier bit 1 
C1LAR9.ID0               11  Identifier bit 0 
C1LAR9.ID12              7   Identifier bit 12
C1LAR9.ID11              6   Identifier bit 11
C1LAR9.ID10              5   Identifier bit 10
C1LAR9.ID9               4   Identifier bit 9 
C1LAR9.ID8               3   Identifier bit 8 
C1LAR9.ID7               2   Identifier bit 7 
C1LAR9.ID6               1   Identifier bit 6 
C1LAR9.ID5               0   Identifier bit 5 
C1MCFG9         0xEF96  CAN1 Message Configuration Register (msg. 9)
C1MCFG9.DLC7     7   Data Length Code bit 7
C1MCFG9.DLC6     6   Data Length Code bit 6
C1MCFG9.DLC5     5   Data Length Code bit 5
C1MCFG9.DLC4     4   Data Length Code bit 4
C1MCFG9.DIR      3   Message Direction
C1MCFG9.XTD      2   Extended Identifier
C1MCRA                  0xEFA0  CAN1 Message Ctrl. Reg. (msg. A)
C1MCRA.RMTPND15          15  Remote Pending bit 15          
C1MCRA.RMTPND14          14  Remote Pending bit 14          
C1MCRA.TXRQ13            13  Transmit Request bit 13        
C1MCRA.TXRQ12            12  Transmit Request bit 12        
C1MCRA.MSGLST_CPUUPD11   11  Message Lost_CPU Update bit 11 
C1MCRA.MSGLST_CPUUPD10   10  Message Lost_CPU Update bit 10 
C1MCRA.NEWDAT9           9   New Data bit 9                 
C1MCRA.NEWDAT8           8   New Data bit 8                 
C1MCRA.MSGVAL7           7   Message Valid bit 7            
C1MCRA.MSGVAL6           6   Message Valid bit 6            
C1MCRA.TXIE5             5   Transmit Interrupt Enable bit 5
C1MCRA.TXIE4             4   Transmit Interrupt Enable bit 4
C1MCRA.RXIE3             3   Receive Interrupt Enable bit 3 
C1MCRA.RXIE2             2   Receive Interrupt Enable bit 2 
C1MCRA.INTPND1           1   Interrupt Pending bit 1        
C1MCRA.INTPND0           0   Interrupt Pending bit 0        
C1UARA          0xEFA2  CAN1 Upper Arbitration Reg. (msg. A)
C1UARA.ID20      15  Identifier bit 20
C1UARA.ID19      14  Identifier bit 19
C1UARA.ID18      13  Identifier bit 18
C1UARA.ID17      12  Identifier bit 17
C1UARA.ID16      11  Identifier bit 16
C1UARA.ID15      10  Identifier bit 15
C1UARA.ID14      9   Identifier bit 14
C1UARA.ID13      8   Identifier bit 13
C1UARA.ID28      7   Identifier bit 28
C1UARA.ID27      6   Identifier bit 27
C1UARA.ID26      5   Identifier bit 26
C1UARA.ID25      4   Identifier bit 25
C1UARA.ID24      3   Identifier bit 24
C1UARA.ID23      2   Identifier bit 23
C1UARA.ID22      1   Identifier bit 22
C1UARA.ID21      0   Identifier bit 21
C1LARA          0xEFA4  CAN1 Lower Arbitration Reg. (msg. A)
C1LARA.ID4       15  Identifier bit 4 
C1LARA.ID3       14  Identifier bit 3 
C1LARA.ID2       13  Identifier bit 2 
C1LARA.ID1       12  Identifier bit 1 
C1LARA.ID0       11  Identifier bit 0 
C1LARA.ID12      7   Identifier bit 12
C1LARA.ID11      6   Identifier bit 11
C1LARA.ID10      5   Identifier bit 10
C1LARA.ID9       4   Identifier bit 9 
C1LARA.ID8       3   Identifier bit 8 
C1LARA.ID7       2   Identifier bit 7 
C1LARA.ID6       1   Identifier bit 6 
C1LARA.ID5       0   Identifier bit 5 
C1MCFGA         0xEFA6  CAN1 Message Configuration Register (msg. A)
C1MCFGA.DLC7     7   Data Length Code bit 7
C1MCFGA.DLC6     6   Data Length Code bit 6
C1MCFGA.DLC5     5   Data Length Code bit 5
C1MCFGA.DLC4     4   Data Length Code bit 4
C1MCFGA.DIR      3   Message Direction
C1MCFGA.XTD      2   Extended Identifier
C1MCRB                  0xEFB0  CAN1 Message Ctrl. Reg. (msg. B)
C1MCRB.RMTPND15          15  Remote Pending bit 15          
C1MCRB.RMTPND14          14  Remote Pending bit 14          
C1MCRB.TXRQ13            13  Transmit Request bit 13        
C1MCRB.TXRQ12            12  Transmit Request bit 12        
C1MCRB.MSGLST_CPUUPD11   11  Message Lost_CPU Update bit 11 
C1MCRB.MSGLST_CPUUPD10   10  Message Lost_CPU Update bit 10 
C1MCRB.NEWDAT9           9   New Data bit 9                 
C1MCRB.NEWDAT8           8   New Data bit 8                 
C1MCRB.MSGVAL7           7   Message Valid bit 7            
C1MCRB.MSGVAL6           6   Message Valid bit 6            
C1MCRB.TXIE5             5   Transmit Interrupt Enable bit 5
C1MCRB.TXIE4             4   Transmit Interrupt Enable bit 4
C1MCRB.RXIE3             3   Receive Interrupt Enable bit 3 
C1MCRB.RXIE2             2   Receive Interrupt Enable bit 2 
C1MCRB.INTPND1           1   Interrupt Pending bit 1        
C1MCRB.INTPND0           0   Interrupt Pending bit 0        
C1UARB          0xEFB2  CAN1 Upper Arbitration Reg. (msg. B)
C1UARB.ID20      15  Identifier bit 20
C1UARB.ID19      14  Identifier bit 19
C1UARB.ID18      13  Identifier bit 18
C1UARB.ID17      12  Identifier bit 17
C1UARB.ID16      11  Identifier bit 16
C1UARB.ID15      10  Identifier bit 15
C1UARB.ID14      9   Identifier bit 14
C1UARB.ID13      8   Identifier bit 13
C1UARB.ID28      7   Identifier bit 28
C1UARB.ID27      6   Identifier bit 27
C1UARB.ID26      5   Identifier bit 26
C1UARB.ID25      4   Identifier bit 25
C1UARB.ID24      3   Identifier bit 24
C1UARB.ID23      2   Identifier bit 23
C1UARB.ID22      1   Identifier bit 22
C1UARB.ID21      0   Identifier bit 21
C1LARB          0xEFB4  CAN1 Lower Arbitration Reg. (msg. B)
C1LARB.ID4       15  Identifier bit 4 
C1LARB.ID3       14  Identifier bit 3 
C1LARB.ID2       13  Identifier bit 2 
C1LARB.ID1       12  Identifier bit 1 
C1LARB.ID0       11  Identifier bit 0 
C1LARB.ID12      7   Identifier bit 12
C1LARB.ID11      6   Identifier bit 11
C1LARB.ID10      5   Identifier bit 10
C1LARB.ID9       4   Identifier bit 9 
C1LARB.ID8       3   Identifier bit 8 
C1LARB.ID7       2   Identifier bit 7 
C1LARB.ID6       1   Identifier bit 6 
C1LARB.ID5       0   Identifier bit 5 
C1MCFGB         0xEFB6  CAN1 Message Configuration Register (msg. B)
C1MCFGB.DLC7     7   Data Length Code bit 7
C1MCFGB.DLC6     6   Data Length Code bit 6
C1MCFGB.DLC5     5   Data Length Code bit 5
C1MCFGB.DLC4     4   Data Length Code bit 4
C1MCFGB.DIR      3   Message Direction
C1MCFGB.XTD      2   Extended Identifier
C1MCRC                  0xEFC0  CAN1 Message Ctrl. Reg. (msg. C)
C1MCRC.RMTPND15          15  Remote Pending bit 15          
C1MCRC.RMTPND14          14  Remote Pending bit 14          
C1MCRC.TXRQ13            13  Transmit Request bit 13        
C1MCRC.TXRQ12            12  Transmit Request bit 12        
C1MCRC.MSGLST_CPUUPD11   11  Message Lost_CPU Update bit 11 
C1MCRC.MSGLST_CPUUPD10   10  Message Lost_CPU Update bit 10 
C1MCRC.NEWDAT9           9   New Data bit 9                 
C1MCRC.NEWDAT8           8   New Data bit 8                 
C1MCRC.MSGVAL7           7   Message Valid bit 7            
C1MCRC.MSGVAL6           6   Message Valid bit 6            
C1MCRC.TXIE5             5   Transmit Interrupt Enable bit 5
C1MCRC.TXIE4             4   Transmit Interrupt Enable bit 4
C1MCRC.RXIE3             3   Receive Interrupt Enable bit 3 
C1MCRC.RXIE2             2   Receive Interrupt Enable bit 2 
C1MCRC.INTPND1           1   Interrupt Pending bit 1        
C1MCRC.INTPND0           0   Interrupt Pending bit 0        
C1UARC                  0xEFC2  CAN1 Upper Arbitration Reg. (msg. C)
C1UARC.ID20              15  Identifier bit 20
C1UARC.ID19              14  Identifier bit 19
C1UARC.ID18              13  Identifier bit 18
C1UARC.ID17              12  Identifier bit 17
C1UARC.ID16              11  Identifier bit 16
C1UARC.ID15              10  Identifier bit 15
C1UARC.ID14              9   Identifier bit 14
C1UARC.ID13              8   Identifier bit 13
C1UARC.ID28              7   Identifier bit 28
C1UARC.ID27              6   Identifier bit 27
C1UARC.ID26              5   Identifier bit 26
C1UARC.ID25              4   Identifier bit 25
C1UARC.ID24              3   Identifier bit 24
C1UARC.ID23              2   Identifier bit 23
C1UARC.ID22              1   Identifier bit 22
C1UARC.ID21              0   Identifier bit 21
C1LARC                  0xEFC4  CAN1 Lower Arbitration Reg. (msg. C)
C1LARC.ID4               15  Identifier bit 4 
C1LARC.ID3               14  Identifier bit 3 
C1LARC.ID2               13  Identifier bit 2 
C1LARC.ID1               12  Identifier bit 1 
C1LARC.ID0               11  Identifier bit 0 
C1LARC.ID12              7   Identifier bit 12
C1LARC.ID11              6   Identifier bit 11
C1LARC.ID10              5   Identifier bit 10
C1LARC.ID9               4   Identifier bit 9 
C1LARC.ID8               3   Identifier bit 8 
C1LARC.ID7               2   Identifier bit 7 
C1LARC.ID6               1   Identifier bit 6 
C1LARC.ID5               0   Identifier bit 5 
C1MCFGC         0xEFC6  CAN1 Message Configuration Register (msg. C)
C1MCFGC.DLC7     7   Data Length Code bit 7
C1MCFGC.DLC6     6   Data Length Code bit 6
C1MCFGC.DLC5     5   Data Length Code bit 5
C1MCFGC.DLC4     4   Data Length Code bit 4
C1MCFGC.DIR      3   Message Direction
C1MCFGC.XTD      2   Extended Identifier
C1MCRD                  0xEFD0  CAN1 Message Ctrl. Reg. (msg. D)
C1MCRD.RMTPND15          15  Remote Pending bit 15          
C1MCRD.RMTPND14          14  Remote Pending bit 14          
C1MCRD.TXRQ13            13  Transmit Request bit 13        
C1MCRD.TXRQ12            12  Transmit Request bit 12        
C1MCRD.MSGLST_CPUUPD11   11  Message Lost_CPU Update bit 11 
C1MCRD.MSGLST_CPUUPD10   10  Message Lost_CPU Update bit 10 
C1MCRD.NEWDAT9           9   New Data bit 9                 
C1MCRD.NEWDAT8           8   New Data bit 8                 
C1MCRD.MSGVAL7           7   Message Valid bit 7            
C1MCRD.MSGVAL6           6   Message Valid bit 6            
C1MCRD.TXIE5             5   Transmit Interrupt Enable bit 5
C1MCRD.TXIE4             4   Transmit Interrupt Enable bit 4
C1MCRD.RXIE3             3   Receive Interrupt Enable bit 3 
C1MCRD.RXIE2             2   Receive Interrupt Enable bit 2 
C1MCRD.INTPND1           1   Interrupt Pending bit 1        
C1MCRD.INTPND0           0   Interrupt Pending bit 0        
C1UARD                  0xEFD2  CAN1 Upper Arbitration Reg. (msg. D)
C1UARD.ID20              15  Identifier bit 20
C1UARD.ID19              14  Identifier bit 19
C1UARD.ID18              13  Identifier bit 18
C1UARD.ID17              12  Identifier bit 17
C1UARD.ID16              11  Identifier bit 16
C1UARD.ID15              10  Identifier bit 15
C1UARD.ID14              9   Identifier bit 14
C1UARD.ID13              8   Identifier bit 13
C1UARD.ID28              7   Identifier bit 28
C1UARD.ID27              6   Identifier bit 27
C1UARD.ID26              5   Identifier bit 26
C1UARD.ID25              4   Identifier bit 25
C1UARD.ID24              3   Identifier bit 24
C1UARD.ID23              2   Identifier bit 23
C1UARD.ID22              1   Identifier bit 22
C1UARD.ID21              0   Identifier bit 21
C1LARD                  0xEFD4  CAN1 Lower Arbitration Reg. (msg. D)
C1LARD.ID4               15  Identifier bit 4 
C1LARD.ID3               14  Identifier bit 3 
C1LARD.ID2               13  Identifier bit 2 
C1LARD.ID1               12  Identifier bit 1 
C1LARD.ID0               11  Identifier bit 0 
C1LARD.ID12              7   Identifier bit 12
C1LARD.ID11              6   Identifier bit 11
C1LARD.ID10              5   Identifier bit 10
C1LARD.ID9               4   Identifier bit 9 
C1LARD.ID8               3   Identifier bit 8 
C1LARD.ID7               2   Identifier bit 7 
C1LARD.ID6               1   Identifier bit 6 
C1LARD.ID5               0   Identifier bit 5 
C1MCFGD         0xEFD6  CAN1 Message Configuration Register (msg. D)
C1MCFGD.DLC7     7   Data Length Code bit 7
C1MCFGD.DLC6     6   Data Length Code bit 6
C1MCFGD.DLC5     5   Data Length Code bit 5
C1MCFGD.DLC4     4   Data Length Code bit 4
C1MCFGD.DIR      3   Message Direction
C1MCFGD.XTD      2   Extended Identifier
C1MCRE                  0xEFE0  CAN1 Message Ctrl. Reg. (msg. E)
C1MCRE.RMTPND15          15  Remote Pending bit 15          
C1MCRE.RMTPND14          14  Remote Pending bit 14          
C1MCRE.TXRQ13            13  Transmit Request bit 13        
C1MCRE.TXRQ12            12  Transmit Request bit 12        
C1MCRE.MSGLST_CPUUPD11   11  Message Lost_CPU Update bit 11 
C1MCRE.MSGLST_CPUUPD10   10  Message Lost_CPU Update bit 10 
C1MCRE.NEWDAT9           9   New Data bit 9                 
C1MCRE.NEWDAT8           8   New Data bit 8                 
C1MCRE.MSGVAL7           7   Message Valid bit 7            
C1MCRE.MSGVAL6           6   Message Valid bit 6            
C1MCRE.TXIE5             5   Transmit Interrupt Enable bit 5
C1MCRE.TXIE4             4   Transmit Interrupt Enable bit 4
C1MCRE.RXIE3             3   Receive Interrupt Enable bit 3 
C1MCRE.RXIE2             2   Receive Interrupt Enable bit 2 
C1MCRE.INTPND1           1   Interrupt Pending bit 1        
C1MCRE.INTPND0           0   Interrupt Pending bit 0        
C1UARE                  0xEFE2  CAN1 Upper Arbitration Reg. (msg. E)
C1UARE.ID20              15  Identifier bit 20
C1UARE.ID19              14  Identifier bit 19
C1UARE.ID18              13  Identifier bit 18
C1UARE.ID17              12  Identifier bit 17
C1UARE.ID16              11  Identifier bit 16
C1UARE.ID15              10  Identifier bit 15
C1UARE.ID14              9   Identifier bit 14
C1UARE.ID13              8   Identifier bit 13
C1UARE.ID28              7   Identifier bit 28
C1UARE.ID27              6   Identifier bit 27
C1UARE.ID26              5   Identifier bit 26
C1UARE.ID25              4   Identifier bit 25
C1UARE.ID24              3   Identifier bit 24
C1UARE.ID23              2   Identifier bit 23
C1UARE.ID22              1   Identifier bit 22
C1UARE.ID21              0   Identifier bit 21
C1LARE                  0xEFE4  CAN1 Lower Arbitration Reg. (msg. E)
C1LARE.ID4               15  Identifier bit 4 
C1LARE.ID3               14  Identifier bit 3 
C1LARE.ID2               13  Identifier bit 2 
C1LARE.ID1               12  Identifier bit 1 
C1LARE.ID0               11  Identifier bit 0 
C1LARE.ID12              7   Identifier bit 12
C1LARE.ID11              6   Identifier bit 11
C1LARE.ID10              5   Identifier bit 10
C1LARE.ID9               4   Identifier bit 9 
C1LARE.ID8               3   Identifier bit 8 
C1LARE.ID7               2   Identifier bit 7 
C1LARE.ID6               1   Identifier bit 6 
C1LARE.ID5               0   Identifier bit 5 
C1MCFGE         0xEFE6  CAN1 Message Configuration Register (msg. E)
C1MCFGE.DLC7     7   Data Length Code bit 7
C1MCFGE.DLC6     6   Data Length Code bit 6
C1MCFGE.DLC5     5   Data Length Code bit 5
C1MCFGE.DLC4     4   Data Length Code bit 4
C1MCFGE.DIR      3   Message Direction
C1MCFGE.XTD      2   Extended Identifier
C1MCRF                  0xEFF0  CAN1 Message Ctrl. Reg. (msg. F)
C1MCRF.RMTPND15          15  Remote Pending bit 15          
C1MCRF.RMTPND14          14  Remote Pending bit 14          
C1MCRF.TXRQ13            13  Transmit Request bit 13        
C1MCRF.TXRQ12            12  Transmit Request bit 12        
C1MCRF.MSGLST_CPUUPD11   11  Message Lost_CPU Update bit 11 
C1MCRF.MSGLST_CPUUPD10   10  Message Lost_CPU Update bit 10 
C1MCRF.NEWDAT9           9   New Data bit 9                 
C1MCRF.NEWDAT8           8   New Data bit 8                 
C1MCRF.MSGVAL7           7   Message Valid bit 7            
C1MCRF.MSGVAL6           6   Message Valid bit 6            
C1MCRF.TXIE5             5   Transmit Interrupt Enable bit 5
C1MCRF.TXIE4             4   Transmit Interrupt Enable bit 4
C1MCRF.RXIE3             3   Receive Interrupt Enable bit 3 
C1MCRF.RXIE2             2   Receive Interrupt Enable bit 2 
C1MCRF.INTPND1           1   Interrupt Pending bit 1        
C1MCRF.INTPND0           0   Interrupt Pending bit 0        
C1UARF                  0xEFF2  CAN1 Upper Arbitration Reg. (msg. F)
C1UARF.ID20              15  Identifier bit 20
C1UARF.ID19              14  Identifier bit 19
C1UARF.ID18              13  Identifier bit 18
C1UARF.ID17              12  Identifier bit 17
C1UARF.ID16              11  Identifier bit 16
C1UARF.ID15              10  Identifier bit 15
C1UARF.ID14              9   Identifier bit 14
C1UARF.ID13              8   Identifier bit 13
C1UARF.ID28              7   Identifier bit 28
C1UARF.ID27              6   Identifier bit 27
C1UARF.ID26              5   Identifier bit 26
C1UARF.ID25              4   Identifier bit 25
C1UARF.ID24              3   Identifier bit 24
C1UARF.ID23              2   Identifier bit 23
C1UARF.ID22              1   Identifier bit 22
C1UARF.ID21              0   Identifier bit 21
C1LARF                  0xEFF4  CAN1 Lower Arbitration Reg. (msg. F)
C1LARF.ID4               15  Identifier bit 4 
C1LARF.ID3               14  Identifier bit 3 
C1LARF.ID2               13  Identifier bit 2 
C1LARF.ID1               12  Identifier bit 1 
C1LARF.ID0               11  Identifier bit 0 
C1LARF.ID12              7   Identifier bit 12
C1LARF.ID11              6   Identifier bit 11
C1LARF.ID10              5   Identifier bit 10
C1LARF.ID9               4   Identifier bit 9 
C1LARF.ID8               3   Identifier bit 8 
C1LARF.ID7               2   Identifier bit 7 
C1LARF.ID6               1   Identifier bit 6 
C1LARF.ID5               0   Identifier bit 5 
C1MCFGF         0xEFF6  CAN1 Message Configuration Register (msg. F)
C1MCFGF.DLC7     7   Data Length Code bit 7
C1MCFGF.DLC6     6   Data Length Code bit 6
C1MCFGF.DLC5     5   Data Length Code bit 5
C1MCFGF.DLC4     4   Data Length Code bit 4
C1MCFGF.DIR      3   Message Direction
C1MCFGF.XTD      2   Extended Identifier

; ESFR
XPERCON          0xF024 X-Peripheral Control Register
XPERCON.XPER15    15  XBUS Module 15 Select
XPERCON.XPER14    14  XBUS Module 14 Select
XPERCON.XPER13    13  XBUS Module 13 Select
XPERCON.XPER12    12  XBUS Module 12 Select
XPERCON.XPER11    11  XBUS Module 11 Select
XPERCON.XPER10    10  XBUS Module 10 Select
XPERCON.XPER9     9   XBUS Module 9 Select
XPERCON.XPER8     8   XBUS Module 8 Select
XPERCON.XPER7     7   XBUS Module 7 Select
XPERCON.XPER6     6   XBUS Module 6 Select
XPERCON.XPER5     5   XBUS Module 5 Select
XPERCON.XPER4     4   XBUS Module 4 Select
XPERCON.XPER3     3   XBUS Module 3 Select
XPERCON.XPER2     2   XBUS Module 2 Select
XPERCON.XPER1     1   XBUS Module 1 Select
XPERCON.XPER0     0   XBUS Module 0 Select
PT0              0xF030 PWM Module Up/Down Counter 0
PT1              0xF032 PWM Module Up/Down Counter 1
PT2              0xF034 PWM Module Up/Down Counter 2
PT3              0xF036 PWM Module Up/Down Counter 3
PP0              0xF038 PWM Module Period Register 0
PP1              0xF03A PWM Module Period Register 1
PP2              0xF03C PWM Module Period Register 2
PP3              0xF03E PWM Module Period Register 3
T7               0xF050 CAPCOM Timer 7 Register
T8               0xF052 CAPCOM Timer 8 Register
T7REL            0xF054 CAPCOM Timer 7 Reload Register
T8REL            0xF056 CAPCOM Timer 8 Reload Register
IDMEM2           0xF076 IDMEM2
IDPROG           0xF078 IDPROG
IDMEM            0xF07A IDMEM
IDCHIP           0xF07C IDCHIP
IDMANUF          0xF07E IDMANUF
POCON0L          0xF080 Port P0L Output Control Register
POCON0L.PN3DC_H   15  Port Nibble 3_H Driver Characteristic
POCON0L.PN3DC_L   14  Port Nibble 3_L Driver Characteristic
POCON0L.PN3EC_H   13  Port Nibble 3_H Edge Characteristic
POCON0L.PN3EC_L   12  Port Nibble 3_L Edge Characteristic
POCON0L.PN2DC_H   11  Port Nibble 2_H Driver Characteristic
POCON0L.PN2DC_L   10  Port Nibble 2_L Driver Characteristic
POCON0L.PN2EC_H   9   Port Nibble 2_H Edge Characteristic  
POCON0L.PN2EC_L   8   Port Nibble 2_L Edge Characteristic  
POCON0L.PN1DC_H   7   Port Nibble 1_H Driver Characteristic
POCON0L.PN1DC_L   6   Port Nibble 1_L Driver Characteristic
POCON0L.PN1EC_H   5   Port Nibble 1_H Edge Characteristic  
POCON0L.PN1EC_L   4   Port Nibble 1_L Edge Characteristic  
POCON0L.PN0DC_H   3   Port Nibble 0_H Driver Characteristic
POCON0L.PN0DC_L   2   Port Nibble 0_L Driver Characteristic
POCON0L.PN0EC_H   1   Port Nibble 0_H Edge Characteristic  
POCON0L.PN0EC_L   0   Port Nibble 0_L Edge Characteristic  
POCON0H          0xF082 Port P0H Output Control Register
POCON0H.PN3DC_H   15  Port Nibble 3_H Driver Characteristic
POCON0H.PN3DC_L   14  Port Nibble 3_L Driver Characteristic
POCON0H.PN3EC_H   13  Port Nibble 3_H Edge Characteristic
POCON0H.PN3EC_L   12  Port Nibble 3_L Edge Characteristic
POCON0H.PN2DC_H   11  Port Nibble 2_H Driver Characteristic
POCON0H.PN2DC_L   10  Port Nibble 2_L Driver Characteristic
POCON0H.PN2EC_H   9   Port Nibble 2_H Edge Characteristic  
POCON0H.PN2EC_L   8   Port Nibble 2_L Edge Characteristic  
POCON0H.PN1DC_H   7   Port Nibble 1_H Driver Characteristic
POCON0H.PN1DC_L   6   Port Nibble 1_L Driver Characteristic
POCON0H.PN1EC_H   5   Port Nibble 1_H Edge Characteristic  
POCON0H.PN1EC_L   4   Port Nibble 1_L Edge Characteristic  
POCON0H.PN0DC_H   3   Port Nibble 0_H Driver Characteristic
POCON0H.PN0DC_L   2   Port Nibble 0_L Driver Characteristic
POCON0H.PN0EC_H   1   Port Nibble 0_H Edge Characteristic  
POCON0H.PN0EC_L   0   Port Nibble 0_L Edge Characteristic  
POCON1L          0xF084 Port P1L Output Control Register
POCON1L.PN3DC_H   15  Port Nibble 3_H Driver Characteristic
POCON1L.PN3DC_L   14  Port Nibble 3_L Driver Characteristic
POCON1L.PN3EC_H   13  Port Nibble 3_H Edge Characteristic
POCON1L.PN3EC_L   12  Port Nibble 3_L Edge Characteristic
POCON1L.PN2DC_H   11  Port Nibble 2_H Driver Characteristic
POCON1L.PN2DC_L   10  Port Nibble 2_L Driver Characteristic
POCON1L.PN2EC_H   9   Port Nibble 2_H Edge Characteristic  
POCON1L.PN2EC_L   8   Port Nibble 2_L Edge Characteristic  
POCON1L.PN1DC_H   7   Port Nibble 1_H Driver Characteristic
POCON1L.PN1DC_L   6   Port Nibble 1_L Driver Characteristic
POCON1L.PN1EC_H   5   Port Nibble 1_H Edge Characteristic  
POCON1L.PN1EC_L   4   Port Nibble 1_L Edge Characteristic  
POCON1L.PN0DC_H   3   Port Nibble 0_H Driver Characteristic
POCON1L.PN0DC_L   2   Port Nibble 0_L Driver Characteristic
POCON1L.PN0EC_H   1   Port Nibble 0_H Edge Characteristic  
POCON1L.PN0EC_L   0   Port Nibble 0_L Edge Characteristic  
POCON1H          0xF086 Port P1H Output Control Register
POCON1H.PN3DC_H   15  Port Nibble 3_H Driver Characteristic
POCON1H.PN3DC_L   14  Port Nibble 3_L Driver Characteristic
POCON1H.PN3EC_H   13  Port Nibble 3_H Edge Characteristic
POCON1H.PN3EC_L   12  Port Nibble 3_L Edge Characteristic
POCON1H.PN2DC_H   11  Port Nibble 2_H Driver Characteristic
POCON1H.PN2DC_L   10  Port Nibble 2_L Driver Characteristic
POCON1H.PN2EC_H   9   Port Nibble 2_H Edge Characteristic  
POCON1H.PN2EC_L   8   Port Nibble 2_L Edge Characteristic  
POCON1H.PN1DC_H   7   Port Nibble 1_H Driver Characteristic
POCON1H.PN1DC_L   6   Port Nibble 1_L Driver Characteristic
POCON1H.PN1EC_H   5   Port Nibble 1_H Edge Characteristic  
POCON1H.PN1EC_L   4   Port Nibble 1_L Edge Characteristic  
POCON1H.PN0DC_H   3   Port Nibble 0_H Driver Characteristic
POCON1H.PN0DC_L   2   Port Nibble 0_L Driver Characteristic
POCON1H.PN0EC_H   1   Port Nibble 0_H Edge Characteristic  
POCON1H.PN0EC_L   0   Port Nibble 0_L Edge Characteristic  
POCON2           0xF088 Port P2 Output Control Register
POCON2.PN3DC_H    15  Port Nibble 3_H Driver Characteristic
POCON2.PN3DC_L    14  Port Nibble 3_L Driver Characteristic
POCON2.PN3EC_H    13  Port Nibble 3_H Edge Characteristic
POCON2.PN3EC_L    12  Port Nibble 3_L Edge Characteristic
POCON2.PN2DC_H    11  Port Nibble 2_H Driver Characteristic
POCON2.PN2DC_L    10  Port Nibble 2_L Driver Characteristic
POCON2.PN2EC_H    9   Port Nibble 2_H Edge Characteristic
POCON2.PN2EC_L    8   Port Nibble 2_L Edge Characteristic
POCON2.PN1DC_H    7   Port Nibble 1_H Driver Characteristic
POCON2.PN1DC_L    6   Port Nibble 1_L Driver Characteristic
POCON2.PN1EC_H    5   Port Nibble 1_H Edge Characteristic
POCON2.PN1EC_L    4   Port Nibble 1_L Edge Characteristic
POCON2.PN0DC_H    3   Port Nibble 0_H Driver Characteristic
POCON2.PN0DC_L    2   Port Nibble 0_L Driver Characteristic
POCON2.PN0EC_H    1   Port Nibble 0_H Edge Characteristic
POCON2.PN0EC_L    0   Port Nibble 0_L Edge Characteristic
POCON3           0xF08A Port P3 Output Control Register
POCON3.PN3DC_H    15  Port Nibble 3_H Driver Characteristic
POCON3.PN3DC_L    14  Port Nibble 3_L Driver Characteristic
POCON3.PN3EC_H    13  Port Nibble 3_H Edge Characteristic
POCON3.PN3EC_L    12  Port Nibble 3_L Edge Characteristic
POCON3.PN2DC_H    11  Port Nibble 2_H Driver Characteristic
POCON3.PN2DC_L    10  Port Nibble 2_L Driver Characteristic
POCON3.PN2EC_H    9   Port Nibble 2_H Edge Characteristic
POCON3.PN2EC_L    8   Port Nibble 2_L Edge Characteristic
POCON3.PN1DC_H    7   Port Nibble 1_H Driver Characteristic
POCON3.PN1DC_L    6   Port Nibble 1_L Driver Characteristic
POCON3.PN1EC_H    5   Port Nibble 1_H Edge Characteristic
POCON3.PN1EC_L    4   Port Nibble 1_L Edge Characteristic
POCON3.PN0DC_H    3   Port Nibble 0_H Driver Characteristic
POCON3.PN0DC_L    2   Port Nibble 0_L Driver Characteristic
POCON3.PN0EC_H    1   Port Nibble 0_H Edge Characteristic
POCON3.PN0EC_L    0   Port Nibble 0_L Edge Characteristic
POCON4           0xF08C Port P4 Output Control Register
POCON4.PN3DC_H    15  Port Nibble 3_H Driver Characteristic
POCON4.PN3DC_L    14  Port Nibble 3_L Driver Characteristic
POCON4.PN3EC_H    13  Port Nibble 3_H Edge Characteristic
POCON4.PN3EC_L    12  Port Nibble 3_L Edge Characteristic
POCON4.PN2DC_H    11  Port Nibble 2_H Driver Characteristic
POCON4.PN2DC_L    10  Port Nibble 2_L Driver Characteristic
POCON4.PN2EC_H    9   Port Nibble 2_H Edge Characteristic
POCON4.PN2EC_L    8   Port Nibble 2_L Edge Characteristic
POCON4.PN1DC_H    7   Port Nibble 1_H Driver Characteristic
POCON4.PN1DC_L    6   Port Nibble 1_L Driver Characteristic
POCON4.PN1EC_H    5   Port Nibble 1_H Edge Characteristic
POCON4.PN1EC_L    4   Port Nibble 1_L Edge Characteristic
POCON4.PN0DC_H    3   Port Nibble 0_H Driver Characteristic
POCON4.PN0DC_L    2   Port Nibble 0_L Driver Characteristic
POCON4.PN0EC_H    1   Port Nibble 0_H Edge Characteristic
POCON4.PN0EC_L    0   Port Nibble 0_L Edge Characteristic
POCON6           0xF08E Port P6 Output Control Register
POCON6.PN3DC_H    15  Port Nibble 3_H Driver Characteristic
POCON6.PN3DC_L    14  Port Nibble 3_L Driver Characteristic
POCON6.PN3EC_H    13  Port Nibble 3_H Edge Characteristic
POCON6.PN3EC_L    12  Port Nibble 3_L Edge Characteristic
POCON6.PN2DC_H    11  Port Nibble 2_H Driver Characteristic
POCON6.PN2DC_L    10  Port Nibble 2_L Driver Characteristic
POCON6.PN2EC_H    9   Port Nibble 2_H Edge Characteristic
POCON6.PN2EC_L    8   Port Nibble 2_L Edge Characteristic
POCON6.PN1DC_H    7   Port Nibble 1_H Driver Characteristic
POCON6.PN1DC_L    6   Port Nibble 1_L Driver Characteristic
POCON6.PN1EC_H    5   Port Nibble 1_H Edge Characteristic
POCON6.PN1EC_L    4   Port Nibble 1_L Edge Characteristic
POCON6.PN0DC_H    3   Port Nibble 0_H Driver Characteristic
POCON6.PN0DC_L    2   Port Nibble 0_L Driver Characteristic
POCON6.PN0EC_H    1   Port Nibble 0_H Edge Characteristic
POCON6.PN0EC_L    0   Port Nibble 0_L Edge Characteristic
POCON7           0xF090 Port P7 Output Control Register
POCON7.PN3DC_H    15  Port Nibble 3_H Driver Characteristic
POCON7.PN3DC_L    14  Port Nibble 3_L Driver Characteristic
POCON7.PN3EC_H    13  Port Nibble 3_H Edge Characteristic
POCON7.PN3EC_L    12  Port Nibble 3_L Edge Characteristic
POCON7.PN2DC_H    11  Port Nibble 2_H Driver Characteristic
POCON7.PN2DC_L    10  Port Nibble 2_L Driver Characteristic
POCON7.PN2EC_H    9   Port Nibble 2_H Edge Characteristic
POCON7.PN2EC_L    8   Port Nibble 2_L Edge Characteristic
POCON7.PN1DC_H    7   Port Nibble 1_H Driver Characteristic
POCON7.PN1DC_L    6   Port Nibble 1_L Driver Characteristic
POCON7.PN1EC_H    5   Port Nibble 1_H Edge Characteristic
POCON7.PN1EC_L    4   Port Nibble 1_L Edge Characteristic
POCON7.PN0DC_H    3   Port Nibble 0_H Driver Characteristic
POCON7.PN0DC_L    2   Port Nibble 0_L Driver Characteristic
POCON7.PN0EC_H    1   Port Nibble 0_H Edge Characteristic
POCON7.PN0EC_L    0   Port Nibble 0_L Edge Characteristic
POCON8           0xF092 Port P8 Output Control Register
POCON8.PN3DC_H    15  Port Nibble 3_H Driver Characteristic
POCON8.PN3DC_L    14  Port Nibble 3_L Driver Characteristic
POCON8.PN3EC_H    13  Port Nibble 3_H Edge Characteristic
POCON8.PN3EC_L    12  Port Nibble 3_L Edge Characteristic
POCON8.PN2DC_H    11  Port Nibble 2_H Driver Characteristic
POCON8.PN2DC_L    10  Port Nibble 2_L Driver Characteristic
POCON8.PN2EC_H    9   Port Nibble 2_H Edge Characteristic
POCON8.PN2EC_L    8   Port Nibble 2_L Edge Characteristic
POCON8.PN1DC_H    7   Port Nibble 1_H Driver Characteristic
POCON8.PN1DC_L    6   Port Nibble 1_L Driver Characteristic
POCON8.PN1EC_H    5   Port Nibble 1_H Edge Characteristic
POCON8.PN1EC_L    4   Port Nibble 1_L Edge Characteristic
POCON8.PN0DC_H    3   Port Nibble 0_H Driver Characteristic
POCON8.PN0DC_L    2   Port Nibble 0_L Driver Characteristic
POCON8.PN0EC_H    1   Port Nibble 0_H Edge Characteristic
POCON8.PN0EC_L    0   Port Nibble 0_L Edge Characteristic
ADDAT2           0xF0A0 A/D Converter 2 Result Register
ADDAT2.CHNR15     15  Channel Number bit 15
ADDAT2.CHNR14     14  Channel Number bit 14
ADDAT2.CHNR13     13  Channel Number bit 13
ADDAT2.CHNR12     12  Channel Number bit 12
ADDAT2.CHX        11  Channel Extension Indicator
ADDAT2.ADRES9     9   A/D Conversion Result bit 9
ADDAT2.ADRES8     8   A/D Conversion Result bit 8
ADDAT2.ADRES7     7   A/D Conversion Result bit 7
ADDAT2.ADRES6     6   A/D Conversion Result bit 6
ADDAT2.ADRES5     5   A/D Conversion Result bit 5
ADDAT2.ADRES4     4   A/D Conversion Result bit 4
ADDAT2.ADRES3     3   A/D Conversion Result bit 3
ADDAT2.ADRES2     2   A/D Conversion Result bit 2
ADDAT2.ADRES1     1   A/D Conversion Result bit 1
ADDAT2.ADRES0     0   A/D Conversion Result bit 0
POCON20          0xF0AA Dedicated Pin Output Control Register
POCON20.PN3DC_H   15  Port Nibble 3_H Driver Characteristic
POCON20.PN3DC_L   14  Port Nibble 3_L Driver Characteristic
POCON20.PN3EC_H   13  Port Nibble 3_H Edge Characteristic
POCON20.PN3EC_L   12  Port Nibble 3_L Edge Characteristic
POCON20.PN2DC_H   11  Port Nibble 2_H Driver Characteristic
POCON20.PN2DC_L   10  Port Nibble 2_L Driver Characteristic
POCON20.PN2EC_H   9   Port Nibble 2_H Edge Characteristic  
POCON20.PN2EC_L   8   Port Nibble 2_L Edge Characteristic  
POCON20.PN1DC_H   7   Port Nibble 1_H Driver Characteristic
POCON20.PN1DC_L   6   Port Nibble 1_L Driver Characteristic
POCON20.PN1EC_H   5   Port Nibble 1_H Edge Characteristic  
POCON20.PN1EC_L   4   Port Nibble 1_L Edge Characteristic  
POCON20.PN0DC_H   3   Port Nibble 0_H Driver Characteristic
POCON20.PN0DC_L   2   Port Nibble 0_L Driver Characteristic
POCON20.PN0EC_H   1   Port Nibble 0_H Edge Characteristic  
POCON20.PN0EC_L   0   Port Nibble 0_L Edge Characteristic  
SSCTB            0xF0B0 SSC Transmit Buffer
SSCRB            0xF0B2 SSC Receive Buffer
SSCBR            0xF0B4 SSC Baudrate Register
T14REL           0xF0D0 RTC Timer 14 Reload Register
T14              0xF0D2 RTC Timer 14 Register
RTCL             0xF0D4 RTC Low Register
RTCH             0xF0D6 RTC High Register
DP0L             0xF100 P0L Direction Control Register
DP0L.DP0L7        7   Port direction register DP0L bit 7
DP0L.DP0L6        6   Port direction register DP0L bit 6
DP0L.DP0L5        5   Port direction register DP0L bit 5
DP0L.DP0L4        4   Port direction register DP0L bit 4
DP0L.DP0L3        3   Port direction register DP0L bit 3
DP0L.DP0L2        2   Port direction register DP0L bit 2
DP0L.DP0L1        1   Port direction register DP0L bit 1
DP0L.DP0L0        0   Port direction register DP0L bit 0
DP0H             0xF102 P0H Direction Control Register
DP0H.DP0H7        7   Port direction register DP0H bit 7
DP0H.DP0H6        6   Port direction register DP0H bit 6
DP0H.DP0H5        5   Port direction register DP0H bit 5
DP0H.DP0H4        4   Port direction register DP0H bit 4
DP0H.DP0H3        3   Port direction register DP0H bit 3
DP0H.DP0H2        2   Port direction register DP0H bit 2
DP0H.DP0H1        1   Port direction register DP0H bit 1
DP0H.DP0H0        0   Port direction register DP0H bit 0
DP1L             0xF104 P1L Direction Control Register
DP1L.DP1L7        7   Port direction register DP1L bit 7
DP1L.DP1L6        6   Port direction register DP1L bit 6
DP1L.DP1L5        5   Port direction register DP1L bit 5
DP1L.DP1L4        4   Port direction register DP1L bit 4
DP1L.DP1L3        3   Port direction register DP1L bit 3
DP1L.DP1L2        2   Port direction register DP1L bit 2
DP1L.DP1L1        1   Port direction register DP1L bit 1
DP1L.DP1L0        0   Port direction register DP1L bit 0
DP1H             0xF106 P1H Direction Control Register
DP1H.DP1H7        7   Port direction register DP1H bit 7
DP1H.DP1H6        6   Port direction register DP1H bit 6
DP1H.DP1H5        5   Port direction register DP1H bit 5
DP1H.DP1H4        4   Port direction register DP1H bit 4
DP1H.DP1H3        3   Port direction register DP1H bit 3
DP1H.DP1H2        2   Port direction register DP1H bit 2
DP1H.DP1H1        1   Port direction register DP1H bit 1
DP1H.DP1H0        0   Port direction register DP1H bit 0
RP0H             0xF108 System Startup Configuration Register (read only)
RP0H.CLKCFG7      7   Clock Generation Mode Configuration bit 7
RP0H.CLKCFG6      6   Clock Generation Mode Configuration bit 6
RP0H.CLKCFG5      5   Clock Generation Mode Configuration bit 5
RP0H.SALSEL4      4   Segment Address Line Selection bit 4
RP0H.SALSEL3      3   Segment Address Line Selection bit 3
RP0H.CSSEL2       2   Chip Select Line Selection bit 2
RP0H.CSSEL1       1   Chip Select Line Selection bit 1
RP0H.WRC          0   Write Configuration
CC16IC           0xF160 CAPCOM Register 16 Interrupt Ctrl. Reg.
CC16IC.CC16IR     7
CC16IC.CC16IE     6
CC16IC.ILVL5      5
CC16IC.ILVL4      4
CC16IC.ILVL3      3
CC16IC.ILVL2      2
CC16IC.GLVL1      1
CC16IC.GLVL0      0
CC17IC           0xF162 CAPCOM Register 17 Interrupt Ctrl. Reg.
CC17IC.CC17IR     7
CC17IC.CC17IE     6
CC17IC.ILVL5      5
CC17IC.ILVL4      4
CC17IC.ILVL3      3
CC17IC.ILVL2      2
CC17IC.GLVL1      1
CC17IC.GLVL0      0
CC18IC           0xF164 CAPCOM Register 18 Interrupt Ctrl. Reg.
CC18IC.CC18IR     7
CC18IC.CC18IE     6
CC18IC.ILVL5      5
CC18IC.ILVL4      4
CC18IC.ILVL3      3
CC18IC.ILVL2      2
CC18IC.GLVL1      1
CC18IC.GLVL0      0
CC19IC           0xF166 CAPCOM Register 19 Interrupt Ctrl. Reg.
CC19IC.CC19IR     7
CC19IC.CC19IE     6
CC19IC.ILVL5      5
CC19IC.ILVL4      4
CC19IC.ILVL3      3
CC19IC.ILVL2      2
CC19IC.GLVL1      1
CC19IC.GLVL0      0
CC20IC           0xF168 CAPCOM Register 20 Interrupt Ctrl. Reg.
CC20IC.CC20IR     7
CC20IC.CC20IE     6
CC20IC.ILVL5      5
CC20IC.ILVL4      4
CC20IC.ILVL3      3
CC20IC.ILVL2      2
CC20IC.GLVL1      1
CC20IC.GLVL0      0
CC21IC           0xF16A CAPCOM Register 21 Interrupt Ctrl. Reg.
CC21IC.CC21IR     7
CC21IC.CC21IE     6
CC21IC.ILVL5      5
CC21IC.ILVL4      4
CC21IC.ILVL3      3
CC21IC.ILVL2      2
CC21IC.GLVL1      1
CC21IC.GLVL0      0
CC22IC           0xF16C CAPCOM Register 22 Interrupt Ctrl. Reg.
CC22IC.CC22IR     7
CC22IC.CC22IE     6
CC22IC.ILVL5      5
CC22IC.ILVL4      4
CC22IC.ILVL3      3
CC22IC.ILVL2      2
CC22IC.GLVL1      1
CC22IC.GLVL0      0
CC23IC           0xF16E CAPCOM Register 23 Interrupt Ctrl. Reg.
CC23IC.CC23IR     7
CC23IC.CC23IE     6
CC23IC.ILVL5      5
CC23IC.ILVL4      4
CC23IC.ILVL3      3
CC23IC.ILVL2      2
CC23IC.GLVL1      1
CC23IC.GLVL0      0
CC24IC           0xF170 CAPCOM Register 24 Interrupt Ctrl. Reg.
CC24IC.CC24IR     7
CC24IC.CC24IE     6
CC24IC.ILVL5      5
CC24IC.ILVL4      4
CC24IC.ILVL3      3
CC24IC.ILVL2      2
CC24IC.GLVL1      1
CC24IC.GLVL0      0
CC25IC           0xF172 CAPCOM Register 25 Interrupt Ctrl. Reg.
CC25IC.CC25IR     7
CC25IC.CC25IE     6
CC25IC.ILVL5      5
CC25IC.ILVL4      4
CC25IC.ILVL3      3
CC25IC.ILVL2      2
CC25IC.GLVL1      1
CC25IC.GLVL0      0
CC26IC           0xF174 CAPCOM Register 26 Interrupt Ctrl. Reg.
CC26IC.CC26IR     7
CC26IC.CC26IE     6
CC26IC.ILVL5      5
CC26IC.ILVL4      4
CC26IC.ILVL3      3
CC26IC.ILVL2      2
CC26IC.GLVL1      1
CC26IC.GLVL0      0
CC27IC           0xF176 CAPCOM Register 27 Interrupt Ctrl. Reg.
CC27IC.CC27IR     7
CC27IC.CC27IE     6
CC27IC.ILVL5      5
CC27IC.ILVL4      4
CC27IC.ILVL3      3
CC27IC.ILVL2      2
CC27IC.GLVL1      1
CC27IC.GLVL0      0
CC28IC           0xF178 CAPCOM Register 28 Interrupt Ctrl. Reg.
CC28IC.CC28IR     7
CC28IC.CC28IE     6
CC28IC.ILVL5      5
CC28IC.ILVL4      4
CC28IC.ILVL3      3
CC28IC.ILVL2      2
CC28IC.GLVL1      1
CC28IC.GLVL0      0
T7IC             0xF17A CAPCOM Timer 7 Interrupt Ctrl. Reg.
T7IC.T7IR         7
T7IC.T7IE         6
T7IC.ILVL5        5
T7IC.ILVL4        4
T7IC.ILVL3        3
T7IC.ILVL2        2
T7IC.GLVL1        1
T7IC.GLVL0        0
T8IC             0xF17C CAPCOM Timer 8 Interrupt Ctrl. Reg.
T8IC.T8IR         7
T8IC.T8IE         6
T8IC.ILVL5        5
T8IC.ILVL4        4
T8IC.ILVL3        3
T8IC.ILVL2        2
T8IC.GLVL1        1
T8IC.GLVL0        0
PWMIC            0xF17E PWM Module Interrupt Control Register
PWMIC.PWMIR       7
PWMIC.PWMIE       6
PWMIC.ILVL5       5
PWMIC.ILVL4       4
PWMIC.ILVL3       3
PWMIC.ILVL2       2
PWMIC.GLVL1       1
PWMIC.GLVL0       0
CC29IC           0xF184 CAPCOM Register 29 Interrupt Ctrl. Reg.
CC29IC.CC29IR     7
CC29IC.CC29IE     6
CC29IC.ILVL5      5
CC29IC.ILVL4      4
CC29IC.ILVL3      3
CC29IC.ILVL2      2
CC29IC.GLVL1      1
CC29IC.GLVL0      0
XP0IC            0xF186 CAN1 Interrupt Control Register
XP0IC.XP0IR       7
XP0IC.XP0IE       6
CC30IC           0xF18C CAPCOM Register 30 Interrupt Ctrl. Reg.
CC30IC.CC30IR     7
CC30IC.CC30IE     6
CC30IC.ILVL5      5
CC30IC.ILVL4      4
CC30IC.ILVL3      3
CC30IC.ILVL2      2
CC30IC.GLVL1      1
CC30IC.GLVL0      0
XP1IC            0xF18E Unassigned Interrupt Control Register
XP1IC.XP1IR       7
XP1IC.XP1IE       6
CC31IC           0xF194 CAPCOM Register 31 Interrupt Ctrl. Reg.
CC31IC.CC31IR     7
CC31IC.CC31IE     6
CC31IC.ILVL5      5
CC31IC.ILVL4      4
CC31IC.ILVL3      3
CC31IC.ILVL2      2
CC31IC.GLVL1      1
CC31IC.GLVL0      0
XP2IC            0xF196 Unassigned Interrupt Control Register
XP2IC.XP2IR       7
XP2IC.XP2IE       6
S0TBIC           0xF19C Serial Channel 0 Transmit Buffer Interrupt Control Register
S0TBIC.S0TBIR     7
S0TBIC.S0TBIE     6
S0TBIC.ILVL5      5
S0TBIC.ILVL4      4
S0TBIC.ILVL3      3
S0TBIC.ILVL2      2
S0TBIC.GLVL1      1
S0TBIC.GLVL0      0
XP3IC            0xF19E PLL/OWD Interrupt Control Register
XP3IC.XP3IR       7
XP3IC.XP3IE       6
EXICON           0xF1C0 External Interrupt Control Register
EXICON.EXI7ESH    15  External Interrupt 7H Edge Selection Field
EXICON.EXI7ESL    14  External Interrupt 7L Edge Selection Field
EXICON.EXI6ESH    13  External Interrupt 6H Edge Selection Field
EXICON.EXI6ESL    12  External Interrupt 6L Edge Selection Field
EXICON.EXI5ESH    11  External Interrupt 5H Edge Selection Field
EXICON.EXI5ESL    10  External Interrupt 5L Edge Selection Field
EXICON.EXI4ESH    9   External Interrupt 4H Edge Selection Field
EXICON.EXI4ESL    8   External Interrupt 4L Edge Selection Field
EXICON.EXI3ESH    7   External Interrupt 3H Edge Selection Field
EXICON.EXI3ESL    6   External Interrupt 3L Edge Selection Field
EXICON.EXI2ESH    5   External Interrupt 2H Edge Selection Field
EXICON.EXI2ESL    4   External Interrupt 2L Edge Selection Field
EXICON.EXI1ESH    3   External Interrupt 1H Edge Selection Field
EXICON.EXI1ESL    2   External Interrupt 1L Edge Selection Field
EXICON.EXI0ESH    1   External Interrupt 0H Edge Selection Field
EXICON.EXI0ESL    0   External Interrupt 0L Edge Selection Field
ODP2             0xF1C2 Port 2 Open Drain Control Register
ODP2.ODP2_15      15  Port 2 Open Drain control register bit 15
ODP2.ODP2_14      14  Port 2 Open Drain control register bit 14
ODP2.ODP2_13      13  Port 2 Open Drain control register bit 13
ODP2.ODP2_12      12  Port 2 Open Drain control register bit 12
ODP2.ODP2_11      11  Port 2 Open Drain control register bit 11
ODP2.ODP2_10      10  Port 2 Open Drain control register bit 10
ODP2.ODP2_9       9   Port 2 Open Drain control register bit 9 
ODP2.ODP2_8       8   Port 2 Open Drain control register bit 8 
ODP2.ODP2_7       7   Port 2 Open Drain control register bit 7 
ODP2.ODP2_6       6   Port 2 Open Drain control register bit 6 
ODP2.ODP2_5       5   Port 2 Open Drain control register bit 5 
ODP2.ODP2_4       4   Port 2 Open Drain control register bit 4 
ODP2.ODP2_3       3   Port 2 Open Drain control register bit 3 
ODP2.ODP2_2       2   Port 2 Open Drain control register bit 2 
ODP2.ODP2_1       1   Port 2 Open Drain control register bit 1 
ODP2.ODP2_0       0   Port 2 Open Drain control register bit 0 
PICON            0xF1C4   Port Input Control Reg.
PICON.P8LIN       7   Port 8 Low Byte Input Level Selection
PICON.P7LIN       6   Port 7 Low Byte Input Level Selection
PICON.P6LIN       5   Port 6 Low Byte Input Level Selection
PICON.P4LIN       4   Port 4 Low Byte Input Level Selection
PICON.P3HIN       3   Port 3 High Byte Input Level Selection
PICON.P3LIN       2   Port 3 Low Byte Input Level Selection
PICON.P2HIN       1   Port 2 High Byte Input Level Selection
PICON.P2LIN       0   Port 2 Low Byte Input Level Selection
ODP3             0xF1C6 Port 3 Open Drain Control Register
ODP3.ODP3_13      13  Port 3 Open Drain control register bit 13
ODP3.ODP3_11      11  Port 3 Open Drain control register bit 11
ODP3.ODP3_10      10  Port 3 Open Drain control register bit 10
ODP3.ODP3_9       9   Port 3 Open Drain control register bit 9 
ODP3.ODP3_8       8   Port 3 Open Drain control register bit 8 
ODP3.ODP3_7       7   Port 3 Open Drain control register bit 7 
ODP3.ODP3_6       6   Port 3 Open Drain control register bit 6 
ODP3.ODP3_5       5   Port 3 Open Drain control register bit 5 
ODP3.ODP3_4       4   Port 3 Open Drain control register bit 4 
ODP3.ODP3_3       3   Port 3 Open Drain control register bit 3 
ODP3.ODP3_2       2   Port 3 Open Drain control register bit 2 
ODP3.ODP3_1       1   Port 3 Open Drain control register bit 1 
ODP3.ODP3_0       0   Port 3 Open Drain control register bit 0 
ODP4             0xF1CA Port 4 Open Drain Control Register
ODP4.ODP4_7       7   Port 4 Open Drain control register bit 7
ODP4.ODP4_6       6   Port 4 Open Drain control register bit 6
ODP4.ODP4_5       5   Port 4 Open Drain control register bit 5
ODP4.ODP4_4       4   Port 4 Open Drain control register bit 4
ODP4.ODP4_3       3   Port 4 Open Drain control register bit 3
ODP4.ODP4_2       2   Port 4 Open Drain control register bit 2
ODP4.ODP4_1       1   Port 4 Open Drain control register bit 1
ODP4.ODP4_0       0   Port 4 Open Drain control register bit 0
ODP6             0xF1CE Port 6 Open Drain Control Register
ODP6.ODP6_7       7   Port 6 Open Drain control register bit 7
ODP6.ODP6_6       6   Port 6 Open Drain control register bit 6
ODP6.ODP6_5       5   Port 6 Open Drain control register bit 5
ODP6.ODP6_4       4   Port 6 Open Drain control register bit 4
ODP6.ODP6_3       3   Port 6 Open Drain control register bit 3
ODP6.ODP6_2       2   Port 6 Open Drain control register bit 2
ODP6.ODP6_1       1   Port 6 Open Drain control register bit 1
ODP6.ODP6_0       0   Port 6 Open Drain control register bit 0
SYSCON2          0xF1D0 CPU System Configuration Register 2
ODP7             0xF1D2 Port 7 Open Drain Control Register
ODP7.ODP7_7       7   Port 7 Open Drain control register bit 7
ODP7.ODP7_6       6   Port 7 Open Drain control register bit 6
ODP7.ODP7_5       5   Port 7 Open Drain control register bit 5
ODP7.ODP7_4       4   Port 7 Open Drain control register bit 4
ODP7.ODP7_3       3   Port 7 Open Drain control register bit 3
ODP7.ODP7_2       2   Port 7 Open Drain control register bit 2
ODP7.ODP7_1       1   Port 7 Open Drain control register bit 1
ODP7.ODP7_0       0   Port 7 Open Drain control register bit 0
SYSCON3          0xF1D4 CPU System Configuration Register 3
ODP8             0xF1D6 Port 8 Open Drain Control Register
ODP8.ODP8_7       7   Port 8 Open Drain control register bit 7
ODP8.ODP8_6       6   Port 8 Open Drain control register bit 6
ODP8.ODP8_5       5   Port 8 Open Drain control register bit 5
ODP8.ODP8_4       4   Port 8 Open Drain control register bit 4
ODP8.ODP8_3       3   Port 8 Open Drain control register bit 3
ODP8.ODP8_2       2   Port 8 Open Drain control register bit 2
ODP8.ODP8_1       1   Port 8 Open Drain control register bit 1
ODP8.ODP8_0       0   Port 8 Open Drain control register bit 0
EXISEL           0xF1DA External Interrupt Source Select Register
EXISEL.EXI7SSH    15  External Interrupt 7H Source Selection Field
EXISEL.EXI7SSL    14  External Interrupt 7L Source Selection Field
EXISEL.EXI6SSH    13  External Interrupt 6H Source Selection Field
EXISEL.EXI6SSL    12  External Interrupt 6L Source Selection Field
EXISEL.EXI5SSH    11  External Interrupt 5H Source Selection Field
EXISEL.EXI5SSL    10  External Interrupt 5L Source Selection Field
EXISEL.EXI4SSH    9   External Interrupt 4H Source Selection Field
EXISEL.EXI4SSL    8   External Interrupt 4L Source Selection Field
EXISEL.EXI3SSH    7   External Interrupt 3H Source Selection Field
EXISEL.EXI3SSL    6   External Interrupt 3L Source Selection Field
EXISEL.EXI2SSH    5   External Interrupt 2H Source Selection Field
EXISEL.EXI2SSL    4   External Interrupt 2L Source Selection Field
EXISEL.EXI1SSH    3   External Interrupt 1H Source Selection Field
EXISEL.EXI1SSL    2   External Interrupt 1L Source Selection Field
EXISEL.EXI0SSH    1   External Interrupt 0H Source Selection Field
EXISEL.EXI0SSL    0   External Interrupt 0L Source Selection Field
SYSCON1          0xF1DC CPU System Configuration Register 1
ISNC             0xF1DE Interrupt Subnode Control Register
ISNC.PLLIE        3
ISNC.PLLIR        2
ISNC.RTCIE        1
ISNC.RTCIR        0
RSTCON           0xF1E0 Reset Control Register

; SFR
DPP0             0xFE00 CPU Data Page Pointer 0 Register (10 bits)
DPP0.DPP0PN9      9   Data Page Number of DPP0 bit 9
DPP0.DPP0PN8      8   Data Page Number of DPP0 bit 8
DPP0.DPP0PN7      7   Data Page Number of DPP0 bit 7
DPP0.DPP0PN6      6   Data Page Number of DPP0 bit 6
DPP0.DPP0PN5      5   Data Page Number of DPP0 bit 5
DPP0.DPP0PN4      4   Data Page Number of DPP0 bit 4
DPP0.DPP0PN3      3   Data Page Number of DPP0 bit 3
DPP0.DPP0PN2      2   Data Page Number of DPP0 bit 2
DPP0.DPP0PN1      1   Data Page Number of DPP0 bit 1
DPP0.DPP0PN0      0   Data Page Number of DPP0 bit 0
DPP1             0xFE02 CPU Data Page Pointer 1 Register (10 bits)
DPP1.DPP1PN9      9   Data Page Number of DPP1 bit 9
DPP1.DPP1PN8      8   Data Page Number of DPP1 bit 8
DPP1.DPP1PN7      7   Data Page Number of DPP1 bit 7
DPP1.DPP1PN6      6   Data Page Number of DPP1 bit 6
DPP1.DPP1PN5      5   Data Page Number of DPP1 bit 5
DPP1.DPP1PN4      4   Data Page Number of DPP1 bit 4
DPP1.DPP1PN3      3   Data Page Number of DPP1 bit 3
DPP1.DPP1PN2      2   Data Page Number of DPP1 bit 2
DPP1.DPP1PN1      1   Data Page Number of DPP1 bit 1
DPP1.DPP1PN0      0   Data Page Number of DPP1 bit 0
DPP2             0xFE04 CPU Data Page Pointer 2 Register (10 bits)
DPP2.DPP2PN9      9   Data Page Number of DPP2 bit 9
DPP2.DPP2PN8      8   Data Page Number of DPP2 bit 8
DPP2.DPP2PN7      7   Data Page Number of DPP2 bit 7
DPP2.DPP2PN6      6   Data Page Number of DPP2 bit 6
DPP2.DPP2PN5      5   Data Page Number of DPP2 bit 5
DPP2.DPP2PN4      4   Data Page Number of DPP2 bit 4
DPP2.DPP2PN3      3   Data Page Number of DPP2 bit 3
DPP2.DPP2PN2      2   Data Page Number of DPP2 bit 2
DPP2.DPP2PN1      1   Data Page Number of DPP2 bit 1
DPP2.DPP2PN0      0   Data Page Number of DPP2 bit 0
DPP3             0xFE06 CPU Data Page Pointer 3 Register (10 bits)
DPP3.DPP3PN9      9   Data Page Number of DPP3 bit 9
DPP3.DPP3PN8      8   Data Page Number of DPP3 bit 8
DPP3.DPP3PN7      7   Data Page Number of DPP3 bit 7
DPP3.DPP3PN6      6   Data Page Number of DPP3 bit 6
DPP3.DPP3PN5      5   Data Page Number of DPP3 bit 5
DPP3.DPP3PN4      4   Data Page Number of DPP3 bit 4
DPP3.DPP3PN3      3   Data Page Number of DPP3 bit 3
DPP3.DPP3PN2      2   Data Page Number of DPP3 bit 2
DPP3.DPP3PN1      1   Data Page Number of DPP3 bit 1
DPP3.DPP3PN0      0   Data Page Number of DPP3 bit 0
CSP              0xFE08 CPU Code Segment Pointer Register (8 bits, not directly writeable)
CSP.SEGNR7        7   Segment Number 7
CSP.SEGNR6        6   Segment Number 6
CSP.SEGNR5        5   Segment Number 5
CSP.SEGNR4        4   Segment Number 4
CSP.SEGNR3        3   Segment Number 3
CSP.SEGNR2        2   Segment Number 2
CSP.SEGNR1        1   Segment Number 1
CSP.SEGNR0        0   Segment Number 0
MDH              0xFE0C   Multiply/Divide High Reg.
MDH.MDH15         15
MDH.MDH14         14
MDH.MDH13         13
MDH.MDH12         12
MDH.MDH11         11
MDH.MDH10         10
MDH.MDH9          9
MDH.MDH8          8
MDH.MDH7          7
MDH.MDH6          6
MDH.MDH5          5
MDH.MDH4          4
MDH.MDH3          3
MDH.MDH2          2
MDH.MDH1          1
MDH.MDH0          0
MDL              0xFE0E   Multiply/Divide Low Reg.
MDL.MDL15         15
MDL.MDL14         14
MDL.MDL13         13
MDL.MDL12         12
MDL.MDL11         11
MDL.MDL10         10
MDL.MDL9          9
MDL.MDL8          8
MDL.MDL7          7
MDL.MDL6          6
MDL.MDL5          5
MDL.MDL4          4
MDL.MDL3          3
MDL.MDL2          2
MDL.MDL1          1
MDL.MDL0          0
CP               0xFE10 CPU Context Pointer Register
CP.CP11           11  Modifiable portion of register CP bit 11
CP.CP10           10  Modifiable portion of register CP bit 10
CP.CP9            9   Modifiable portion of register CP bit 9 
CP.CP8            8   Modifiable portion of register CP bit 8 
CP.CP7            7   Modifiable portion of register CP bit 7 
CP.CP6            6   Modifiable portion of register CP bit 6 
CP.CP5            5   Modifiable portion of register CP bit 5 
CP.CP4            4   Modifiable portion of register CP bit 4 
CP.CP3            3   Modifiable portion of register CP bit 3 
CP.CP2            2   Modifiable portion of register CP bit 2 
CP.CP1            1   Modifiable portion of register CP bit 1 
SP               0xFE12 CPU System Stack Pointer Register
SP.SP11           11  Modifiable portion of register SP bit 11
SP.SP10           10  Modifiable portion of register SP bit 10
SP.SP9            9   Modifiable portion of register SP bit 9 
SP.SP8            8   Modifiable portion of register SP bit 8 
SP.SP7            7   Modifiable portion of register SP bit 7 
SP.SP6            6   Modifiable portion of register SP bit 6 
SP.SP5            5   Modifiable portion of register SP bit 5 
SP.SP4            4   Modifiable portion of register SP bit 4 
SP.SP3            3   Modifiable portion of register SP bit 3 
SP.SP2            2   Modifiable portion of register SP bit 2 
SP.SP1            1   Modifiable portion of register SP bit 1 
STKOV            0xFE14 CPU Stack Overflow Pointer Register
STKOV.STKOV11     11  Modifiable portion of register STKOV bit 11
STKOV.STKOV10     10  Modifiable portion of register STKOV bit 10
STKOV.STKOV9      9   Modifiable portion of register STKOV bit 9 
STKOV.STKOV8      8   Modifiable portion of register STKOV bit 8 
STKOV.STKOV7      7   Modifiable portion of register STKOV bit 7 
STKOV.STKOV6      6   Modifiable portion of register STKOV bit 6 
STKOV.STKOV5      5   Modifiable portion of register STKOV bit 5 
STKOV.STKOV4      4   Modifiable portion of register STKOV bit 4 
STKOV.STKOV3      3   Modifiable portion of register STKOV bit 3 
STKOV.STKOV2      2   Modifiable portion of register STKOV bit 2 
STKOV.STKOV1      1   Modifiable portion of register STKOV bit 1 
STKUN            0xFE16 CPU Stack Underflow Pointer Register
STKUN.STKUN11     11  Modifiable portion of register STKUN bit 11
STKUN.STKUN10     10  Modifiable portion of register STKUN bit 10
STKUN.STKUN9      9   Modifiable portion of register STKUN bit 9 
STKUN.STKUN8      8   Modifiable portion of register STKUN bit 8 
STKUN.STKUN7      7   Modifiable portion of register STKUN bit 7 
STKUN.STKUN6      6   Modifiable portion of register STKUN bit 6 
STKUN.STKUN5      5   Modifiable portion of register STKUN bit 5 
STKUN.STKUN4      4   Modifiable portion of register STKUN bit 4 
STKUN.STKUN3      3   Modifiable portion of register STKUN bit 3 
STKUN.STKUN2      2   Modifiable portion of register STKUN bit 2 
STKUN.STKUN1      1   Modifiable portion of register STKUN bit 1 
ADDRSEL1         0xFE18 Address Select Register 1
ADDRSEL1.RGSAD15  15  Range Start Address bit 15
ADDRSEL1.RGSAD14  14  Range Start Address bit 14
ADDRSEL1.RGSAD13  13  Range Start Address bit 13
ADDRSEL1.RGSAD12  12  Range Start Address bit 12
ADDRSEL1.RGSAD11  11  Range Start Address bit 11
ADDRSEL1.RGSAD10  10  Range Start Address bit 10
ADDRSEL1.RGSAD9   9   Range Start Address bit 9 
ADDRSEL1.RGSAD8   8   Range Start Address bit 8 
ADDRSEL1.RGSAD7   7   Range Start Address bit 7 
ADDRSEL1.RGSAD6   6   Range Start Address bit 6 
ADDRSEL1.RGSAD5   5   Range Start Address bit 5 
ADDRSEL1.RGSAD4   4   Range Start Address bit 4 
ADDRSEL1.RGSZ3    3   Range Size Selection bit 3
ADDRSEL1.RGSZ2    2   Range Size Selection bit 2
ADDRSEL1.RGSZ1    1   Range Size Selection bit 1
ADDRSEL1.RGSZ0    0   Range Size Selection bit 0
ADDRSEL2         0xFE1A Address Select Register 2
ADDRSEL2.RGSAD15  15  Range Start Address bit 15
ADDRSEL2.RGSAD14  14  Range Start Address bit 14
ADDRSEL2.RGSAD13  13  Range Start Address bit 13
ADDRSEL2.RGSAD12  12  Range Start Address bit 12
ADDRSEL2.RGSAD11  11  Range Start Address bit 11
ADDRSEL2.RGSAD10  10  Range Start Address bit 10
ADDRSEL2.RGSAD9   9   Range Start Address bit 9 
ADDRSEL2.RGSAD8   8   Range Start Address bit 8 
ADDRSEL2.RGSAD7   7   Range Start Address bit 7 
ADDRSEL2.RGSAD6   6   Range Start Address bit 6 
ADDRSEL2.RGSAD5   5   Range Start Address bit 5 
ADDRSEL2.RGSAD4   4   Range Start Address bit 4 
ADDRSEL2.RGSZ3    3   Range Size Selection bit 3
ADDRSEL2.RGSZ2    2   Range Size Selection bit 2
ADDRSEL2.RGSZ1    1   Range Size Selection bit 1
ADDRSEL2.RGSZ0    0   Range Size Selection bit 0
ADDRSEL3         0xFE1C Address Select Register 3
ADDRSEL3.RGSAD15  15  Range Start Address bit 15
ADDRSEL3.RGSAD14  14  Range Start Address bit 14
ADDRSEL3.RGSAD13  13  Range Start Address bit 13
ADDRSEL3.RGSAD12  12  Range Start Address bit 12
ADDRSEL3.RGSAD11  11  Range Start Address bit 11
ADDRSEL3.RGSAD10  10  Range Start Address bit 10
ADDRSEL3.RGSAD9   9   Range Start Address bit 9 
ADDRSEL3.RGSAD8   8   Range Start Address bit 8 
ADDRSEL3.RGSAD7   7   Range Start Address bit 7 
ADDRSEL3.RGSAD6   6   Range Start Address bit 6 
ADDRSEL3.RGSAD5   5   Range Start Address bit 5 
ADDRSEL3.RGSAD4   4   Range Start Address bit 4 
ADDRSEL3.RGSZ3    3   Range Size Selection bit 3
ADDRSEL3.RGSZ2    2   Range Size Selection bit 2
ADDRSEL3.RGSZ1    1   Range Size Selection bit 1
ADDRSEL3.RGSZ0    0   Range Size Selection bit 0
ADDRSEL4         0xFE1E Address Select Register 4
ADDRSEL4.RGSAD15  15  Range Start Address bit 15
ADDRSEL4.RGSAD14  14  Range Start Address bit 14
ADDRSEL4.RGSAD13  13  Range Start Address bit 13
ADDRSEL4.RGSAD12  12  Range Start Address bit 12
ADDRSEL4.RGSAD11  11  Range Start Address bit 11
ADDRSEL4.RGSAD10  10  Range Start Address bit 10
ADDRSEL4.RGSAD9   9   Range Start Address bit 9 
ADDRSEL4.RGSAD8   8   Range Start Address bit 8 
ADDRSEL4.RGSAD7   7   Range Start Address bit 7 
ADDRSEL4.RGSAD6   6   Range Start Address bit 6 
ADDRSEL4.RGSAD5   5   Range Start Address bit 5 
ADDRSEL4.RGSAD4   4   Range Start Address bit 4 
ADDRSEL4.RGSZ3    3   Range Size Selection bit 3
ADDRSEL4.RGSZ2    2   Range Size Selection bit 2
ADDRSEL4.RGSZ1    1   Range Size Selection bit 1
ADDRSEL4.RGSZ0    0   Range Size Selection bit 0
PW0              0xFE30 PWM Module Pulse Width Register 0
PW1              0xFE32 PWM Module Pulse Width Register 1
PW2              0xFE34 PWM Module Pulse Width Register 2
PW3              0xFE36 PWM Module Pulse Width Register 3
T2               0xFE40 GPT1 Timer 2 Register
T3               0xFE42 GPT1 Timer 3 Register
T4               0xFE44 GPT1 Timer 4 Register
T5               0xFE46 GPT2 Timer 5 Register
T6               0xFE48 GPT2 Timer 6 Register
CAPREL           0xFE4A GPT2 Capture/Reload Register
T0               0xFE50 CAPCOM Timer 0 Register
T1               0xFE52 CAPCOM Timer 1 Register
T0REL            0xFE54 CAPCOM Timer 0 Reload Register
T1REL            0xFE56 CAPCOM Timer 1 Reload Register
CC16             0xFE60 CAPCOM Register 16
CC17             0xFE62 CAPCOM Register 17
CC18             0xFE64 CAPCOM Register 18
CC19             0xFE66 CAPCOM Register 19
CC20             0xFE68 CAPCOM Register 20
CC21             0xFE6A CAPCOM Register 21
CC22             0xFE6C CAPCOM Register 22
CC23             0xFE6E CAPCOM Register 23
CC24             0xFE70 CAPCOM Register 24
CC25             0xFE72 CAPCOM Register 25
CC26             0xFE74 CAPCOM Register 26
CC27             0xFE76 CAPCOM Register 27
CC28             0xFE78 CAPCOM Register 28
CC29             0xFE7A CAPCOM Register 29
CC30             0xFE7C CAPCOM Register 30
CC31             0xFE7E CAPCOM Register 31
CC0              0xFE80 CAPCOM Register 0
CC1              0xFE82 CAPCOM Register 1
CC2              0xFE84 CAPCOM Register 2
CC3              0xFE86 CAPCOM Register 3
CC4              0xFE88 CAPCOM Register 4
CC5              0xFE8A CAPCOM Register 5
CC6              0xFE8C CAPCOM Register 6
CC7              0xFE8E CAPCOM Register 7
CC8              0xFE90 CAPCOM Register 8
CC9              0xFE92 CAPCOM Register 9
CC10             0xFE94 CAPCOM Register 10
CC11             0xFE96 CAPCOM Register 11
CC12             0xFE98 CAPCOM Register 12
CC13             0xFE9A CAPCOM Register 13
CC14             0xFE9C CAPCOM Register 14
CC15             0xFE9E CAPCOM Register 15
ADDAT            0xFEA0 A/D Converter Result Register
ADDAT.CHNR15      15  Channel Number bit 15      
ADDAT.CHNR14      14  Channel Number bit 14      
ADDAT.CHNR13      13  Channel Number bit 13      
ADDAT.CHNR12      12  Channel Number bit 12      
ADDAT.CHX         11  Channel Extension Indicator
ADDAT.ADRES9      9   A/D Conversion Result bit 9
ADDAT.ADRES8      8   A/D Conversion Result bit 8
ADDAT.ADRES7      7   A/D Conversion Result bit 7
ADDAT.ADRES6      6   A/D Conversion Result bit 6
ADDAT.ADRES5      5   A/D Conversion Result bit 5
ADDAT.ADRES4      4   A/D Conversion Result bit 4
ADDAT.ADRES3      3   A/D Conversion Result bit 3
ADDAT.ADRES2      2   A/D Conversion Result bit 2
ADDAT.ADRES1      1   A/D Conversion Result bit 1
ADDAT.ADRES0      0   A/D Conversion Result bit 0
P1DIDIS          0xFEA4 PORT1 Digital Input Disable Register
P1DIDIS.P1D_7     7   Port P1L Bit 7 Digital Input Control
P1DIDIS.P1D_6     6   Port P1L Bit 6 Digital Input Control
P1DIDIS.P1D_5     5   Port P1L Bit 5 Digital Input Control
P1DIDIS.P1D_4     4   Port P1L Bit 4 Digital Input Control
P1DIDIS.P1D_3     3   Port P1L Bit 3 Digital Input Control
P1DIDIS.P1D_2     2   Port P1L Bit 2 Digital Input Control
P1DIDIS.P1D_1     1   Port P1L Bit 1 Digital Input Control
P1DIDIS.P1D_0     0   Port P1L Bit 0 Digital Input Control
WDT              0xFEAE Watchdog Timer Register (read only)
S0TBUF           0xFEB0 Serial Channel 0 Transmit Buffer Register
S0RBUF           0xFEB2 Serial Channel 0 Receive Buffer Register (read only)
S0BG             0xFEB4 Serial Channel 0 Baud Rate Generator Reload Register
PECC0            0xFEC0 PEC Channel 0 Control Register
PECC0.INC10       10  Increment Control bit 10
PECC0.INC9        9   Increment Control bit 9 
PECC0.BWT         8   Byte/Word Transfer Selection
PECC0.COUNT7      7   PEC Transfer Count bit 7
PECC0.COUNT6      6   PEC Transfer Count bit 6
PECC0.COUNT5      5   PEC Transfer Count bit 5
PECC0.COUNT4      4   PEC Transfer Count bit 4
PECC0.COUNT3      3   PEC Transfer Count bit 3
PECC0.COUNT2      2   PEC Transfer Count bit 2
PECC0.COUNT1      1   PEC Transfer Count bit 1
PECC0.COUNT0      0   PEC Transfer Count bit 0
PECC1            0xFEC2 PEC Channel 1 Control Register
PECC1.INC10       10  Increment Control bit 10    
PECC1.INC9        9   Increment Control bit 9     
PECC1.BWT         8   Byte/Word Transfer Selection
PECC1.COUNT7      7   PEC Transfer Count bit 7    
PECC1.COUNT6      6   PEC Transfer Count bit 6    
PECC1.COUNT5      5   PEC Transfer Count bit 5    
PECC1.COUNT4      4   PEC Transfer Count bit 4    
PECC1.COUNT3      3   PEC Transfer Count bit 3    
PECC1.COUNT2      2   PEC Transfer Count bit 2    
PECC1.COUNT1      1   PEC Transfer Count bit 1    
PECC1.COUNT0      0   PEC Transfer Count bit 0    
PECC2            0xFEC4 PEC Channel 2 Control Register
PECC2.INC10       10  Increment Control bit 10    
PECC2.INC9        9   Increment Control bit 9     
PECC2.BWT         8   Byte/Word Transfer Selection
PECC2.COUNT7      7   PEC Transfer Count bit 7    
PECC2.COUNT6      6   PEC Transfer Count bit 6    
PECC2.COUNT5      5   PEC Transfer Count bit 5    
PECC2.COUNT4      4   PEC Transfer Count bit 4    
PECC2.COUNT3      3   PEC Transfer Count bit 3    
PECC2.COUNT2      2   PEC Transfer Count bit 2    
PECC2.COUNT1      1   PEC Transfer Count bit 1    
PECC2.COUNT0      0   PEC Transfer Count bit 0    
PECC3            0xFEC6 PEC Channel 3 Control Register
PECC3.INC10       10  Increment Control bit 10    
PECC3.INC9        9   Increment Control bit 9     
PECC3.BWT         8   Byte/Word Transfer Selection
PECC3.COUNT7      7   PEC Transfer Count bit 7    
PECC3.COUNT6      6   PEC Transfer Count bit 6    
PECC3.COUNT5      5   PEC Transfer Count bit 5    
PECC3.COUNT4      4   PEC Transfer Count bit 4    
PECC3.COUNT3      3   PEC Transfer Count bit 3    
PECC3.COUNT2      2   PEC Transfer Count bit 2    
PECC3.COUNT1      1   PEC Transfer Count bit 1    
PECC3.COUNT0      0   PEC Transfer Count bit 0    
PECC4            0xFEC8 PEC Channel 4 Control Register
PECC4.INC10       10  Increment Control bit 10    
PECC4.INC9        9   Increment Control bit 9     
PECC4.BWT         8   Byte/Word Transfer Selection
PECC4.COUNT7      7   PEC Transfer Count bit 7    
PECC4.COUNT6      6   PEC Transfer Count bit 6    
PECC4.COUNT5      5   PEC Transfer Count bit 5    
PECC4.COUNT4      4   PEC Transfer Count bit 4    
PECC4.COUNT3      3   PEC Transfer Count bit 3    
PECC4.COUNT2      2   PEC Transfer Count bit 2    
PECC4.COUNT1      1   PEC Transfer Count bit 1    
PECC4.COUNT0      0   PEC Transfer Count bit 0    
PECC5            0xFECA PEC Channel 5 Control Register
PECC5.INC10       10  Increment Control bit 10    
PECC5.INC9        9   Increment Control bit 9     
PECC5.BWT         8   Byte/Word Transfer Selection
PECC5.COUNT7      7   PEC Transfer Count bit 7    
PECC5.COUNT6      6   PEC Transfer Count bit 6    
PECC5.COUNT5      5   PEC Transfer Count bit 5    
PECC5.COUNT4      4   PEC Transfer Count bit 4    
PECC5.COUNT3      3   PEC Transfer Count bit 3    
PECC5.COUNT2      2   PEC Transfer Count bit 2    
PECC5.COUNT1      1   PEC Transfer Count bit 1    
PECC5.COUNT0      0   PEC Transfer Count bit 0    
PECC6            0xFECC PEC Channel 6 Control Register
PECC6.INC10       10  Increment Control bit 10    
PECC6.INC9        9   Increment Control bit 9     
PECC6.BWT         8   Byte/Word Transfer Selection
PECC6.COUNT7      7   PEC Transfer Count bit 7    
PECC6.COUNT6      6   PEC Transfer Count bit 6    
PECC6.COUNT5      5   PEC Transfer Count bit 5    
PECC6.COUNT4      4   PEC Transfer Count bit 4    
PECC6.COUNT3      3   PEC Transfer Count bit 3    
PECC6.COUNT2      2   PEC Transfer Count bit 2    
PECC6.COUNT1      1   PEC Transfer Count bit 1    
PECC6.COUNT0      0   PEC Transfer Count bit 0    
PECC7            0xFECE PEC Channel 7 Control Register
PECC7.INC10       10  Increment Control bit 10    
PECC7.INC9        9   Increment Control bit 9     
PECC7.BWT         8   Byte/Word Transfer Selection
PECC7.COUNT7      7   PEC Transfer Count bit 7    
PECC7.COUNT6      6   PEC Transfer Count bit 6    
PECC7.COUNT5      5   PEC Transfer Count bit 5    
PECC7.COUNT4      4   PEC Transfer Count bit 4    
PECC7.COUNT3      3   PEC Transfer Count bit 3    
PECC7.COUNT2      2   PEC Transfer Count bit 2    
PECC7.COUNT1      1   PEC Transfer Count bit 1    
PECC7.COUNT0      0   PEC Transfer Count bit 0    
P0L              0xFF00 Port 0 Low Register (Lower half of PORT0)
P0L.P0L7          7   Port data register P0L bit 7
P0L.P0L6          6   Port data register P0L bit 6
P0L.P0L5          5   Port data register P0L bit 5
P0L.P0L4          4   Port data register P0L bit 4
P0L.P0L3          3   Port data register P0L bit 3
P0L.P0L2          2   Port data register P0L bit 2
P0L.P0L1          1   Port data register P0L bit 1
P0L.P0L0          0   Port data register P0L bit 0
P0H              0xFF02 Port 0 High Register (Upper half of PORT0)
P0H.P0H7          7   Port data register P0H bit 7
P0H.P0H6          6   Port data register P0H bit 6
P0H.P0H5          5   Port data register P0H bit 5
P0H.P0H4          4   Port data register P0H bit 4
P0H.P0H3          3   Port data register P0H bit 3
P0H.P0H2          2   Port data register P0H bit 2
P0H.P0H1          1   Port data register P0H bit 1
P0H.P0H0          0   Port data register P0H bit 0
P1L              0xFF04 Port 1 Low Register (Lower half of PORT1)
P1L.P1L7          7   Port data register P1L bit 7
P1L.P1L6          6   Port data register P1L bit 6
P1L.P1L5          5   Port data register P1L bit 5
P1L.P1L4          4   Port data register P1L bit 4
P1L.P1L3          3   Port data register P1L bit 3
P1L.P1L2          2   Port data register P1L bit 2
P1L.P1L1          1   Port data register P1L bit 1
P1L.P1L0          0   Port data register P1L bit 0
P1H              0xFF06 Port 1 High Register (Upper half of PORT1)
P1H.P1H7          7   Port data register P1H bit 7
P1H.P1H6          6   Port data register P1H bit 6
P1H.P1H5          5   Port data register P1H bit 5
P1H.P1H4          4   Port data register P1H bit 4
P1H.P1H3          3   Port data register P1H bit 3
P1H.P1H2          2   Port data register P1H bit 2
P1H.P1H1          1   Port data register P1H bit 1
P1H.P1H0          0   Port data register P1H bit 0
BUSCON0          0xFF0C Bus Configuration Register 0
BUSCON0.CSWEN0    15  Write Chip Select Enable
BUSCON0.CSREN0    14  Read Chip Select Enable
BUSCON0.RDYEN0    12  READY Input Enable
BUSCON0.BSWC0     11  BUSCON Switch Control
BUSCON0.BUSACT0   10  Bus Active Control
BUSCON0.ALECTL0   9   ALE Lengthening Control
BUSCON0.EWEN0     8   Early Write Enable
BUSCON0.BTYP7     7   External Bus Configuration bit 7
BUSCON0.BTYP6     6   External Bus Configuration bit 6
BUSCON0.MTTC0     5   Memory Tristate Time Control
BUSCON0.RWDC0     4   Read/Write Delay Control for BUSCON
BUSCON0.MCTC3     3   Memory Cycle Time Control bit 3
BUSCON0.MCTC2     2   Memory Cycle Time Control bit 2
BUSCON0.MCTC1     1   Memory Cycle Time Control bit 1
BUSCON0.MCTC0     0   Memory Cycle Time Control bit 0
MDC              0xFF0E CPU Multiply Divide Control Register
MDC.MDRIU         4   Multiply/Divide Register In Use
PSW              0xFF10 CPU Program Status Word
PSW.ILVL15        15  ILVL15 - Interrupt and EBC Control Fields
PSW.ILVL14        14  ILVL14 - Interrupt and EBC Control Fields
PSW.ILVL13        13  ILVL13 - Interrupt and EBC Control Fields
PSW.ILVL12        12  ILVL12 - Interrupt and EBC Control Fields
PSW.IEN           11  IEN    - Interrupt and EBC Control Fields
PSW.HLDEN         10  HLDEN  - Interrupt and EBC Control Fields
PSW.USR0          6   User General Purpose Flag
PSW.MULIP         5   Multiplication/Division In Progress
PSW.E             4   End of Table Flag
PSW.Z             3   Zero Flag
PSW.V             2   Overflow Result
PSW.C             1   Carry Flag
PSW.N             0   Negative Result
SYSCON               0xFF12 CPU System Configuration Register
SYSCON.STKSZ15        15  System Stack Size bit 15
SYSCON.STKSZ14        14  System Stack Size bit 14
SYSCON.STKSZ13        13  System Stack Size bit 13
SYSCON.ROMS1          12  Internal ROM Mapping
SYSCON.SGTDIS         11  Segmentation Disable/Enable Control
SYSCON.ROMEN          10  Internal ROM Enable
SYSCON.BYTDIS         9   Disable/Enable Control for Pin BHE
SYSCON.CLKEN          8   System Clock Output Enable
SYSCON.WRCFG          7   Write Configuration Control
SYSCON.CSCFG          6   Chip Select Configuration Control
SYSCON.OWDDIS         4   Oscillator Watchdog Disable Bit
SYSCON.BDRSTEN        3   Bidirectional Reset Enable Bit
SYSCON.XPEN           2   XBUS Peripheral Enable Bit
SYSCON.VISIBLE        1   Visible Mode Control
SYSCON.XPER_SHARE     0   XBUS Peripheral Share Mode Control
BUSCON1          0xFF14 Bus Configuration Register 1
BUSCON1.CSWEN1    15  Write Chip Select Enable           
BUSCON1.CSREN1    14  Read Chip Select Enable            
BUSCON1.RDYEN1    12  READY Input Enable                 
BUSCON1.BSWC1     11  BUSCON Switch Control
BUSCON1.BUSACT1   10  Bus Active Control                 
BUSCON1.ALECTL1   9   ALE Lengthening Control            
BUSCON1.EWEN1     8   Early Write Enable
BUSCON1.BTYP7     7   External Bus Configuration bit 7   
BUSCON1.BTYP6     6   External Bus Configuration bit 6   
BUSCON1.MTTC1     5   Memory Tristate Time Control       
BUSCON1.RWDC1     4   Read/Write Delay Control for BUSCON
BUSCON1.MCTC3     3   Memory Cycle Time Control bit 3    
BUSCON1.MCTC2     2   Memory Cycle Time Control bit 2    
BUSCON1.MCTC1     1   Memory Cycle Time Control bit 1    
BUSCON1.MCTC0     0   Memory Cycle Time Control bit 0    
BUSCON2          0xFF16 Bus Configuration Register 2
BUSCON2.CSWEN2    15  Write Chip Select Enable           
BUSCON2.CSREN2    14  Read Chip Select Enable            
BUSCON2.RDYEN2    12  READY Input Enable                 
BUSCON2.BSWC2     11  BUSCON Switch Control
BUSCON2.BUSACT2   10  Bus Active Control                 
BUSCON2.ALECTL2   9   ALE Lengthening Control            
BUSCON2.EWEN2     8   Early Write Enable
BUSCON2.BTYP7     7   External Bus Configuration bit 7   
BUSCON2.BTYP6     6   External Bus Configuration bit 6   
BUSCON2.MTTC2     5   Memory Tristate Time Control       
BUSCON2.RWDC2     4   Read/Write Delay Control for BUSCON
BUSCON2.MCTC3     3   Memory Cycle Time Control bit 3    
BUSCON2.MCTC2     2   Memory Cycle Time Control bit 2    
BUSCON2.MCTC1     1   Memory Cycle Time Control bit 1    
BUSCON2.MCTC0     0   Memory Cycle Time Control bit 0    
BUSCON3          0xFF18 Bus Configuration Register 3
BUSCON3.CSWEN3    15  Write Chip Select Enable           
BUSCON3.CSREN3    14  Read Chip Select Enable            
BUSCON3.RDYEN3    12  READY Input Enable                 
BUSCON3.BSWC3     11  BUSCON Switch Control
BUSCON3.BUSACT3   10  Bus Active Control                 
BUSCON3.ALECTL3   9   ALE Lengthening Control            
BUSCON3.EWEN3     8   Early Write Enable
BUSCON3.BTYP7     7   External Bus Configuration bit 7   
BUSCON3.BTYP6     6   External Bus Configuration bit 6   
BUSCON3.MTTC3     5   Memory Tristate Time Control       
BUSCON3.RWDC3     4   Read/Write Delay Control for BUSCON
BUSCON3.MCTC3     3   Memory Cycle Time Control bit 3    
BUSCON3.MCTC2     2   Memory Cycle Time Control bit 2    
BUSCON3.MCTC1     1   Memory Cycle Time Control bit 1    
BUSCON3.MCTC0     0   Memory Cycle Time Control bit 0    
BUSCON4          0xFF1A Bus Configuration Register 4
BUSCON4.CSWEN4    15  Write Chip Select Enable           
BUSCON4.CSREN4    14  Read Chip Select Enable            
BUSCON4.RDYEN4    12  READY Input Enable                 
BUSCON4.BSWC4     11  BUSCON Switch Control
BUSCON4.BUSACT4   10  Bus Active Control                 
BUSCON4.ALECTL4   9   ALE Lengthening Control            
BUSCON4.EWEN4     8   Early Write Enable
BUSCON4.BTYP7     7   External Bus Configuration bit 7   
BUSCON4.BTYP6     6   External Bus Configuration bit 6   
BUSCON4.MTTC4     5   Memory Tristate Time Control       
BUSCON4.RWDC4     4   Read/Write Delay Control for BUSCON
BUSCON4.MCTC3     3   Memory Cycle Time Control bit 3    
BUSCON4.MCTC2     2   Memory Cycle Time Control bit 2    
BUSCON4.MCTC1     1   Memory Cycle Time Control bit 1    
BUSCON4.MCTC0     0   Memory Cycle Time Control bit 0    
ZEROS            0xFF1C Constant Value 0's Register (read only)
ONES             0xFF1E Constant Value 1's Register (read only)
T78CON           0xFF20 CAPCOM Timer 7 and 8 Control Register
T78CON.T8R        14  Timer/Counter 8 Run Control
T78CON.T8M        11  Timer/Counter 8 Mode Selection
T78CON.T8I10      10  Timer/Counter 8 Input Selection bit 10
T78CON.T8I9       9   Timer/Counter 8 Input Selection bit 9 
T78CON.T8I8       8   Timer/Counter 8 Input Selection bit 8 
T78CON.T7R        6   Timer/Counter 7 Run Control
T78CON.T7M        3   Timer/Counter 7 Mode Selection
T78CON.T7I2       2   Timer/Counter 7 Input Selection bit 2
T78CON.T7I1       1   Timer/Counter 7 Input Selection bit 1
T78CON.T7I0       0   Timer/Counter 7 Input Selection bit 0
CCM4             0xFF22 CAPCOM Mode Control Register 4
CCM4.ACC19        15  Allocation Bit for Capture/Compare Register CC4
CCM4.CCMOD19_14   14  Mode Selection for Capture/Compare Register CC4 bit 14
CCM4.CCMOD19_13   13  Mode Selection for Capture/Compare Register CC4 bit 13
CCM4.CCMOD19_12   12  Mode Selection for Capture/Compare Register CC4 bit 12
CCM4.ACC18        11  Allocation Bit for Capture/Compare Register CC4       
CCM4.CCMOD18_10   10  Mode Selection for Capture/Compare Register CC4 bit 10
CCM4.CCMOD18_9    9   Mode Selection for Capture/Compare Register CC4 bit 9 
CCM4.CCMOD18_8    8   Mode Selection for Capture/Compare Register CC4 bit 8 
CCM4.ACC17        7   Allocation Bit for Capture/Compare Register CC4       
CCM4.CCMOD17_6    6   Mode Selection for Capture/Compare Register CC4 bit 6 
CCM4.CCMOD17_5    5   Mode Selection for Capture/Compare Register CC4 bit 5 
CCM4.CCMOD17_4    4   Mode Selection for Capture/Compare Register CC4 bit 4 
CCM4.ACC16        3   Allocation Bit for Capture/Compare Register CC4       
CCM4.CCMOD16_2    2   Mode Selection for Capture/Compare Register CC4 bit 2 
CCM4.CCMOD16_1    1   Mode Selection for Capture/Compare Register CC4 bit 1 
CCM4.CCMOD16_0    0   Mode Selection for Capture/Compare Register CC4 bit 0 
CCM5             0xFF24 CAPCOM Mode Control Register 5
CCM5.ACC23        15  Allocation Bit for Capture/Compare Register CC4       
CCM5.CCMOD23_14   14  Mode Selection for Capture/Compare Register CC4 bit 14
CCM5.CCMOD23_13   13  Mode Selection for Capture/Compare Register CC4 bit 13
CCM5.CCMOD23_12   12  Mode Selection for Capture/Compare Register CC4 bit 12
CCM5.ACC22        11  Allocation Bit for Capture/Compare Register CC4       
CCM5.CCMOD22_10   10  Mode Selection for Capture/Compare Register CC4 bit 10
CCM5.CCMOD22_9    9   Mode Selection for Capture/Compare Register CC4 bit 9 
CCM5.CCMOD22_8    8   Mode Selection for Capture/Compare Register CC4 bit 8 
CCM5.ACC21        7   Allocation Bit for Capture/Compare Register CC4       
CCM5.CCMOD21_6    6   Mode Selection for Capture/Compare Register CC4 bit 6 
CCM5.CCMOD21_5    5   Mode Selection for Capture/Compare Register CC4 bit 5 
CCM5.CCMOD21_4    4   Mode Selection for Capture/Compare Register CC4 bit 4 
CCM5.ACC20        3   Allocation Bit for Capture/Compare Register CC4       
CCM5.CCMOD20_2    2   Mode Selection for Capture/Compare Register CC4 bit 2 
CCM5.CCMOD20_1    1   Mode Selection for Capture/Compare Register CC4 bit 1 
CCM5.CCMOD20_0    0   Mode Selection for Capture/Compare Register CC4 bit 0 
CCM6             0xFF26 CAPCOM Mode Control Register 6
CCM6.ACC27        15  Allocation Bit for Capture/Compare Register CC4       
CCM6.CCMOD27_14   14  Mode Selection for Capture/Compare Register CC4 bit 14
CCM6.CCMOD27_13   13  Mode Selection for Capture/Compare Register CC4 bit 13
CCM6.CCMOD27_12   12  Mode Selection for Capture/Compare Register CC4 bit 12
CCM6.ACC26        11  Allocation Bit for Capture/Compare Register CC4       
CCM6.CCMOD26_10   10  Mode Selection for Capture/Compare Register CC4 bit 10
CCM6.CCMOD26_9    9   Mode Selection for Capture/Compare Register CC4 bit 9 
CCM6.CCMOD26_8    8   Mode Selection for Capture/Compare Register CC4 bit 8 
CCM6.ACC25        7   Allocation Bit for Capture/Compare Register CC4       
CCM6.CCMOD25_6    6   Mode Selection for Capture/Compare Register CC4 bit 6 
CCM6.CCMOD25_5    5   Mode Selection for Capture/Compare Register CC4 bit 5 
CCM6.CCMOD25_4    4   Mode Selection for Capture/Compare Register CC4 bit 4 
CCM6.ACC24        3   Allocation Bit for Capture/Compare Register CC4       
CCM6.CCMOD24_2    2   Mode Selection for Capture/Compare Register CC4 bit 2 
CCM6.CCMOD24_1    1   Mode Selection for Capture/Compare Register CC4 bit 1 
CCM6.CCMOD24_0    0   Mode Selection for Capture/Compare Register CC4 bit 0 
CCM7             0xFF28 CAPCOM Mode Control Register 7
CCM7.ACC31        15  Allocation Bit for Capture/Compare Register CC4       
CCM7.CCMOD31_14   14  Mode Selection for Capture/Compare Register CC4 bit 14
CCM7.CCMOD31_13   13  Mode Selection for Capture/Compare Register CC4 bit 13
CCM7.CCMOD31_12   12  Mode Selection for Capture/Compare Register CC4 bit 12
CCM7.ACC30        11  Allocation Bit for Capture/Compare Register CC4       
CCM7.CCMOD30_10   10  Mode Selection for Capture/Compare Register CC4 bit 10
CCM7.CCMOD30_9    9   Mode Selection for Capture/Compare Register CC4 bit 9 
CCM7.CCMOD30_8    8   Mode Selection for Capture/Compare Register CC4 bit 8 
CCM7.ACC29        7   Allocation Bit for Capture/Compare Register CC4       
CCM7.CCMOD29_6    6   Mode Selection for Capture/Compare Register CC4 bit 6 
CCM7.CCMOD29_5    5   Mode Selection for Capture/Compare Register CC4 bit 5 
CCM7.CCMOD29_4    4   Mode Selection for Capture/Compare Register CC4 bit 4 
CCM7.ACC28        3   Allocation Bit for Capture/Compare Register CC4       
CCM7.CCMOD28_2    2   Mode Selection for Capture/Compare Register CC4 bit 2 
CCM7.CCMOD28_1    1   Mode Selection for Capture/Compare Register CC4 bit 1 
CCM7.CCMOD28_0    0   Mode Selection for Capture/Compare Register CC4 bit 0 
PWMCON0          0xFF30 PWM Control Register 0
PWMCON0.PIR3      15  PWM Channel 3 Interrupt Request Flag
PWMCON0.PIR2      14  PWM Channel 2 Interrupt Request Flag
PWMCON0.PIR1      13  PWM Channel 1 Interrupt Request Flag
PWMCON0.PIR0      12  PWM Channel 0 Interrupt Request Flag
PWMCON0.PIE3      11  PWM Channel 3 Interrupt Enable Flag
PWMCON0.PIE2      10  PWM Channel 2 Interrupt Enable Flag
PWMCON0.PIE1      9   PWM Channel 1 Interrupt Enable Flag
PWMCON0.PIE0      8   PWM Channel 0 Interrupt Enable Flag
PWMCON0.PTI3      7   PWM Timer 3 Input Clock Selection
PWMCON0.PTI2      6   PWM Timer 2 Input Clock Selection
PWMCON0.PTI1      5   PWM Timer 1 Input Clock Selection
PWMCON0.PTI0      4   PWM Timer 0 Input Clock Selection
PWMCON0.PTR3      3   PWM Timer 3 Run Control Bit
PWMCON0.PTR2      2   PWM Timer 2 Run Control Bit
PWMCON0.PTR1      1   PWM Timer 1 Run Control Bit
PWMCON0.PTR0      0   PWM Timer 0 Run Control Bit
PWMCON1          0xFF32 PWM Control Register 1
PWMCON1.PS3       15  PWM Channel 3 Single Shot Mode Control Bit
PWMCON1.PS2       14  PWM Channel 2 Single Shot Mode Control Bit
PWMCON1.PB01      12  PWM Channel 0/1 Burst Mode Control Bit
PWMCON1.PM3       7   PWM Channel 3 Mode Control Bit
PWMCON1.PM2       6   PWM Channel 2 Mode Control Bit
PWMCON1.PM1       5   PWM Channel 1 Mode Control Bit
PWMCON1.PM0       4   PWM Channel 0 Mode Control Bit
PWMCON1.PEN3      3   PWM Channel 3 Output Enable Bit
PWMCON1.PEN2      2   PWM Channel 2 Output Enable Bit
PWMCON1.PEN1      1   PWM Channel 1 Output Enable Bit
PWMCON1.PEN0      0   PWM Channel 0 Output Enable Bit
T2CON            0xFF40 GPT1 Timer 2 Control Register
T2CON.T2UDE       8   Timer 2 External Up/Down Enable
T2CON.T2UD        7   Timer 2 Up/Down Control
T2CON.T2R         6   Timer 2 Run Bit
T2CON.T2M5        5   Timer 2 Mode Control bit 5
T2CON.T2M4        4   Timer 2 Mode Control bit 4
T2CON.T2M3        3   Timer 2 Mode Control bit 3
T2CON.T2I2        2   Timer 2 Input Selection bit 2
T2CON.T2I1        1   Timer 2 Input Selection bit 1
T2CON.T2I0        0   Timer 2 Input Selection bit 0
T3CON            0xFF42 GPT1 Timer 3 Control Register
T3CON.T3OTL       10  Timer 3 Output Toggle Latch
T3CON.T3OE        9   Alternate Output Function Enable
T3CON.T3UDE       8   Timer 3 External Up/Down Enable
T3CON.T3UD        7   Timer 3 Up/Down Control
T3CON.T3R         6   Timer 3 Run Bit
T3CON.T3M5        5   Timer 3 Mode Control bit 5
T3CON.T3M4        4   Timer 3 Mode Control bit 4
T3CON.T3M3        3   Timer 3 Mode Control bit 3
T3CON.T3I2        2   Timer 3 Input Selection bit 2
T3CON.T3I1        1   Timer 3 Input Selection bit 1
T3CON.T3I0        0   Timer 3 Input Selection bit 0
T4CON            0xFF44 GPT1 Timer 4 Control Register
T4CON.T4UDE       8   Timer 4 External Up/Down Enable
T4CON.T4UD        7   Timer 4 Up/Down Control
T4CON.T4R         6   Timer 4 Run Bit
T4CON.T4M5        5   Timer 4 Mode Control bit 5
T4CON.T4M4        4   Timer 4 Mode Control bit 4
T4CON.T4M3        3   Timer 4 Mode Control bit 3
T4CON.T4I2        2   Timer 4 Input Selection bit 2
T4CON.T4I1        1   Timer 4 Input Selection bit 1
T4CON.T4I0        0   Timer 4 Input Selection bit 0
T5CON            0xFF46 GPT2 Timer 5 Control Register
T5CON.T5SC        15  Timer 5 Capture Mode Enable
T5CON.T5CLR       14  Timer 5 Clear Bit
T5CON.CI13        13  Register CAPREL Capture Trigger Selection bit 13
T5CON.CI12        12  Register CAPREL Capture Trigger Selection bit 12
T5CON.CT3         10  Timer 3 Capture Trigger Enable
T5CON.T5UDE       8   Timer 5 External Up/Down Enable
T5CON.T5UD        7   Timer 5 Up / Down Control
T5CON.T5R         6   Timer 5 Run Bit
T5CON.T5M5        5   Timer 5 Mode Control bit 5
T5CON.T5M4        4   Timer 5 Mode Control bit 4
T5CON.T5M3        3   Timer 5 Mode Control bit 3
T5CON.T5I2        2   Timer 5 Input Selection bit 2
T5CON.T5I1        1   Timer 5 Input Selection bit 1
T5CON.T5I0        0   Timer 5 Input Selection bit 0
T6CON            0xFF48 GPT2 Timer 6 Control Register
T6CON.T6SR        15  Timer 6 Reload Mode Enable
T6CON.T6OTL       10  Timer 6 Output Toggle Latch
T6CON.T6OE        9   Alternate Output Function Enable
T6CON.T6UDE       8   Timer 6 External Up/Down Enable
T6CON.T6UD        7   Timer 6 Up/Down Control
T6CON.T6R         6   Timer 6 Run Bit
T6CON.T6M5        5   Timer 6 Mode Control bit 5
T6CON.T6M4        4   Timer 6 Mode Control bit 4
T6CON.T6M3        3   Timer 6 Mode Control bit 3
T6CON.T6I2        2   Timer 6 Input Selection bit 2
T6CON.T6I1        1   Timer 6 Input Selection bit 1
T6CON.T6I0        0   Timer 6 Input Selection bit 0
T01CON           0xFF50 CAPCOM Timer 0 and Timer 1 Ctrl. Reg.
T01CON.T1R        14  Timer/Counter 1 Run Control
T01CON.T1M        11  Timer/Counter 1 Mode Selection
T01CON.T1I10      10  Timer/Counter 1 Input Selection bit 10
T01CON.T1I9       9   Timer/Counter 1 Input Selection bit 9 
T01CON.T1I8       8   Timer/Counter 1 Input Selection bit 8 
T01CON.T0R        6   Timer/Counter 0 Run Control
T01CON.T0M        3   Timer/Counter 0 Mode Selection
T01CON.T0I2       2   Timer/Counter 0 Input Selection bit 2
T01CON.T0I1       1   Timer/Counter 0 Input Selection bit 1
T01CON.T0I0       0   Timer/Counter 0 Input Selection bit 0
CCM0             0xFF52 CAPCOM Mode Control Register 0
CCM0.ACC3         15  Allocation Bit for Capture/Compare Register CC0       
CCM0.CCMOD3_14    14  Mode Selection for Capture/Compare Register CC0 bit 14
CCM0.CCMOD3_13    13  Mode Selection for Capture/Compare Register CC0 bit 13
CCM0.CCMOD3_12    12  Mode Selection for Capture/Compare Register CC0 bit 12
CCM0.ACC2         11  Allocation Bit for Capture/Compare Register CC0       
CCM0.CCMOD2_10    10  Mode Selection for Capture/Compare Register CC0 bit 10
CCM0.CCMOD2_9     9   Mode Selection for Capture/Compare Register CC0 bit 9 
CCM0.CCMOD2_8     8   Mode Selection for Capture/Compare Register CC0 bit 8 
CCM0.ACC1         7   Allocation Bit for Capture/Compare Register CC0       
CCM0.CCMOD1_6     6   Mode Selection for Capture/Compare Register CC0 bit 6 
CCM0.CCMOD1_5     5   Mode Selection for Capture/Compare Register CC0 bit 5 
CCM0.CCMOD1_4     4   Mode Selection for Capture/Compare Register CC0 bit 4 
CCM0.ACC0         3   Allocation Bit for Capture/Compare Register CC0       
CCM0.CCMOD0_2     2   Mode Selection for Capture/Compare Register CC0 bit 2 
CCM0.CCMOD0_1     1   Mode Selection for Capture/Compare Register CC0 bit 1 
CCM0.CCMOD0_0     0   Mode Selection for Capture/Compare Register CC0 bit 0 
CCM1             0xFF54 CAPCOM Mode Control Register 1
CCM1.ACC7         15  Allocation Bit for Capture/Compare Register CC1       
CCM1.CCMOD7_14    14  Mode Selection for Capture/Compare Register CC1 bit 14
CCM1.CCMOD7_13    13  Mode Selection for Capture/Compare Register CC1 bit 13
CCM1.CCMOD7_12    12  Mode Selection for Capture/Compare Register CC1 bit 12
CCM1.ACC6         11  Allocation Bit for Capture/Compare Register CC1       
CCM1.CCMOD6_10    10  Mode Selection for Capture/Compare Register CC1 bit 10
CCM1.CCMOD6_9     9   Mode Selection for Capture/Compare Register CC1 bit 9 
CCM1.CCMOD6_8     8   Mode Selection for Capture/Compare Register CC1 bit 8 
CCM1.ACC5         7   Allocation Bit for Capture/Compare Register CC1       
CCM1.CCMOD5_6     6   Mode Selection for Capture/Compare Register CC1 bit 6 
CCM1.CCMOD5_5     5   Mode Selection for Capture/Compare Register CC1 bit 5 
CCM1.CCMOD5_4     4   Mode Selection for Capture/Compare Register CC1 bit 4 
CCM1.ACC4         3   Allocation Bit for Capture/Compare Register CC1       
CCM1.CCMOD4_2     2   Mode Selection for Capture/Compare Register CC1 bit 2 
CCM1.CCMOD4_1     1   Mode Selection for Capture/Compare Register CC1 bit 1 
CCM1.CCMOD4_0     0   Mode Selection for Capture/Compare Register CC1 bit 0 
CCM2             0xFF56 CAPCOM Mode Control Register 2
CCM2.ACC11        15  Allocation Bit for Capture/Compare Register CC2
CCM2.CCMOD11_14   14  Mode Selection for Capture/Compare Register CC2 bit 14
CCM2.CCMOD11_13   13  Mode Selection for Capture/Compare Register CC2 bit 13
CCM2.CCMOD11_12   12  Mode Selection for Capture/Compare Register CC2 bit 12
CCM2.ACC10        11  Allocation Bit for Capture/Compare Register CC2     
CCM2.CCMOD10_10   10  Mode Selection for Capture/Compare Register CC2 bit 10
CCM2.CCMOD10_9    9   Mode Selection for Capture/Compare Register CC2 bit 9 
CCM2.CCMOD10_8    8   Mode Selection for Capture/Compare Register CC2 bit 8 
CCM2.ACC9         7   Allocation Bit for Capture/Compare Register CC2     
CCM2.CCMOD9_6     6   Mode Selection for Capture/Compare Register CC2 bit 6
CCM2.CCMOD9_5     5   Mode Selection for Capture/Compare Register CC2 bit 5
CCM2.CCMOD9_4     4   Mode Selection for Capture/Compare Register CC2 bit 4
CCM2.ACC8         3   Allocation Bit for Capture/Compare Register CC2      
CCM2.CCMOD8_2     2   Mode Selection for Capture/Compare Register CC2 bit 2
CCM2.CCMOD8_1     1   Mode Selection for Capture/Compare Register CC2 bit 1
CCM2.CCMOD8_0     0   Mode Selection for Capture/Compare Register CC2 bit 0
CCM3             0xFF58 CAPCOM Mode Control Register 3
CCM3.ACC15        15  Allocation Bit for Capture/Compare Register CC3       
CCM3.CCMOD15_14   14  Mode Selection for Capture/Compare Register CC3 bit 14
CCM3.CCMOD15_13   13  Mode Selection for Capture/Compare Register CC3 bit 13
CCM3.CCMOD15_12   12  Mode Selection for Capture/Compare Register CC3 bit 12
CCM3.ACC14        11  Allocation Bit for Capture/Compare Register CC3       
CCM3.CCMOD14_10   10  Mode Selection for Capture/Compare Register CC3 bit 10
CCM3.CCMOD14_9    9   Mode Selection for Capture/Compare Register CC3 bit 9 
CCM3.CCMOD14_8    8   Mode Selection for Capture/Compare Register CC3 bit 8 
CCM3.ACC13        7   Allocation Bit for Capture/Compare Register CC3       
CCM3.CCMOD13_6    6   Mode Selection for Capture/Compare Register CC3 bit 6 
CCM3.CCMOD13_5    5   Mode Selection for Capture/Compare Register CC3 bit 5 
CCM3.CCMOD13_4    4   Mode Selection for Capture/Compare Register CC3 bit 4 
CCM3.ACC12        3   Allocation Bit for Capture/Compare Register CC3       
CCM3.CCMOD12_2    2   Mode Selection for Capture/Compare Register CC3 bit 2 
CCM3.CCMOD12_1    1   Mode Selection for Capture/Compare Register CC3 bit 1 
CCM3.CCMOD12_0    0   Mode Selection for Capture/Compare Register CC3 bit 0 
T2IC             0xFF60 GPT1 Timer 2 Interrupt Control Register
T2IC.T2IR         7
T2IC.T2IE         6
T2IC.ILVL5        5
T2IC.ILVL4        4
T2IC.ILVL3        3
T2IC.ILVL2        2
T2IC.GLVL1        1
T2IC.GLVL0        0
T3IC             0xFF62 GPT1 Timer 3 Interrupt Control Register
T3IC.T3IR         7
T3IC.T3IE         6
T3IC.ILVL5        5
T3IC.ILVL4        4
T3IC.ILVL3        3
T3IC.ILVL2        2
T3IC.GLVL1        1
T3IC.GLVL0        0
T4IC             0xFF64 GPT1 Timer 4 Interrupt Control Register
T4IC.T4IR         7
T4IC.T4IE         6
T4IC.ILVL5        5
T4IC.ILVL4        4
T4IC.ILVL3        3
T4IC.ILVL2        2
T4IC.GLVL1        1
T4IC.GLVL0        0
T5IC             0xFF66 GPT2 Timer 5 Interrupt Control Register
T5IC.T5IR         7
T5IC.T5IE         6
T5IC.ILVL5        5
T5IC.ILVL4        4
T5IC.ILVL3        3
T5IC.ILVL2        2
T5IC.GLVL1        1
T5IC.GLVL0        0
T6IC             0xFF68 GPT2 Timer 6 Interrupt Control Register
T6IC.T6IR         7
T6IC.T6IE         6
T6IC.ILVL5        5
T6IC.ILVL4        4
T6IC.ILVL3        3
T6IC.ILVL2        2
T6IC.GLVL1        1
T6IC.GLVL0        0
CRIC             0xFF6A GPT2 CAPREL Interrupt Control Register
CRIC.CRIR         7
CRIC.CRIE         6
CRIC.ILVL5        5
CRIC.ILVL4        4
CRIC.ILVL3        3
CRIC.ILVL2        2
CRIC.GLVL1        1
CRIC.GLVL0        0
S0TIC            0xFF6C Serial Channel 0 Transmit Interrupt Control Register
S0TIC.S0TIR       7
S0TIC.S0TIE       6
S0TIC.ILVL5       5
S0TIC.ILVL4       4
S0TIC.ILVL3       3
S0TIC.ILVL2       2
S0TIC.GLVL1       1
S0TIC.GLVL0       0
S0RIC            0xFF6E Serial Channel 0 Receive Interrupt Control Register
S0RIC.S0RIR       7
S0RIC.S0RIE       6
S0RIC.ILVL5       5
S0RIC.ILVL4       4
S0RIC.ILVL3       3
S0RIC.ILVL2       2
S0RIC.GLVL1       1
S0RIC.GLVL0       0
S0EIC            0xFF70 Serial Channel 0 Error Interrupt Ctrl. Reg.
S0EIC.S0EIR       7
S0EIC.S0EIE       6
S0EIC.ILVL5       5
S0EIC.ILVL4       4
S0EIC.ILVL3       3
S0EIC.ILVL2       2
S0EIC.GLVL1       1
S0EIC.GLVL0       0
SSCTIC           0xFF72 SSC Transmit Interrupt Control Register
SSCTIC.SSCTIR     7
SSCTIC.SSCTIE     6
SSCTIC.ILVL5      5
SSCTIC.ILVL4      4
SSCTIC.ILVL3      3
SSCTIC.ILVL2      2
SSCTIC.GLVL1      1
SSCTIC.GLVL0      0
SSCRIC           0xFF74 SSC Receive Interrupt Control Register
SSCRIC.SSCRIR     7
SSCRIC.SSCRIE     6
SSCRIC.ILVL5      5
SSCRIC.ILVL4      4
SSCRIC.ILVL3      3
SSCRIC.ILVL2      2
SSCRIC.GLVL1      1
SSCRIC.GLVL0      0
SSCEIC           0xFF76 SSC Error Interrupt Control Register
SSCEIC.SSCEIR     7
SSCEIC.SSCEIE     6
SSCEIC.ILVL5      5
SSCEIC.ILVL4      4
SSCEIC.ILVL3      3
SSCEIC.ILVL2      2
SSCEIC.GLVL1      1
SSCEIC.GLVL0      0
CC0IC            0xFF78 CAPCOM Register 0 Interrupt Ctrl. Reg.
CC0IC.CC0IR       7
CC0IC.CC0IE       6
CC0IC.ILVL5       5
CC0IC.ILVL4       4
CC0IC.ILVL3       3
CC0IC.ILVL2       2
CC0IC.GLVL1       1
CC0IC.GLVL0       0
CC1IC            0xFF7A CAPCOM Register 1 Interrupt Ctrl. Reg.
CC1IC.CC1IR       7
CC1IC.CC1IE       6
CC1IC.ILVL5       5
CC1IC.ILVL4       4
CC1IC.ILVL3       3
CC1IC.ILVL2       2
CC1IC.GLVL1       1
CC1IC.GLVL0       0
CC2IC            0xFF7C CAPCOM Register 2 Interrupt Ctrl. Reg.
CC2IC.CC2IR       7
CC2IC.CC2IE       6
CC2IC.ILVL5       5
CC2IC.ILVL4       4
CC2IC.ILVL3       3
CC2IC.ILVL2       2
CC2IC.GLVL1       1
CC2IC.GLVL0       0
CC3IC            0xFF7E CAPCOM Register 3 Interrupt Ctrl. Reg.
CC3IC.CC3IR       7
CC3IC.CC3IE       6
CC3IC.ILVL5       5
CC3IC.ILVL4       4
CC3IC.ILVL3       3
CC3IC.ILVL2       2
CC3IC.GLVL1       1
CC3IC.GLVL0       0
CC4IC            0xFF80 CAPCOM Register 4 Interrupt Ctrl. Reg.
CC4IC.CC4IR       7
CC4IC.CC4IE       6
CC4IC.ILVL5       5
CC4IC.ILVL4       4
CC4IC.ILVL3       3
CC4IC.ILVL2       2
CC4IC.GLVL1       1
CC4IC.GLVL0       0
CC5IC            0xFF82 CAPCOM Register 5 Interrupt Ctrl. Reg.
CC5IC.CC5IR       7
CC5IC.CC5IE       6
CC5IC.ILVL5       5
CC5IC.ILVL4       4
CC5IC.ILVL3       3
CC5IC.ILVL2       2
CC5IC.GLVL1       1
CC5IC.GLVL0       0
CC6IC            0xFF84 CAPCOM Register 6Interrupt Ctrl. Reg.
CC6IC.CC6IR       7
CC6IC.CC6IE       6
CC6IC.ILVL5       5
CC6IC.ILVL4       4
CC6IC.ILVL3       3
CC6IC.ILVL2       2
CC6IC.GLVL1       1
CC6IC.GLVL0       0
CC7IC            0xFF86 CAPCOM Register 7 Interrupt Ctrl. Reg.
CC7IC.CC7IR       7
CC7IC.CC7IE       6
CC7IC.ILVL5       5
CC7IC.ILVL4       4
CC7IC.ILVL3       3
CC7IC.ILVL2       2
CC7IC.GLVL1       1
CC7IC.GLVL0       0
CC8IC            0xFF88 CAPCOM Register 8 Interrupt Ctrl. Reg.
CC8IC.CC8IR       7
CC8IC.CC8IE       6
CC8IC.ILVL5       5
CC8IC.ILVL4       4
CC8IC.ILVL3       3
CC8IC.ILVL2       2
CC8IC.GLVL1       1
CC8IC.GLVL0       0
CC9IC            0xFF8A CAPCOM Register 9 Interrupt Ctrl. Reg.
CC9IC.CC9IR       7
CC9IC.CC9IE       6
CC9IC.ILVL5       5
CC9IC.ILVL4       4
CC9IC.ILVL3       3
CC9IC.ILVL2       2
CC9IC.GLVL1       1
CC9IC.GLVL0       0
CC10IC           0xFF8C CAPCOM Register 10 Interrupt Ctrl. Reg.
CC10IC.CC10IR     7
CC10IC.CC10IE     6
CC10IC.ILVL5      5
CC10IC.ILVL4      4
CC10IC.ILVL3      3
CC10IC.ILVL2      2
CC10IC.GLVL1      1
CC10IC.GLVL0      0
CC11IC           0xFF8E CAPCOM Register 11 Interrupt Ctrl. Reg.
CC11IC.CC11IR     7
CC11IC.CC11IE     6
CC11IC.ILVL5      5
CC11IC.ILVL4      4
CC11IC.ILVL3      3
CC11IC.ILVL2      2
CC11IC.GLVL1      1
CC11IC.GLVL0      0
CC12IC           0xFF90 CAPCOM Register 12 Interrupt Ctrl. Reg.
CC12IC.CC12IR     7
CC12IC.CC12IE     6
CC12IC.ILVL5      5
CC12IC.ILVL4      4
CC12IC.ILVL3      3
CC12IC.ILVL2      2
CC12IC.GLVL1      1
CC12IC.GLVL0      0
CC13IC           0xFF92 CAPCOM Register 13 Interrupt Ctrl. Reg.
CC13IC.CC13IR     7
CC13IC.CC13IE     6
CC13IC.ILVL5      5
CC13IC.ILVL4      4
CC13IC.ILVL3      3
CC13IC.ILVL2      2
CC13IC.GLVL1      1
CC13IC.GLVL0      0
CC14IC           0xFF94 CAPCOM Register 14 Interrupt Ctrl. Reg.
CC14IC.CC14IR     7
CC14IC.CC14IE     6
CC14IC.ILVL5      5
CC14IC.ILVL4      4
CC14IC.ILVL3      3
CC14IC.ILVL2      2
CC14IC.GLVL1      1
CC14IC.GLVL0      0
CC15IC           0xFF96 CAPCOM Register 15 Interrupt Ctrl. Reg.
CC15IC.CC15IR     7
CC15IC.CC15IE     6
CC15IC.ILVL5      5
CC15IC.ILVL4      4
CC15IC.ILVL3      3
CC15IC.ILVL2      2
CC15IC.GLVL1      1
CC15IC.GLVL0      0
ADCIC            0xFF98 A/D Converter End of Conversion Interrupt Control Register
ADCIC.ADCIR       7
ADCIC.ADCIE       6
ADCIC.ILVL5       5
ADCIC.ILVL4       4
ADCIC.ILVL3       3
ADCIC.ILVL2       2
ADCIC.GLVL1       1
ADCIC.GLVL0       0
ADEIC            0xFF9A A/D Converter Overrun Error Interrupt Control Register
ADEIC.ADEIR       7
ADEIC.ADEIE       6
ADEIC.ILVL5       5
ADEIC.ILVL4       4
ADEIC.ILVL3       3
ADEIC.ILVL2       2
ADEIC.GLVL1       1
ADEIC.GLVL0       0
T0IC             0xFF9C CAPCOM Timer 0 Interrupt Ctrl. Reg.
T0IC.T0IR         7
T0IC.T0IE         6
T0IC.ILVL5        5
T0IC.ILVL4        4
T0IC.ILVL3        3
T0IC.ILVL2        2
T0IC.GLVL1        1
T0IC.GLVL0        0
T1IC             0xFF9E CAPCOM Timer 1 Interrupt Ctrl. Reg.
T1IC.T1IR         7
T1IC.T1IE         6
T1IC.ILVL5        5
T1IC.ILVL4        4
T1IC.ILVL3        3
T1IC.ILVL2        2
T1IC.GLVL1        1
T1IC.GLVL0        0
ADCON            0xFFA0 A/D Converter Control Register
ADCON.ADCTC15     15  ADC Conversion Time Control bit 15
ADCON.ADCTC14     14  ADC Conversion Time Control bit 14
ADCON.ADSTC13     13  ADC Sample Time Control bit 13
ADCON.ADSTC12     12  ADC Sample Time Control bit 12
ADCON.ADCRQ       11  ADC Channel Injection Request Flag
ADCON.ADCIN       10  ADC Channel Injection Enable
ADCON.ADWR        9   ADC Wait for Read Control
ADCON.ADBSY       8   ADC Busy Flag
ADCON.ADST        7   ADC Start Bit
ADCON.ADM5        5   ADC Mode Selection bit 5
ADCON.ADM4        4   ADC Mode Selection bit 4
ADCON.ADCH3       3   ADC Analog Channel Input Selection bit 3
ADCON.ADCH2       2   ADC Analog Channel Input Selection bit 2
ADCON.ADCH1       1   ADC Analog Channel Input Selection bit 1
ADCON.ADCH0       0   ADC Analog Channel Input Selection bit 0
P5               0xFFA2 Port 5 Register (read only)
P5.P5_15          15  Port data register P5 bit 15
P5.P5_14          14  Port data register P5 bit 14
P5.P5_13          13  Port data register P5 bit 13
P5.P5_12          12  Port data register P5 bit 12
P5.P5_11          11  Port data register P5 bit 11
P5.P5_10          10  Port data register P5 bit 10
P5.P5_9           9   Port data register P5 bit 9 
P5.P5_8           8   Port data register P5 bit 8 
P5.P5_7           7   Port data register P5 bit 7 
P5.P5_6           6   Port data register P5 bit 6 
P5.P5_5           5   Port data register P5 bit 5 
P5.P5_4           4   Port data register P5 bit 4 
P5.P5_3           3   Port data register P5 bit 3 
P5.P5_2           2   Port data register P5 bit 2 
P5.P5_1           1   Port data register P5 bit 1 
P5.P5_0           0   Port data register P5 bit 0 
P5DIDIS          0xFFA4 Port 5 Digital Inp.Disable Reg.
P5DIDIS.P5D15     15  Port 5 Bit 15 Digital Input Control
P5DIDIS.P5D14     14  Port 5 Bit 14 Digital Input Control
P5DIDIS.P5D13     13  Port 5 Bit 13 Digital Input Control
P5DIDIS.P5D12     12  Port 5 Bit 12 Digital Input Control
P5DIDIS.P5D11     11  Port 5 Bit 11 Digital Input Control
P5DIDIS.P5D10     10  Port 5 Bit 10 Digital Input Control
P5DIDIS.P5D9      9   Port 5 Bit 9 Digital Input Control
P5DIDIS.P5D8      8   Port 5 Bit 8 Digital Input Control
P5DIDIS.P5D7      7   Port 5 Bit 7 Digital Input Control
P5DIDIS.P5D6      6   Port 5 Bit 6 Digital Input Control
P5DIDIS.P5D5      5   Port 5 Bit 5 Digital Input Control
P5DIDIS.P5D4      4   Port 5 Bit 4 Digital Input Control
P5DIDIS.P5D3      3   Port 5 Bit 3 Digital Input Control
P5DIDIS.P5D2      2   Port 5 Bit 2 Digital Input Control
P5DIDIS.P5D1      1   Port 5 Bit 1 Digital Input Control
P5DIDIS.P5D0      0   Port 5 Bit 0 Digital Input Control
FOCON            0xFFAA Frequency Output Control Register
TFR              0xFFAC Trap Flag Register
TFR.NMI           15  Non Maskable Interrupt Flag
TFR.STKOF         14  Stack Overflow Flag
TFR.STKUF         13  Stack Underflow Flag
TFR.UNDOPC        7   Undefined Opcode Flag
TFR.PRTFLT        3   Protection Fault Flag
TFR.ILLOPA        2   Illegal Word Operand Access Flag
TFR.ILLINA        1   Illegal Instruction Access Flag
TFR.ILLBUS        0   Illegal External Bus Access Flag
WDTCON           0xFFAE Watchdog Timer Control Register
WDTCON.WDTREL15   15  Watchdog Timer Reload Value bit 15
WDTCON.WDTREL14   14  Watchdog Timer Reload Value bit 14
WDTCON.WDTREL13   13  Watchdog Timer Reload Value bit 13
WDTCON.WDTREL12   12  Watchdog Timer Reload Value bit 12
WDTCON.WDTREL11   11  Watchdog Timer Reload Value bit 11
WDTCON.WDTREL10   10  Watchdog Timer Reload Value bit 10
WDTCON.WDTREL9    9   Watchdog Timer Reload Value bit 9 
WDTCON.WDTREL8    8   Watchdog Timer Reload Value bit 8 
WDTCON.WDTPRE     7   Watchdog Timer Input Prescaler Control
WDTCON.LHWR       4   Long Hardware Reset Indication Flag
WDTCON.SHWR       3   Short Hardware Reset Indication Flag
WDTCON.SWR        2   Software Reset Indication Flag
WDTCON.WDTR       1   Watchdog Timer Reset Indication Flag
WDTCON.WDTIN      0   Watchdog Timer Input Frequency Select
S0CON            0xFFB0 Serial Channel 0 Control Register
S0CON.S0R         15  Baudrate Generator Run Bit
S0CON.S0LB        14  LoopBack Mode Enable Bit
S0CON.S0BRS       13  Baudrate Selection Bit
S0CON.S0ODD       12  Parity Selection Bit
S0CON.S0OE        10  Overrun Error Flag
S0CON.S0FE        9   Framing Error Flag
S0CON.S0PE        8   Parity Error Flag
S0CON.S0OEN       7   Overrun Check Enable Bit
S0CON.S0FEN       6   Framing Check Enable Bit
S0CON.S0PEN       5   Parity Check Enable Bit
S0CON.S0REN       4   Receiver Enable Bit
S0CON.S0STP       3   Number of Stop Bits Selection
S0CON.S0M2        2   ASC0 Mode Control bit 2
S0CON.S0M1        1   ASC0 Mode Control bit 1
S0CON.S0M0        0   ASC0 Mode Control bit 0
SSCCON           0xFFB2 SSC Control Register
SSCCON.SSCEN_0    15  SSC Enable Bit = '0'
SSCCON.SSCMS      14  SSC Master Select Bit
SSCCON.SSCAREN    12  SSC Automatic Reset Enable Bit
SSCCON.SSCBEN     11  SSC Baudrate Error Enable Bit
SSCCON.SSCPEN     10  SSC Phase Error Enable Bit
SSCCON.SSCREN      9  SSC Receive Error Enable Bit
SSCCON.SSCTEN      8  SSC Transmit Error Enable Bit
SSCCON.SSCPO       6  SSC Clock Polarity Control Bit
SSCCON.SSCPH       5  SSC Clock Phase Control Bit
SSCCON.SSCHB       4  SSC Heading Control Bit
SSCCON.SSCBM_3     3  SSC Data Width Selection bit 3
SSCCON.SSCBM_2     2  SSC Data Width Selection bit 2
SSCCON.SSCBM_1     1  SSC Data Width Selection bit 1
SSCCON.SSCBM_0     0  SSC Data Width Selection bit 0
; SSCCON           0xFFB2 SSC Control Register
; SSCCON.SSCEN_1    15  SSC Enable Bit = '1'
; SSCCON.SSCMS      14  SSC Master Select Bit
; SSCCON.SSCBSY     12  SSC Busy Flag
; SSCCON.SSCBE      11  SSC Baudrate Error Flag
; SSCCON.SSCPE      10  SSC Phase Error Flag
; SSCCON.SSCRE       9  SSC Receive Error Flag
; SSCCON.SSCTE       8  SSC Transmit Error Flag
; SSCCON.SSCBC_3     3  SSC Bit Count Field bit 3
; SSCCON.SSCBC_2     2  SSC Bit Count Field bit 2
; SSCCON.SSCBC_1     1  SSC Bit Count Field bit 1
; SSCCON.SSCBC_0     0  SSC Bit Count Field bit 0
P2               0xFFC0 Port 2 Register
P2.P2_15          15  Port data register P2 bit 15
P2.P2_14          14  Port data register P2 bit 14
P2.P2_13          13  Port data register P2 bit 13
P2.P2_12          12  Port data register P2 bit 12
P2.P2_11          11  Port data register P2 bit 11
P2.P2_10          10  Port data register P2 bit 10
P2.P2_9           9   Port data register P2 bit 9 
P2.P2_8           8   Port data register P2 bit 8 
P2.P2_7           7   Port data register P2 bit 7 
P2.P2_6           6   Port data register P2 bit 6 
P2.P2_5           5   Port data register P2 bit 5 
P2.P2_4           4   Port data register P2 bit 4 
P2.P2_3           3   Port data register P2 bit 3 
P2.P2_2           2   Port data register P2 bit 2 
P2.P2_1           1   Port data register P2 bit 1 
P2.P2_0           0   Port data register P2 bit 0 
DP2              0xFFC2 Port 2 Direction Control Register
DP2.DP2_15        15  Port direction register DP2 bit 15
DP2.DP2_14        14  Port direction register DP2 bit 14
DP2.DP2_13        13  Port direction register DP2 bit 13
DP2.DP2_12        12  Port direction register DP2 bit 12
DP2.DP2_11        11  Port direction register DP2 bit 11
DP2.DP2_10        10  Port direction register DP2 bit 10
DP2.DP2_9         9   Port direction register DP2 bit 9 
DP2.DP2_8         8   Port direction register DP2 bit 8 
DP2.DP2_7         7   Port direction register DP2 bit 7 
DP2.DP2_6         6   Port direction register DP2 bit 6 
DP2.DP2_5         5   Port direction register DP2 bit 5 
DP2.DP2_4         4   Port direction register DP2 bit 4 
DP2.DP2_3         3   Port direction register DP2 bit 3 
DP2.DP2_2         2   Port direction register DP2 bit 2 
DP2.DP2_1         1   Port direction register DP2 bit 1 
DP2.DP2_0         0   Port direction register DP2 bit 0 
P3               0xFFC4 Port 3 Register
P3.P3_15          15  Port data register P3 bit 15
P3.P3_13          13  Port data register P3 bit 13
P3.P3_12          12  Port data register P3 bit 12
P3.P3_11          11  Port data register P3 bit 11
P3.P3_10          10  Port data register P3 bit 10
P3.P3_9           9   Port data register P3 bit 9 
P3.P3_8           8   Port data register P3 bit 8 
P3.P3_7           7   Port data register P3 bit 7 
P3.P3_6           6   Port data register P3 bit 6 
P3.P3_5           5   Port data register P3 bit 5 
P3.P3_4           4   Port data register P3 bit 4 
P3.P3_3           3   Port data register P3 bit 3 
P3.P3_2           2   Port data register P3 bit 2 
P3.P3_1           1   Port data register P3 bit 1 
P3.P3_0           0   Port data register P3 bit 0 
DP3              0xFFC6 Port 3 Direction Control Register
DP3.DP3_15        15  Port direction register DP3 bit 15
DP3.DP3_13        13  Port direction register DP3 bit 13
DP3.DP3_12        12  Port direction register DP3 bit 12
DP3.DP3_11        11  Port direction register DP3 bit 11
DP3.DP3_10        10  Port direction register DP3 bit 10
DP3.DP3_9         9   Port direction register DP3 bit 9 
DP3.DP3_8         8   Port direction register DP3 bit 8 
DP3.DP3_7         7   Port direction register DP3 bit 7 
DP3.DP3_6         6   Port direction register DP3 bit 6 
DP3.DP3_5         5   Port direction register DP3 bit 5 
DP3.DP3_4         4   Port direction register DP3 bit 4 
DP3.DP3_3         3   Port direction register DP3 bit 3 
DP3.DP3_2         2   Port direction register DP3 bit 2 
DP3.DP3_1         1   Port direction register DP3 bit 1 
DP3.DP3_0         0   Port direction register DP3 bit 0 
P4               0xFFC8 Port 4 Register (7 bits)
P4.P4_7           7   Port data register P4 bit 7
P4.P4_6           6   Port data register P4 bit 6
P4.P4_5           5   Port data register P4 bit 5
P4.P4_4           4   Port data register P4 bit 4
P4.P4_3           3   Port data register P4 bit 3
P4.P4_2           2   Port data register P4 bit 2
P4.P4_1           1   Port data register P4 bit 1
P4.P4_0           0   Port data register P4 bit 0
DP4              0xFFCA Port 4 Direction Control Register
DP4.DP4_7         7   Port direction register DP4 bit 7 
DP4.DP4_6         6   Port direction register DP4 bit 6 
DP4.DP4_5         5   Port direction register DP4 bit 5 
DP4.DP4_4         4   Port direction register DP4 bit 4 
DP4.DP4_3         3   Port direction register DP4 bit 3 
DP4.DP4_2         2   Port direction register DP4 bit 2 
DP4.DP4_1         1   Port direction register DP4 bit 1 
DP4.DP4_0         0   Port direction register DP4 bit 0 
P6               0xFFCC Port 6 Register (8 bits)
P6.P6_7           7   Port data register P6 bit 7
P6.P6_6           6   Port data register P6 bit 6
P6.P6_5           5   Port data register P6 bit 5
P6.P6_4           4   Port data register P6 bit 4
P6.P6_3           3   Port data register P6 bit 3
P6.P6_2           2   Port data register P6 bit 2
P6.P6_1           1   Port data register P6 bit 1
P6.P6_0           0   Port data register P6 bit 0
DP6              0xFFCE Port 6 Direction Control Register
DP6.DP6_7         7   Port direction register DP6 bit 7
DP6.DP6_6         6   Port direction register DP6 bit 6
DP6.DP6_5         5   Port direction register DP6 bit 5
DP6.DP6_4         4   Port direction register DP6 bit 4
DP6.DP6_3         3   Port direction register DP6 bit 3
DP6.DP6_2         2   Port direction register DP6 bit 2
DP6.DP6_1         1   Port direction register DP6 bit 1
DP6.DP6_0         0   Port direction register DP6 bit 0
P7               0xFFD0 Port 7 Register (8 bits)
P7.P7_7           7   Port data register P7 bit 7
P7.P7_6           6   Port data register P7 bit 6
P7.P7_5           5   Port data register P7 bit 5
P7.P7_4           4   Port data register P7 bit 4
P7.P7_3           3   Port data register P7 bit 3
P7.P7_2           2   Port data register P7 bit 2
P7.P7_1           1   Port data register P7 bit 1
P7.P7_0           0   Port data register P7 bit 0
DP7              0xFFD2 Port 7 Direction Control Register
DP7.DP7_7         7   Port direction register DP7 bit 7
DP7.DP7_6         6   Port direction register DP7 bit 6
DP7.DP7_5         5   Port direction register DP7 bit 5
DP7.DP7_4         4   Port direction register DP7 bit 4
DP7.DP7_3         3   Port direction register DP7 bit 3
DP7.DP7_2         2   Port direction register DP7 bit 2
DP7.DP7_1         1   Port direction register DP7 bit 1
DP7.DP7_0         0   Port direction register DP7 bit 0
P8               0xFFD4 Port 8 Register (8 bits)
P8.P8_7           7   Port data register P8 bit 7
P8.P8_6           6   Port data register P8 bit 6
P8.P8_5           5   Port data register P8 bit 5
P8.P8_4           4   Port data register P8 bit 4
P8.P8_3           3   Port data register P8 bit 3
P8.P8_2           2   Port data register P8 bit 2
P8.P8_1           1   Port data register P8 bit 1
P8.P8_0           0   Port data register P8 bit 0
DP8              0xFFD6 Port 8 Direction Control Register
DP8.DP8_7         7   Port direction register DP8 bit 7
DP8.DP8_6         6   Port direction register DP8 bit 6
DP8.DP8_5         5   Port direction register DP8 bit 5
DP8.DP8_4         4   Port direction register DP8 bit 4
DP8.DP8_3         3   Port direction register DP8 bit 3
DP8.DP8_2         2   Port direction register DP8 bit 2
DP8.DP8_1         1   Port direction register DP8 bit 1
DP8.DP8_0         0   Port direction register DP8 bit 0


