;
; This file defines internal registers for Motorola 68HC16 processors.
;
; This file can be configured for different devices.
; At the beginning of the file there are definitions common for all devices
; Device-specific definitions are introduced by
;
;       .devicename
;
; line. Also an optional directive
;
;       .default=devicename
;
; designates the default device name.
;

.default MC68HC16Z

; ANALOG TO DIGITAL CONVERTER PERIPHERAL REGISTERS

ADMCR     0xFF700 A/D Module Config Reg
ADCTEST   0xFF702 A/D Test Register
PADR      0xFF706 Port Data Reg
ADCTL0    0xFF70A A/D Control Reg 0
ADCTL1    0xFF70C A/D Control Reg 1
ADSTAT    0xFF70E A/D Status Reg
URRES0    0xFF710 Unsigned Right Result 0
URRES1    0xFF712 Unsigned Right Result 1
URRES2    0xFF714 Unsigned Right Result 2
URRES3    0xFF716 Unsigned Right Result 3
URRES4    0xFF718 Unsigned Right Result 4
URRES5    0xFF71A Unsigned Right Result 5
URRES6    0xFF71C Unsigned Right Result 6
URRES7    0xFF71E Unsigned Right Result 7
SLRES0    0xFF720 Signed Left Result 0
SLRES1    0xFF722 Signed Left Result 1
SLRES2    0xFF724 Signed Left Result 2
SLRES3    0xFF726 Signed Left Result 3
SLRES4    0xFF728 Signed Left Result 4
SLRES5    0xFF72A Signed Left Result 5
SLRES6    0xFF72C Signed Left Result 6
SLRES7    0xFF72E Signed Left Result 7
ULRES0    0xFF730 Unsigned Left Result 0
ULRES1    0xFF732 Unsigned Left Result 1
ULRES2    0xFF734 Unsigned Left Result 2
ULRES3    0xFF736 Unsigned Left Result 3
ULRES4    0xFF738 Unsigned Left Result 4
ULRES5    0xFF73A Unsigned Left Result 5
ULRES6    0xFF73C Unsigned Left Result 6
ULRES7    0xFF73E Unsigned Left Result 7

; GENERAL PURPOSE TIMER MODULE PERIPHERAL REGISTER

GPTMCR    0xFF900 Module Configuration Reg
ICR       0xFF904 Interrupt Configuration Reg
PDDR      0xFF906 Parallel Data Direction
PDR       0xFF907 Parallel Data Reg
OC1M      0xFF908 Action Mask Reg
OC1D      0xFF909 Action Data Reg
TCNT      0xFF90A Timer Counter Reg
PACTL     0xFF90C Pulse Accu Control Reg
PACNT     0xFF90D Pulse Accu Counter Reg
TIC1      0xFF90E Input Capture Reg 1
TIC2      0xFF910 Input Capture Reg 2
TIC3      0xFF912 Input Capture Reg 3
TOC1      0xFF914 Output Compare Reg 1
TOC2      0xFF916 Output Compare Reg 2
TOC3      0xFF918 Output Compare Reg 3
TOC4      0xFF91A Output Compare Reg 4
TI4O5     0xFF91C Input 4 or Output Reg 5
TCTL1     0xFF91E Timer Control Reg 1
TCTL2     0xFF91F Timer Control Reg 2
TMSK1     0xFF920 Timer Interrupt Mask Reg 1
TMSK2     0xFF921 Timer Interrupt Mask Reg 2
TFLG1     0xFF922 Timer Interrupt Flag Reg 1
TFLG2     0xFF923 Timer Interrupt Flag Reg 2
CFRPWM    0xFF924 Compare Force and PWM Ctrl
PWMC      0xFF925 PWM Reg C
PWMA      0xFF926 PWM Reg A
PWMB      0xFF927 PWM Reg B
PWMCNT    0xFF928 PWM Count Reg
PWBUFA    0xFF92A PWM Buffer Reg A
PWBUFB    0xFF92B PWM Buffer Reg B
PRESCL    0xFF92C GPT Prescaler



;-------------------------------
; Device specific definitions



.MC68HC16Y1

; SINGLE-CHIP INTEGRATION MODULE PERIPHERAL REGISTERS Y1

SCIMCR    0xFFA00 Module Configuration Reg
SCIMTR    0xFFA02 Factory Test Reg
SYNCR     0xFFA04 Clock Synthesizer Ctrl Reg
RSR       0xFFA07 Reset Status Reg
SCIMTRE   0xFFA08 SCIM Test E Reg
PORTA     0xFFA0A Port A Data Reg
PORTB     0xFFA0B Port B Data Reg
PORTG     0xFFA0C Port G Data Reg
PORTH     0xFFA0D Port H Data Reg
PORTE0    0xFFA11 Port E0 Data Reg
PORTE1    0xFFA13 Port E1 Data Reg
DDRAB     0xFFA14 Port A/B Data Direction Reg
DDRE      0xFFA15 Port E Data Direction Reg
PEPAR     0xFFA17 Port E Pin Assignment Reg
PORTF0    0xFFA19 Port F0 Data Reg
PORTF1    0xFFA1B Port F1 Data Reg
DDRF      0xFFA1D Port F Data Direction Reg
PFPAR     0xFFA1F Port F Pin Assignment Reg
SYPCR     0xFFA21 System Protection Ctrl Reg
PICR      0xFFA22 Periodic Interrupt Ctrl Reg
PITR      0xFFA24 Periodic Interrupt Timer
SWSR      0xFFA27 Software Service Reg
PORTFE    0xFFA29 Port F Edge Control Reg
PFIVR     0xFFA2B Port F Edge It Vector Reg
TSTMSRA   0xFFA30 Test Module Master Shift A
TSTMSRB   0xFFA32 Test Module Master Shift B
TSTSC     0xFFA34 Test Module Shift Count
TSTRC     0xFFA36 Test Module Repeat Counter
CREG      0xFFA38 Test Module Control Reg
DREG      0xFFA3A Test Module Distributed Reg
PORTC     0xFFA41 Port C Data Reg
CSPAR0    0xFFA44 Chip Select Pin Asgn Reg 0
CSPAR1    0xFFA46 Chip Select Pin Asgn Reg 1
CSBARBT   0xFFA48 Chip Select Base Reg Boot
CSORBT    0xFFA4A Chip Select Option Reg Boot
CSBAR0    0xFFA4C Chip Select Base Reg 0
CSOR0     0xFFA4E Chip Select Option Reg 0
CSBAR3    0xFFA58 Chip Select Base Reg 3
CSOR3     0xFFA5A Chip Select Option Reg 3
CSBAR5    0xFFA60 Chip Select Base Reg 5
CSOR5     0xFFA62 Chip Select Option Reg 5
CSBAR6    0xFFA64 Chip Select Base Reg 6
CSOR6     0xFFA66 Chip Select Option Reg 6
CSBAR7    0xFFA68 Chip Select Base Reg 7
CSOR7     0xFFA6A Chip Select Option Reg 7
CSBAR8    0xFFA6C Chip Select Base Reg 8
CSOR8     0xFFA6E Chip Select Option Reg 8
CSBAR9    0xFFA70 Chip Select Base Reg 9
CSOR9     0xFFA72 Chip Select Option Reg 9
CSBAR10   0xFFA74 Chip Select Base Reg 10
CSOR10    0xFFA76 Chip Select Option Reg 10

; STANDBY RAM MODULE PERIPHERAL REGISTERS Y1

STBRAMMCR 0xFFB00 ; Module Configuration Reg
STBRAMTST 0xFFB02 ; Ram Test Reg
STBRAMBAR 0xFFB04 ; Ram Base Address Reg

; MULTICHANNEL COMMUNICATION  PERIPHERAL REGISTERS Y1

MMCR      0xFFC00 Module Configuration Reg
MTEST     0xFFC02 MCCI Test Reg
ILSCI     0xFFC04 SCI Interrupt Reg
MIVR      0xFFC05 SCI Interrupt Vector Reg
ILSPI     0xFFC06 SPI Interrupt Reg
PMCPAR    0xFFC09 Port Pin Assignment Reg
DDRMC     0xFFC0B Port Data Direction Reg
PORTMC    0xFFC0D Port Data Register
SCCR0A    0xFFC18 SCIA Control Reg 0
SCCR1A    0xFFC1A SCIA Control Reg 1
SCSRA     0xFFC1C SCIA Status Register
SCDRA     0xFFC1E SCIA Data Register
SCCR0B    0xFFC28 SCIB Control Reg 0
SCCR1B    0xFFC2A SCIB Control Reg 1
SCSRB     0xFFC2C SCIB Status Register
SCDRB     0xFFC2E SCIB Data Register
SPCR      0xFFC38 SPI Control Register
SPSR      0xFFC3C SPI Status Register
SPDR      0xFFC3E SPI Data Register

; TPU RAM MODULE PERIPHERAL REGISTERS Y1

TRAMMCR   0xFFD00 Module Configuration Reg
TRAMTST   0xFFD02 Ram Test Reg
TRAMBAR   0xFFD04 Ram Base Address Reg



.MC68HC16Z

; SYSTEM INTEGRATION MODULE PERIPHERAL REGISTERS

MCR       0xFFA00 Module Configuration Reg
SYNCR     0xFFA04 Clock Synthesizer Ctrl Reg
RSR       0xFFA07 Reset Status Reg
PORTE     0xFFA11 Port E Data Reg
DDRE      0xFFA15 Port E Data Direction Reg
PEPAR     0xFFA17 Port E Pin Assignment Reg
PORTF     0xFFA19 Port F Data Reg
DDRF      0xFFA1D Port F Data Direction Reg
PFPAR     0xFFA1F Port F Pin Assignment Reg
SYPCR     0xFFA21 System Protection Ctrl Reg
PICR      0xFFA22 Periodic Interrupt Ctrl Reg
PITR      0xFFA24 Periodic Interrupt Timer
SWSR      0xFFA27 Software Service Reg
CSPDR     0xFFA41 Chip Select Pin Data Reg
CSPAR0    0xFFA44 Chip Select Pin Asgn Reg 0
CSPAR1    0xFFA46 Chip Select Pin Asgn Reg 1
CSBARBT   0xFFA48 Chip Select Base Reg Boot
CSORBT    0xFFA4A Chip Select Option Reg Boot
CSBAR0    0xFFA4C Chip Select Base Reg 0
CSOR0     0xFFA4E Chip Select Option Reg 0
CSBAR1    0xFFA50 Chip Select Base Reg 1
CSOR1     0xFFA52 Chip Select Option Reg 1
CSBAR2    0xFFA54 Chip Select Base Reg 2
CSOR2     0xFFA56 Chip Select Option Reg 2
CSBAR3    0xFFA58 Chip Select Base Reg 3
CSOR3     0xFFA5A Chip Select Option Reg 3
CSBAR4    0xFFA5C Chip Select Base Reg 4
CSOR4     0xFFA5E Chip Select Option Reg 4
CSBAR5    0xFFA60 Chip Select Base Reg 5
CSOR5     0xFFA62 Chip Select Option Reg 5
CSBAR6    0xFFA64 Chip Select Base Reg 6
CSOR6     0xFFA66 Chip Select Option Reg 6
CSBAR7    0xFFA68 Chip Select Base Reg 7
CSOR7     0xFFA6A Chip Select Option Reg 7
CSBAR8    0xFFA6C Chip Select Base Reg 8
CSOR8     0xFFA6E Chip Select Option Reg 8
CSBAR9    0xFFA70 Chip Select Base Reg 9
CSOR9     0xFFA72 Chip Select Option Reg 9
CSBAR10   0xFFA74 Chip Select Base Reg 10
CSOR10    0xFFA76 Chip Select Option Reg 10

; STANDBY RAM MODULE PERIPHERAL REGISTERS

RAMMCR    0xFFB00 Module Configuration Reg
RAMTST    0xFFB02 Ram Test Reg
RAMBAH    0xFFB04 Array Base Address Reg High
RAMBAL    0xFFB06 Array Base Address Reg Low

; QUEUED SERIAL MODULE PERIPHERAL REGISTERS

QMCR      0xFFC00 Module Configuration Reg
QTEST     0xFFC02 QSM Test Register
QILR      0xFFC04 Interrupt Level Reg
QIVR      0xFFC05 Interrupt Vector Reg
SCCR0     0xFFC08 SCI Control Reg 0
SCCR1     0xFFC0A SCI Control Reg 1
SCSR      0xFFC0C SCI Status Reg
SCDR      0xFFC0E SCI Data Reg
QPDR      0xFFC15 Port Data Reg
QPAR      0xFFC16 Pin Assignment Reg
QDDR      0xFFC17 Data Direction Reg
SPCR0     0xFFC18 SPI Control Reg 0
SPCR1     0xFFC1A SPI Control Reg 1
SPCR2     0xFFC1C SPI Control Reg 2
SPCR3     0xFFC1E SPI Control Reg 3
SPSR      0xFFC1F SPI Status Reg
REC_RAM   0xFFD00 Receive Data Ram
TRAN_RAM  0xFFD20 Transmit Data Ram
COMD_RAM  0xFFD40 Command Ram



; insert definitions here

